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@thislooksfun
Last active April 17, 2020 02:26
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# ------------------------------------------------
# Generic C Makefile
#
# Adapted from https://stackoverflow.com/questions/7004702
# ------------------------------------------------
##### START CONFIG #####
### START BASIC CONFIG ###
# project name (generate executable with this name)
TARGET = assn1
# change these to proper directories where each file should be
SRCDIR = src
DEPDIR = .dep
OBJDIR = .obj
BINDIR = bin
### END BASIC CONFIG ###
### START ADVANCED CONFIG ###
CC = gcc
CFLAGS = -std=gnu99 -g -Wall -I.
LINKER = gcc
LFLAGS = -Wall -I. -lm
DEPFLAGS = -MT $@ -MMD -MP -MF $(DEPDIR)/$*.d
SOURCES := $(wildcard $(SRCDIR)/*.c)
DEPENDS := $(SOURCES:$(SRCDIR)/%.c=$(DEPDIR)/%.d)
OBJECTS := $(SOURCES:$(SRCDIR)/%.c=$(OBJDIR)/%.o)
rm = rm -f
### END ADVANCED CONFIG ###
##### END CONFIG #####
##### BEGIN RULES #####
.PHONY: bin
bin: dirs $(BINDIR)/$(TARGET)
.PHONY: dirs
dirs:
@mkdir -p $(DEPDIR) $(OBJDIR) $(BINDIR)
$(BINDIR)/$(TARGET): $(OBJECTS)
@$(LINKER) $(OBJECTS) $(LFLAGS) -o $@
@echo "Linking complete!"
$(OBJDIR)/%.o : $(SRCDIR)/%.c
@$(CC) $(CFLAGS) $(DEPFLAGS) -c $< -o $@
@echo "Compiled "$<" successfully!"
ifneq ($(MAKECMDGOALS),clean)
-include $(DEPENDS)
endif
.PHONY: clean
clean:
@$(rm) -r $(OBJDIR) $(DEPDIR) $(BINDIR)
@echo "Cleanup complete!"
##### END RULES #####
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