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thomasrussellmurphy/gist:ef3c66fea395142db471

Created October 14, 2014 01:01
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Snippit of fixed-value Verilog ROM
Raw
gistfile1.v
[...]
// store address every clock cycle
always @( posedge clk )
addr_reg <= addr;
// 2-bit color 8x16 (wide x high) 64-character ROM
always @(*) begin
case ( addr_reg )
//code 0x00, space
11'h000: data = 8'b00000000; //
11'h001: data = 8'b00000000; //
11'h002: data = 8'b00000000; //
11'h003: data = 8'b00000000; //
11'h004: data = 8'b00000000; //
11'h005: data = 8'b00000000; //
11'h006: data = 8'b00000000; //
11'h007: data = 8'b00000000; //
11'h008: data = 8'b00000000; //
11'h009: data = 8'b00000000; //
11'h00a: data = 8'b00000000; //
11'h00b: data = 8'b00000000; //
11'h00c: data = 8'b00000000; //
11'h00d: data = 8'b00000000; //
11'h00e: data = 8'b00000000; //
11'h00f: data = 8'b00000000; //
//code 0x01
[...]
//code 0xff
[...]
end
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