Created
June 5, 2021 21:29
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sim.exe: top.v sim.cpp | |
verilator --cc --coverage --exe -Wno-lint -trace --top-module top \ | |
--Mdir bench_dir $^ | |
$(MAKE) -C bench_dir -f Vtop.mk | |
cp bench_dir/Vtop $@ | |
clean: | |
rm -f bench_dir sim.exe | |
.PHONY: clean |
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#include <verilated.h> | |
#include "Vtop.h" | |
vluint64_t main_time = 0; | |
double sc_time_stamp() { | |
return main_time; // Note does conversion to real, to match SystemC | |
} | |
int main(int argc, char** argv, char** env) { | |
Verilated::debug(0); | |
Verilated::randReset(2); | |
Verilated::traceEverOn(true); | |
Verilated::commandArgs(argc, argv); | |
Verilated::mkdir("logs"); | |
Vtop* top = new Vtop; // Or use a const unique_ptr, or the VL_UNIQUE_PTR wrapper | |
top->clk = 0; | |
while (!Verilated::gotFinish()) { | |
++main_time; | |
top->clk = !top->clk; | |
top->resetn = (main_time < 10) ? 0 : 1; | |
if (main_time < 5) { | |
// Zero coverage if still early in reset, otherwise toggles there may | |
// falsely indicate a signal is covered | |
VerilatedCov::zero(); | |
} | |
top->eval(); | |
} | |
top->final(); | |
// Coverage analysis (since test passed) | |
#if VM_COVERAGE | |
Verilated::mkdir("logs"); | |
VerilatedCov::write("logs/coverage.dat"); | |
#endif | |
delete top; | |
top = NULL; | |
exit(0); | |
} |
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module top | |
( input wire logic clk | |
, input wire logic resetn | |
); | |
reg [31:0] counter; | |
always_ff @(posedge clk) begin | |
counter <= (!resetn) ? 0 : counter + 1; | |
if (counter >= 99) begin | |
$write("ok done\n"); | |
$finish(0); | |
end | |
end | |
endmodule: top |
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