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@thoughtpolice
Created February 10, 2022 23:55
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intel questa simulation example
# Setup compilation
set QSYS_SIMDIR ../prj
source $QSYS_SIMDIR/mentor/msim_setup.tcl
dev_com
com
# add sources, but skip the top level BSP since its unused
foreach f [glob -type f path/to/sources/*.sv] {
vlog -sv -work work "$f"
}
vlog -sv -work work sim_top.sv
# Elaborate with all wires available
set TOP_LEVEL_NAME sim_top
elab_debug
# Setup waves
add wave *
view structure
view signals
run -all
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