insert_sort.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sort is port (
    -- external interface
    clk, reset: in STD_LOGIC;
    n: in STD_LOGIC_VECTOR(3 downto 0);

    sorted: out STD_LOGIC_VECTOR(31 downto 0)
); end;

architecture insert_sort_arch of sort is
    type NIBBLE_MEMORY is array (0 to 7) of STD_LOGIC_VECTOR(3 downto 0);
    signal memory: NIBBLE_MEMORY;
begin
    sorted(3 downto 0) <= memory(0);
    sorted(7 downto 4) <= memory(1);
    sorted(11 downto 8) <= memory(2);
    sorted(15 downto 12) <= memory(3);
    sorted(19 downto 16) <= memory(4);
    sorted(23 downto 20) <= memory(5);
    sorted(27 downto 24) <= memory(6);
    sorted(31 downto 28) <= memory(7);

    process (clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                for i in 0 to memory'high loop
                    memory(i) <= (others => '0');
                end loop;
            else
                for i in 0 to memory'high - 1 loop
                    if memory(i + 1) < n then
                        memory(i) <= memory(i + 1);
                    elsif memory(i) < n then
                        memory(i) <= n;
                    end if;
                    if memory(memory'high) < n then
                        memory(memory'high) <= n;
                    end if;
                end loop;
            end if;
        end if;
    end process;
end insert_sort_arch;