Created
September 7, 2023 14:03
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DTS collection
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| /dts-v1/; | |
| / { | |
| #address-cells = <0x02>; | |
| model = "riscv-virtio,qemu"; | |
| #size-cells = <0x02>; | |
| compatible = "riscv-virtio"; | |
| flash@20000000 { | |
| bank-width = <0x04>; | |
| compatible = "cfi-flash"; | |
| reg = <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>; | |
| }; | |
| poweroff { | |
| offset = <0x00>; | |
| compatible = "syscon-poweroff"; | |
| value = <0x5555>; | |
| regmap = <0x04>; | |
| }; | |
| soc { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| compatible = "simple-bus"; | |
| ranges; | |
| clint@2000000 { | |
| interrupts-extended = <0x02 0x03 0x02 0x07>; | |
| compatible = "sifive,clint0\0riscv,clint0"; | |
| reg = <0x00 0x2000000 0x00 0x10000>; | |
| }; | |
| virtio_mmio@10007000 { | |
| interrupts = <0x07>; | |
| interrupt-parent = <0x03>; | |
| compatible = "virtio,mmio"; | |
| reg = <0x00 0x10007000 0x00 0x1000>; | |
| }; | |
| virtio_mmio@10004000 { | |
| interrupts = <0x04>; | |
| interrupt-parent = <0x03>; | |
| compatible = "virtio,mmio"; | |
| reg = <0x00 0x10004000 0x00 0x1000>; | |
| }; | |
| virtio_mmio@10001000 { | |
| interrupts = <0x01>; | |
| interrupt-parent = <0x03>; | |
| compatible = "virtio,mmio"; | |
| reg = <0x00 0x10001000 0x00 0x1000>; | |
| }; | |
| plic@c000000 { | |
| #address-cells = <0x00>; | |
| interrupts-extended = <0x02 0xffffffff 0x02 0x09>; | |
| compatible = "sifive,plic-1.0.0\0riscv,plic0"; | |
| #interrupt-cells = <0x01>; | |
| reg = <0x00 0xc000000 0x00 0x600000>; | |
| phandle = <0x03>; | |
| riscv,ndev = <0x5f>; | |
| interrupt-controller; | |
| }; | |
| virtio_mmio@10006000 { | |
| interrupts = <0x06>; | |
| interrupt-parent = <0x03>; | |
| compatible = "virtio,mmio"; | |
| reg = <0x00 0x10006000 0x00 0x1000>; | |
| }; | |
| virtio_mmio@10003000 { | |
| interrupts = <0x03>; | |
| interrupt-parent = <0x03>; | |
| compatible = "virtio,mmio"; | |
| reg = <0x00 0x10003000 0x00 0x1000>; | |
| }; | |
| serial@10000000 { | |
| interrupts = <0x0a>; | |
| interrupt-parent = <0x03>; | |
| clock-frequency = "\08@"; | |
| compatible = "ns16550a"; | |
| reg = <0x00 0x10000000 0x00 0x100>; | |
| }; | |
| pci@30000000 { | |
| #address-cells = <0x03>; | |
| dma-coherent; | |
| bus-range = <0x00 0xff>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x03 0x20 0x00 0x00 0x00 0x02 0x03 0x21 0x00 0x00 0x00 0x03 0x03 0x22 0x00 0x00 0x00 0x04 0x03 0x23 0x800 0x00 0x00 0x01 0x03 0x21 0x800 0x00 0x00 0x02 0x03 0x22 0x800 0x00 0x00 0x03 0x03 0x23 0x800 0x00 0x00 0x04 0x03 0x20 0x1000 0x00 0x00 0x01 0x03 0x22 0x1000 0x00 0x00 0x02 0x03 0x23 0x1000 0x00 0x00 0x03 0x03 0x20 0x1000 0x00 0x00 0x04 0x03 0x21 0x1800 0x00 0x00 0x01 0x03 0x23 0x1800 0x00 0x00 0x02 0x03 0x20 0x1800 0x00 0x00 0x03 0x03 0x21 0x1800 0x00 0x00 0x04 0x03 0x22>; | |
| #size-cells = <0x02>; | |
| device_type = "pci"; | |
| interrupt-map-mask = <0x1800 0x00 0x00 0x07>; | |
| compatible = "pci-host-ecam-generic"; | |
| ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x00 0x04 0x00>; | |
| #interrupt-cells = <0x01>; | |
| reg = <0x00 0x30000000 0x00 0x10000000>; | |
| linux,pci-domain = <0x00>; | |
| }; | |
| rtc@101000 { | |
| interrupts = <0x0b>; | |
| interrupt-parent = <0x03>; | |
| compatible = "google,goldfish-rtc"; | |
| reg = <0x00 0x101000 0x00 0x1000>; | |
| }; | |
| virtio_mmio@10008000 { | |
| interrupts = <0x08>; | |
| interrupt-parent = <0x03>; | |
| compatible = "virtio,mmio"; | |
| reg = <0x00 0x10008000 0x00 0x1000>; | |
| }; | |
| virtio_mmio@10005000 { | |
| interrupts = <0x05>; | |
| interrupt-parent = <0x03>; | |
| compatible = "virtio,mmio"; | |
| reg = <0x00 0x10005000 0x00 0x1000>; | |
| }; | |
| virtio_mmio@10002000 { | |
| interrupts = <0x02>; | |
| interrupt-parent = <0x03>; | |
| compatible = "virtio,mmio"; | |
| reg = <0x00 0x10002000 0x00 0x1000>; | |
| }; | |
| pmu { | |
| compatible = "riscv,pmu"; | |
| }; | |
| test@100000 { | |
| compatible = "sifive,test1\0sifive,test0\0syscon"; | |
| reg = <0x00 0x100000 0x00 0x1000>; | |
| phandle = <0x04>; | |
| }; | |
| }; | |
| memory@80000000 { | |
| device_type = "memory"; | |
| reg = <0x00 0x80000000 0x00 0x8000000>; | |
| }; | |
| reboot { | |
| offset = <0x00>; | |
| compatible = "syscon-reboot"; | |
| value = <0x7777>; | |
| regmap = <0x04>; | |
| }; | |
| fw-cfg@10100000 { | |
| dma-coherent; | |
| compatible = "qemu,fw-cfg-mmio"; | |
| reg = <0x00 0x10100000 0x00 0x18>; | |
| }; | |
| chosen { | |
| bootargs = "rootwait root=/dev/vda ro"; | |
| stdout-path = "/soc/serial@10000000"; | |
| }; | |
| platform-bus@4000000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| interrupt-parent = <0x03>; | |
| compatible = "qemu,platform\0simple-bus"; | |
| ranges = <0x00 0x00 0x4000000 0x2000000>; | |
| }; | |
| cpus { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| timebase-frequency = <0x989680>; | |
| cpu-map { | |
| cluster0 { | |
| core0 { | |
| cpu = <0x01>; | |
| }; | |
| }; | |
| }; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "riscv"; | |
| mmu-type = "riscv,sv57"; | |
| status = "okay"; | |
| reg = <0x00>; | |
| phandle = <0x01>; | |
| riscv,cboz-block-size = <0x40>; | |
| riscv,isa = "rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sstc_svadu"; | |
| riscv,cbom-block-size = <0x40>; | |
| interrupt-controller { | |
| compatible = "riscv,cpu-intc"; | |
| #interrupt-cells = <0x01>; | |
| phandle = <0x02>; | |
| interrupt-controller; | |
| }; | |
| }; | |
| }; | |
| reserved-memory { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| mmode_resv1@80020000 { | |
| reg = <0x00 0x80020000 0x00 0x20000>; | |
| no-map; | |
| }; | |
| mmode_resv0@80000000 { | |
| reg = <0x00 0x80000000 0x00 0x20000>; | |
| no-map; | |
| }; | |
| }; | |
| }; |
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