scheduling

gistfile1.txt

a.cc:
void Bar();

void Foo(std::atomic<uint32_t> *a) {
  if (a->load(std::memory_order_acquire) != 0) {
    Bar();
  }
}



# *** IR Dump After Rename Disconnected Subregister Components ***:
...
32B   %vreg1<def> = LWZ 0, %vreg0; mem:Volatile LD4[%_M_i.i1] GPRC:%vreg1 G8RC_and_G8RC_NOX0:%vreg0
48B   SYNC 1
64B   %vreg2<def> = CMPLWI %vreg1, 0; CRRC:%vreg2 GPRC:%vreg1
...

# *** IR Dump After Machine Instruction Scheduler ***:
...
32B   %vreg1<def> = LWZ 0, %vreg0; mem:Volatile LD4[%_M_i.i1] GPRC:%vreg1 G8RC_and_G8RC_NOX0:%vreg0
64B   %vreg2<def> = CMPLWI %vreg1, 0; CRRC:%vreg2 GPRC:%vreg1
72B   SYNC 1
...