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# left | |
pin1 F18 | |
pin2 H17 | |
pin3 H18 | |
pin4 J17 | |
pin5 N17 | |
pin6 M18 | |
pin7 M17 | |
pin8 G18 | |
pin9 D18 |
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from selenium import webdriver | |
from selenium.webdriver.common.keys import Keys | |
from selenium.webdriver.chrome.options import Options | |
import xml.dom.minidom as minidom | |
import pycountry | |
import traceback | |
chrome_options = Options() | |
chrome_options.add_argument("--headless") |
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def create_layers(img, name): | |
from PIL import Image | |
def combine(img, layers): | |
result = Image.new('RGB', img.size, 0x000000) | |
for i in range(img.size[0]): | |
for j in range(img.size[1]): | |
if img.getpixel((i, j)) in layers: | |
result.putpixel((i, j), 0xFFFFFF) | |
else: |
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/** | |
* Simple UART module to explore basic HardwareC concepts. | |
* | |
* HardwareC is a working name for a new hardware description language. The | |
* goal is to make FPGAs easier for hobbyists to take advantage of. To achieve | |
* this goal, some design choices have been made: | |
* | |
* 1. Use familiar syntax. C/C++ syntax is borrowed everywhere, no reason to | |
* reinvent the wheel. Where C/C++ falls short, borrow from Verilog/SystemVerilog. | |
* 2. Interrop with C/C++. A HardwareC module should be able to be used seamlessly |
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module wor_mux #( | |
parameter WIDTH = 32, | |
parameter DEPTH = 8 | |
) ( | |
input [DEPTH - 1 : 0] en, | |
input [(WIDTH * DEPTH) - 1 : 0] mux_in, | |
output [WIDTH - 1 : 0] mux_out | |
); | |
reg [WIDTH - 1 : 0] bus; |
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// simple RV32I processor inspired by Berkely CS152 notes and PicoRV32: | |
// * http://www-inst.eecs.berkeley.edu/~cs152/fa16/handouts/microcode.pdf | |
// * http://www-inst.eecs.berkeley.edu/~cs152/fa16/lectures/L02-SimpleImps.pdf | |
// * https://github.com/cliffordwolf/picorv32 | |
// * https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf | |
// | |
// intention is for this to be smaller and higher frequency than PicoRV32, but | |
// at the cost of much lower overall performance. if used with the XIP SPI | |
// controller, the lower performance may not make much of a difference when | |
// coupled to the slow speed of executing instructions directly from SPI |
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// reg_sel mux select | |
reg [1:0] reg_sel; | |
`define REG_SEL_RD 'h0 | |
`define REG_SEL_RS1 'h1 | |
`define REG_SEL_RS2 'h2 | |
`define REG_SEL_PC 'h3 | |
// alu_rhs_sel mux select | |
reg [1:0] alu_rhs_sel; | |
`define ALU_RHS_SEL_B 'h0 |