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@tmeissner
Last active March 14, 2016 10:36
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Test case of evaluating PSL endpoint & ended constructs in VHDL code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
entity psl_test_endpoint is
end entity psl_test_endpoint;
architecture test of psl_test_endpoint is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING psl_test_endpoint test case";
report "==========================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1';
wait until rising_edge(s_clk); -- endpoint active
s_read <= '1';
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait until rising_edge(s_clk);
stop(0);
end process TestP;
-- sequence & endpoint definition
-- psl sequence S_TEST is {not(s_write); s_write}@rising_edge(s_clk);
-- psl endpoint E_TEST is S_TEST;
-- It's not possible to use endpoints on sequences VHDL code
EndpointP: process is
begin
wait until E_TEST;
report "TEST";
wait;
end process EndpointP;
end architecture test;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
entity psl_test_ended is
end entity psl_test_ended;
architecture test of psl_test_ended is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING psl_test_ended test case";
report "==========================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1';
wait until rising_edge(s_clk); -- sequence active
s_read <= '1';
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait until rising_edge(s_clk);
stop(0);
end process TestP;
-- sequence & endpoint definition
-- psl sequence S_TEST is {not(s_write); s_write}@rising_edge(s_clk);
-- It's not possible to use ended on sequences in VHDL code
EndedP: process is
begin
wait until ended(S_TEST);
report "TEST";
wait;
end process EndedP;
end architecture test;
@tmeissner
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The log from Modelsim DE 10.5, which supports evaluating enpoints & ended() in VHDL, looks like this:

# vsim -t 1ps -wlf ../log/vsim.wlf -logfile ../log/mentor_transcript.log work.psl_test_endpoint 
# Start time: 11:26:18 on Mar 14,2016
# //  ModelSim DE 10.5 Feb 12 2016 Linux 3.2.0-4-amd64
# //
# //  Copyright 1991-2016 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  ModelSim DE and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading std.env(body)
# Loading work.psl_test_endpoint(test)
#1
#1
# ** Note: RUNNING psl_test_endpoint test case
#    Time: 0 ps  Iteration: 0  Instance: /psl_test_endpoint
# ** Note: ==========================================
#    Time: 0 ps  Iteration: 0  Instance: /psl_test_endpoint
# ** Note: TEST
#    Time: 130 ns  Iteration: 0  Instance: /psl_test_endpoint
# Break in Process TestP at ../psl_test_endpoint.vhd line 45
# Stopped at ../psl_test_endpoint.vhd line 45
# End time: 11:26:19 on Mar 14,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vsim -t 1ps -wlf ../log/vsim.wlf -logfile ../log/mentor_transcript.log work.psl_test_ended 
# Start time: 11:26:19 on Mar 14,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading std.env(body)
# Loading work.psl_test_ended(test)
# ** Note: RUNNING psl_test_ended test case
#    Time: 0 ps  Iteration: 0  Instance: /psl_test_ended
# ** Note: ==========================================
#    Time: 0 ps  Iteration: 0  Instance: /psl_test_ended
# ** Note: TEST
#    Time: 130 ns  Iteration: 0  Instance: /psl_test_ended
# Break in Process TestP at ../psl_test_ended.vhd line 45
# Stopped at ../psl_test_ended.vhd line 45
# End time: 11:26:19 on Mar 14,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

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