Skip to content

Instantly share code, notes, and snippets.

@tomoasleep

tomoasleep/alu.rb

Last active December 28, 2015 17:59
Show Gist options
  • Save tomoasleep/7540058 to your computer and use it in GitHub Desktop.
Save tomoasleep/7540058 to your computer and use it in GitHub Desktop.
Download ZIP
Raw
alu.rb
VhdlTestScript.scenario "../src/alu.vhd" do
dependencies "../src/const/const_alu_ctl.vhd"
ports :alu_ctl, :a, :b, :result
clock :clk
MAX = 0xffffffff
step "alu_ctl_add", 1, 2, 3
step "alu_ctl_add", 0xfffffffe, 1, 0xffffffff
step "alu_ctl_add", MAX, 1, 0
step "alu_ctl_sub", 3, 5, -2
step "alu_ctl_sub", 8, 5, 3
step "alu_ctl_mul", 8, 5, _
step "alu_ctl_mflo", 0, 0, 40
step "alu_ctl_div", 8, 5, _
step "alu_ctl_mflo", 0, 0, 1
step "alu_ctl_mfhi", 0, 0, 3
step "alu_ctl_div", 2, 5, _
step "alu_ctl_mflo", 0, 0, 0
step "alu_ctl_mfhi", 0, 0, 2
step "alu_ctl_lshift_r", 0b10, 1, 0b1
step "alu_ctl_lshift_l", 0b10, 1, 0b100
step "alu_ctl_lshift_l", 0b10, 10, 0b10 << 10
step "alu_ctl_lshift_r", MAX, 1, 0x7fffffff
step "alu_ctl_lshift_r", MAX, 4, 0x0fffffff
step "alu_ctl_ashift_r", MAX, 1, 0xffffffff
step "alu_ctl_and", 0b0111, 0b1010, 0b0010
step "alu_ctl_or", 0b0111, 0b1010, 0b1111
step "alu_ctl_xor", 0b0111, 0b1010, 0b1101
step "alu_ctl_nor", 0b0111, 0b1010, 0xfffffff0
step "alu_ctl_nor", 0b0111, 0b1010, 0xfffffff0
step "alu_ctl_slt", 7, 9, 1
step "alu_ctl_slt", 15, 9, 0
step "alu_ctl_slt", -1, 1, 1
step "alu_ctl_slt", -1, -99, 0
step "alu_ctl_sltu", 7, 9, 1
step "alu_ctl_sltu", 15, 9, 0
step "alu_ctl_sltu", MAX, 0, 0
step "alu_ctl_sltu", 0xf0000000, MAX, 1
step "alu_ctl_seq", 32, 32, 1
step "alu_ctl_seq", 32, 12, 0
step "alu_ctl_sne", 32, 32, 0
step "alu_ctl_sne", 32, 12, 1
step "alu_ctl_cmpz_le", 0, 0, 1
step "alu_ctl_cmpz_le", 3, 0, 0
step "alu_ctl_cmpz_le", -1, 0, 1
step "alu_ctl_cmpz_gt", 0, 1, 0
step "alu_ctl_cmpz_gt", 3, 1, 1
step "alu_ctl_cmpz_gt", -1, 1, 0
step "alu_ctl_cmpz_lt", 0, 0, 0
step "alu_ctl_cmpz_lt", 3, 0, 0
step "alu_ctl_cmpz_lt", -1, 0, 1
step "alu_ctl_cmpz_ge", 0, 1, 1
step "alu_ctl_cmpz_ge", 3, 1, 1
step "alu_ctl_cmpz_ge", -1, 1, 0
step "alu_ctl_select_a", 3, 9, 3
step "alu_ctl_select_b", 3, 9, 9
step "alu_ctl_mthi", 3, _, _
step "alu_ctl_mtlo", 8, _, _
step "alu_ctl_mflo", 0, 0, 8
step "alu_ctl_mfhi", 0, 0, 3
step "alu_ctl_lui", 0, 0x0000ffff, 0xffff0000
end
Raw
fib.rb
VhdlTestScript.scenario "./tb/nemips_tbq.vhd", :fib, :fib_debug do
asm = %q{
.text
j _min_caml_start
fib.10:
li r3, 1
bgt r2, r3, ble_else.24
jr r31
ble_else.24:
addi r3, r2, -1
sw r2, 0(r29) # save argv[0]
move r2, r3
sw r31, -1(r29)
addi r29, r29, -2
jal fib.10 # fib(argv[0] - 1)
addi r29, r29, 2
lw r31, -1(r29)
lw r3, 0(r29) # load argv[0]
addi r3, r3, -2 # argv[0] - 2
sw r2, -1(r29) # save fib(argv[0] - 1)
move r2, r3
sw r31, -2(r29)
addi r29, r29, -3
jal fib.10
addi r29, r29, 3
lw r31, -2(r29)
lw r3, -1(r29) # load fib(argv[0] - 1)
move r4, r2
add r2, r3, r4 # fib(argv[0] - 1) + fib(argv[0] - 2)
jr r31
_min_caml_start: # main entry point
# main program start
li r2, 4
sw r31, 0(r29)
addi r29, r29, -1
jal fib.10
addi r29, r29, 1
lw r31, 0(r29)
ow r2
ow r3
ow r4
# main program end
break
halt
}
inst_path = InstRom.from_asm(asm).path
dependencies "../src/const/*.vhd", "../src/*.vhd", "../src/rs232c/*.vhd",
"../src/sram/sram_controller.vhd", "../src/sram/sram_mock.vhd", "../src/top/nemips.vhd",
inst_path
generics io_wait: 4
clock :clk
context "fib 4" do
step reset: 1; step reset: 0
wait_step 4000
step is_break: 1
step read_length: "io_length_word", read_data: 3, read_ready: 1
step read_length: "io_length_word", read_data: 2, read_ready: 1
step read_length: "io_length_word", read_data: 1, read_ready: 1
step read_length: "io_length_byte", read_ready: 0
end
end
Raw
io_receiver.rb
require_relative "./asm_helper.rb"
VhdlTestScript.scenario "./tb/nemips_tb.vhd", :branch, :bne do
asm = %q{
.text
main:
li r1, 12
bne r1, r0, bne.1
li r2, 0
j rtn
bne.1:
li r2, 1
rtn:
ow r2
break
halt
}
inst_path = InstRom.from_asm(asm).path
dependencies "../src/const/*.vhd", "../src/*.vhd", "../src/rs232c/*.vhd", "../src/sram/sram_mock.vhd",
"../src/sram/sram_controller.vhd", "../src/debug/*.vhd", "../src/top/nemips.vhd",
inst_path
generics io_wait: 4
clock :clk
context "can branch" do
step reset: 1
step reset: 0
wait_step 400
step read_length: "io_length_word", read_addr: 0, read_data: 1, read_ready: 1
step read_length: "io_length_byte", read_addr: 4, read_ready: 0
end
end
VhdlTestScript.scenario "./tb/nemips_tbq.vhd", :branch, :bltz, :bgez do
asm = %q{
.text
li r4, 12
li r5, 0
li r5, -1
main:
bltz r4, blt.1
li r2, 0
j next.1
blt.1:
li r2, 1
next.1:
ow r2
bltz r5, blt.2
li r2, 0
j next.2
blt.2:
li r2, 1
next.2:
ow r2
bgez r4, bge.1
li r3, 0
j next.3
bge.1:
li r3, 1
next.3:
ow r3
bgez r5, bge.2
li r3, 0
j rtn
bge.2:
li r3, 1
rtn:
ow r3
break
halt
}
inst_path = InstRom.from_asm(asm).path
dependencies "../src/const/*.vhd", "../src/*.vhd", "../src/rs232c/*.vhd", "../src/sram/sram_mock.vhd",
"../src/sram/sram_controller.vhd", "../src/debug/*.vhd", "../src/top/nemips.vhd",
inst_path
generics io_wait: 4
clock :clk
context "bltz, bgez" do
step reset: 1
step reset: 0
wait_step 1600
context "bltz doesn't jump when src(= 12)" do
step read_length: "io_length_word", read_data: 0, read_ready: 1
end
context "bltz doesn't jumps when src(= 0)" do
step read_length: "io_length_word", read_data: 0, read_ready: 1
end
context "bgez jumps when src(= 12)" do
step read_length: "io_length_word", read_data: 1, read_ready: 1
end
context "bgez jump when src(= 0)" do
step read_length: "io_length_word", read_data: 1, read_ready: 1
end
step read_length: "io_length_byte", read_ready: 0
end
end
Raw
nemips_test1.rb
VhdlTestScript.scenario "../src/fsm.vhd" do
ports :opcode, :funct, :reset, :go, :state
clock :clk
dependencies "../src/const/const_state.vhd",
"../src/const/const_opcode.vhd"
testcases = {
i_op_lw: ["state_memadr", "state_mem_read", "state_mem_read_wait", "state_mem_wb"],
i_op_sw: ["state_memadr", "state_mem_write"],
i_op_beq: ["state_branch"],
i_op_bltz: ["state_branch"],
i_op_bgtz: ["state_branch"],
i_op_blez: ["state_branch"],
i_op_bgez: ["state_branch"],
i_op_addi: ["state_alu_imm", "state_alu_imm_wb"],
i_op_addiu: ["state_alu_zimm", "state_alu_imm_wb"],
i_op_break: ["state_break"],
j_op_j: ["state_jmp"],
j_op_jal: ["state_jal"]
}
testcases.each do |k, v|
step 0, 0, 1, 1, "state_fetch"
step 0, 0, 0, 1, "state_decode"
step k.to_s, 0, 0, 0, 1, v[0]
step k.to_s, 0, 0, 0, 1, v[1] if v.size > 1
step k.to_s, 0, 0, 0, 1, v[2] if v.size > 2
step k.to_s, 0, 0, 0, 1, v[3] if v.size > 3
step k.to_s, 0, 0, 0, 1, "state_fetch"
end
r_fun_tests = {
r_fun_add: ["state_alu", "state_alu_wb"],
r_fun_sll: ["state_alu_sft", "state_alu_wb"],
r_fun_mul: ["state_alu"],
r_fun_jr: ["state_jmpr"],
r_fun_jalr: ["state_jalr"],
r_fun_lwx: ["state_memadrx", "state_mem_read", "state_mem_read_wait", "state_mem_wbx"],
r_fun_swx: ["state_memadrx", "state_mem_writex"],
}
r_fun_tests.each do |k, v|
step 0, 0, 1, 1, "state_fetch"
step 0, 0, 0, 1, "state_decode"
step "i_op_r_group", k.to_s, 0, 1, v[0]
step "i_op_r_group", k.to_s, 0, 1, v[1] if v.size > 1
step "i_op_r_group", k.to_s, 0, 1, v[2] if v.size > 2
step "i_op_r_group", k.to_s, 0, 1, v[3] if v.size > 3
step "i_op_r_group", k.to_s, 0, 1, "state_fetch"
end
io_fun_tests = {
io_fun_iw: ["state_io_read_w", "state_io_wb"],
io_fun_ibu: ["state_io_read_b", "state_io_wb"],
io_fun_ihu: ["state_io_read_h", "state_io_wb"],
io_fun_ow: ["state_io_write_w"],
io_fun_obu: ["state_io_write_b"],
io_fun_ohu: ["state_io_write_h"]
}
io_fun_tests.each do |k, v|
step 0, 0, 1, 1, "state_fetch"
step 0, 0, 0, 1, "state_decode"
step "i_op_io", k.to_s, 0, 1, v[0]
step "i_op_io", k.to_s, 0, 1, v[1] if v.size > 1
step "i_op_io", k.to_s, 0, 1, v[2] if v.size > 2
step "i_op_io", k.to_s, 0, 1, "state_fetch"
end
end
Raw
vhd_test1.rb
require_relative "./asm_helper.rb"
VhdlTestScript.scenario "./tb/nemips_tb.vhd", :branch, :bne do
asm = %q{
.text
main:
li r1, 12
bne r1, r0, bne.1
li r2, 0
j rtn
bne.1:
li r2, 1
rtn:
ow r2
break
halt
}
inst_path = InstRom.from_asm(asm).path
dependencies "../src/const/*.vhd", "../src/*.vhd", "../src/rs232c/*.vhd", "../src/sram/sram_mock.vhd",
"../src/sram/sram_controller.vhd", "../src/debug/*.vhd", "../src/top/nemips.vhd",
inst_path
generics io_wait: 4
clock :clk
context "can branch" do
step reset: 1
step reset: 0
wait_step 400
step read_length: "io_length_word", read_addr: 0, read_data: 1, read_ready: 1
step read_length: "io_length_byte", read_addr: 4, read_ready: 0
end
end
VhdlTestScript.scenario "./tb/nemips_tbq.vhd", :branch, :bltz, :bgez do
asm = %q{
.text
li r4, 12
li r5, 0
li r5, -1
main:
bltz r4, blt.1
li r2, 0
j next.1
blt.1:
li r2, 1
next.1:
ow r2
bltz r5, blt.2
li r2, 0
j next.2
blt.2:
li r2, 1
next.2:
ow r2
bgez r4, bge.1
li r3, 0
j next.3
bge.1:
li r3, 1
next.3:
ow r3
bgez r5, bge.2
li r3, 0
j rtn
bge.2:
li r3, 1
rtn:
ow r3
break
halt
}
inst_path = InstRom.from_asm(asm).path
dependencies "../src/const/*.vhd", "../src/*.vhd", "../src/rs232c/*.vhd", "../src/sram/sram_mock.vhd",
"../src/sram/sram_controller.vhd", "../src/debug/*.vhd", "../src/top/nemips.vhd",
inst_path
generics io_wait: 4
clock :clk
context "bltz, bgez" do
step reset: 1
step reset: 0
wait_step 1600
context "bltz doesn't jump when src(= 12)" do
step read_length: "io_length_word", read_data: 0, read_ready: 1
end
context "bltz doesn't jumps when src(= 0)" do
step read_length: "io_length_word", read_data: 0, read_ready: 1
end
context "bgez jumps when src(= 12)" do
step read_length: "io_length_word", read_data: 1, read_ready: 1
end
context "bgez jump when src(= 0)" do
step read_length: "io_length_word", read_data: 1, read_ready: 1
end
step read_length: "io_length_byte", read_ready: 0
end
end
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment