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Kria KV260 Vision AI Starter Kit > Resources > Documentation
- UG1091 - Kria SOM Carrier Card Design Guide (UG1091) (v1.3) Document Type: User Guides Describes the electrical and mechanical requirements to design a carrier card to mate with the Kria™ SOM.
- Associated files:
- Kria K26 SOM XDC file (XTP685)...xtp685-kria-k26-som-xdc.zip
- Kria K26 carrier card XDC file (XTP686)...xtp686-kria-k26-carrier-card-xdc.zip
- 2022-11-01 404 file not found
- Kria K26 trace delay values (XTP688)...xtp688-kria-k26-trace-delay.zip
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working with the kria som in vivado@microzed-chronicles
from Kria_KV_CarrierCard_Rev1.xdc in xtp685-kria-k26-som-xdc.zip
xtp686-kria-k26-carrier-card-xdc.zip 404
set_property IOSTANDARD LVCMOS33 [get_ports "som240_1_a17"]; # Net name HDA11
set_property IOSTANDARD LVCMOS33 [get_ports "som240_1_d20"]; # Net name HDA12
set_property IOSTANDARD LVCMOS33 [get_ports "som240_1_d21"]; # Net name HDA13
set_property IOSTANDARD LVCMOS33 [get_ports "som240_1_d22"]; # Net name HDA14
set_property IOSTANDARD LVCMOS33 [get_ports "som240_1_b20"]; # Net name HDA15
set_property IOSTANDARD LVCMOS33 [get_ports "som240_1_b21"]; # Net name HDA16_CC
set_property IOSTANDARD LVCMOS33 [get_ports "som240_1_b22"]; # Net name HDA17
set_property IOSTANDARD LVCMOS33 [get_ports "som240_1_c22"]; # Net name HDA18
set_property SLEW SLOW [get_ports "som240_1_a17"]; # Net name HDA11
set_property SLEW SLOW [get_ports "som240_1_d20"]; # Net name HDA12
set_property SLEW SLOW [get_ports "som240_1_d21"]; # Net name HDA13
set_property SLEW SLOW [get_ports "som240_1_d22"]; # Net name HDA14
set_property SLEW SLOW [get_ports "som240_1_b20"]; # Net name HDA15
set_property SLEW SLOW [get_ports "som240_1_b21"]; # Net name HDA16_CC
set_property SLEW SLOW [get_ports "som240_1_b22"]; # Net name HDA17
set_property SLEW SLOW [get_ports "som240_1_c22"]; # Net name HDA18
set_property DRIVE 4 [get_ports "som240_1_a17"]; # Net name HDA11
set_property DRIVE 4 [get_ports "som240_1_d20"]; # Net name HDA12
set_property DRIVE 4 [get_ports "som240_1_d21"]; # Net name HDA13
set_property DRIVE 4 [get_ports "som240_1_d22"]; # Net name HDA14
set_property DRIVE 4 [get_ports "som240_1_b20"]; # Net name HDA15
set_property DRIVE 4 [get_ports "som240_1_b21"]; # Net name HDA16_CC
set_property DRIVE 4 [get_ports "som240_1_b22"]; # Net name HDA17
set_property DRIVE 4 [get_ports "som240_1_c22"]; # Net name HDA18
I2S audio Rx and Tx PL interfaces via optional PMOD@kv260_ispMipiRx_vcu_DP/xdc/pin.xdc
pin.xdc
#Digilent PMOD pins
set_property PACKAGE_PIN H12 [get_ports mclk_out_tx]
set_property IOSTANDARD LVCMOS33 [get_ports mclk_out_tx]
set_property SLEW SLOW [get_ports mclk_out_tx]
set_property DRIVE 4 [get_ports mclk_out_tx]
set_property PACKAGE_PIN E10 [get_ports lrclk_tx]
set_property IOSTANDARD LVCMOS33 [get_ports lrclk_tx]
set_property SLEW SLOW [get_ports lrclk_tx]
set_property DRIVE 4 [get_ports lrclk_tx]
set_property PACKAGE_PIN D10 [get_ports sclk_tx]
set_property IOSTANDARD LVCMOS33 [get_ports sclk_tx]
set_property SLEW SLOW [get_ports sclk_tx]
set_property DRIVE 4 [get_ports sclk_tx]
set_property PACKAGE_PIN C11 [get_ports sdata_tx]
set_property IOSTANDARD LVCMOS33 [get_ports sdata_tx]
set_property SLEW SLOW [get_ports sdata_tx]
set_property DRIVE 4 [get_ports sdata_tx]
##input side
set_property PACKAGE_PIN B10 [get_ports mclk_out_rx]
set_property IOSTANDARD LVCMOS33 [get_ports mclk_out_rx]
set_property SLEW SLOW [get_ports mclk_out_rx]
set_property DRIVE 4 [get_ports mclk_out_rx]
set_property PACKAGE_PIN E12 [get_ports lrclk_rx]
set_property IOSTANDARD LVCMOS33 [get_ports lrclk_rx]
set_property SLEW SLOW [get_ports lrclk_rx]
set_property DRIVE 4 [get_ports lrclk_rx]
set_property PACKAGE_PIN D11 [get_ports sclk_rx]
set_property IOSTANDARD LVCMOS33 [get_ports sclk_rx]
set_property SLEW SLOW [get_ports sclk_rx]
set_property DRIVE 4 [get_ports sclk_rx]
set_property PACKAGE_PIN B11 [get_ports sdata_rx]
set_property IOSTANDARD LVCMOS33 [get_ports sdata_rx]
| PmodPin | kv260Pin | Signal Description |
|---|---|---|
| 1 | H12 | D/A MCLK I2S Line Out Converter Master Clock |
| 2 | E10 | D/A LRCK I2S Line Out Converter Word Select |
| 3 | D10 | D/A SCLK I2S Line Out Converter Serial Clock |
| 4 | C11 | D/A SDIN I2S Line Out Converter Serial Data Input |
| 7 | B10 | A/D MCLK I2S Line In Converter Master Clock |
| 8 | E12 | A/D LRCK I2S Line In Converter Word Select |
| 9 | D11 | A/D SCLK I2S Line In Converter Serial Clock |
| 10 | B11 | A/D SDOUT I2S Line In Converter Serial Data Output |
Create port connections@scripts/config_bd.tcl
connect_bd_net -net audio_ss_0_mclk_out_tx [get_bd_ports mclk_out_tx] [get_bd_pins audio_ss_0/mclk_out_tx]
connect_bd_net -net audio_ss_0_lrclk_tx [get_bd_ports lrclk_tx] [get_bd_pins audio_ss_0/lrclk_tx]
connect_bd_net -net audio_ss_0_sclk_tx [get_bd_ports sclk_tx] [get_bd_pins audio_ss_0/sclk_tx]
connect_bd_net -net audio_ss_0_sdata_tx [get_bd_ports sdata_tx] [get_bd_pins audio_ss_0/sdata_tx]
connect_bd_net -net audio_ss_0_mclk_out_rx [get_bd_ports mclk_out_rx] [get_bd_pins audio_ss_0/mclk_out_rx]
connect_bd_net -net audio_ss_0_lrclk_rx [get_bd_ports lrclk_rx] [get_bd_pins audio_ss_0/lrclk_rx]
connect_bd_net -net audio_ss_0_sclk_rx [get_bd_ports sclk_rx] [get_bd_pins audio_ss_0/sclk_rx]
connect_bd_net -net sdata_rx_0_1 [get_bd_ports sdata_rx] [get_bd_pins audio_ss_0/sdata_rx]
and some other resources.
'A17' : { 'net' : 'HDA11', 'dest' : [ 'pmod_1' ], 'v':3.3, 'func': 'pmod', 'io':'LVCMOS33', 'pin':'H12' },
'D20' : { 'net' : 'HDA12', 'dest' : [ 'pmod_3' ], 'v': 3.3, 'cmt' : '', 'io':'LVCMOS33', 'func':'pmod', 'pin':'E10' },
'D21' : { 'net' : 'HDA13', 'dest' : [ 'pmod_5' ], 'v': 3.3, 'cmt' : '', 'io':'LVCMOS33', 'func':'pmod', 'pin':'D10' },
'D22' : { 'net' : 'HDA14', 'dest' : [ 'pmod_7' ], 'v': 3.3, 'cmt' : '', 'io':'LVCMOS33', 'func':'pmod', 'pin':'C11' },
'B20' : { 'net' : 'HDA15', 'dest' : [ 'pmod_2' ], 'v':3.3, 'cmt' : '', 'func': 'pmod', 'io':'LVCMOS33', 'pin':'B10' },
'B21' : { 'net' : 'HDA16_CC', 'dest' : [ 'pmod_4' ], 'v':3.3, 'cmt' : '', 'func': 'pmod', 'io':'LVCMOS33', 'pin':'E12' },
'B22' : { 'net' : 'HDA17', 'dest' : [ 'pmod_6' ], 'v':3.3, 'cmt' : '', 'func': 'pmod', 'io':'LVCMOS33', 'pin':'D11' },
'C22' : { 'net' : 'HDA18', 'dest' : [ 'pmod_8' ], 'v':3.3, 'cmt' : '', 'func': 'pmod', 'io':'LVCMOS33', 'pin':'B11' },