gistfile1.txt

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:31:39 09/10/2013 
// Design Name: 
// Module Name:    count_sec 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module count_sec(
    input clk,
    input rst,
    input ce,
    output [7:0] q
    );
   
reg [7:0] shr;
reg dir;

always @ (posedge clk)
begin
	if (shr[0] == 1) dir <= 1'b0;
	else if (shr[7] == 1) dir <= 1'b1;
	
	if (rst)
		shr <= 8'b111;
	else if (ce)
		case (dir)
			1'b0: shr <= {shr[6:0], 0};
			1'b1: shr <= {0, shr[7:1]};
		endcase
end

assign q = shr;

endmodule