gistfile1.txt

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:30:49 09/10/2013 
// Design Name: 
// Module Name:    rategen 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module rategen(
    input clk,
    input rst,
    output cy
    );

reg [25:0] g;
always @ (posedge clk) begin
  if (rst | cy)
		g <= 0;
	else
		g <= g+1;
end

assign cy = (g == 4999999);
//assign cy = (g == 5);
endmodule