uart.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: M.Yasir
// Create Date:    13:55:43 02/11/2011 

// Design Name: 
// Module Name:    UART_Tx 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module UART_Tx( reset,clk,start,tx_out );
        input reset;
       input clk;
       input start;
       output tx_out;
       //reg load = 1'b1;
       //reg load_data = 1'b0;
       reg load;
       reg load_data;
       reg [15:0]Baud_Rate_Counter;
       reg [7:0]Bit_Counter;
       reg [9:0]Shift_Reg;
       reg [7:0]Data = 8'h55;  // ASCII value of 'U'
       wire Shif_Pulse; //= 1'b0; // shift pulse from comparator
       // FSM
       reg [2:0]CS,NS;
       //reg temp;
       always @(posedge clk)   
       begin
           if(reset == 1'b1)
              CS <= 3'b000;
           else    
              CS <= NS; 
        end
       always @(CS or start or Bit_Counter )   
       begin
          load <= 1'b1;
          load_data <= 1'b0;
          case (CS)
             3'b000 : 
             begin
                 if(start == 1'b1)
                    NS <= 3'b001;
                 else    
                 begin
                     NS <= 3'b000;
                 end
             load <= 1'b1;
             load_data <= 1'b0;
             end
            3'b001 : 
            begin
               NS <= 3'b010;
            load <= 1'b0;
            load_data <= 1'b1;
            end
            3'b010 : 
            begin
               if(Bit_Counter == 8'd10)
                   NS <= 3'b000;
               else 
                  NS <= 3'b010;
               load <= 1'b0;
               load_data <= 1'b0;
            end
            default :
            begin
               NS <= 3'b000;
            load <= 1'b1;
            load_data <= 1'b0;     
          end    
       endcase
    
    end
    
    always @(posedge clk)
    begin//2
    // Baud Rate Counter
    if(reset == 1'b1)
       Baud_Rate_Counter <= 16'h00;
    else if( (load == 1'b1)|( Shif_Pulse == 1'b1 ) ) 
    begin
       Baud_Rate_Counter <= 16'h00;
    end  
    else
       Baud_Rate_Counter <= Baud_Rate_Counter+1;    
         
    end //2
    always @(posedge clk)
    begin//1
       // Bit Counter
       if(reset == 1'b1)
          Bit_Counter <= 8'h00;
       else if(load_data == 1'b1)
          Bit_Counter <= 8'h00;
      else if( Shif_Pulse == 1'b1 ) 
          Bit_Counter <= Bit_Counter+1;
      else 
          Bit_Counter <= Bit_Counter;
    end //1    
    always @(posedge clk)
    begin//2
        // Shift Register
       if((reset == 1'b1)||(load == 1'b1))
           Shift_Reg <= 10'h3FF;
       else if( load_data == 1'b1 ) 
           Shift_Reg <= {1'b1,Data,1'b0};
        else if( Shif_Pulse == 1'b1 ) 
           Shift_Reg <= {1'b1,Shift_Reg[9:1]};
        else 
           Shift_Reg <= Shift_Reg;    
    end //2
    assign Shif_Pulse = ( Baud_Rate_Counter == 434 )? 1'b1 : 1'b0;
    assign tx_out = Shift_Reg[0];
   
endmodule