spi_temp 3. mereslaboron

spi_temp.v

`timescale 1ns / 1ps

module spi_temp(
    input clk,
    input rst,
    output cs,
    output sck,
    input so,
    output [12:0] temp,
    output DBG_CS,
    output DBG_SCK,
    output DBG_SO
    );

reg [23:0] cntr;
reg q;
reg [15:0] shr_16;
reg [12:0] reg_13;

// 24 bites szamlalo
always @ (posedge clk)
  if (rst)
		cntr <= 0;
	else
		cntr <= cntr + 1;
		
// D-FF
always @ (posedge clk)
	if (cntr[23:0] == 7)
		q <= 0;
	else if (cntr[23:0] == 135 || rst)
		q <= 1;
		
// 16 bites balra shift regiszter
always @ (posedge clk)
	if (cntr[2:0] == 3'b011 && ~q)
		shr_16 <= {shr_16[14:0], so};

// 13 bites regiszter
always @ (posedge clk)
	if (q)
		reg_13 <= shr_16[15:3];
		
assign sck = cntr[2];
assign DBG_SCK = sck;
assign cs = q;
assign DBG_CS = cs;
assign DBG_SO = so;

assign temp = reg_13;

endmodule

tb_spi_temp.v

`timescale 1ns / 1ps

module tb_spi_temp;

  // Inputs
	reg clk;
	reg rst;
	wire so;

	// Outputs
	wire cs;
	wire sck;
	wire [12:0] temp;
	wire DBG_CS;
	wire DBG_SCK;
	wire DBG_SO;

	// Instantiate the Unit Under Test (UUT)
	spi_temp uut (
		.clk(clk), 
		.rst(rst), 
		.cs(cs), 
		.sck(sck), 
		.so(so), 
		.temp(temp), 
		.DBG_CS(DBG_CS), 
		.DBG_SCK(DBG_SCK), 
		.DBG_SO(DBG_SO)
	);

	initial begin

	clk = 1;
	rst = 1;
	#102 rst = 0;

	end
	
	always #10 clk = ~clk;
	
	reg [15:0] spi_data = 16'h1234;
	reg [3:0]  bit_cntr = 15;
	wire cs_dl;
	
	assign #2 cs_dl = cs;
	
	always @ (negedge cs)
		bit_cntr <= 15;
	
	always @ (negedge sck)
		if (~cs_dl)
			bit_cntr <= bit_cntr - 1;
			
	assign so = spi_data[bit_cntr];
      
endmodule