Created
October 22, 2013 07:49
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# | |
#Edition of used I/O line: | |
# #NET "" --> NET "Signal_name" | |
# #NET "" --> NET "Signal_name<i>" | |
# | |
# FPGA system clock: | |
#------------------- | |
# Signal FPGA Comment | |
# name pin | |
NET "CLK" LOC = "T9"; #GCLK, 50 MHz | |
# Pushbuttons, switches and LEDs: | |
#--------------------------------- | |
# Signal FPGA Comment | |
# name pin | |
NET "RST" LOC = "M13"; | |
NET "BTN1" LOC = "M14"; | |
#NET "BTN2" LOC = "L13"; | |
#NET "BTN3" LOC = "L14"; | |
# | |
#NET "SW0" LOC = "F12"; | |
#NET "SW1" LOC = "G12"; | |
#NET "SW2" LOC = "H14"; | |
#NET "SW3" LOC = "H13"; | |
NET "SW4" LOC = "J14"; | |
NET "SW5" LOC = "J13"; | |
#NET "SW6" LOC = "K14"; | |
NET "SW7" LOC = "K13"; | |
# | |
#NET "LD0" LOC = "K12"; | |
#NET "LD1" LOC = "P14"; | |
#NET "LD2" LOC = "L12"; | |
#NET "LD3" LOC = "N14"; | |
#NET "LD4" LOC = "P13"; | |
#NET "LD5" LOC = "N12"; | |
#NET "LD6" LOC = "P12"; | |
#NET "LD7" LOC = "P11"; | |
# Seven-Segment LED Displays: | |
#---------------------------- | |
# For lighting both Digit select (ANi) | |
# and Segment signal should be '0' | |
# Signal FPGA Comment | |
# name pin | |
# | |
NET "DIGEN<3>" LOC = "E13"; #Most left digit enable | |
NET "DIGEN<2>" LOC = "F14"; # digit enable | |
NET "DIGEN<1>" LOC = "G14"; # digit enable | |
NET "DIGEN<0>" LOC = "D14"; #Most right digit enable | |
# | |
NET "SEGM<0>" LOC = "E14"; #Segments A | |
NET "SEGM<1>" LOC = "G13"; #Segments B | |
NET "SEGM<2>" LOC = "N15"; #Segments C | |
NET "SEGM<3>" LOC = "P15"; #Segments D | |
NET "SEGM<4>" LOC = "R16"; #Segments E | |
NET "SEGM<5>" LOC = "F13"; #Segments F | |
NET "SEGM<6>" LOC = "N16"; #Segments G | |
NET "DP" LOC = "P16"; #Segments Decimal Point | |
# RS-232 serial port: | |
#-------------------- | |
# Signal FPGA DB9 / connect to | |
# name pin pin / DTE (PC_) signal | |
#NET "RXD" LOC = "T13"; # 2 / PC_RXD | |
#NET "TXD" LOC = "R13"; # 3 / PC_TXD | |
# Spartan-3 Board, Extension connector B1 | |
# used for Logic Analyzer connection | |
#---------------------------------------- | |
# Signal FPGA B1 / Log Analyzer | |
# name pin pin / channel | |
#NET "" LOC = "C15"; # 21 / LA_CLK1 | |
#NET "" LOC = "C10"; # 4 / LA_CLK2 | |
#NET "" LOC = "M11"; # 40 / LA_D0 | |
#NET "" LOC = "N9"; # 38 / LA_D1 | |
#NET "" LOC = "L15"; # 35 / LA_D2 | |
#NET "" LOC = "K15"; # 34 / LA_D3 | |
#NET "" LOC = "K16"; # 33 / LA_D4 | |
#NET "" LOC = "J16"; # 32 / LA_D5 | |
#NET "" LOC = "H16"; # 31 / LA_D6 | |
#NET "" LOC = "H15"; # 30 / LA_D7 | |
#NET "" LOC = "G16"; # 29 / LA_D8 | |
#NET "" LOC = "G15"; # 29 / LA_D9 | |
#NET "" LOC = "F15"; # 27 / LA_D10 | |
#NET "" LOC = "E16"; # 26 / LA_D11 | |
#NET "" LOC = "E15"; # 25 / LA_D12 | |
#NET "" LOC = "D16"; # 24 / LA_D13 | |
#NET "" LOC = "D15"; # 23 / LA_D14 | |
#NET "" LOC = "C16"; # 22 / LA_D15 | |
#NET "" LOC = "R3"; # 20 / LA_D16 | |
#NET "" LOC = "M6"; # 19 / LA_D17 | |
#NET "" LOC = "B16"; # 18 / LA_D18 | |
#NET "" LOC = "N6"; # 17 / LA_D19 | |
#NET "" LOC = "E11"; # 16 / LA_D20 | |
#NET "" LOC = "R7"; # 15 / LA_D21 | |
#NET "" LOC = "D12"; # 14 / LA_D22 | |
#NET "" LOC = "T7"; # 13 / LA_D23 | |
#NET "" LOC = "C12"; # 12 / LA_D24 | |
#NET "" LOC = "R10"; # 11 / LA_D25 | |
#NET "" LOC = "D11"; # 10 / LA_D26 | |
#NET "" LOC = "P10"; # 9 / LA_D27 | |
#NET "" LOC = "C11"; # 8 / LA_D28 | |
#NET "" LOC = "N11"; # 7 / LA_D29 | |
#NET "" LOC = "E10"; # 6 / LA_D30 | |
#NET "" LOC = "T3"; # 5 / LA_D31 | |
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