Verilog

dff.v

module dff(d, clk, q, qb);
  input d, clk;
  output reg q, qb;
always @(posedge clk)
  begin
    q=d;
    qb=~q;
  end
endmodule

Fulladder-1bit.v

// Mạch full adder 1 bit
module halfadd(a, b, sum, carry);
  input a, b;
  output sum, carry;
  
  assign sum = a ^ b;
  assign carry = a & b;
endmodule

module fulladd(Ain, Bin, Cin, SumOut, CarryOut);
  input Ain, Bin, Cin;
  output SumOut, CarryOut;
  wire u0_S, u0_Co, u1_Co;
  
  halfadd u0(.a(Ain), .b(Bin), .sum(u0_S), .carry(u0_Co));
  halfadd u1(.a(u0_S), .b(Cin), .sum(SumOut), .carry(u1_Co));
  
  assign CarryOut = u0_Co | u1_Co;
endmodule

Fulladder-4bit.v

// Mạch full adder 4 bit từ full adder 1 bit
module halfadd(a, b, sum, carry);
  input a, b;
  output sum, carry;
  
  assign sum = a ^ b;
  assign carry = a & b;
endmodule

module fulladd(Ain, Bin, Cin, SumOut, CarryOut);
  input Ain, Bin, Cin;
  output SumOut, CarryOut;
  wire u0_S, u0_Co, u1_Co;
  
  halfadd u0(.a(Ain), .b(Bin), .sum(u0_S), .carry(u0_Co));
  halfadd u1(.a(u0_S), .b(Cin), .sum(SumOut), .carry(u1_Co));
  
  assign CarryOut = u0_Co | u1_Co;
endmodule

module fulladder4(A, B, C, Sum, Cout);
  input [3:0] A, B;
  input C;
  output [3:0] Sum;
  output Cout;
  wire [3:0] s;
  
  fulladd fa0 (.Ain(A[0]), .Bin(B[0]), .Cin(C), .SumOut(Sum[0]), .CarryOut(s[0]));
  fulladd fa1 (.Ain(A[1]), .Bin(B[1]), .Cin(s[0]), .SumOut(Sum[1]), .CarryOut(s[1]));
  fulladd fa2 (.Ain(A[2]), .Bin(B[2]), .Cin(s[1]), .SumOut(Sum[2]), .CarryOut(s[2]));
  fulladd fa3 (.Ain(A[3]), .Bin(B[3]), .Cin(s[2]), .SumOut(Sum[3]), .CarryOut(s[3]));
  
  assign Cout = s[0] | s[1] | s[2];
  
endmodule

Fulladder_4bit_operator_plus.v

// Full adder sử dụng toán tử +

module fulladder_4bit(A, B, Cin, Cout, Sum);
  input [3:0] A, B;
  input Cin;
  output Cout;
  output [3:0] Sum;
  
  assign {Cout, Sum} = A + B + Cin;
   
endmodule

jkff.v

module jkff( j,k,clk,q,qb);
  input j, k, clk;
  output reg q, qb;
  reg temp;
  
always @(posedge clk)
  begin
    if(j!=k) 
      begin
        q=j;
        qb=k;
      end
    else if(j==1'b1 && k==1'b1) 
      begin
        temp=qb;
        qb=q;
        q=temp;
      end
  end
endmodule

mini_alu.v

module alu(A, B, Y, Cin, Cout, ctrl, OE);
  input [7:0] A, B;
  input Cin, OE;
  input [1:0] ctrl;
  
  output [7:0] Y;
  output Cout;
  
  reg [7:0] alu_result;
  reg regC;
  
  assign Y = alu_result;
  assign Cout = regC;
  
  always @(*)
    begin
      if(OE != 1'b0)
        begin
          case(ctrl)
          2'b00:
          {regC, alu_result} = A + B + Cin;
          2'b01:
          {regC, alu_result} = A - B - Cin;
          2'b10:
          alu_result = A & B;
          2'b11:
          alu_result = A | B;
          default:
          {regC, alu_result} = A + B + Cin;
      endcase
        end
      else
        begin
          alu_result = 8'b00000000;
        end
    end
endmodule
 

rsff.v

module srff(s,r,clk,q, qb);
  input s, r, clk;
  output reg q, qb;
  
  always @(posedge clk)
    begin
      if(s!=r)
        begin
          q=s;
          qb=r;
        end
      else if(s==1'b1 && r==1'b1)
        begin
          q=1'b0;
          qb=1'b0;
        end
    end
endmodule

tff.v

module tff (clk, rstn, t, q);
  input t, clk, rstn;
  output reg q;
  
  always @ (posedge clk) begin
    if (!rstn) 
      q <= 0;
    else
      if (t)
          q <= ~q;
      else
          q <= q;
  end
endmodule