Travis Downs travisdowns
MLP vs size for SKL, SKX and Zen2. Insprired by similar charts produced by Andrei at AnandTech.
Size here is in 8-byte units (sorry), so 10^7 means 80,000,000 bytes.
Data is generated using the console version of MemoryLanes:
MLP_CSV=2 MLP_START=1 MLP_STOP=20000 ./testingmlp > out
Charts generated like:
The counters that are the easiest to understand and the best for making ratios that are internally consistent (i.e., always fall in the range 0.0 to 1.0) are the mem_load_retired events, e.g., mem_load_retired.l1_hit and mem_load_retired.l1_miss.
These count at the instruction level, i.e., the universe of retired instructions. For example, could make a reasonable hit ratio from mem_load_retired.l1_hit / mem_inst_retired.all_loads and it will be sane (never indicate a hit rate more than 100%, for example).
That one isn't perfect though, in that it may not reflect the true costs of cache misses and the behavior of the program for at least the following reasons:
- It appplies only to loads and can't catch misses imposed by stores (AFAICT there is no event that counts store misses).
- It only counts loads that retire - a lot of the load activity in your process may be due to loads on a speculative path that never retire. Loads on a speculative path may bring in data that is never used, causing misses and d
In a recent paper, a method is described for calculating the loop-carried dependencies (LCD), if any, of a assembly level loop, as follows:
OSACA can detect LCDs by creating a DAG of a code comprising two back-to-back copies of the loop body. It can thus analyze all possible paths from each vertex of the first kernel section and detect cyclic LCDs if there exists a dependency chain from one instruction form to its corresponding duplicate.
However, I don't think this is sufficient to catch all loop carried dependencies. In particular, you can have a case where a dependency is loop carried, but where no vertex (instruction) in the second iteration depends on the same vertex1 in the first. Rather, some other vertex in the second depends on the first, and in some subsequent iteration, the cycle is completed.
add eax, 1 ; A (deps: E-previous)
|Driver: intel_pstate, governor: performance|
|Vendor ID: GenuineIntel|
|Model name: Intel(R) Core(TM) i3-8121U CPU @ 2.20GHz|
|loading msr kernel module|
|intel_pstate/no_turbo reports that turbo is already disabled|
|Using timer: clock|
|Welcome to uarch-bench (b6d37f9)|
|Supported CPU features: SSE3 PCLMULQDQ VMX EST TM2 SSSE3 FMA CX16 SSE4_1 SSE4_2 MOVBE POPCNT AES AVX RDRND TSC_ADJ BMI1 AVX2 BMI2 ERMS MPX AVX512F AVX512DQ RDSEED ADX AVX512IFMA CLFLUSHOPT INTEL_PT AVX512CD SHA AVX512BW AVX512VL|
|Pinned to CPU 0|
|Median CPU speed: 2.194 GHz|