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View Shuffle.java
package com.example.scrap;
import java.util.Random;
import java.util.function.Consumer;
import java.util.stream.IntStream;
public class Shuffle {
private static final Random r = new Random();
private static final int TRIALS = 100000;
View CNL_stores.txt
Driver: intel_pstate, governor: performance
Vendor ID: GenuineIntel
Model name: Intel(R) Core(TM) i3-8121U CPU @ 2.20GHz
loading msr kernel module
intel_pstate/no_turbo reports that turbo is already disabled
Using timer: clock
Welcome to uarch-bench (b6d37f9)
Supported CPU features: SSE3 PCLMULQDQ VMX EST TM2 SSSE3 FMA CX16 SSE4_1 SSE4_2 MOVBE POPCNT AES AVX RDRND TSC_ADJ BMI1 AVX2 BMI2 ERMS MPX AVX512F AVX512DQ RDSEED ADX AVX512IFMA CLFLUSHOPT INTEL_PT AVX512CD SHA AVX512BW AVX512VL
Pinned to CPU 0
Median CPU speed: 2.194 GHz
View nop-helper.h
// if NOPCOUNT is not defined, use 0 which makes NOPS a no-op
#ifndef NOPCOUNT
#define NOPCOUNT 0
#endif
#define NOPS_HELPER2(N) asm(".rept " #N ";nop;.endr");
#define NOPS_HELPER1(N) NOPS_HELPER2(N)
#define NOPS NOPS_HELPER1(NOPCOUNT)
View parser.java
// Output created by jacc on Sun Apr 07 22:44:19 COT 2019
package travisdowns.github.io;
class RegexParser extends ParserBase implements RegexTokens {
private int yyss = 100;
private int yytok;
private int yysp = 0;
private int[] yyst;
protected int yyerrno = (-1);
View store_fwd_litmus.txt
An example of an allowed outcome not explained solely by StoreLoad reordering (i.e., could not occur on
a system with a total store order and only StoreLoad reordering).
all memory initially zero
thread 1:
mov [x], 1
mov a, [x]
mov b, [y]
View DecodeSim.java
package com.example.scrap;
import java.util.ArrayList;
import java.util.stream.Collectors;
import com.google.common.collect.Iterables;
import com.google.common.collect.Iterators;
import com.google.common.collect.PeekingIterator;
public class DecodeSim {
View hsl_vs_skl_decode.txt
Results of HSW vs SKL decode tests, for different patterns of multi-byte nops.
Tests run with:
./uarch-bench.sh --timer=libpfc --test-name=misc/decode* --extra-events=inst_retired,lsd.uops,idq.dsb_uops,idq.mite_uops --precision=3
Haswell (i7-4770) Results:
** Running group misc : Miscellaneous tests **
Benchmark Cycles INST_R LSD:UO IDQ:DS IDQ:MI
View tinymembench-i7-4770.txt
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
View linux-compile.sh
#!/bin/bash
LINUX=linux-4.19.5
set -e
set -x
if [ -z "$THREADS" ]; then
echo "set THREADS to the number of compilation threads"
exit 1
View lzbench.sh
#!/bin/bash
sudo apt update
sudo apt-get install -y build-essential unzip
git clone https://github.com/inikep/lzbench
cd lzbench
curl http://sun.aei.polsl.pl/~sdeor/corpus/silesia.zip > silesia.zip
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