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Pixhawk4Pro DMA assignments
// auto-generated DMA mapping from dma_resolver.py
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_ADC_ADC1_DMA_CHAN STM32_DMAMUX1_ADC1
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) // shared I2C1_RX,I2C3_TX
#define STM32_I2C_I2C1_RX_DMA_CHAN STM32_DMAMUX1_I2C1_RX
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) // shared SPI4_TX,SPI2_TX,USART3_TX,I2C1_TX,SPI5_TX
#define STM32_I2C_I2C1_TX_DMA_CHAN STM32_DMAMUX1_I2C1_TX
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) // shared SPI4_RX,I2C2_RX,SPI2_RX,SPI5_RX
#define STM32_I2C_I2C2_RX_DMA_CHAN STM32_DMAMUX1_I2C2_RX
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_I2C_I2C2_TX_DMA_CHAN STM32_DMAMUX1_I2C2_TX
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_I2C_I2C3_RX_DMA_CHAN STM32_DMAMUX1_I2C3_RX
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) // shared I2C1_RX,I2C3_TX
#define STM32_I2C_I2C3_TX_DMA_CHAN STM32_DMAMUX1_I2C3_TX
#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2C_I2C4_RX_BDMA_CHAN STM32_DMAMUX2_I2C4_RX
#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C4_TX_BDMA_CHAN STM32_DMAMUX2_I2C4_TX
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI1_RX_DMA_CHAN STM32_DMAMUX1_SPI1_RX
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI1_TX_DMA_CHAN STM32_DMAMUX1_SPI1_TX
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) // shared SPI4_RX,I2C2_RX,SPI2_RX,SPI5_RX
#define STM32_SPI_SPI2_RX_DMA_CHAN STM32_DMAMUX1_SPI2_RX
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) // shared SPI4_TX,SPI2_TX,USART3_TX,I2C1_TX,SPI5_TX
#define STM32_SPI_SPI2_TX_DMA_CHAN STM32_DMAMUX1_SPI2_TX
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) // shared SPI4_RX,I2C2_RX,SPI2_RX,SPI5_RX
#define STM32_SPI_SPI4_RX_DMA_CHAN STM32_DMAMUX1_SPI4_RX
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) // shared SPI4_TX,SPI2_TX,USART3_TX,I2C1_TX,SPI5_TX
#define STM32_SPI_SPI4_TX_DMA_CHAN STM32_DMAMUX1_SPI4_TX
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) // shared SPI4_RX,I2C2_RX,SPI2_RX,SPI5_RX
#define STM32_SPI_SPI5_RX_DMA_CHAN STM32_DMAMUX1_SPI5_RX
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) // shared SPI4_TX,SPI2_TX,USART3_TX,I2C1_TX,SPI5_TX
#define STM32_SPI_SPI5_TX_DMA_CHAN STM32_DMAMUX1_SPI5_TX
#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_SPI_SPI6_RX_BDMA_CHAN STM32_DMAMUX2_SPI6_RX
#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI6_TX_BDMA_CHAN STM32_DMAMUX2_SPI6_TX
#define STM32_TIM_TIM1_UP_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_TIM_TIM1_UP_DMA_CHAN STM32_DMAMUX1_TIM1_UP
#define STM32_TIM_TIM4_UP_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_TIM_TIM4_UP_DMA_CHAN STM32_DMAMUX1_TIM4_UP
#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_UART8_RX_DMA_CHAN STM32_DMAMUX1_UART8_RX
#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART8_TX_DMA_CHAN STM32_DMAMUX1_UART8_TX
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_RX_DMA_CHAN STM32_DMAMUX1_USART2_RX
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_UART_USART2_TX_DMA_CHAN STM32_DMAMUX1_USART2_TX
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_CHAN STM32_DMAMUX1_USART3_RX
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) // shared SPI4_TX,SPI2_TX,USART3_TX,I2C1_TX,SPI5_TX
#define STM32_UART_USART3_TX_DMA_CHAN STM32_DMAMUX1_USART3_TX
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