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trylek/Vector2_3_4.ngendump

Created April 19, 2021 17:59
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NgenDump of the offending method Vector2_3_4TestNative::CreateVector2FromFloats
Raw
Vector2_3_4.ngendump
D:\git\runtime2\.dotnet
****** START compiling Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2 (MethodHash=24bf0f7f)
Generating code for Windows x86
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: No PGO data
OPTIONS: Jit invoked for ngen
IL to import:
IL_0000 02 ldarg.0
IL_0001 03 ldarg.1
IL_0002 28 01 00 00 0a call 0xA000001
IL_0007 0b stloc.1
IL_0008 07 ldloc.1
IL_0009 0a stloc.0
IL_000a dd 01 00 00 00 leave 1 (IL_0010)
IL_000f dc endfinally
IL_0010 06 ldloc.0
IL_0011 2a ret
SIMD Candidate Type System.Numerics.Vector2
Found Vector2
Known type Vector2
'__retBuf' passed in register ecx
Known type Vector2
Known type Vector2
; Initial local variable assignments
;
; V00 RetBuf byref
; V01 arg0 float
; V02 arg1 float
; V03 loc0 simd8
; V04 loc1 simd8
*************** In compInitDebuggingInfo() for Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 5
VarNum LVNum Name Beg End
0: 00h 00h V00 RetBuf 000h 012h
1: 01h 01h V01 arg0 000h 012h
2: 02h 02h V02 arg1 000h 012h
3: 03h 03h V03 loc0 000h 012h
4: 04h 04h V04 loc1 000h 012h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE )
*************** In fgFindBasicBlocks() for Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2
Marked V03 as a single def local
Marked V04 as a single def local
Jump targets:
IL_0000
IL_000f
IL_0010
New Basic Block BB01 [0000] created.
BB01 [000..00F)
New Basic Block BB02 [0001] created.
BB02 [00F..010)
New Basic Block BB03 [0002] created.
BB03 [010..012)
EH clause #0:
Flags: 0x2 (finally)
TryOffset: 0x0
TryLength: 0xf
HandlerOffset: 0xf
HandlerLength: 0x1
ClassToken: 0x0
*************** After fgFindBasicBlocks() has created the EH table
*************** Exception Handling table
index nest, eTry, eHnd
0 :: 0 - Try at BB01..BB01 [000..00F), Finally at BB02..BB02 [00F..010)
*************** In fgNormalizeEH()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 0 1 [000..00F)-> BB03 (leave ) T0 try { } keep try
BB02 [0001] 1 0 1 [00F..010) (finret) H0 finally { } keep
BB03 [0002] 1 1 [010..012) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index nest, eTry, eHnd
0 :: 0 - Try at BB01..BB01 [000..00F), Finally at BB02..BB02 [00F..010)
No EH normalization performed.
INLINER: during 'prejit' result 'failed this callee' reason 'has exception handling' for 'n/a' calling 'Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2'
INLINER: Marking Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2 as NOINLINE because of has exception handling
INLINER: during 'prejit' result 'failed this callee' reason 'has exception handling'
IL Code Size,Instr 18, 10, Basic Block count 3, Local Variable Num,Ref count 5, 6 for method Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2
OPTIONS: opts.MinOpts() == false
Basic block list for 'Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 0 1 [000..00F)-> BB03 (leave ) T0 try { } keep try
BB02 [0001] 1 0 1 [00F..010) (finret) H0 finally { } keep
BB03 [0002] 1 1 [010..012) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
*************** Starting PHASE Profile incorporation
BBOPT set, but no profile data available (hr=80004001)
*************** Finishing PHASE Profile incorporation [no changes]
*************** Starting PHASE Importation
*************** In impImport() for Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2
impImportBlockPending for BB01
impImportBlockPending for BB02
Importing BB01 (PC=000) of 'Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldarg.1
[ 2] 2 (0x002) call 0A000001
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 8
Inline a CALLI PINVOKE call from method Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2' calling 'Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2'
INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result'
lvaGrabTemp returning 5 (V05 loc2) called for Return value temp for multireg return.
Known type Vector2
STMT00000 (IL 0x000... ???)
[000005] -AC-G------- * ASG simd8 (copy)
[000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
[000002] --C-G------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
[000001] ------------ arg0 +--* LCL_VAR float V02 arg1
[000000] ------------ arg1 \--* LCL_VAR float V01 arg0
[ 1] 7 (0x007) stloc.1
STMT00001 (IL ???... ???)
[000009] -A---------- * ASG simd8 (copy)
[000007] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[000006] -------N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
[ 0] 8 (0x008) ldloc.1
[ 1] 9 (0x009) stloc.0
STMT00002 (IL 0x008... ???)
[000013] -A---------- * ASG simd8 (copy)
[000011] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[ 0] 10 (0x00a) leave 0010
Before import CEE_LEAVE:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 0 1 [000..00F)-> BB03 (leave ) T0 try { } keep try
BB02 [0001] 1 0 1 [00F..010) (finret) H0 finally { } keep
BB03 [0002] 1 1 [010..012) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index nest, eTry, eHnd
0 :: 0 - Try at BB01..BB01 [000..00F), Finally at BB02..BB02 [00F..010)
impImportLeave - jumping out of a finally-protected try, convert block to BBJ_CALLFINALLY block BB01 [0000]
New Basic Block BB04 [0003] created.
EH#0: New last block of try: BB04
impImportLeave - jumping out of a finally-protected try, created step (BBJ_ALWAYS) block BB04 [0003]
fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB04, jumpBlk=BB00, runRarely=false)
fgNewBBinRegion(jumpKind=6, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB04
New Basic Block BB05 [0004] created.
impImportLeave - finalStep block required (encFinallies(1) > 0), new block BB05 [0004]
impImportBlockPending for BB03
After import CEE_LEAVE:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 0 1 [000..00F)-> BB02 (callf ) T0 try { keep try
BB04 [0003] 0 0 1 [???..???)-> BB05 (ALWAYS) T0 } i internal KEEP
BB05 [0004] 0 1 [???..???)-> BB03 (ALWAYS) i internal KEEP
BB02 [0001] 1 0 1 [00F..010) (finret) H0 finally { } keep
BB03 [0002] 1 1 [010..012) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index nest, eTry, eHnd
0 :: 0 - Try at BB01..BB04 [000..00F), Finally at BB02..BB02 [00F..010)
impImportBlockPending for BB02
Importing BB03 (PC=016) of 'Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2'
[ 0] 16 (0x010) ldloc.0
[ 1] 17 (0x011) ret
STMT00004 (IL 0x010... ???)
[000018] -A---------- * ASG simd8 (copy)
[000017] ------------ +--* IND simd8
[000016] ------------ | \--* LCL_VAR byref V00 RetBuf
[000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
STMT00005 (IL ???... ???)
[000019] ------------ * RETURN void
Importing BB02 (PC=015) of 'Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2'
[ 0] 15 (0x00f) endfinally
STMT00006 (IL 0x00F... ???)
[000020] ------------ * RETFILT void
After impImport() added block for try,catch,finally
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 0 1 [000..00F)-> BB02 (callf ) T0 try { keep i try
BB04 [0003] 0 0 1 [???..???)-> BB05 (ALWAYS) T0 } i internal KEEP
BB05 [0004] 0 1 [???..???)-> BB03 (ALWAYS) i internal KEEP
BB02 [0001] 1 0 1 [00F..010) (finret) H0 finally { } keep i
BB03 [0002] 1 1 [010..012) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Importation
Trees after Importation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 0 1 [000..00F)-> BB02 (callf ) T0 try { keep i try
BB04 [0003] 0 0 1 [???..???)-> BB05 (ALWAYS) T0 } i internal KEEP
BB05 [0004] 0 1 [???..???)-> BB03 (ALWAYS) i internal KEEP
BB02 [0001] 1 0 1 [00F..010) (finret) H0 finally { } keep i
BB03 [0002] 1 1 [010..012) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB02 (callf), preds={} succs={BB02}
***** BB01
STMT00000 (IL 0x000...0x007)
[000005] -AC-G------- * ASG simd8 (copy)
[000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
[000002] --C-G------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
[000001] ------------ arg0 +--* LCL_VAR float V02 arg1
[000000] ------------ arg1 \--* LCL_VAR float V01 arg0
***** BB01
STMT00001 (IL ???... ???)
[000009] -A---------- * ASG simd8 (copy)
[000007] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[000006] -------N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
***** BB01
STMT00002 (IL 0x008...0x009)
[000013] -A---------- * ASG simd8 (copy)
[000011] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
------------ BB04 [???..???) -> BB05 (ALWAYS), preds={} succs={BB05}
------------ BB05 [???..???) -> BB03 (ALWAYS), preds={} succs={BB03}
***** BB05
STMT00003 (IL ???... ???)
[000014] ------------ * END_LFIN void endNstLvl=0
------------ BB02 [00F..010) (finret), preds={} succs={BB04}
***** BB02
STMT00006 (IL 0x00F...0x00F)
[000020] ------------ * RETFILT void
------------ BB03 [010..012) (return), preds={} succs={}
***** BB03
STMT00004 (IL 0x010...0x011)
[000018] -A---------- * ASG simd8 (copy)
[000017] ------------ +--* IND simd8
[000016] ------------ | \--* LCL_VAR byref V00 RetBuf
[000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
***** BB03
STMT00005 (IL ???... ???)
[000019] ------------ * RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Indirect call transform
-- no candidates to transform
*************** Finishing PHASE Indirect call transform [no changes]
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import
*************** Starting PHASE Morph - Init
New BlockSet epoch 1, # of blocks (including unused BB00): 6, bitset array size: 1 (short)
*************** In fgRemoveEmptyBlocks
*************** Finishing PHASE Morph - Init
*************** In fgDebugCheckBBlist
*************** Starting PHASE Morph - Inlining
**************** Inline Tree
Inlines into 06000006 [via DefaultPolicy] Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2
[0 IL=0002 TR=000002 00000000] [FAILED: noinline per IL/cached result] Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2
Budget: initialTime=114, finalTime=114, initialBudget=1140, currentBudget=1140
Budget: initialSize=541, finalSize=541
*************** Finishing PHASE Morph - Inlining [no changes]
*************** Starting PHASE Allocate Objects
no newobjs in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
New Basic Block BB06 [0005] created.
New scratch BB06
fgNewBBinRegion(jumpKind=4, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=true): inserting after BB03
New Basic Block BB07 [0006] created.
newReturnBB [BB07] created
mergeReturns statement tree [000021] added to genReturnBB BB07 [0006]
[000021] ------------ * RETURN void
lvaGrabTemp returning 6 (V06 tmp1) (a long lifetime temp) called for Pinvoke FrameVar.
Local V06 should not be enregistered because: it is address exposed
*************** After fgAddInternal()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB06 [0005] 1 1 [???..???) keep i internal
BB01 [0000] 1 0 1 [000..00F)-> BB02 (callf ) T0 try { keep i try
BB04 [0003] 0 0 1 [???..???)-> BB05 (ALWAYS) T0 } i internal KEEP
BB05 [0004] 0 1 [???..???)-> BB03 (ALWAYS) i internal KEEP
BB02 [0001] 1 0 1 [00F..010) (finret) H0 finally { } keep i
BB03 [0002] 1 1 [010..012) (return) i
BB07 [0006] 1 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index nest, eTry, eHnd
0 :: 0 - Try at BB01..BB04 [000..00F), Finally at BB02..BB02 [00F..010)
*************** Finishing PHASE Morph - Add internal blocks
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
*************** Before fgRemoveEmptyTry()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB06 [0005] 1 1 [???..???) keep i internal
BB01 [0000] 1 0 1 [000..00F)-> BB02 (callf ) T0 try { keep i try
BB04 [0003] 0 0 1 [???..???)-> BB05 (ALWAYS) T0 } i internal KEEP
BB05 [0004] 0 1 [???..???)-> BB03 (ALWAYS) i internal KEEP
BB02 [0001] 1 0 1 [00F..010) (finret) H0 finally { } keep i
BB03 [0002] 1 1 [010..012) (return) i
BB07 [0006] 1 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index nest, eTry, eHnd
0 :: 0 - Try at BB01..BB04 [000..00F), Finally at BB02..BB02 [00F..010)
EH#0 first try block BB01 not empty; skipping.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty finally
*************** Before fgRemoveEmptyFinally()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB06 [0005] 1 1 [???..???) keep i internal
BB01 [0000] 1 0 1 [000..00F)-> BB02 (callf ) T0 try { keep i try
BB04 [0003] 0 0 1 [???..???)-> BB05 (ALWAYS) T0 } i internal KEEP
BB05 [0004] 0 1 [???..???)-> BB03 (ALWAYS) i internal KEEP
BB02 [0001] 1 0 1 [00F..010) (finret) H0 finally { } keep i
BB03 [0002] 1 1 [010..012) (return) i
BB07 [0006] 1 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index nest, eTry, eHnd
0 :: 0 - Try at BB01..BB04 [000..00F), Finally at BB02..BB02 [00F..010)
EH#0 has empty finally, removing the region.
Modifying callfinally BB01 leave BB04 finally BB02 continuation BB05
so that BB01 jumps to BB05; then remove BB04
fgRemoveBlock BB04
Removing unreachable BB04
EH#0: New last block of try: BB01
Removing statement STMT00003 (IL ???... ???)
[000014] ------------ * END_LFIN void endNstLvl=0
in BB05 as useless:
BB05 becomes empty
Remove now-unreachable handler BB02
fgRemoveBlock BB02
Removing unreachable BB02
Removing statement STMT00006 (IL 0x00F...0x00F)
[000020] ------------ * RETFILT void
in BB02 as useless:
BB02 becomes empty
EH#0: New last block of handler: BB05
fgRemoveEmptyFinally() removed 1 try-finally clauses from 1 finallys
*************** After fgRemoveEmptyFinally()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB06 [0005] 1 1 [???..???) keep i internal
BB01 [0000] 1 1 [000..00F) keep i
BB05 [0004] 0 1 [???..???) i internal
BB03 [0002] 1 1 [010..012) (return) i
BB07 [0006] 1 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Remove empty finally
Trees after Remove empty finally
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB06 [0005] 1 1 [???..???) keep i internal
BB01 [0000] 1 1 [000..00F) keep i
BB05 [0004] 0 1 [???..???) i internal
BB03 [0002] 1 1 [010..012) (return) i
BB07 [0006] 1 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB06 [???..???), preds={} succs={BB01}
------------ BB01 [000..00F), preds={} succs={BB05}
***** BB01
STMT00000 (IL 0x000...0x007)
[000005] -AC-G------- * ASG simd8 (copy)
[000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
[000002] --C-G------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
[000001] ------------ arg0 +--* LCL_VAR float V02 arg1
[000000] ------------ arg1 \--* LCL_VAR float V01 arg0
***** BB01
STMT00001 (IL ???... ???)
[000009] -A---------- * ASG simd8 (copy)
[000007] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[000006] -------N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
***** BB01
STMT00002 (IL 0x008...0x009)
[000013] -A---------- * ASG simd8 (copy)
[000011] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
------------ BB05 [???..???), preds={} succs={BB03}
------------ BB03 [010..012) (return), preds={} succs={}
***** BB03
STMT00004 (IL 0x010...0x011)
[000018] -A---------- * ASG simd8 (copy)
[000017] ------------ +--* IND simd8
[000016] ------------ | \--* LCL_VAR byref V00 RetBuf
[000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
***** BB03
STMT00005 (IL ???... ???)
[000019] ------------ * RETURN void
------------ BB07 [???..???) (return), preds={} succs={}
***** BB07
STMT00007 (IL ???... ???)
[000021] ------------ * RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Compute preds
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB06 [0005] 1 1 [???..???) keep i internal
BB01 [0000] 1 1 [000..00F) keep i
BB05 [0004] 0 1 [???..???) i internal
BB03 [0002] 1 1 [010..012) (return) i
BB07 [0006] 1 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB06 to BB01
Renumber BB01 to BB02
Renumber BB05 to BB03
Renumber BB03 to BB04
Renumber BB07 to BB05
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 1 [000..00F) keep i
BB03 [0004] 0 1 [???..???) i internal
BB04 [0002] 1 1 [010..012) (return) i
BB05 [0006] 1 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 2, # of blocks (including unused BB00): 6, bitset array size: 1 (short)
*************** In fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 1 [000..00F) keep i
BB03 [0004] 0 1 [???..???) i internal
BB04 [0002] 1 1 [010..012) (return) i
BB05 [0006] 1 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38]
Setting edge weights for BB02 -> BB03 to [0 .. 3.402823e+38]
Setting edge weights for BB03 -> BB04 to [0 .. 3.402823e+38]
*************** After fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..00F) keep i
BB03 [0004] 1 BB02 1 [???..???) i internal
BB04 [0002] 1 BB03 1 [010..012) (return) i
BB05 [0006] 0 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Compute preds
*************** Starting PHASE Merge throw blocks
*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.
*************** Finishing PHASE Merge throw blocks [no changes]
*************** Starting PHASE Update flow graph early pass
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..00F) keep i
BB03 [0004] 1 BB02 1 [???..???) i internal
BB04 [0002] 1 BB03 1 [010..012) (return) i
BB05 [0006] 0 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
Compacting blocks BB02 and BB03:
*************** In fgDebugCheckBBlist
Compacting blocks BB02 and BB04:
*************** In fgDebugCheckBBlist
After updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) (return) keep i
BB05 [0006] 0 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Update flow graph early pass
*************** Starting PHASE Morph - Promote Structs
*************** In fgPromoteStructs()
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 RetBuf byref
; V01 arg0 float
; V02 arg1 float
; V03 loc0 simd8
; V04 loc1 simd8
; V05 loc2 simd8 multireg-ret "Return value temp for multireg return"
; V06 PInvokeFrame blk do-not-enreg[X] addr-exposed "Pinvoke FrameVar"
lvaTable after fgPromoteStructs
; Initial local variable assignments
;
; V00 RetBuf byref
; V01 arg0 float
; V02 arg1 float
; V03 loc0 simd8
; V04 loc1 simd8
; V05 loc2 simd8 multireg-ret "Return value temp for multireg return"
; V06 PInvokeFrame blk do-not-enreg[X] addr-exposed "Pinvoke FrameVar"
*************** Finishing PHASE Morph - Promote Structs
*************** Starting PHASE Morph - Structs/AddrExp
*************** In fgMarkAddressExposedLocals()
LocalAddressVisitor visiting statement:
STMT00000 (IL 0x000...0x007)
[000005] -AC-G------- * ASG simd8 (copy)
[000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
[000002] --C-G------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
[000001] ------------ arg0 +--* LCL_VAR float V02 arg1
[000000] ------------ arg1 \--* LCL_VAR float V01 arg0
LocalAddressVisitor visiting statement:
STMT00001 (IL ???... ???)
[000009] -A---------- * ASG simd8 (copy)
[000007] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[000006] -------N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
LocalAddressVisitor visiting statement:
STMT00002 (IL 0x008...0x009)
[000013] -A---------- * ASG simd8 (copy)
[000011] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
LocalAddressVisitor visiting statement:
STMT00004 (IL 0x010...0x011)
[000018] -A---------- * ASG simd8 (copy)
[000017] ------------ +--* IND simd8
[000016] ------------ | \--* LCL_VAR byref V00 RetBuf
[000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
LocalAddressVisitor visiting statement:
STMT00005 (IL ???... ???)
[000019] ------------ * RETURN void
LocalAddressVisitor visiting statement:
STMT00007 (IL ???... ???)
[000021] ------------ * RETURN void
*************** Finishing PHASE Morph - Structs/AddrExp
*************** Starting PHASE Morph - ByRefs
*************** Finishing PHASE Morph - ByRefs
*************** Starting PHASE Morph - Global
*************** In fgMorphBlocks()
Morphing BB01 of 'Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2'
Morphing BB02 of 'Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2'
fgMorphTree BB02, STMT00000 (before)
[000005] -AC-G------- * ASG simd8 (copy)
[000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
[000002] --C-G------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
[000001] ------------ arg0 +--* LCL_VAR float V02 arg1
[000000] ------------ arg1 \--* LCL_VAR float V01 arg0
Initializing arg info for 2.CALL:
ArgTable for 2.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 1.LCL_VAR float (By ref), numSlots=1, slotNum=0, byteSize=4, byteOffset=0, byteAlignment=4]
fgArgTabEntry[arg 1 0.LCL_VAR float (By ref), numSlots=1, slotNum=1, byteSize=4, byteOffset=4, byteAlignment=4]
Morphing args for 2.CALL:
ArgTable for 2.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 1.LCL_VAR float (By ref), numSlots=1, slotNum=0, byteSize=4, byteOffset=0, byteAlignment=4]
fgArgTabEntry[arg 1 0.LCL_VAR float (By ref), numSlots=1, slotNum=1, byteSize=4, byteOffset=4, byteAlignment=4]
fgMorphCopyBlock:
not morphing a multireg call return
fgMorphTree BB02, STMT00001 (before)
[000009] -A---------- * ASG simd8 (copy)
[000007] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[000006] -------N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
fgMorphCopyBlock:
fgMorphBlkNode for dst tree, before:
[000007] D----+-N---- * LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
fgMorphBlkNode after:
[000007] D----+-N---- * LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
fgMorphBlkNode for src tree, before:
[000006] -----+-N---- * LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
fgMorphBlkNode after:
[000006] -----+-N---- * LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
fgMorphOneAsgBlock (after):
[000009] -A---------- * ASG simd8 (copy)
[000007] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[000006] -----+-N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
using oneAsgTree.
fgMorphCopyBlock (after):
[000009] -A---------- * ASG simd8 (copy)
[000007] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[000006] -----+-N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
GenTreeNode creates assertion:
[000009] -A---------- * ASG simd8 (copy)
In BB02 New Local Copy Assertion: V04 == V05 index=#01, mask=0000000000000001
fgMorphTree BB02, STMT00002 (before)
[000013] -A---------- * ASG simd8 (copy)
[000011] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
Assertion prop in BB02:
Copy Assertion: V04 == V05 index=#01, mask=0000000000000001
[000010] ------------ * LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
fgMorphCopyBlock:
fgMorphBlkNode for dst tree, before:
[000011] D----+-N---- * LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
fgMorphBlkNode after:
[000011] D----+-N---- * LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
fgMorphBlkNode for src tree, before:
[000010] -----+------ * LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
fgMorphBlkNode after:
[000010] -----+------ * LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
fgMorphOneAsgBlock (after):
[000013] -A---------- * ASG simd8 (copy)
[000011] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
using oneAsgTree.
fgMorphCopyBlock (after):
[000013] -A---------- * ASG simd8 (copy)
[000011] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
GenTreeNode creates assertion:
[000013] -A---------- * ASG simd8 (copy)
In BB02 New Local Copy Assertion: V03 == V05 index=#02, mask=0000000000000002
fgMorphTree BB02, STMT00002 (after)
[000013] -A---+------ * ASG simd8 (copy)
[000011] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
fgMorphTree BB02, STMT00004 (before)
[000018] -A---------- * ASG simd8 (copy)
[000017] ------------ +--* IND simd8
[000016] ------------ | \--* LCL_VAR byref V00 RetBuf
[000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
Assertion prop in BB02:
Copy Assertion: V03 == V05 index=#02, mask=0000000000000002
[000015] ------------ * LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
fgMorphCopyBlock:
fgMorphBlkNode for dst tree, before:
[000017] ---X-+-N---- * IND simd8
[000016] -----+------ \--* LCL_VAR byref V00 RetBuf
fgMorphBlkNode after:
[000017] ---X-+-N---- * IND simd8
[000016] -----+------ \--* LCL_VAR byref V00 RetBuf
fgMorphBlkNode for src tree, before:
[000015] -----+------ * LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
fgMorphBlkNode after:
[000015] -----+------ * LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
fgMorphOneAsgBlock (after):
[000018] -A-XG------- * ASG simd8 (copy)
[000017] *--XG+-N---- +--* IND simd8
[000016] -----+------ | \--* LCL_VAR byref V00 RetBuf
[000015] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
using oneAsgTree.
fgMorphCopyBlock (after):
[000018] -A-XG------- * ASG simd8 (copy)
[000017] *--XG+-N---- +--* IND simd8
[000016] -----+------ | \--* LCL_VAR byref V00 RetBuf
[000015] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
fgMorphTree BB02, STMT00004 (after)
[000018] -A-XG+------ * ASG simd8 (copy)
[000017] *--XG+-N---- +--* IND simd8
[000016] -----+------ | \--* LCL_VAR byref V00 RetBuf
[000015] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
fgMorphTree BB02, STMT00005 (before)
[000019] ------------ * RETURN void
Setting edge weights for BB02 -> BB05 to [0 .. 3.402823e+38]
Removing statement STMT00005 (IL ???... ???)
[000019] -----+------ * RETURN void
in BB02 as useless:
Update BB02 to jump to common return block.
BB02 [0000] 1 BB01 1 [000..012)-> BB05 (always) keep i hascall gcsafe
Morphing BB05 of 'Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2'
fgMorphTree BB05, STMT00007 (before)
[000021] ------------ * RETURN void
*************** Finishing PHASE Morph - Global
Trees after Morph - Global
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012)-> BB05 (always) keep i hascall gcsafe
BB05 [0006] 1 BB02 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012) -> BB05 (always), preds={BB01} succs={BB05}
***** BB02
STMT00000 (IL 0x000...0x007)
[000005] -ACXG+------ * ASG simd8 (copy)
[000003] M----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
[000002] --CXG+------ \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
[000001] -----+------ arg0 +--* LCL_VAR float V02 arg1
[000000] -----+------ arg1 \--* LCL_VAR float V01 arg0
***** BB02
STMT00001 (IL ???... ???)
[000009] -A---+------ * ASG simd8 (copy)
[000007] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[000006] -----+-N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
***** BB02
STMT00002 (IL 0x008...0x009)
[000013] -A---+------ * ASG simd8 (copy)
[000011] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
***** BB02
STMT00004 (IL 0x010...0x011)
[000018] -A-XG+------ * ASG simd8 (copy)
[000017] *--XG+-N---- +--* IND simd8
[000016] -----+------ | \--* LCL_VAR byref V00 RetBuf
[000015] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
------------ BB05 [???..???) (return), preds={BB02} succs={}
***** BB05
STMT00007 (IL ???... ???)
[000021] -----+------ * RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie
*************** Starting PHASE Compute edge weights (1, false)
*************** In fgComputeBlockAndEdgeWeights()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012)-> BB05 (always) keep i hascall gcsafe
BB05 [0006] 1 BB02 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
-- not optimizing or no profile data, so not computing edge weights
*************** Finishing PHASE Compute edge weights (1, false)
*************** Starting PHASE Invert loops
*************** Finishing PHASE Invert loops
Trees after Invert loops
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012)-> BB05 (always) keep i hascall gcsafe
BB05 [0006] 1 BB02 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012) -> BB05 (always), preds={BB01} succs={BB05}
***** BB02
STMT00000 (IL 0x000...0x007)
[000005] -ACXG+------ * ASG simd8 (copy)
[000003] M----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
[000002] --CXG+------ \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
[000001] -----+------ arg0 +--* LCL_VAR float V02 arg1
[000000] -----+------ arg1 \--* LCL_VAR float V01 arg0
***** BB02
STMT00001 (IL ???... ???)
[000009] -A---+------ * ASG simd8 (copy)
[000007] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[000006] -----+-N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
***** BB02
STMT00002 (IL 0x008...0x009)
[000013] -A---+------ * ASG simd8 (copy)
[000011] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
***** BB02
STMT00004 (IL 0x010...0x011)
[000018] -A-XG+------ * ASG simd8 (copy)
[000017] *--XG+-N---- +--* IND simd8
[000016] -----+------ | \--* LCL_VAR byref V00 RetBuf
[000015] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
------------ BB05 [???..???) (return), preds={BB02} succs={}
***** BB05
STMT00007 (IL ???... ???)
[000021] -----+------ * RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Optimize layout
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012)-> BB05 (always) keep i hascall gcsafe
BB05 [0006] 1 BB02 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
Removing unconditional jump to next block (BB02 -> BB05) (converted BB02 to fall-through)
After updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB05 [0006] 1 BB02 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** In fgRelocateEHRegions()
*************** In fgReorderBlocks()
Initial BasicBlocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB05 [0006] 1 BB02 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB05 [0006] 1 BB02 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize layout
Trees after Optimize layout
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB05 [0006] 1 BB02 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB05}
***** BB02
STMT00000 (IL 0x000...0x007)
[000005] -ACXG+------ * ASG simd8 (copy)
[000003] M----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
[000002] --CXG+------ \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
[000001] -----+------ arg0 +--* LCL_VAR float V02 arg1
[000000] -----+------ arg1 \--* LCL_VAR float V01 arg0
***** BB02
STMT00001 (IL ???... ???)
[000009] -A---+------ * ASG simd8 (copy)
[000007] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[000006] -----+-N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
***** BB02
STMT00002 (IL 0x008...0x009)
[000013] -A---+------ * ASG simd8 (copy)
[000011] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
***** BB02
STMT00004 (IL 0x010...0x011)
[000018] -A-XG+------ * ASG simd8 (copy)
[000017] *--XG+-N---- +--* IND simd8
[000016] -----+------ | \--* LCL_VAR byref V00 RetBuf
[000015] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
------------ BB05 [???..???) (return), preds={BB02} succs={}
***** BB05
STMT00007 (IL ???... ???)
[000021] -----+------ * RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Compute blocks reachability
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB05 [0006] 1 BB02 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB05 to BB03
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 3, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
BB02 : BB01 BB02
BB03 : BB01 BB02 BB03
After computing reachability:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
BB02: BB02 BB01
BB03: BB03 BB02 BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB02
BB02 : BB03
After numbering the dominator tree:
BB01: pre=01, post=03
BB02: pre=02, post=02
BB03: pre=03, post=01
*************** Finishing PHASE Compute blocks reachability
*************** Starting PHASE Find loops
*************** In optFindLoops()
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Find loops
Trees after Find loops
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
***** BB02
STMT00000 (IL 0x000...0x007)
[000005] -ACXG+------ * ASG simd8 (copy)
[000003] M----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
[000002] --CXG+------ \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
[000001] -----+------ arg0 +--* LCL_VAR float V02 arg1
[000000] -----+------ arg1 \--* LCL_VAR float V01 arg0
***** BB02
STMT00001 (IL ???... ???)
[000009] -A---+------ * ASG simd8 (copy)
[000007] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[000006] -----+-N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
***** BB02
STMT00002 (IL 0x008...0x009)
[000013] -A---+------ * ASG simd8 (copy)
[000011] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
***** BB02
STMT00004 (IL 0x010...0x011)
[000018] -A-XG+------ * ASG simd8 (copy)
[000017] *--XG+-N---- +--* IND simd8
[000016] -----+------ | \--* LCL_VAR byref V00 RetBuf
[000015] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
------------ BB03 [???..???) (return), preds={BB02} succs={}
***** BB03
STMT00007 (IL ???... ???)
[000021] -----+------ * RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Clone loops
*************** In optCloneLoops()
No loops to clone
*************** Finishing PHASE Clone loops
*************** Starting PHASE Unroll loops
*************** Finishing PHASE Unroll loops
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
lvaGrabTemp returning 7 (V07 tmp2) (a long lifetime temp) called for lvaShadowSPslotsVar.
Local V07 should not be enregistered because: it is address exposed
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
*** marking local variables in block BB01 (weight=1 )
*** marking local variables in block BB02 (weight=1 )
STMT00000 (IL 0x000...0x007)
[000005] -ACXG+------ * ASG simd8 (copy)
[000003] M----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
[000002] --CXG+------ \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
[000001] -----+------ arg0 +--* LCL_VAR float V02 arg1
[000000] -----+------ arg1 \--* LCL_VAR float V01 arg0
New refCnts for V05: refCnt = 1, refCntWtd = 2
EH Var V05 needs explicit zero init. Disqualified as a register candidate.
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
STMT00001 (IL ???... ???)
[000009] -A---+------ * ASG simd8 (copy)
[000007] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
[000006] -----+-N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
New refCnts for V04: refCnt = 1, refCntWtd = 1
Marking EH Var V04 as a register candidate.
New refCnts for V05: refCnt = 2, refCntWtd = 4
STMT00002 (IL 0x008...0x009)
[000013] -A---+------ * ASG simd8 (copy)
[000011] D----+-N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
[000010] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
New refCnts for V03: refCnt = 1, refCntWtd = 1
Marking EH Var V03 as a register candidate.
New refCnts for V05: refCnt = 3, refCntWtd = 6
STMT00004 (IL 0x010...0x011)
[000018] -A-XG+------ * ASG simd8 (copy)
[000017] *--XG+-N---- +--* IND simd8
[000016] -----+------ | \--* LCL_VAR byref V00 RetBuf
[000015] -----+------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V05: refCnt = 4, refCntWtd = 8
*** marking local variables in block BB03 (weight=1 )
STMT00007 (IL ???... ???)
[000021] -----+------ * RETURN void
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
*************** In optAddCopies()
*************** Finishing PHASE Mark local vars
*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize bools
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 5 tree nodes
*************** Finishing PHASE Set block order
Trees before Build SSA representation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
***** BB02
STMT00000 (IL 0x000...0x007)
N005 ( 30, 12) [000005] -ACXG---R--- * ASG simd8 (copy)
N004 ( 3, 2) [000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
N003 ( 26, 9) [000002] --CXG------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
N001 ( 3, 2) [000001] ------------ arg0 +--* LCL_VAR float V02 arg1
N002 ( 3, 2) [000000] ------------ arg1 \--* LCL_VAR float V01 arg0
***** BB02
STMT00001 (IL ???... ???)
N003 ( 7, 5) [000009] -A------R--- * ASG simd8 (copy)
N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
N001 ( 3, 2) [000006] -------N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
***** BB02
STMT00002 (IL 0x008...0x009)
N003 ( 7, 5) [000013] -A------R--- * ASG simd8 (copy)
N002 ( 3, 2) [000011] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
N001 ( 3, 2) [000010] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
***** BB02
STMT00004 (IL 0x010...0x011)
N004 ( 7, 5) [000018] -A-XG------- * ASG simd8 (copy)
N002 ( 3, 2) [000017] *--XG--N---- +--* IND simd8
N001 ( 1, 1) [000016] ------------ | \--* LCL_VAR byref V00 RetBuf
N003 ( 3, 2) [000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
------------ BB03 [???..???) (return), preds={BB02} succs={}
***** BB03
STMT00007 (IL ???... ???)
N001 ( 0, 0) [000021] ------------ * RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 4.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB02
BB02 : BB03
*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Tracked variable (6 out of 8) table:
V00 RetBuf [ byref]: refCnt = 3, refCntWtd = 3
V05 loc2 [ simd8]: refCnt = 4, refCntWtd = 8
V01 arg0 [ float]: refCnt = 1, refCntWtd = 1
V02 arg1 [ float]: refCnt = 1, refCntWtd = 1
V03 loc0 [ simd8]: refCnt = 1, refCntWtd = 1
V04 loc1 [ simd8]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={}
DEF(0)={}
BB02 USE(3)={V00 V01 V02 } + ByrefExposed + GcHeap
DEF(3)={ V05 V03 V04} + ByrefExposed* + GcHeap*
BB03 USE(0)={}
DEF(0)={}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (3)={V00 V01 V02} + ByrefExposed + GcHeap
OUT(3)={V00 V01 V02} + ByrefExposed + GcHeap
BB02 IN (3)={V00 V01 V02} + ByrefExposed + GcHeap
OUT(0)={ }
BB03 IN (0)={}
OUT(0)={}
top level assign
removing stmt with no side effects
Removing statement STMT00002 (IL 0x008...0x009)
N003 ( 7, 5) [000013] -A------R--- * ASG simd8 (copy)
N002 ( 3, 2) [000011] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V03 loc0
N001 ( 3, 2) [000010] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
in BB02 as useless:
top level assign
removing stmt with no side effects
Removing statement STMT00001 (IL ???... ???)
N003 ( 7, 5) [000009] -A------R--- * ASG simd8 (copy)
N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V04 loc1
N001 ( 3, 2) [000006] -------N---- \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2
in BB02 as useless:
*************** In optRemoveRedundantZeroInits()
Marking L05 as having an explicit init
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
***** BB02
STMT00000 (IL 0x000...0x007)
N005 ( 30, 12) [000005] -ACXG---R--- * ASG simd8 (copy)
N004 ( 3, 2) [000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2
N003 ( 26, 9) [000002] --CXG------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
N001 ( 3, 2) [000001] ------------ arg0 +--* LCL_VAR float V02 arg1 u:1 (last use)
N002 ( 3, 2) [000000] ------------ arg1 \--* LCL_VAR float V01 arg0 u:1 (last use)
***** BB02
STMT00004 (IL 0x010...0x011)
N004 ( 7, 5) [000018] -A-XG------- * ASG simd8 (copy)
N002 ( 3, 2) [000017] *--XG--N---- +--* IND simd8
N001 ( 1, 1) [000016] ------------ | \--* LCL_VAR byref V00 RetBuf u:1 (last use)
N003 ( 3, 2) [000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use)
------------ BB03 [???..???) (return), preds={BB02} succs={}
***** BB03
STMT00007 (IL ???... ???)
N001 ( 0, 0) [000021] ------------ * RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
***** BB02
STMT00000 (IL 0x000...0x007)
N005 ( 30, 12) [000005] -ACXG---R--- * ASG simd8 (copy)
N004 ( 3, 2) [000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2
N003 ( 26, 9) [000002] --CXG------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
N001 ( 3, 2) [000001] ------------ arg0 +--* LCL_VAR float V02 arg1 u:1 (last use)
N002 ( 3, 2) [000000] ------------ arg1 \--* LCL_VAR float V01 arg0 u:1 (last use)
***** BB02
STMT00004 (IL 0x010...0x011)
N004 ( 7, 5) [000018] -A-XG------- * ASG simd8 (copy)
N002 ( 3, 2) [000017] *--XG--N---- +--* IND simd8
N001 ( 1, 1) [000016] ------------ | \--* LCL_VAR byref V00 RetBuf u:1 (last use)
N003 ( 3, 2) [000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use)
------------ BB03 [???..???) (return), preds={BB02} succs={}
***** BB03
STMT00007 (IL ???... ???)
N001 ( 0, 0) [000021] ------------ * RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Early Value Propagation
*************** In optEarlyProp()
After optEarlyProp:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
***** BB02
STMT00000 (IL 0x000...0x007)
N005 ( 30, 12) [000005] -ACXG---R--- * ASG simd8 (copy)
N004 ( 3, 2) [000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2
N003 ( 26, 9) [000002] --CXG------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
N001 ( 3, 2) [000001] ------------ arg0 +--* LCL_VAR float V02 arg1 u:1 (last use)
N002 ( 3, 2) [000000] ------------ arg1 \--* LCL_VAR float V01 arg0 u:1 (last use)
***** BB02
STMT00004 (IL 0x010...0x011)
N004 ( 7, 5) [000018] -A-XG------- * ASG simd8 (copy)
N002 ( 3, 2) [000017] *--XG--N---- +--* IND simd8
N001 ( 1, 1) [000016] ------------ | \--* LCL_VAR byref V00 RetBuf u:1 (last use)
N003 ( 3, 2) [000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use)
------------ BB03 [???..???) (return), preds={BB02} succs={}
***** BB03
STMT00007 (IL ???... ???)
N001 ( 0, 0) [000021] ------------ * RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Early Value Propagation
*************** Starting PHASE Do value numbering
*************** In fgValueNumber()
Memory Initial Value in BB01 is: $140
The SSA definition for ByrefExposed (#1) at start of BB01 is $140 {InitVal($43)}
The SSA definition for GcHeap (#1) at start of BB01 is $140 {InitVal($43)}
finish(BB01).
Succ(BB02).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#1) at start of BB02 is $140 {InitVal($43)}
The SSA definition for GcHeap (#1) at start of BB02 is $140 {InitVal($43)}
***** BB02, STMT00000(before)
N005 ( 30, 12) [000005] -ACXG---R--- * ASG simd8 (copy)
N004 ( 3, 2) [000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2
N003 ( 26, 9) [000002] --CXG------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats
N001 ( 3, 2) [000001] ------------ arg0 +--* LCL_VAR float V02 arg1 u:1 (last use)
N002 ( 3, 2) [000000] ------------ arg1 \--* LCL_VAR float V01 arg0 u:1 (last use)
N001 [000001] LCL_VAR V02 arg1 u:1 (last use) => $c1 {InitVal($42)}
N002 [000000] LCL_VAR V01 arg0 u:1 (last use) => $c0 {InitVal($41)}
fgCurMemoryVN[GcHeap] assigned for CALL at [000002] to VN: $1c0.
N003 [000002] CALL r2r_ind => $180 {180}
VNForCastOper(simd8) is $44
N004 [000003] LCL_VAR V05 loc2 d:2 => $240 {Cast($180, $44)}
N005 [000005] ASG => $240 {Cast($180, $44)}
***** BB02, STMT00000(after)
N005 ( 30, 12) [000005] -ACXG---R--- * ASG simd8 (copy) $240
N004 ( 3, 2) [000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2 $240
N003 ( 26, 9) [000002] --CXG------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
N001 ( 3, 2) [000001] ------------ arg0 +--* LCL_VAR float V02 arg1 u:1 (last use) $c1
N002 ( 3, 2) [000000] ------------ arg1 \--* LCL_VAR float V01 arg0 u:1 (last use) $c0
---------
***** BB02, STMT00004(before)
N004 ( 7, 5) [000018] -A-XG------- * ASG simd8 (copy)
N002 ( 3, 2) [000017] *--XG--N---- +--* IND simd8
N001 ( 1, 1) [000016] ------------ | \--* LCL_VAR byref V00 RetBuf u:1 (last use)
N003 ( 3, 2) [000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use)
N001 [000016] LCL_VAR V00 RetBuf u:1 (last use) => $80 {InitVal($40)}
N003 [000015] LCL_VAR V05 loc2 u:2 (last use) => $240 {Cast($180, $44)}
fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000018] to VN: $1c1.
N004 [000018] ASG => $VN.Void
***** BB02, STMT00004(after)
N004 ( 7, 5) [000018] -A-XG------- * ASG simd8 (copy) $VN.Void
N002 ( 3, 2) [000017] *--XG--N---- +--* IND simd8 $240
N001 ( 1, 1) [000016] ------------ | \--* LCL_VAR byref V00 RetBuf u:1 (last use) $80
N003 ( 3, 2) [000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use) $240
finish(BB02).
Succ(BB03).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#2) at start of BB03 is $1c1 {1c1}
The SSA definition for GcHeap (#2) at start of BB03 is $1c1 {1c1}
***** BB03, STMT00007(before)
N001 ( 0, 0) [000021] ------------ * RETURN void
N001 [000021] RETURN => $280 {280}
***** BB03, STMT00007(after)
N001 ( 0, 0) [000021] ------------ * RETURN void $280
finish(BB03).
*************** Finishing PHASE Do value numbering
*************** Starting PHASE Hoist loop code
*************** Finishing PHASE Hoist loop code
*************** Starting PHASE VN based copy prop
*************** In optVnCopyProp()
Copy Assertion for BB01
curSsaName stack: { }
Copy Assertion for BB02
curSsaName stack: { }
Live vars: {V00 V01 V02} => {V00 V01}
Live vars: {V00 V01} => {V00}
Live vars: {V00} => {V00 V05}
Live vars: {V00 V05} => {V05}
Live vars: {V05} => {}
Copy Assertion for BB03
curSsaName stack: { 0-[000016]:V00 1-[000000]:V01 2-[000001]:V02 5-[000003]:V05 }
*************** Finishing PHASE VN based copy prop
*************** Starting PHASE Redundant branch opts
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Redundant branch opts [no changes]
*************** Starting PHASE Optimize Valnum CSEs
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
***** BB02
STMT00000 (IL 0x000...0x007)
N005 ( 30, 12) [000005] -ACXG---R--- * ASG simd8 (copy) $240
N004 ( 3, 2) [000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2 $240
N003 ( 26, 9) [000002] --CXG------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
N001 ( 3, 2) [000001] ------------ arg0 +--* LCL_VAR float V02 arg1 u:1 (last use) $c1
N002 ( 3, 2) [000000] ------------ arg1 \--* LCL_VAR float V01 arg0 u:1 (last use) $c0
***** BB02
STMT00004 (IL 0x010...0x011)
N004 ( 7, 5) [000018] -A-XG------- * ASG simd8 (copy) $VN.Void
N002 ( 3, 2) [000017] *--XG--N---- +--* IND simd8 $240
N001 ( 1, 1) [000016] ------------ | \--* LCL_VAR byref V00 RetBuf u:1 (last use) $80
N003 ( 3, 2) [000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use) $240
------------ BB03 [???..???) (return), preds={BB02} succs={}
***** BB03
STMT00007 (IL ???... ???)
N001 ( 0, 0) [000021] ------------ * RETURN void $280
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
*************** Finishing PHASE Optimize Valnum CSEs
*************** Starting PHASE Assertion prop
*************** In optAssertionPropMain()
Blocks/Trees at start of phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
***** BB02
STMT00000 (IL 0x000...0x007)
N005 ( 30, 12) [000005] -ACXG---R--- * ASG simd8 (copy) $240
N004 ( 3, 2) [000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2 $240
N003 ( 26, 9) [000002] --CXG------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
N001 ( 3, 2) [000001] ------------ arg0 +--* LCL_VAR float V02 arg1 u:1 (last use) $c1
N002 ( 3, 2) [000000] ------------ arg1 \--* LCL_VAR float V01 arg0 u:1 (last use) $c0
***** BB02
STMT00004 (IL 0x010...0x011)
N004 ( 7, 5) [000018] -A-XG------- * ASG simd8 (copy) $VN.Void
N002 ( 3, 2) [000017] *--XG--N---- +--* IND simd8 $240
N001 ( 1, 1) [000016] ------------ | \--* LCL_VAR byref V00 RetBuf u:1 (last use) $80
N003 ( 3, 2) [000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use) $240
------------ BB03 [???..???) (return), preds={BB02} succs={}
***** BB03
STMT00007 (IL ???... ???)
N001 ( 0, 0) [000021] ------------ * RETURN void $280
-------------------------------------------------------------------------------------------------------------------
GenTreeNode creates assertion:
N002 ( 3, 2) [000017] *--XG--N---- * IND simd8 $240
In BB02 New Global Constant Assertion: (128, 0) ($80,$0) Value_Number {InitVal($40)} is not 0 index=#01, mask=0000000000000001
BB01 valueGen = 0000000000000000
BB02 valueGen = 0000000000000001
BB03 valueGen = 0000000000000000
AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000
AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000
AssertionPropCallback::Changed : BB01 before out -> 0000000000000001; after out -> 0000000000000000;
jumpDest before out -> 0000000000000001; jumpDest after out -> 0000000000000000;
AssertionPropCallback::StartMerge: BB02 in -> 0000000000000001
AssertionPropCallback::Merge : BB02 in -> 0000000000000001, predBlock BB01 out -> 0000000000000000
AssertionPropCallback::EndMerge : BB02 in -> 0000000000000000
AssertionPropCallback::Changed : BB02 before out -> 0000000000000001; after out -> 0000000000000001;
jumpDest before out -> 0000000000000001; jumpDest after out -> 0000000000000000;
AssertionPropCallback::StartMerge: BB03 in -> 0000000000000001
AssertionPropCallback::Merge : BB03 in -> 0000000000000001, predBlock BB02 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB03 in -> 0000000000000001
AssertionPropCallback::Unchanged : BB03 out -> 0000000000000001; jumpDest out -> 0000000000000001
BB01 valueIn = 0000000000000000 valueOut = 0000000000000000
BB02 valueIn = 0000000000000000 valueOut = 0000000000000001
BB03 valueIn = 0000000000000001 valueOut = 0000000000000001
Propagating 0000000000000000 assertions for BB02, stmt STMT00000, tree [000001], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt STMT00000, tree [000000], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt STMT00000, tree [000002], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt STMT00000, tree [000003], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt STMT00000, tree [000005], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt STMT00004, tree [000016], tree -> 0
Propagating 0000000000000000 assertions for BB02, stmt STMT00004, tree [000017], tree -> 1
Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000015], tree -> 0
Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000018], tree -> 0
Propagating 0000000000000001 assertions for BB03, stmt STMT00007, tree [000021], tree -> 0
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Assertion prop
*************** Starting PHASE Optimize index checks
*************** In OptimizeRangeChecks()
Blocks/trees before phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
***** BB02
STMT00000 (IL 0x000...0x007)
N005 ( 30, 12) [000005] -ACXG---R--- * ASG simd8 (copy) $240
N004 ( 3, 2) [000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2 $240
N003 ( 26, 9) [000002] --CXG------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
N001 ( 3, 2) [000001] ------------ arg0 +--* LCL_VAR float V02 arg1 u:1 (last use) $c1
N002 ( 3, 2) [000000] ------------ arg1 \--* LCL_VAR float V01 arg0 u:1 (last use) $c0
***** BB02
STMT00004 (IL 0x010...0x011)
N004 ( 7, 5) [000018] -A-XG------- * ASG simd8 (copy) $VN.Void
N002 ( 3, 2) [000017] *--XG--N---- +--* IND simd8 $240
N001 ( 1, 1) [000016] ------------ | \--* LCL_VAR byref V00 RetBuf u:1 (last use) $80
N003 ( 3, 2) [000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use) $240
------------ BB03 [???..???) (return), preds={BB02} succs={}
***** BB03
STMT00007 (IL ???... ???)
N001 ( 0, 0) [000021] ------------ * RETURN void $280
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Optimize index checks
*************** Starting PHASE Insert GC Polls
*************** Finishing PHASE Insert GC Polls [no changes]
*************** Starting PHASE Determine first cold block
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** Finishing PHASE Determine first cold block
Trees before Rationalize IR
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
***** BB02
STMT00000 (IL 0x000...0x007)
N005 ( 30, 12) [000005] -ACXG---R--- * ASG simd8 (copy) $240
N004 ( 3, 2) [000003] M------N---- +--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2 $240
N003 ( 26, 9) [000002] --CXG------- \--* CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
N001 ( 3, 2) [000001] ------------ arg0 +--* LCL_VAR float V02 arg1 u:1 (last use) $c1
N002 ( 3, 2) [000000] ------------ arg1 \--* LCL_VAR float V01 arg0 u:1 (last use) $c0
***** BB02
STMT00004 (IL 0x010...0x011)
N004 ( 7, 5) [000018] -A-XG------- * ASG simd8 (copy) $VN.Void
N002 ( 3, 2) [000017] *--XG--N---- +--* IND simd8 $240
N001 ( 1, 1) [000016] ------------ | \--* LCL_VAR byref V00 RetBuf u:1 (last use) $80
N003 ( 3, 2) [000015] ------------ \--* LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use) $240
------------ BB03 [???..???) (return), preds={BB02} succs={}
***** BB03
STMT00007 (IL ???... ???)
N001 ( 0, 0) [000021] ------------ * RETURN void $280
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Rationalize IR
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 30, 12) [000005] MACXG------- * STORE_LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal LIR
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
[000022] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR float V02 arg1 u:1 (last use) $c1
N002 ( 3, 2) [000000] ------------ t0 = LCL_VAR float V01 arg0 u:1 (last use) $c0
/--* t1 float arg0
+--* t0 float arg1
N003 ( 26, 9) [000002] --CXG------- t2 = * CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
/--* t2 struct
N005 ( 30, 12) [000005] MA-XG------- * STORE_LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2
[000023] ------------ IL_OFFSET void IL offset: 0x10
N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR byref V00 RetBuf u:1 (last use) $80
N003 ( 3, 2) [000015] ------------ t15 = LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use) $240
/--* t16 byref
+--* t15 simd8
[000024] -A-XG------- * STOREIND simd8
------------ BB03 [???..???) (return), preds={BB02} succs={}
N001 ( 0, 0) [000021] ------------ RETURN void $280
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Do 'simple' lowering
*************** Finishing PHASE Do 'simple' lowering
*************** In fgDebugCheckBBlist
Trees before Lowering nodeinfo
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal LIR
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
[000022] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR float V02 arg1 u:1 (last use) $c1
N002 ( 3, 2) [000000] ------------ t0 = LCL_VAR float V01 arg0 u:1 (last use) $c0
/--* t1 float arg0
+--* t0 float arg1
N003 ( 26, 9) [000002] --CXG------- t2 = * CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
/--* t2 struct
N005 ( 30, 12) [000005] MA-XG------- * STORE_LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2
[000023] ------------ IL_OFFSET void IL offset: 0x10
N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR byref V00 RetBuf u:1 (last use) $80
N003 ( 3, 2) [000015] ------------ t15 = LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use) $240
/--* t16 byref
+--* t15 simd8
[000024] -A-XG------- * STOREIND simd8
------------ BB03 [???..???) (return), preds={BB02} succs={}
N001 ( 0, 0) [000021] ------------ RETURN void $280
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Lowering nodeinfo
lowering call (before):
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR float V02 arg1 u:1 (last use) $c1
N002 ( 3, 2) [000000] ------------ t0 = LCL_VAR float V01 arg0 u:1 (last use) $c0
/--* t1 float arg0
+--* t0 float arg1
N003 ( 26, 9) [000002] --CXG------- t2 = * CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
objp:
======
args:
======
lowering arg : N001 ( 3, 2) [000001] ------------ * LCL_VAR float V02 arg1 u:1 (last use) $c1
new node is : [000025] ------------ * PUTARG_STK [+0x00] void (1 slots), (4 stackByteSize), (0 slot), (0 byteOffset)
lowering arg : N002 ( 3, 2) [000000] ------------ * LCL_VAR float V01 arg0 u:1 (last use) $c0
new node is : [000026] ------------ * PUTARG_STK [+0x04] void (1 slots), (4 stackByteSize), (1 slot), (4 byteOffset)
late:
======
======= Inserting PInvoke call prolog
Initializing arg info for 30.CALL:
ArgTable for 30.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 28.LCL_VAR_ADDR int (By ref), 1 reg: ecx, byteAlignment=4]
fgArgTabEntry[arg 1 29.CNS_INT int (By ref), 1 reg: edx, byteAlignment=4]
Morphing args for 30.CALL:
Sorting the arguments:
Deferred argument ('ecx'):
[000028] ------------ * LCL_VAR_ADDR int V06 PInvokeFrame
Replaced with placeholder node:
[000031] ----------L- * ARGPLACE int
Deferred argument ('edx'):
[000029] ------------ * CNS_INT int 8
Replaced with placeholder node:
[000032] ----------L- * ARGPLACE int
Shuffled argument table: ecx edx
ArgTable for 30.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 28.LCL_VAR_ADDR int (By ref), 1 reg: ecx, byteAlignment=4, lateArgInx=0, processed]
fgArgTabEntry[arg 1 29.CNS_INT int (By ref), 1 reg: edx, byteAlignment=4, lateArgInx=1, processed]
lowering call (before):
N001 ( 3, 3) [000028] ------------ t28 = LCL_VAR_ADDR int V06 PInvokeFrame
N002 ( 1, 1) [000029] ------------ t29 = CNS_INT int 8
/--* t28 int arg0 in ecx
+--* t29 int arg1 in edx
N003 ( 18, 11) [000030] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
objp:
======
args:
======
lowering arg : ( 0, 0) [000031] ----------L- * ARGPLACE int
lowering arg : ( 0, 0) [000032] ----------L- * ARGPLACE int
late:
======
lowering arg : N001 ( 3, 3) [000028] ------------ * LCL_VAR_ADDR int V06 PInvokeFrame
new node is : [000033] ------------ * PUTARG_REG int REG ecx
lowering arg : N002 ( 1, 1) [000029] ------------ * CNS_INT int 8
new node is : [000034] ------------ * PUTARG_REG int REG edx
results of lowering call:
N001 ( 1, 4) [000035] H----------- t35 = CNS_INT(h) int 0x420220 ftn
/--* t35 int
N002 ( 3, 6) [000036] ------------ t36 = * IND int
lowering call (after):
N001 ( 3, 3) [000028] ------------ t28 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t28 int
[000033] ------------ t33 = * PUTARG_REG int REG ecx
N002 ( 1, 1) [000029] ------------ t29 = CNS_INT int 8
/--* t29 int
[000034] ------------ t34 = * PUTARG_REG int REG edx
N001 ( 1, 4) [000035] Hc---------- t35 = CNS_INT(h) int 0x420220 ftn
/--* t35 int
N002 ( 3, 6) [000036] -c---------- t36 = * IND int REG NA
/--* t33 int arg0 in ecx
+--* t34 int arg1 in edx
+--* t36 int control expr
N003 ( 18, 11) [000030] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
======= Inserting PInvoke call epilog
Initializing arg info for 41.CALL:
ArgTable for 41.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 40.LCL_VAR_ADDR int (By ref), 1 reg: ecx, byteAlignment=4]
Morphing args for 41.CALL:
Sorting the arguments:
Deferred argument ('ecx'):
[000040] ------------ * LCL_VAR_ADDR int V06 PInvokeFrame
Replaced with placeholder node:
[000042] ----------L- * ARGPLACE int
Shuffled argument table: ecx
ArgTable for 41.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 40.LCL_VAR_ADDR int (By ref), 1 reg: ecx, byteAlignment=4, lateArgInx=0, processed]
results of lowering call:
N001 ( 1, 4) [000037] H----------- t37 = CNS_INT(h) int 0x420368 ftn
/--* t37 int
N002 ( 3, 6) [000038] ------------ t38 = * IND int
/--* t38 int
N003 ( 6, 8) [000039] ------------ t39 = * IND int
lowering call (after):
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR float V02 arg1 u:1 (last use) $c1
/--* t1 float
[000025] ------------ * PUTARG_STK [+0x00] void (1 slots), (4 stackByteSize), (0 slot), (0 byteOffset)
N002 ( 3, 2) [000000] ------------ t0 = LCL_VAR float V01 arg0 u:1 (last use) $c0
/--* t0 float
[000026] ------------ * PUTARG_STK [+0x04] void (1 slots), (4 stackByteSize), (1 slot), (4 byteOffset)
[000027] ------------ PINVOKE_PROLOG void
N001 ( 3, 3) [000028] ------------ t28 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t28 int
[000033] ------------ t33 = * PUTARG_REG int REG ecx
N002 ( 1, 1) [000029] ------------ t29 = CNS_INT int 8
/--* t29 int
[000034] ------------ t34 = * PUTARG_REG int REG edx
N001 ( 1, 4) [000035] Hc---------- t35 = CNS_INT(h) int 0x420220 ftn
/--* t35 int
N002 ( 3, 6) [000036] -c---------- t36 = * IND int REG NA
/--* t33 int arg0 in ecx
+--* t34 int arg1 in edx
+--* t36 int control expr
N003 ( 18, 11) [000030] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
N001 ( 1, 4) [000037] Hc---------- t37 = CNS_INT(h) int 0x420368 ftn
/--* t37 int
N002 ( 3, 6) [000038] ------------ t38 = * IND int
/--* t38 int
N003 ( 6, 8) [000039] -c---------- t39 = * IND int REG NA
/--* t39 int control expr
N003 ( 26, 9) [000002] --CXG------- t2 = * CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
lowering call (before):
N001 ( 3, 3) [000040] ------------ t40 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t40 int arg0 in ecx
N002 ( 17, 9) [000041] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END
objp:
======
args:
======
lowering arg : ( 0, 0) [000042] ----------L- * ARGPLACE int
late:
======
lowering arg : N001 ( 3, 3) [000040] ------------ * LCL_VAR_ADDR int V06 PInvokeFrame
new node is : [000043] ------------ * PUTARG_REG int REG ecx
results of lowering call:
N001 ( 1, 4) [000044] H----------- t44 = CNS_INT(h) int 0x420230 ftn
/--* t44 int
N002 ( 3, 6) [000045] ------------ t45 = * IND int
lowering call (after):
N001 ( 3, 3) [000040] ------------ t40 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t40 int
[000043] ------------ t43 = * PUTARG_REG int REG ecx
N001 ( 1, 4) [000044] Hc---------- t44 = CNS_INT(h) int 0x420230 ftn
/--* t44 int
N002 ( 3, 6) [000045] -c---------- t45 = * IND int REG NA
/--* t43 int arg0 in ecx
+--* t45 int control expr
N002 ( 17, 9) [000041] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END
lowering store lcl var/field (before):
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR float V02 arg1 u:1 (last use) $c1
/--* t1 float
[000025] ------------ * PUTARG_STK [+0x00] void (1 slots), (4 stackByteSize), (0 slot), (0 byteOffset)
N002 ( 3, 2) [000000] ------------ t0 = LCL_VAR float V01 arg0 u:1 (last use) $c0
/--* t0 float
[000026] ------------ * PUTARG_STK [+0x04] void (1 slots), (4 stackByteSize), (1 slot), (4 byteOffset)
[000027] ------------ PINVOKE_PROLOG void
N001 ( 3, 3) [000028] ------------ t28 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t28 int
[000033] ------------ t33 = * PUTARG_REG int REG ecx
N002 ( 1, 1) [000029] ------------ t29 = CNS_INT int 8
/--* t29 int
[000034] ------------ t34 = * PUTARG_REG int REG edx
N001 ( 1, 4) [000035] Hc---------- t35 = CNS_INT(h) int 0x420220 ftn
/--* t35 int
N002 ( 3, 6) [000036] -c---------- t36 = * IND int REG NA
/--* t33 int arg0 in ecx
+--* t34 int arg1 in edx
+--* t36 int control expr
N003 ( 18, 11) [000030] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
N001 ( 1, 4) [000037] Hc---------- t37 = CNS_INT(h) int 0x420368 ftn
/--* t37 int
N002 ( 3, 6) [000038] ------------ t38 = * IND int
/--* t38 int
N003 ( 6, 8) [000039] -c---------- t39 = * IND int REG NA
/--* t39 int control expr
N003 ( 26, 9) [000002] --CXG------- t2 = * CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
N001 ( 3, 3) [000040] ------------ t40 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t40 int
[000043] ------------ t43 = * PUTARG_REG int REG ecx
N001 ( 1, 4) [000044] Hc---------- t44 = CNS_INT(h) int 0x420230 ftn
/--* t44 int
N002 ( 3, 6) [000045] -c---------- t45 = * IND int REG NA
/--* t43 int arg0 in ecx
+--* t45 int control expr
N002 ( 17, 9) [000041] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END
/--* t2 struct
N005 ( 30, 12) [000005] MA-XG------- * STORE_LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2
lowering store lcl var/field (after):
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR float V02 arg1 u:1 (last use) $c1
/--* t1 float
[000025] ------------ * PUTARG_STK [+0x00] void (1 slots), (4 stackByteSize), (0 slot), (0 byteOffset)
N002 ( 3, 2) [000000] ------------ t0 = LCL_VAR float V01 arg0 u:1 (last use) $c0
/--* t0 float
[000026] ------------ * PUTARG_STK [+0x04] void (1 slots), (4 stackByteSize), (1 slot), (4 byteOffset)
[000027] ------------ PINVOKE_PROLOG void
N001 ( 3, 3) [000028] ------------ t28 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t28 int
[000033] ------------ t33 = * PUTARG_REG int REG ecx
N002 ( 1, 1) [000029] ------------ t29 = CNS_INT int 8
/--* t29 int
[000034] ------------ t34 = * PUTARG_REG int REG edx
N001 ( 1, 4) [000035] Hc---------- t35 = CNS_INT(h) int 0x420220 ftn
/--* t35 int
N002 ( 3, 6) [000036] -c---------- t36 = * IND int REG NA
/--* t33 int arg0 in ecx
+--* t34 int arg1 in edx
+--* t36 int control expr
N003 ( 18, 11) [000030] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
N001 ( 1, 4) [000037] Hc---------- t37 = CNS_INT(h) int 0x420368 ftn
/--* t37 int
N002 ( 3, 6) [000038] ------------ t38 = * IND int
/--* t38 int
N003 ( 6, 8) [000039] -c---------- t39 = * IND int REG NA
/--* t39 int control expr
N003 ( 26, 9) [000002] --CXG------- t2 = * CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
N001 ( 3, 3) [000040] ------------ t40 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t40 int
[000043] ------------ t43 = * PUTARG_REG int REG ecx
N001 ( 1, 4) [000044] Hc---------- t44 = CNS_INT(h) int 0x420230 ftn
/--* t44 int
N002 ( 3, 6) [000045] -c---------- t45 = * IND int REG NA
/--* t43 int arg0 in ecx
+--* t45 int control expr
N002 ( 17, 9) [000041] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END
/--* t2 struct
N005 ( 30, 12) [000005] DA-XG------- * STORE_LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2
Lower of StoreInd didn't mark the node as self contained for reason: 4
N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR byref V00 RetBuf u:1 (last use) $80
N003 ( 3, 2) [000015] ------------ t15 = LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use) $240
/--* t16 byref
+--* t15 simd8
[000024] -A-XG------- * STOREIND simd8
lowering GT_RETURN
N001 ( 0, 0) [000021] ------------ * RETURN void $280
============Lower has completed modifying nodes.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal LIR
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
[000022] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR float V02 arg1 u:1 (last use) $c1
/--* t1 float
[000025] ------------ * PUTARG_STK [+0x00] void (1 slots), (4 stackByteSize), (0 slot), (0 byteOffset)
N002 ( 3, 2) [000000] ------------ t0 = LCL_VAR float V01 arg0 u:1 (last use) $c0
/--* t0 float
[000026] ------------ * PUTARG_STK [+0x04] void (1 slots), (4 stackByteSize), (1 slot), (4 byteOffset)
[000027] ------------ PINVOKE_PROLOG void
N001 ( 3, 3) [000028] ------------ t28 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t28 int
[000033] ------------ t33 = * PUTARG_REG int REG ecx
N002 ( 1, 1) [000029] ------------ t29 = CNS_INT int 8
/--* t29 int
[000034] ------------ t34 = * PUTARG_REG int REG edx
N001 ( 1, 4) [000035] Hc---------- t35 = CNS_INT(h) int 0x420220 ftn
/--* t35 int
N002 ( 3, 6) [000036] -c---------- t36 = * IND int REG NA
/--* t33 int arg0 in ecx
+--* t34 int arg1 in edx
+--* t36 int control expr
N003 ( 18, 11) [000030] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
N001 ( 1, 4) [000037] Hc---------- t37 = CNS_INT(h) int 0x420368 ftn
/--* t37 int
N002 ( 3, 6) [000038] ------------ t38 = * IND int
/--* t38 int
N003 ( 6, 8) [000039] -c---------- t39 = * IND int REG NA
/--* t39 int control expr
N003 ( 26, 9) [000002] --CXG------- t2 = * CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
N001 ( 3, 3) [000040] ------------ t40 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t40 int
[000043] ------------ t43 = * PUTARG_REG int REG ecx
N001 ( 1, 4) [000044] Hc---------- t44 = CNS_INT(h) int 0x420230 ftn
/--* t44 int
N002 ( 3, 6) [000045] -c---------- t45 = * IND int REG NA
/--* t43 int arg0 in ecx
+--* t45 int control expr
N002 ( 17, 9) [000041] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END
/--* t2 struct
N005 ( 30, 12) [000005] DA-XG------- * STORE_LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2
[000023] ------------ IL_OFFSET void IL offset: 0x10
N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR byref V00 RetBuf u:1 (last use) $80
N003 ( 3, 2) [000015] ------------ t15 = LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use) $240
/--* t16 byref
+--* t15 simd8
[000024] -A-XG------- * STOREIND simd8
------------ BB03 [???..???) (return), preds={BB02} succs={}
N001 ( 0, 0) [000021] ------------ RETURN void $280
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V06: refCnt = 2, refCntWtd = 2
New refCnts for V06: refCnt = 3, refCntWtd = 3
New refCnts for V05: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V05: refCnt = 2, refCntWtd = 4
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 RetBuf byref
; V01 arg0 float
; V02 arg1 float
; V03 loc0 simd8
; V04 loc1 simd8
; V05 loc2 simd8 multireg-ret "Return value temp for multireg return"
; V06 PInvokeFrame blk do-not-enreg[X] addr-exposed "Pinvoke FrameVar"
; V07 EHSlots blk do-not-enreg[X] addr-exposed "lvaShadowSPslotsVar"
In fgLocalVarLivenessInit
Tracked variable (4 out of 8) table:
V00 RetBuf [ byref]: refCnt = 3, refCntWtd = 3
V05 loc2 [ simd8]: refCnt = 2, refCntWtd = 4
V01 arg0 [ float]: refCnt = 1, refCntWtd = 1
V02 arg1 [ float]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(0)={}
DEF(0)={}
BB02 USE(3)={V00 V01 V02} + ByrefExposed + GcHeap
DEF(1)={ V05 } + ByrefExposed* + GcHeap*
BB03 USE(0)={}
DEF(0)={}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
BB liveness after fgLiveVarAnalysis():
BB01 IN (3)={V00 V01 V02} + ByrefExposed + GcHeap
OUT(3)={V00 V01 V02} + ByrefExposed + GcHeap
BB02 IN (3)={V00 V01 V02} + ByrefExposed + GcHeap
OUT(0)={ }
BB03 IN (0)={}
OUT(0)={}
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal LIR
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V06: refCnt = 2, refCntWtd = 2
New refCnts for V06: refCnt = 3, refCntWtd = 3
New refCnts for V05: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V05: refCnt = 2, refCntWtd = 4
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V00: refCnt = 3, refCntWtd = 3
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal LIR
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
[000022] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR float V02 arg1 u:1 (last use) $c1
/--* t1 float
[000025] ------------ * PUTARG_STK [+0x00] void (1 slots), (4 stackByteSize), (0 slot), (0 byteOffset)
N002 ( 3, 2) [000000] ------------ t0 = LCL_VAR float V01 arg0 u:1 (last use) $c0
/--* t0 float
[000026] ------------ * PUTARG_STK [+0x04] void (1 slots), (4 stackByteSize), (1 slot), (4 byteOffset)
[000027] ------------ PINVOKE_PROLOG void
N001 ( 3, 3) [000028] ------------ t28 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t28 int
[000033] ------------ t33 = * PUTARG_REG int REG ecx
N002 ( 1, 1) [000029] ------------ t29 = CNS_INT int 8
/--* t29 int
[000034] ------------ t34 = * PUTARG_REG int REG edx
N001 ( 1, 4) [000035] Hc---------- t35 = CNS_INT(h) int 0x420220 ftn
/--* t35 int
N002 ( 3, 6) [000036] -c---------- t36 = * IND int REG NA
/--* t33 int arg0 in ecx
+--* t34 int arg1 in edx
+--* t36 int control expr
N003 ( 18, 11) [000030] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
N001 ( 1, 4) [000037] Hc---------- t37 = CNS_INT(h) int 0x420368 ftn
/--* t37 int
N002 ( 3, 6) [000038] ------------ t38 = * IND int
/--* t38 int
N003 ( 6, 8) [000039] -c---------- t39 = * IND int REG NA
/--* t39 int control expr
N003 ( 26, 9) [000002] --CXG------- t2 = * CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
N001 ( 3, 3) [000040] ------------ t40 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t40 int
[000043] ------------ t43 = * PUTARG_REG int REG ecx
N001 ( 1, 4) [000044] Hc---------- t44 = CNS_INT(h) int 0x420230 ftn
/--* t44 int
N002 ( 3, 6) [000045] -c---------- t45 = * IND int REG NA
/--* t43 int arg0 in ecx
+--* t45 int control expr
N002 ( 17, 9) [000041] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END
/--* t2 struct
N005 ( 30, 12) [000005] DA-XG------- * STORE_LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2
[000023] ------------ IL_OFFSET void IL offset: 0x10
N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR byref V00 RetBuf u:1 (last use) $80
N003 ( 3, 2) [000015] ------------ t15 = LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use) $240
/--* t16 byref
+--* t15 simd8
[000024] -A-XG------- * STOREIND simd8
------------ BB03 [???..???) (return), preds={BB02} succs={}
N001 ( 0, 0) [000021] ------------ RETURN void $280
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Trees before Calculate stack level slots
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal LIR
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
[000022] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR float V02 arg1 u:1 (last use) $c1
/--* t1 float
[000025] ------------ * PUTARG_STK [+0x00] void (1 slots), (4 stackByteSize), (0 slot), (0 byteOffset)
N002 ( 3, 2) [000000] ------------ t0 = LCL_VAR float V01 arg0 u:1 (last use) $c0
/--* t0 float
[000026] ------------ * PUTARG_STK [+0x04] void (1 slots), (4 stackByteSize), (1 slot), (4 byteOffset)
[000027] ------------ PINVOKE_PROLOG void
N001 ( 3, 3) [000028] ------------ t28 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t28 int
[000033] ------------ t33 = * PUTARG_REG int REG ecx
N002 ( 1, 1) [000029] ------------ t29 = CNS_INT int 8
/--* t29 int
[000034] ------------ t34 = * PUTARG_REG int REG edx
N001 ( 1, 4) [000035] Hc---------- t35 = CNS_INT(h) int 0x420220 ftn
/--* t35 int
N002 ( 3, 6) [000036] -c---------- t36 = * IND int REG NA
/--* t33 int arg0 in ecx
+--* t34 int arg1 in edx
+--* t36 int control expr
N003 ( 18, 11) [000030] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
N001 ( 1, 4) [000037] Hc---------- t37 = CNS_INT(h) int 0x420368 ftn
/--* t37 int
N002 ( 3, 6) [000038] ------------ t38 = * IND int
/--* t38 int
N003 ( 6, 8) [000039] -c---------- t39 = * IND int REG NA
/--* t39 int control expr
N003 ( 26, 9) [000002] --CXG------- t2 = * CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats $180
N001 ( 3, 3) [000040] ------------ t40 = LCL_VAR_ADDR int V06 PInvokeFrame
/--* t40 int
[000043] ------------ t43 = * PUTARG_REG int REG ecx
N001 ( 1, 4) [000044] Hc---------- t44 = CNS_INT(h) int 0x420230 ftn
/--* t44 int
N002 ( 3, 6) [000045] -c---------- t45 = * IND int REG NA
/--* t43 int arg0 in ecx
+--* t45 int control expr
N002 ( 17, 9) [000041] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END
/--* t2 struct
N005 ( 30, 12) [000005] DA-XG------- * STORE_LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2
[000023] ------------ IL_OFFSET void IL offset: 0x10
N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR byref V00 RetBuf u:1 (last use) $80
N003 ( 3, 2) [000015] ------------ t15 = LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 (last use) $240
/--* t16 byref
+--* t15 simd8
[000024] -A-XG------- * STOREIND simd8
------------ BB03 [???..???) (return), preds={BB02} succs={}
N001 ( 0, 0) [000021] ------------ RETURN void $280
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots [no changes]
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{}
{}
{V00 V01 V02}
{V00 V01 V02}
BB02 use def in out
{V00 V01 V02}
{V05}
{V00 V01 V02}
{}
BB03 use def in out
{}
{}
{}
{}
Interval 0: byref RefPositions {} physReg:NA Preferences=[allInt]
Interval 0: (V00) byref RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: float RefPositions {} physReg:NA Preferences=[allFloat]
Interval 1: (V01) float RefPositions {} physReg:NA Preferences=[allFloat]
Interval 2: float RefPositions {} physReg:NA Preferences=[allFloat]
Interval 2: (V02) float RefPositions {} physReg:NA Preferences=[allFloat]
Interval 3: simd8 RefPositions {} physReg:NA Preferences=[allFloat]
Interval 3: (V05) simd8 RefPositions {} physReg:NA Preferences=[allFloat]
FP callee save candidate vars: {V05}
floatVarCount = 3; hasLoops = 0, singleExit = 1
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 )
BB02( 1 )
BB03( 1 )
BB01 [???..???), preds={} succs={BB02}
=====
BB02 [000..012), preds={BB01} succs={BB03}
=====
N000. IL_OFFSET IL offset: 0x0
N001. V02(t1*)
N000. PUTARG_STK [+0x00]; t1*
N002. V01(t0*)
N000. PUTARG_STK [+0x04]; t0*
N000. PINVOKE_PROLOG
N001. t28 = LCL_VAR_ADDR V06 PInvokeFrame
N000. t33 = PUTARG_REG; t28
N002. t29 = CNS_INT 8
N000. t34 = PUTARG_REG; t29
N001. CNS_INT(h) 0x420220 ftn
N002. IND
N003. CALL help; t33,t34
N001. CNS_INT(h) 0x420368 ftn
N002. t38 = IND
N003. t39 = IND ; t38
N003. t2 = CALL r2r_ind; t39
N001. t40 = LCL_VAR_ADDR V06 PInvokeFrame
N000. t43 = PUTARG_REG; t40
N001. CNS_INT(h) 0x420230 ftn
N002. IND
N002. CALL help; t43
N005. V05(t5); t2
N000. IL_OFFSET IL offset: 0x10
N001. V00(t16*)
N003. V05(t15*)
N000. STOREIND ; t16*,t15*
BB03 [???..???) (return), preds={BB02} succs={}
=====
N001. RETURN
buildIntervals second part ========
Int arg V00 in reg ecx
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[allFloat] minReg=1>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[allFloat] minReg=1>
NEW BLOCK BB01
<RefPosition #3 @1 RefTypeBB BB01 regmask=[] minReg=1>
CHECKING LAST USES for BB01, liveout={V00 V01 V02}
==============================
use: {}
def: {}
NEW BLOCK BB02
Setting BB01 as the predecessor for determining incoming variable registers of BB02
<RefPosition #4 @3 RefTypeBB BB02 regmask=[] minReg=1>
DefList: { }
N005 (???,???) [000022] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
DefList: { }
N007 ( 3, 2) [000001] ------------ * LCL_VAR float V02 arg1 u:1 NA (last use) REG NA $c1
DefList: { }
N009 (???,???) [000025] ------------ * PUTARG_STK [+0x00] void (1 slots), (4 stackByteSize), (0 slot), (0 byteOffset) REG NA
<RefPosition #5 @9 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
DefList: { }
N011 ( 3, 2) [000000] ------------ * LCL_VAR float V01 arg0 u:1 NA (last use) REG NA $c0
DefList: { }
N013 (???,???) [000026] ------------ * PUTARG_STK [+0x04] void (1 slots), (4 stackByteSize), (1 slot), (4 byteOffset) REG NA
<RefPosition #6 @13 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
DefList: { }
N015 (???,???) [000027] ------------ * PINVOKE_PROLOG void REG NA
DefList: { }
N017 ( 3, 3) [000028] ------------ * LCL_VAR_ADDR int V06 PInvokeFrame NA REG NA
Interval 4: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #7 @18 RefTypeDef <Ivl:4> LCL_VAR_ADDR BB02 regmask=[allInt] minReg=1>
DefList: { N017.t28. LCL_VAR_ADDR }
N019 (???,???) [000033] ------------ * PUTARG_REG int REG ecx
<RefPosition #8 @19 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #9 @19 RefTypeUse <Ivl:4> BB02 regmask=[ecx] minReg=1 last fixed>
Interval 5: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #10 @20 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #11 @20 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[ecx] minReg=1 fixed>
DefList: { N019.t33. PUTARG_REG }
N021 ( 1, 1) [000029] ------------ * CNS_INT int 8 REG NA
Interval 6: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #12 @22 RefTypeDef <Ivl:6> CNS_INT BB02 regmask=[allInt] minReg=1>
DefList: { N019.t33. PUTARG_REG; N021.t29. CNS_INT }
N023 (???,???) [000034] ------------ * PUTARG_REG int REG edx
<RefPosition #13 @23 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #14 @23 RefTypeUse <Ivl:6> BB02 regmask=[edx] minReg=1 last fixed>
Interval 7: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #15 @24 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #16 @24 RefTypeDef <Ivl:7> PUTARG_REG BB02 regmask=[edx] minReg=1 fixed>
DefList: { N019.t33. PUTARG_REG; N023.t34. PUTARG_REG }
N025 ( 1, 4) [000035] Hc---------- * CNS_INT(h) int 0x420220 ftn REG NA
Contained
DefList: { N019.t33. PUTARG_REG; N023.t34. PUTARG_REG }
N027 ( 3, 6) [000036] -c---------- * IND int REG NA
Contained
DefList: { N019.t33. PUTARG_REG; N023.t34. PUTARG_REG }
N029 ( 18, 11) [000030] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN REG NA
<RefPosition #17 @29 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #18 @29 RefTypeUse <Ivl:5> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #19 @29 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #20 @29 RefTypeUse <Ivl:7> BB02 regmask=[edx] minReg=1 last fixed>
<RefPosition #21 @30 RefTypeKill <Reg:eax> BB02 regmask=[eax] minReg=1>
<RefPosition #22 @30 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #23 @30 RefTypeKill <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #24 @30 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] minReg=1>
<RefPosition #25 @30 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] minReg=1>
<RefPosition #26 @30 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] minReg=1>
<RefPosition #27 @30 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] minReg=1>
<RefPosition #28 @30 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] minReg=1>
<RefPosition #29 @30 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] minReg=1>
<RefPosition #30 @30 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] minReg=1>
<RefPosition #31 @30 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] minReg=1>
<RefPosition #32 @30 RefTypeKillGCRefs CALL BB02 regmask=[eax ebx esi edi] minReg=1>
DefList: { }
N031 ( 1, 4) [000037] Hc---------- * CNS_INT(h) int 0x420368 ftn REG NA
Contained
DefList: { }
N033 ( 3, 6) [000038] ------------ * IND int REG NA
Interval 8: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #33 @34 RefTypeDef <Ivl:8> IND BB02 regmask=[allInt] minReg=1>
DefList: { N033.t38. IND }
N035 ( 6, 8) [000039] -c---------- * IND int REG NA
Contained
DefList: { N033.t38. IND }
N037 ( 26, 9) [000002] --CXG------- * CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats REG NA,NA $180
<RefPosition #34 @37 RefTypeUse <Ivl:8> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #35 @38 RefTypeKill <Reg:eax> BB02 regmask=[eax] minReg=1>
<RefPosition #36 @38 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #37 @38 RefTypeKill <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #38 @38 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] minReg=1>
<RefPosition #39 @38 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] minReg=1>
<RefPosition #40 @38 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] minReg=1>
<RefPosition #41 @38 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] minReg=1>
<RefPosition #42 @38 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] minReg=1>
<RefPosition #43 @38 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] minReg=1>
<RefPosition #44 @38 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] minReg=1>
<RefPosition #45 @38 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] minReg=1>
<RefPosition #46 @38 RefTypeKillGCRefs CALL[0] BB02 regmask=[eax ebx esi edi] minReg=1>
Interval 9: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #47 @38 RefTypeFixedReg <Reg:eax> BB02 regmask=[eax] minReg=1>
<RefPosition #48 @38 RefTypeDef <Ivl:9> CALL[0] BB02 regmask=[eax] minReg=1 fixed>
Interval 10: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #49 @38 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #50 @38 RefTypeDef <Ivl:10> CALL[1] BB02 regmask=[edx] minReg=1 fixed>
DefList: { N037.t2. CALL; N037.t2. CALL }
N039 ( 3, 3) [000040] ------------ * LCL_VAR_ADDR int V06 PInvokeFrame NA REG NA
Interval 11: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #51 @40 RefTypeDef <Ivl:11> LCL_VAR_ADDR BB02 regmask=[allInt] minReg=1>
DefList: { N037.t2. CALL; N037.t2. CALL; N039.t40. LCL_VAR_ADDR }
N041 (???,???) [000043] ------------ * PUTARG_REG int REG ecx
<RefPosition #52 @41 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #53 @41 RefTypeUse <Ivl:11> BB02 regmask=[ecx] minReg=1 last fixed>
Interval 12: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #54 @42 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #55 @42 RefTypeDef <Ivl:12> PUTARG_REG BB02 regmask=[ecx] minReg=1 fixed>
DefList: { N037.t2. CALL; N037.t2. CALL; N041.t43. PUTARG_REG }
N043 ( 1, 4) [000044] Hc---------- * CNS_INT(h) int 0x420230 ftn REG NA
Contained
DefList: { N037.t2. CALL; N037.t2. CALL; N041.t43. PUTARG_REG }
N045 ( 3, 6) [000045] -c---------- * IND int REG NA
Contained
DefList: { N037.t2. CALL; N037.t2. CALL; N041.t43. PUTARG_REG }
N047 ( 17, 9) [000041] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END REG NA
<RefPosition #56 @47 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #57 @47 RefTypeUse <Ivl:12> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #58 @48 RefTypeKill <Reg:eax> BB02 regmask=[eax] minReg=1>
<RefPosition #59 @48 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #60 @48 RefTypeKill <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #61 @48 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] minReg=1>
<RefPosition #62 @48 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] minReg=1>
<RefPosition #63 @48 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] minReg=1>
<RefPosition #64 @48 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] minReg=1>
<RefPosition #65 @48 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] minReg=1>
<RefPosition #66 @48 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] minReg=1>
<RefPosition #67 @48 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] minReg=1>
<RefPosition #68 @48 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] minReg=1>
DefList: { N037.t2. CALL; N037.t2. CALL }
N049 ( 30, 12) [000005] DA-XG------- * STORE_LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2 NA REG NA
<RefPosition #69 @49 RefTypeUse <Ivl:9> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #70 @49 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #71 @50 RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
DefList: { }
N051 (???,???) [000023] ------------ * IL_OFFSET void IL offset: 0x10 REG NA
DefList: { }
N053 ( 1, 1) [000016] ------------ * LCL_VAR byref V00 RetBuf u:1 NA (last use) REG NA $80
DefList: { }
N055 ( 3, 2) [000015] ------------ * LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 NA (last use) REG NA $240
DefList: { }
N057 (???,???) [000024] -A-XG------- * STOREIND simd8 REG NA
<RefPosition #72 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #73 @57 RefTypeUse <Ivl:3 V05> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
CHECKING LAST USES for BB02, liveout={}
==============================
use: {V00 V01 V02}
def: {V05}
NEW BLOCK BB03
Setting BB02 as the predecessor for determining incoming variable registers of BB03
<RefPosition #74 @59 RefTypeBB BB03 regmask=[] minReg=1>
DefList: { }
N061 ( 0, 0) [000021] ------------ * RETURN void REG NA $280
CHECKING LAST USES for BB03, liveout={}
==============================
use: {}
def: {}
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) byref RefPositions {#0@0 #72@57} physReg:ecx Preferences=[ebx esi edi]
Interval 1: (V01) float RefPositions {#1@0 #6@13} physReg:NA Preferences=[allFloat]
Interval 2: (V02) float RefPositions {#2@0 #5@9} physReg:NA Preferences=[allFloat]
Interval 3: (V05) simd8 RefPositions {#71@50 #73@57} physReg:NA Preferences=[allFloat]
Interval 4: int RefPositions {#7@18 #9@19} physReg:NA Preferences=[ecx]
Interval 5: int RefPositions {#11@20 #18@29} physReg:NA Preferences=[ecx]
Interval 6: int (constant) RefPositions {#12@22 #14@23} physReg:NA Preferences=[edx]
Interval 7: int RefPositions {#16@24 #20@29} physReg:NA Preferences=[edx]
Interval 8: int RefPositions {#33@34 #34@37} physReg:NA Preferences=[allInt]
Interval 9: int RefPositions {#48@38 #69@49} physReg:NA Preferences=[eax]
Interval 10: int RefPositions {#50@38 #70@49} physReg:NA Preferences=[edx]
Interval 11: int RefPositions {#51@40 #53@41} physReg:NA Preferences=[ecx]
Interval 12: int RefPositions {#55@42 #57@47} physReg:NA Preferences=[ecx]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[allFloat] minReg=1 regOptional>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[allFloat] minReg=1 regOptional>
<RefPosition #3 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #4 @3 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #5 @9 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #6 @13 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #7 @18 RefTypeDef <Ivl:4> LCL_VAR_ADDR BB02 regmask=[ecx] minReg=1>
<RefPosition #8 @19 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #9 @19 RefTypeUse <Ivl:4> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #10 @20 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #11 @20 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[ecx] minReg=1 fixed>
<RefPosition #12 @22 RefTypeDef <Ivl:6> CNS_INT BB02 regmask=[edx] minReg=1>
<RefPosition #13 @23 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #14 @23 RefTypeUse <Ivl:6> BB02 regmask=[edx] minReg=1 last fixed>
<RefPosition #15 @24 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #16 @24 RefTypeDef <Ivl:7> PUTARG_REG BB02 regmask=[edx] minReg=1 fixed>
<RefPosition #17 @29 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #18 @29 RefTypeUse <Ivl:5> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #19 @29 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #20 @29 RefTypeUse <Ivl:7> BB02 regmask=[edx] minReg=1 last fixed>
<RefPosition #21 @30 RefTypeKill <Reg:eax> BB02 regmask=[eax] minReg=1 last>
<RefPosition #22 @30 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] minReg=1 last>
<RefPosition #23 @30 RefTypeKill <Reg:edx> BB02 regmask=[edx] minReg=1 last>
<RefPosition #24 @30 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #25 @30 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] minReg=1 last>
<RefPosition #26 @30 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] minReg=1 last>
<RefPosition #27 @30 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] minReg=1 last>
<RefPosition #28 @30 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] minReg=1 last>
<RefPosition #29 @30 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] minReg=1 last>
<RefPosition #30 @30 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] minReg=1 last>
<RefPosition #31 @30 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] minReg=1 last>
<RefPosition #32 @30 RefTypeKillGCRefs CALL BB02 regmask=[eax ebx esi edi] minReg=1>
<RefPosition #33 @34 RefTypeDef <Ivl:8> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #34 @37 RefTypeUse <Ivl:8> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #35 @38 RefTypeKill <Reg:eax> BB02 regmask=[eax] minReg=1 last>
<RefPosition #36 @38 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] minReg=1 last>
<RefPosition #37 @38 RefTypeKill <Reg:edx> BB02 regmask=[edx] minReg=1 last>
<RefPosition #38 @38 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #39 @38 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] minReg=1 last>
<RefPosition #40 @38 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] minReg=1 last>
<RefPosition #41 @38 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] minReg=1 last>
<RefPosition #42 @38 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] minReg=1 last>
<RefPosition #43 @38 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] minReg=1 last>
<RefPosition #44 @38 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] minReg=1 last>
<RefPosition #45 @38 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] minReg=1 last>
<RefPosition #46 @38 RefTypeKillGCRefs CALL[0] BB02 regmask=[eax ebx esi edi] minReg=1>
<RefPosition #47 @38 RefTypeFixedReg <Reg:eax> BB02 regmask=[eax] minReg=1>
<RefPosition #48 @38 RefTypeDef <Ivl:9> CALL[0] BB02 regmask=[eax] minReg=1 fixed>
<RefPosition #49 @38 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #50 @38 RefTypeDef <Ivl:10> CALL[1] BB02 regmask=[edx] minReg=1 fixed>
<RefPosition #51 @40 RefTypeDef <Ivl:11> LCL_VAR_ADDR BB02 regmask=[ecx] minReg=1>
<RefPosition #52 @41 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #53 @41 RefTypeUse <Ivl:11> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #54 @42 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #55 @42 RefTypeDef <Ivl:12> PUTARG_REG BB02 regmask=[ecx] minReg=1 fixed>
<RefPosition #56 @47 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #57 @47 RefTypeUse <Ivl:12> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #58 @48 RefTypeKill <Reg:eax> BB02 regmask=[eax] minReg=1 last>
<RefPosition #59 @48 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] minReg=1 last>
<RefPosition #60 @48 RefTypeKill <Reg:edx> BB02 regmask=[edx] minReg=1 last>
<RefPosition #61 @48 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #62 @48 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] minReg=1 last>
<RefPosition #63 @48 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] minReg=1 last>
<RefPosition #64 @48 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] minReg=1 last>
<RefPosition #65 @48 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] minReg=1 last>
<RefPosition #66 @48 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] minReg=1 last>
<RefPosition #67 @48 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] minReg=1 last>
<RefPosition #68 @48 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] minReg=1 last>
<RefPosition #69 @49 RefTypeUse <Ivl:9> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #70 @49 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #71 @50 RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #72 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #73 @57 RefTypeUse <Ivl:3 V05> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #74 @59 RefTypeBB BB03 regmask=[] minReg=1>
-----------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional>
<RefPosition #72 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #71 @50 RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #73 @57 RefTypeUse <Ivl:3 V05> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
-----------------
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[allFloat] minReg=1 regOptional>
<RefPosition #6 @13 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
-----------------
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[allFloat] minReg=1 regOptional>
<RefPosition #5 @9 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V00 V01 V02
BB01 [???..???), preds={} succs={BB02}
=====
BB02 [000..012), preds={BB01} succs={BB03}
=====
N005. IL_OFFSET IL offset: 0x0
N007. V02(L2)
N009. PUTARG_STK [+0x00]
Use:<V02/L2>(#5) *
N011. V01(L1)
N013. PUTARG_STK [+0x04]
Use:<V01/L1>(#6) *
N015. PINVOKE_PROLOG
N017. LCL_VAR_ADDR V06 PInvokeFrame NA
Def:<I4>(#7)
N019. PUTARG_REG
Use:<I4>(#9) Fixed:ecx(#8) *
Def:<I5>(#11) ecx
N021. CNS_INT 8
Def:<I6>(#12)
N023. PUTARG_REG
Use:<I6>(#14) Fixed:edx(#13) *
Def:<I7>(#16) edx
N025. CNS_INT(h) 0x420220 ftn
N027. IND
N029. CALL help
Use:<I5>(#18) Fixed:ecx(#17) *
Use:<I7>(#20) Fixed:edx(#19) *
Kill: eax ecx edx mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7
N031. CNS_INT(h) 0x420368 ftn
N033. IND
N035. IND
N037. CALL r2r_ind
N039. LCL_VAR_ADDR V06 PInvokeFrame NA
N041. PUTARG_REG
N043. CNS_INT(h) 0x420230 ftn
N045. IND
N047. CALL help
N049. V05(L3)
N051. IL_OFFSET IL offset: 0x10
N053. V00(L0)
N055. V05(L3)
N057. STOREIND
N061. RETURN
Linear scan intervals after buildIntervals:
Interval 0: (V00) byref RefPositions {#0@0 #72@57} physReg:ecx Preferences=[ebx esi edi]
Interval 1: (V01) float RefPositions {#1@0 #6@13} physReg:NA Preferences=[allFloat]
Interval 2: (V02) float RefPositions {#2@0 #5@9} physReg:NA Preferences=[allFloat]
Interval 3: (V05) simd8 RefPositions {#71@50 #73@57} physReg:NA Preferences=[allFloat]
Interval 4: int RefPositions {#7@18 #9@19} physReg:NA Preferences=[ecx]
Interval 5: int RefPositions {#11@20 #18@29} physReg:NA Preferences=[ecx]
Interval 6: int (constant) RefPositions {#12@22 #14@23} physReg:NA Preferences=[edx]
Interval 7: int RefPositions {#16@24 #20@29} physReg:NA Preferences=[edx]
Interval 8: int RefPositions {#33@34 #34@37} physReg:NA Preferences=[allInt]
Interval 9: int RefPositions {#48@38 #69@49} physReg:NA Preferences=[eax]
Interval 10: int RefPositions {#50@38 #70@49} physReg:NA Preferences=[edx]
Interval 11: int RefPositions {#51@40 #53@41} physReg:NA Preferences=[ecx]
Interval 12: int RefPositions {#55@42 #57@47} physReg:NA Preferences=[ecx]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) byref RefPositions {#0@0 #72@57} physReg:ecx Preferences=[ebx esi edi]
Interval 1: (V01) float RefPositions {#1@0 #6@13} physReg:NA Preferences=[allFloat]
Interval 2: (V02) float RefPositions {#2@0 #5@9} physReg:NA Preferences=[allFloat]
Interval 3: (V05) simd8 RefPositions {#71@50 #73@57} physReg:NA Preferences=[allFloat]
Interval 4: int RefPositions {#7@18 #9@19} physReg:NA Preferences=[ecx]
Interval 5: int RefPositions {#11@20 #18@29} physReg:NA Preferences=[ecx]
Interval 6: int (constant) RefPositions {#12@22 #14@23} physReg:NA Preferences=[edx]
Interval 7: int RefPositions {#16@24 #20@29} physReg:NA Preferences=[edx]
Interval 8: int RefPositions {#33@34 #34@37} physReg:NA Preferences=[allInt]
Interval 9: int RefPositions {#48@38 #69@49} physReg:NA Preferences=[eax]
Interval 10: int RefPositions {#50@38 #70@49} physReg:NA Preferences=[edx]
Interval 11: int RefPositions {#51@40 #53@41} physReg:NA Preferences=[ecx]
Interval 12: int RefPositions {#55@42 #57@47} physReg:NA Preferences=[ecx]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[allFloat] minReg=1 regOptional>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[allFloat] minReg=1 regOptional>
<RefPosition #3 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #4 @3 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #5 @9 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #6 @13 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #7 @18 RefTypeDef <Ivl:4> LCL_VAR_ADDR BB02 regmask=[ecx] minReg=1>
<RefPosition #8 @19 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #9 @19 RefTypeUse <Ivl:4> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #10 @20 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #11 @20 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[ecx] minReg=1 fixed>
<RefPosition #12 @22 RefTypeDef <Ivl:6> CNS_INT BB02 regmask=[edx] minReg=1>
<RefPosition #13 @23 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #14 @23 RefTypeUse <Ivl:6> BB02 regmask=[edx] minReg=1 last fixed>
<RefPosition #15 @24 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #16 @24 RefTypeDef <Ivl:7> PUTARG_REG BB02 regmask=[edx] minReg=1 fixed>
<RefPosition #17 @29 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #18 @29 RefTypeUse <Ivl:5> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #19 @29 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #20 @29 RefTypeUse <Ivl:7> BB02 regmask=[edx] minReg=1 last fixed>
<RefPosition #21 @30 RefTypeKill <Reg:eax> BB02 regmask=[eax] minReg=1 last>
<RefPosition #22 @30 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] minReg=1 last>
<RefPosition #23 @30 RefTypeKill <Reg:edx> BB02 regmask=[edx] minReg=1 last>
<RefPosition #24 @30 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #25 @30 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] minReg=1 last>
<RefPosition #26 @30 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] minReg=1 last>
<RefPosition #27 @30 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] minReg=1 last>
<RefPosition #28 @30 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] minReg=1 last>
<RefPosition #29 @30 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] minReg=1 last>
<RefPosition #30 @30 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] minReg=1 last>
<RefPosition #31 @30 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] minReg=1 last>
<RefPosition #32 @30 RefTypeKillGCRefs CALL BB02 regmask=[eax ebx esi edi] minReg=1>
<RefPosition #33 @34 RefTypeDef <Ivl:8> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #34 @37 RefTypeUse <Ivl:8> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #35 @38 RefTypeKill <Reg:eax> BB02 regmask=[eax] minReg=1 last>
<RefPosition #36 @38 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] minReg=1 last>
<RefPosition #37 @38 RefTypeKill <Reg:edx> BB02 regmask=[edx] minReg=1 last>
<RefPosition #38 @38 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #39 @38 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] minReg=1 last>
<RefPosition #40 @38 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] minReg=1 last>
<RefPosition #41 @38 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] minReg=1 last>
<RefPosition #42 @38 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] minReg=1 last>
<RefPosition #43 @38 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] minReg=1 last>
<RefPosition #44 @38 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] minReg=1 last>
<RefPosition #45 @38 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] minReg=1 last>
<RefPosition #46 @38 RefTypeKillGCRefs CALL[0] BB02 regmask=[eax ebx esi edi] minReg=1>
<RefPosition #47 @38 RefTypeFixedReg <Reg:eax> BB02 regmask=[eax] minReg=1>
<RefPosition #48 @38 RefTypeDef <Ivl:9> CALL[0] BB02 regmask=[eax] minReg=1 fixed>
<RefPosition #49 @38 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #50 @38 RefTypeDef <Ivl:10> CALL[1] BB02 regmask=[edx] minReg=1 fixed>
<RefPosition #51 @40 RefTypeDef <Ivl:11> LCL_VAR_ADDR BB02 regmask=[ecx] minReg=1>
<RefPosition #52 @41 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #53 @41 RefTypeUse <Ivl:11> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #54 @42 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #55 @42 RefTypeDef <Ivl:12> PUTARG_REG BB02 regmask=[ecx] minReg=1 fixed>
<RefPosition #56 @47 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #57 @47 RefTypeUse <Ivl:12> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #58 @48 RefTypeKill <Reg:eax> BB02 regmask=[eax] minReg=1 last>
<RefPosition #59 @48 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] minReg=1 last>
<RefPosition #60 @48 RefTypeKill <Reg:edx> BB02 regmask=[edx] minReg=1 last>
<RefPosition #61 @48 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #62 @48 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] minReg=1 last>
<RefPosition #63 @48 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] minReg=1 last>
<RefPosition #64 @48 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] minReg=1 last>
<RefPosition #65 @48 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] minReg=1 last>
<RefPosition #66 @48 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] minReg=1 last>
<RefPosition #67 @48 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] minReg=1 last>
<RefPosition #68 @48 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] minReg=1 last>
<RefPosition #69 @49 RefTypeUse <Ivl:9> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #70 @49 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #71 @50 RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #72 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #73 @57 RefTypeUse <Ivl:3 V05> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #74 @59 RefTypeBB BB03 regmask=[] minReg=1>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[ecx] minReg=1 fixed regOptional>
<RefPosition #72 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
--- V01 (Interval 1)
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[allFloat] minReg=1 regOptional>
<RefPosition #6 @13 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
--- V02 (Interval 2)
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[allFloat] minReg=1 regOptional>
<RefPosition #5 @9 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
--- V03
--- V04
--- V05 (Interval 3)
<RefPosition #71 @50 RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #73 @57 RefTypeUse <Ivl:3 V05> LCL_VAR BB02 regmask=[allFloat] minReg=1 last>
--- V06
--- V07
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
Columns are only printed up to the last modifed register, which may increase during allocation,
in which case additional columns will appear.
Registers which are not marked modified have ---- in their column.
------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+----+
| |V0 a| | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edx |esi |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+----+----+
0.#0 V0 Parm Alloc esi | | | |V0 a| | | | | | |
0.#1 V1 Parm LoRef | | | |V0 a| | | | | | |
0.#2 V2 Parm LoRef | | | |V0 a| | | | | | |
1.#3 BB1 PredBB0 | | | |V0 a| | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edx |esi |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+----+----+
3.#4 BB2 PredBB1 | | | |V0 a| | | | | | |
9.#5 V2 Use * ReLod NA | | | |V0 a| | | | | | |
Alloc mm0 | | | |V0 a| |V2 a| | | | |
13.#6 V1 Use * ReLod NA | | | |V0 a| | | | | | |
Alloc mm0 | | | |V0 a| |V1 a| | | | |
18.#7 I4 Def Alloc ecx | |I4 a| |V0 a| | | | | | |
19.#8 ecx Fixd Keep ecx | |I4 a| |V0 a| | | | | | |
19.#9 I4 Use * Keep ecx | |I4 a| |V0 a| | | | | | |
20.#10 ecx Fixd Keep ecx | | | |V0 a| | | | | | |
20.#11 I5 Def Alloc ecx | |I5 a| |V0 a| | | | | | |
22.#12 C6 Def Alloc edx | |I5 a|C6 a|V0 a| | | | | | |
23.#13 edx Fixd Keep edx | |I5 a|C6 a|V0 a| | | | | | |
23.#14 C6 Use * Keep edx | |I5 a|C6 a|V0 a| | | | | | |
24.#15 edx Fixd Keep edx | |I5 a| |V0 a| | | | | | |
24.#16 I7 Def Alloc edx | |I5 a|I7 a|V0 a| | | | | | |
29.#17 ecx Fixd Keep ecx | |I5 a|I7 a|V0 a| | | | | | |
29.#18 I5 Use * Keep ecx | |I5 a|I7 a|V0 a| | | | | | |
29.#19 edx Fixd Keep edx | |I5 a|I7 a|V0 a| | | | | | |
29.#20 I7 Use * Keep edx | |I5 a|I7 a|V0 a| | | | | | |
30.#21 eax Kill Keep eax | | | |V0 a| | | | | | |
30.#22 ecx Kill Keep ecx | | | |V0 a| | | | | | |
30.#23 edx Kill Keep edx | | | |V0 a| | | | | | |
30.#24 mm0 Kill Keep mm0 | | | |V0 a| | | | | | |
30.#25 mm1 Kill Keep mm1 | | | |V0 a| | | | | | |
30.#26 mm2 Kill Keep mm2 | | | |V0 a| | | | | | |
30.#27 mm3 Kill Keep mm3 | | | |V0 a| | | | | | |
30.#28 mm4 Kill Keep mm4 | | | |V0 a| | | | | | |
30.#29 mm5 Kill Keep mm5 | | | |V0 a| | | | | | |
30.#30 mm6 Kill Keep mm6 | | | |V0 a| | | | | | |
30.#31 mm7 Kill Keep mm7 | | | |V0 a| | | | | | |
30.#32 KlGC Spill esi | | | | | | | | | | |
Done | | | | | | | | | | |
34.#33 I8 Def Alloc eax |I8 a| | | | | | | | | |
37.#34 I8 Use * Keep eax |I8 a| | | | | | | | | |
38.#35 eax Kill Keep eax | | | | | | | | | | |
38.#36 ecx Kill Keep ecx | | | | | | | | | | |
38.#37 edx Kill Keep edx | | | | | | | | | | |
38.#38 mm0 Kill Keep mm0 | | | | | | | | | | |
38.#39 mm1 Kill Keep mm1 | | | | | | | | | | |
38.#40 mm2 Kill Keep mm2 | | | | | | | | | | |
38.#41 mm3 Kill Keep mm3 | | | | | | | | | | |
38.#42 mm4 Kill Keep mm4 | | | | | | | | | | |
38.#43 mm5 Kill Keep mm5 | | | | | | | | | | |
38.#44 mm6 Kill Keep mm6 | | | | | | | | | | |
38.#45 mm7 Kill Keep mm7 | | | | | | | | | | |
38.#46 KlGC None | | | | | | | | | | |
38.#47 eax Fixd Keep eax | | | | | | | | | | |
38.#48 I9 Def Alloc esi | | | |I9 a| | | | | | |
38.#49 edx Fixd Keep edx | | | |I9 a| | | | | | |
38.#50 I10 Def Alloc edi | | | |I9 a|I10a| | | | | |
40.#51 I11 Def Alloc ecx | |I11a| |I9 a|I10a| | | | | |
41.#52 ecx Fixd Keep ecx | |I11a| |I9 a|I10a| | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edx |esi |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+----+----+
41.#53 I11 Use * Keep ecx | |I11a| |I9 a|I10a| | | | | |
42.#54 ecx Fixd Keep ecx | | | |I9 a|I10a| | | | | |
42.#55 I12 Def Alloc ecx | |I12a| |I9 a|I10a| | | | | |
47.#56 ecx Fixd Keep ecx | |I12a| |I9 a|I10a| | | | | |
47.#57 I12 Use * Keep ecx | |I12a| |I9 a|I10a| | | | | |
48.#58 eax Kill Keep eax | | | |I9 a|I10a| | | | | |
48.#59 ecx Kill Keep ecx | | | |I9 a|I10a| | | | | |
48.#60 edx Kill Keep edx | | | |I9 a|I10a| | | | | |
48.#61 mm0 Kill Keep mm0 | | | |I9 a|I10a| | | | | |
48.#62 mm1 Kill Keep mm1 | | | |I9 a|I10a| | | | | |
48.#63 mm2 Kill Keep mm2 | | | |I9 a|I10a| | | | | |
48.#64 mm3 Kill Keep mm3 | | | |I9 a|I10a| | | | | |
48.#65 mm4 Kill Keep mm4 | | | |I9 a|I10a| | | | | |
48.#66 mm5 Kill Keep mm5 | | | |I9 a|I10a| | | | | |
48.#67 mm6 Kill Keep mm6 | | | |I9 a|I10a| | | | | |
48.#68 mm7 Kill Keep mm7 | | | |I9 a|I10a| | | | | |
49.#69 I9 Use * Keep esi | | | |I9 a|I10a| | | | | |
49.#70 I10 Use * Keep edi | | | |I9 a|I10a| | | | | |
50.#71 V5 Def Alloc mm0 | | | | | |V5 a| | | | |
57.#72 V0 Use * ReLod NA | | | | | |V5 a| | | | |
Alloc esi | | | |V0 a| |V5 a| | | | |
57.#73 V5 Use * Keep mm0 | | | |V0 a| |V5 a| | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edx |esi |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+----+----+
59.#74 BB3 PredBB2 | | | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[] minReg=1 regOptional>
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[] minReg=1 regOptional>
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[] minReg=1 regOptional>
<RefPosition #3 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #4 @3 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #5 @9 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[mm0] minReg=1 last reload>
<RefPosition #6 @13 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[mm0] minReg=1 last reload>
<RefPosition #7 @18 RefTypeDef <Ivl:4> LCL_VAR_ADDR BB02 regmask=[ecx] minReg=1>
<RefPosition #8 @19 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #9 @19 RefTypeUse <Ivl:4> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #10 @20 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #11 @20 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[ecx] minReg=1 fixed>
<RefPosition #12 @22 RefTypeDef <Ivl:6> CNS_INT BB02 regmask=[edx] minReg=1>
<RefPosition #13 @23 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #14 @23 RefTypeUse <Ivl:6> BB02 regmask=[edx] minReg=1 last fixed>
<RefPosition #15 @24 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #16 @24 RefTypeDef <Ivl:7> PUTARG_REG BB02 regmask=[edx] minReg=1 fixed>
<RefPosition #17 @29 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #18 @29 RefTypeUse <Ivl:5> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #19 @29 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #20 @29 RefTypeUse <Ivl:7> BB02 regmask=[edx] minReg=1 last fixed>
<RefPosition #21 @30 RefTypeKill <Reg:eax> BB02 regmask=[eax] minReg=1 last>
<RefPosition #22 @30 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] minReg=1 last>
<RefPosition #23 @30 RefTypeKill <Reg:edx> BB02 regmask=[edx] minReg=1 last>
<RefPosition #24 @30 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #25 @30 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] minReg=1 last>
<RefPosition #26 @30 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] minReg=1 last>
<RefPosition #27 @30 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] minReg=1 last>
<RefPosition #28 @30 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] minReg=1 last>
<RefPosition #29 @30 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] minReg=1 last>
<RefPosition #30 @30 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] minReg=1 last>
<RefPosition #31 @30 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] minReg=1 last>
<RefPosition #32 @30 RefTypeKillGCRefs CALL BB02 regmask=[eax ebx esi edi] minReg=1>
<RefPosition #33 @34 RefTypeDef <Ivl:8> IND BB02 regmask=[eax] minReg=1>
<RefPosition #34 @37 RefTypeUse <Ivl:8> BB02 regmask=[eax] minReg=1 last>
<RefPosition #35 @38 RefTypeKill <Reg:eax> BB02 regmask=[eax] minReg=1 last>
<RefPosition #36 @38 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] minReg=1 last>
<RefPosition #37 @38 RefTypeKill <Reg:edx> BB02 regmask=[edx] minReg=1 last>
<RefPosition #38 @38 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #39 @38 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] minReg=1 last>
<RefPosition #40 @38 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] minReg=1 last>
<RefPosition #41 @38 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] minReg=1 last>
<RefPosition #42 @38 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] minReg=1 last>
<RefPosition #43 @38 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] minReg=1 last>
<RefPosition #44 @38 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] minReg=1 last>
<RefPosition #45 @38 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] minReg=1 last>
<RefPosition #46 @38 RefTypeKillGCRefs CALL[0] BB02 regmask=[eax ebx esi edi] minReg=1>
<RefPosition #47 @38 RefTypeFixedReg <Reg:eax> BB02 regmask=[eax] minReg=1>
<RefPosition #48 @38 RefTypeDef <Ivl:9> CALL[0] BB02 regmask=[esi] minReg=1 fixed>
<RefPosition #49 @38 RefTypeFixedReg <Reg:edx> BB02 regmask=[edx] minReg=1>
<RefPosition #50 @38 RefTypeDef <Ivl:10> CALL[1] BB02 regmask=[edi] minReg=1 fixed>
<RefPosition #51 @40 RefTypeDef <Ivl:11> LCL_VAR_ADDR BB02 regmask=[ecx] minReg=1>
<RefPosition #52 @41 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #53 @41 RefTypeUse <Ivl:11> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #54 @42 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #55 @42 RefTypeDef <Ivl:12> PUTARG_REG BB02 regmask=[ecx] minReg=1 fixed>
<RefPosition #56 @47 RefTypeFixedReg <Reg:ecx> BB02 regmask=[ecx] minReg=1>
<RefPosition #57 @47 RefTypeUse <Ivl:12> BB02 regmask=[ecx] minReg=1 last fixed>
<RefPosition #58 @48 RefTypeKill <Reg:eax> BB02 regmask=[eax] minReg=1 last>
<RefPosition #59 @48 RefTypeKill <Reg:ecx> BB02 regmask=[ecx] minReg=1 last>
<RefPosition #60 @48 RefTypeKill <Reg:edx> BB02 regmask=[edx] minReg=1 last>
<RefPosition #61 @48 RefTypeKill <Reg:mm0> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #62 @48 RefTypeKill <Reg:mm1> BB02 regmask=[mm1] minReg=1 last>
<RefPosition #63 @48 RefTypeKill <Reg:mm2> BB02 regmask=[mm2] minReg=1 last>
<RefPosition #64 @48 RefTypeKill <Reg:mm3> BB02 regmask=[mm3] minReg=1 last>
<RefPosition #65 @48 RefTypeKill <Reg:mm4> BB02 regmask=[mm4] minReg=1 last>
<RefPosition #66 @48 RefTypeKill <Reg:mm5> BB02 regmask=[mm5] minReg=1 last>
<RefPosition #67 @48 RefTypeKill <Reg:mm6> BB02 regmask=[mm6] minReg=1 last>
<RefPosition #68 @48 RefTypeKill <Reg:mm7> BB02 regmask=[mm7] minReg=1 last>
<RefPosition #69 @49 RefTypeUse <Ivl:9> BB02 regmask=[esi] minReg=1 last>
<RefPosition #70 @49 RefTypeUse <Ivl:10> BB02 regmask=[edi] minReg=1 last>
<RefPosition #71 @50 RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB02 regmask=[mm0] minReg=1>
<RefPosition #72 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[esi] minReg=1 last reload>
<RefPosition #73 @57 RefTypeUse <Ivl:3 V05> LCL_VAR BB02 regmask=[mm0] minReg=1 last>
<RefPosition #74 @59 RefTypeBB BB03 regmask=[] minReg=1>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[] minReg=1 regOptional>
<RefPosition #72 @57 RefTypeUse <Ivl:0 V00> LCL_VAR BB02 regmask=[esi] minReg=1 last reload>
--- V01 (Interval 1)
<RefPosition #1 @0 RefTypeParamDef <Ivl:1 V01> BB00 regmask=[] minReg=1 regOptional>
<RefPosition #6 @13 RefTypeUse <Ivl:1 V01> LCL_VAR BB02 regmask=[mm0] minReg=1 last reload>
--- V02 (Interval 2)
<RefPosition #2 @0 RefTypeParamDef <Ivl:2 V02> BB00 regmask=[] minReg=1 regOptional>
<RefPosition #5 @9 RefTypeUse <Ivl:2 V02> LCL_VAR BB02 regmask=[mm0] minReg=1 last reload>
--- V03
--- V04
--- V05 (Interval 3)
<RefPosition #71 @50 RefTypeDef <Ivl:3 V05> STORE_LCL_VAR BB02 regmask=[mm0] minReg=1>
<RefPosition #73 @57 RefTypeUse <Ivl:3 V05> LCL_VAR BB02 regmask=[mm0] minReg=1 last>
--- V06
--- V07
Active intervals at end of allocation:
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V01 V02}
Has No Critical Edges
Prior to Resolution
BB01
use def in out
{}
{}
{V00 V01 V02}
{V00 V01 V02}
Var=Reg beg of BB01: none
Var=Reg end of BB01: none
BB02
use def in out
{V00 V01 V02}
{V05}
{V00 V01 V02}
{}
Var=Reg beg of BB02: none
Var=Reg end of BB02: none
BB03
use def in out
{}
{}
{}
{}
Var=Reg beg of BB03: none
Var=Reg end of BB03: none
RESOLVING EDGES
Set V00 argument initial register to STK
Set V01 argument initial register to STK
Set V02 argument initial register to STK
Trees after linear scan register allocator (LSRA)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal LIR
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
------------ BB02 [000..012), preds={BB01} succs={BB03}
N005 (???,???) [000022] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N007 ( 3, 2) [000001] -----------z t1 = LCL_VAR float V02 arg1 u:1 mm0 (last use) REG mm0 $c1
/--* t1 float
N009 (???,???) [000025] ------------ * PUTARG_STK [+0x00] void (1 slots), (4 stackByteSize), (0 slot), (0 byteOffset) REG NA
N011 ( 3, 2) [000000] -----------z t0 = LCL_VAR float V01 arg0 u:1 mm0 (last use) REG mm0 $c0
/--* t0 float
N013 (???,???) [000026] ------------ * PUTARG_STK [+0x04] void (1 slots), (4 stackByteSize), (1 slot), (4 byteOffset) REG NA
N015 (???,???) [000027] ------------ PINVOKE_PROLOG void REG NA
N017 ( 3, 3) [000028] ------------ t28 = LCL_VAR_ADDR int V06 PInvokeFrame ecx REG ecx
/--* t28 int
N019 (???,???) [000033] ------------ t33 = * PUTARG_REG int REG ecx
N021 ( 1, 1) [000029] ------------ t29 = CNS_INT int 8 REG edx
/--* t29 int
N023 (???,???) [000034] ------------ t34 = * PUTARG_REG int REG edx
N025 ( 1, 4) [000035] Hc---------- t35 = CNS_INT(h) int 0x420220 ftn REG NA
/--* t35 int
N027 ( 3, 6) [000036] -c---------- t36 = * IND int REG NA
/--* t33 int arg0 in ecx
+--* t34 int arg1 in edx
+--* t36 int control expr
N029 ( 18, 11) [000030] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN REG NA
N031 ( 1, 4) [000037] Hc---------- t37 = CNS_INT(h) int 0x420368 ftn REG NA
/--* t37 int
N033 ( 3, 6) [000038] ------------ t38 = * IND int REG eax
/--* t38 int
N035 ( 6, 8) [000039] -c---------- t39 = * IND int REG NA
/--* t39 int control expr
N037 ( 26, 9) [000002] --CXG------- t2 = * CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats REG esi,edi $180
N039 ( 3, 3) [000040] ------------ t40 = LCL_VAR_ADDR int V06 PInvokeFrame ecx REG ecx
/--* t40 int
N041 (???,???) [000043] ------------ t43 = * PUTARG_REG int REG ecx
N043 ( 1, 4) [000044] Hc---------- t44 = CNS_INT(h) int 0x420230 ftn REG NA
/--* t44 int
N045 ( 3, 6) [000045] -c---------- t45 = * IND int REG NA
/--* t43 int arg0 in ecx
+--* t45 int control expr
N047 ( 17, 9) [000041] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END REG NA
/--* t2 struct
N049 ( 30, 12) [000005] DA-XG------- * STORE_LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2 mm0 REG mm0
N051 (???,???) [000023] ------------ IL_OFFSET void IL offset: 0x10 REG NA
N053 ( 1, 1) [000016] -----------z t16 = LCL_VAR byref V00 RetBuf u:1 esi (last use) REG esi $80
N055 ( 3, 2) [000015] ------------ t15 = LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 u:2 mm0 (last use) REG mm0 $240
/--* t16 byref
+--* t15 simd8
N057 (???,???) [000024] -A-XG------- * STOREIND simd8 REG NA
------------ BB03 [???..???) (return), preds={BB02} succs={}
N061 ( 0, 0) [000021] ------------ RETURN void REG NA $280
-------------------------------------------------------------------------------------------------------------------
Final allocation
------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edx |esi |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+----+----+
0.#0 V0 Parm NoReg | | | | | | | | | | |
0.#1 V1 Parm NoReg | | | | | | | | | | |
0.#2 V2 Parm NoReg | | | | | | | | | | |
1.#3 BB1 PredBB0 | | | | | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edx |esi |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+----+----+
3.#4 BB2 PredBB1 | | | | | | | | | | |
9.#5 V2 Use * ReLod mm0 | | | | | |V2 a| | | | |
Keep mm0 | | | | | |V2 i| | | | |
13.#6 V1 Use * ReLod mm0 | | | | | |V1 a| | | | |
Keep mm0 | | | | | |V1 i| | | | |
18.#7 I4 Def Alloc ecx | |I4 a| | | | | | | | |
19.#8 ecx Fixd Keep ecx | |I4 a| | | | | | | | |
19.#9 I4 Use * Keep ecx | |I4 i| | | | | | | | |
20.#10 ecx Fixd Keep ecx | | | | | | | | | | |
20.#11 I5 Def Alloc ecx | |I5 a| | | | | | | | |
22.#12 C6 Def Alloc edx | |I5 a|C6 a| | | | | | | |
23.#13 edx Fixd Keep edx | |I5 a|C6 a| | | | | | | |
23.#14 C6 Use * Keep edx | |I5 a|C6 i| | | | | | | |
24.#15 edx Fixd Keep edx | |I5 a| | | | | | | | |
24.#16 I7 Def Alloc edx | |I5 a|I7 a| | | | | | | |
29.#17 ecx Fixd Keep ecx | |I5 a|I7 a| | | | | | | |
29.#18 I5 Use * Keep ecx | |I5 i|I7 a| | | | | | | |
29.#19 edx Fixd Keep edx | | |I7 a| | | | | | | |
29.#20 I7 Use * Keep edx | | |I7 i| | | | | | | |
30.#21 eax Kill Keep eax | | | | | | | | | | |
30.#22 ecx Kill Keep ecx | | | | | | | | | | |
30.#23 edx Kill Keep edx | | | | | | | | | | |
30.#24 mm0 Kill Keep mm0 | | | | | | | | | | |
30.#25 mm1 Kill Keep mm1 | | | | | | | | | | |
30.#26 mm2 Kill Keep mm2 | | | | | | | | | | |
30.#27 mm3 Kill Keep mm3 | | | | | | | | | | |
30.#28 mm4 Kill Keep mm4 | | | | | | | | | | |
30.#29 mm5 Kill Keep mm5 | | | | | | | | | | |
30.#30 mm6 Kill Keep mm6 | | | | | | | | | | |
30.#31 mm7 Kill Keep mm7 | | | | | | | | | | |
| | | | | | | | | | |
34.#33 I8 Def Alloc eax |I8 a| | | | | | | | | |
37.#34 I8 Use * Keep eax |I8 i| | | | | | | | | |
38.#35 eax Kill Keep eax | | | | | | | | | | |
38.#36 ecx Kill Keep ecx | | | | | | | | | | |
38.#37 edx Kill Keep edx | | | | | | | | | | |
38.#38 mm0 Kill Keep mm0 | | | | | | | | | | |
38.#39 mm1 Kill Keep mm1 | | | | | | | | | | |
38.#40 mm2 Kill Keep mm2 | | | | | | | | | | |
38.#41 mm3 Kill Keep mm3 | | | | | | | | | | |
38.#42 mm4 Kill Keep mm4 | | | | | | | | | | |
38.#43 mm5 Kill Keep mm5 | | | | | | | | | | |
38.#44 mm6 Kill Keep mm6 | | | | | | | | | | |
38.#45 mm7 Kill Keep mm7 | | | | | | | | | | |
| | | | | | | | | | |
38.#47 eax Fixd Keep eax | | | | | | | | | | |
38.#48 I9 Def Alloc esi | | | |I9 a| | | | | | |
38.#49 edx Fixd Keep edx | | | |I9 a| | | | | | |
38.#50 I10 Def Alloc edi | | | |I9 a|I10a| | | | | |
40.#51 I11 Def Alloc ecx | |I11a| |I9 a|I10a| | | | | |
41.#52 ecx Fixd Keep ecx | |I11a| |I9 a|I10a| | | | | |
41.#53 I11 Use * Keep ecx | |I11i| |I9 a|I10a| | | | | |
42.#54 ecx Fixd Keep ecx | | | |I9 a|I10a| | | | | |
42.#55 I12 Def Alloc ecx | |I12a| |I9 a|I10a| | | | | |
47.#56 ecx Fixd Keep ecx | |I12a| |I9 a|I10a| | | | | |
47.#57 I12 Use * Keep ecx | |I12i| |I9 a|I10a| | | | | |
48.#58 eax Kill Keep eax | | | |I9 a|I10a| | | | | |
48.#59 ecx Kill Keep ecx | | | |I9 a|I10a| | | | | |
48.#60 edx Kill Keep edx | | | |I9 a|I10a| | | | | |
48.#61 mm0 Kill Keep mm0 | | | |I9 a|I10a| | | | | |
48.#62 mm1 Kill Keep mm1 | | | |I9 a|I10a| | | | | |
48.#63 mm2 Kill Keep mm2 | | | |I9 a|I10a| | | | | |
48.#64 mm3 Kill Keep mm3 | | | |I9 a|I10a| | | | | |
48.#65 mm4 Kill Keep mm4 | | | |I9 a|I10a| | | | | |
48.#66 mm5 Kill Keep mm5 | | | |I9 a|I10a| | | | | |
48.#67 mm6 Kill Keep mm6 | | | |I9 a|I10a| | | | | |
48.#68 mm7 Kill Keep mm7 | | | |I9 a|I10a| | | | | |
49.#69 I9 Use * Keep esi | | | |I9 i|I10a| | | | | |
49.#70 I10 Use * Keep edi | | | | |I10i| | | | | |
50.#71 V5 Def Alloc mm0 | | | | | |V5 a| | | | |
57.#72 V0 Use * ReLod esi | | | |V0 a| |V5 a| | | | |
Keep esi | | | |V0 i| |V5 a| | | | |
57.#73 V5 Use * Keep mm0 | | | | | |V5 i| | | | |
------------------------------+----+----+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edx |esi |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+----+----+
59.#74 BB3 PredBB2 | | | | | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 4
Total Reg Cand Vars: 4
Total number of Intervals: 12
Total number of RefPositions: 74
Total Number of spill temps created: 0
..........
BB00 [ 100.00]: SpillCount = 1, REG_ORDER = 1
BB02 [ 100.00]: THIS_ASSIGNED = 1, COVERS = 1, REG_ORDER = 6
..........
Total SpillCount : 1 Weighted: 100.000000
Total CopyReg : 0 Weighted: 0.000000
Total ResolutionMovs : 0 Weighted: 0.000000
Total SplitEdges : 0 Weighted: 0.000000
..........
Total THIS_ASSIGNED [# 3] : 1 Weighted: 100.000000
Total COVERS [# 4] : 1 Weighted: 100.000000
Total REG_ORDER [#13] : 7 Weighted: 700.000000
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V00(ecx=>STK) V01(STK) V02(STK)
BB01 [???..???), preds={} succs={BB02}
=====
Var=Reg end of BB01: none
BB02 [000..012), preds={BB01} succs={BB03}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB02: none
N005. IL_OFFSET IL offset: 0x0
N007. V02(mm0*)R
N009. PUTARG_STK [+0x00]; mm0*
N011. V01(mm0*)R
N013. PUTARG_STK [+0x04]; mm0*
N015. PINVOKE_PROLOG
N017. ecx = LCL_VAR_ADDR V06 PInvokeFrame ecx
N019. ecx = PUTARG_REG; ecx
N021. edx = CNS_INT 8
N023. edx = PUTARG_REG; edx
N025. CNS_INT(h) 0x420220 ftn
N027. IND
N029. CALL help; ecx,edx
N031. CNS_INT(h) 0x420368 ftn
N033. eax = IND
N035. STK = IND ; eax
N037. esi,edi = CALL r2r_ind; STK
N039. ecx = LCL_VAR_ADDR V06 PInvokeFrame ecx
N041. ecx = PUTARG_REG; ecx
N043. CNS_INT(h) 0x420230 ftn
N045. IND
N047. CALL help; ecx
* N049. V05(mm0); esi,edi
N051. IL_OFFSET IL offset: 0x10
N053. V00(esi*)R
N055. V05(mm0*)
N057. STOREIND ; esi*,mm0*
Var=Reg end of BB02: none
BB03 [???..???) (return), preds={BB02} succs={}
=====
Predecessor for variable locations: BB02
Var=Reg beg of BB03: none
N061. RETURN
Var=Reg end of BB03: none
*************** Finishing PHASE Linear scan register alloc
*************** In genGenerateCode()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal LIR
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
<none>
Modified regs: [eax ecx edx esi edi mm0-mm7]
Marking regs modified: [ebx esi edi] ([eax ecx edx esi edi mm0-mm7] => [eax ecx edx ebx esi edi mm0-mm7])
Callee-saved registers pushed: 3 [ebx esi edi]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V07 EHSlots, size=16, stkOffs=-0x28
Assign V00 RetBuf, size=4, stkOffs=-0x2c
Assign V06 PInvokeFrame, size=44, stkOffs=-0x58
--- delta bump 4 for RA
--- delta bump 4 for FP
--- virtual stack offset to actual stack offset delta is 8
-- V00 was -44, now -36
-- V01 was 4, now 12
-- V02 was 0, now 8
-- V06 was -88, now -80
-- V07 was -40, now -32
; Final local variable assignments
;
; V00 RetBuf [V00,T00] ( 3, 3 ) byref -> [ebp-24H]
; V01 arg0 [V01,T02] ( 1, 1 ) float -> [ebp+0CH]
; V02 arg1 [V02,T03] ( 1, 1 ) float -> [ebp+08H]
;* V03 loc0 [V03 ] ( 0, 0 ) simd8 -> zero-ref
;* V04 loc1 [V04 ] ( 0, 0 ) simd8 -> zero-ref
; V05 loc2 [V05,T01] ( 2, 4 ) simd8 -> mm0 multireg-ret "Return value temp for multireg return"
; V06 PInvokeFrame [V06 ] ( 3, 3 ) blk (44) [ebp-50H] do-not-enreg[X] addr-exposed "Pinvoke FrameVar"
; V07 EHSlots [V07 ] ( 1, 1 ) blk (16) [ebp-20H] do-not-enreg[X] must-init addr-exposed "lvaShadowSPslotsVar"
;
; Lcl frame size = 68
Mark labels for codegen
BB01 : first block
*************** After genMarkLabelsForCodegen()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0005] 1 1 [???..???) keep i internal label LIR
BB02 [0000] 1 BB01 1 [000..012) keep i hascall gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???) (return) keep internal gcsafe LIR
-----------------------------------------------------------------------------------------------------------------------------------------
Setting stack level from -572662307 to 0
=============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x00000000.20010070: keep i internal label LIR
BB01 IN (3)={V00 V01 V02} + ByrefExposed + GcHeap
OUT(3)={V00 V01 V02} + ByrefExposed + GcHeap
Recording Var Locations at start of BB01
<none>
Change life 0000000000000000 {} -> 000000000000000D {V00 V01 V02}
V00 becoming live
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M61568_BB01:
Mapped BB01 to G_M61568_IG02
Label: IG02, GCvars=0000000000000001 {V00}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB01, IL range [???..???)
Scope info: ignoring block beginning
Scope info: end block BB01, IL range [???..???)
Scope info: ignoring block end
=============== Generating BB02 [000..012), preds={BB01} succs={BB03} flags=0x00000002.20080030: keep i hascall gcsafe LIR
BB02 IN (3)={V00 V01 V02} + ByrefExposed + GcHeap
OUT(0)={ }
Recording Var Locations at start of BB02
<none>
Liveness not changing: 000000000000000D {V00 V01 V02}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M61568_BB02:
Scope info: begin block BB02, IL range [000..012)
Scope info: open scopes =
0 (V00 RetBuf) [000..012)
1 (V01 arg0) [000..012)
2 (V02 arg1) [000..012)
Added IP mapping: 0x0000 STACK_EMPTY (G_M61568_IG02,ins#0,ofs#0) label
Generating: N005 (???,???) [000022] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N007 ( 3, 2) [000001] -----------z t1 = LCL_VAR float V02 arg1 u:1 mm0 (last use) REG mm0 $c1
/--* t1 float
Generating: N009 (???,???) [000025] ------------ * PUTARG_STK [+0x00] void (1 slots), (4 stackByteSize), (0 slot), (0 byteOffset) REG NA
IN0001: movss xmm0, dword ptr [V02 ebp+08H]
V02 in reg mm0 is becoming live [000001]
Live regs: 00000000 {} => 00000000 {xmm0}
V02 in reg mm0 is becoming dead [000001]
Live regs: 00000000 {xmm0} => 00000000 {}
Live vars: {V00 V01 V02} => {V00 V01}
IN0002: sub esp, 4
Upping emitMaxStackDepth from 0 to 4
IN0003: movss dword ptr [esp], xmm0
Adjusting stack level from 0 to 4
Generating: N011 ( 3, 2) [000000] -----------z t0 = LCL_VAR float V01 arg0 u:1 mm0 (last use) REG mm0 $c0
/--* t0 float
Generating: N013 (???,???) [000026] ------------ * PUTARG_STK [+0x04] void (1 slots), (4 stackByteSize), (1 slot), (4 byteOffset) REG NA
IN0004: movss xmm0, dword ptr [V01 ebp+0CH]
V01 in reg mm0 is becoming live [000000]
Live regs: 00000000 {} => 00000000 {xmm0}
V01 in reg mm0 is becoming dead [000000]
Live regs: 00000000 {xmm0} => 00000000 {}
Live vars: {V00 V01} => {V00}
IN0005: sub esp, 4
Upping emitMaxStackDepth from 4 to 8
IN0006: movss dword ptr [esp], xmm0
Adjusting stack level from 4 to 8
Generating: N015 (???,???) [000027] ------------ PINVOKE_PROLOG void REG NA
Generating: N017 ( 3, 3) [000028] ------------ t28 = LCL_VAR_ADDR int V06 PInvokeFrame ecx REG ecx
IN0007: lea ecx, [V06 ebp-50H]
/--* t28 int
Generating: N019 (???,???) [000033] ------------ t33 = * PUTARG_REG int REG ecx
Generating: N021 ( 1, 1) [000029] ------------ t29 = CNS_INT int 8 REG edx
IN0008: mov edx, 8
/--* t29 int
Generating: N023 (???,???) [000034] ------------ t34 = * PUTARG_REG int REG edx
Generating: N025 ( 1, 4) [000035] Hc---------- t35 = CNS_INT(h) int 0x420220 ftn REG NA
/--* t35 int
Generating: N027 ( 3, 6) [000036] -c---------- t36 = * IND int REG NA
/--* t33 int arg0 in ecx
+--* t34 int arg1 in edx
+--* t36 int control expr
Generating: N029 ( 18, 11) [000030] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN REG NA
New Basic Block BB04 [0007] created.
Mark BB04 as label: codegen temp block
L_M61568_BB04:
G_M61568_IG02: ; offs=000000H, funclet=00, bbWeight=1
Mapped BB04 to G_M61568_IG03
Label: IG03, GCvars=0000000000000001 {V00}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Call: GCvars=0000000000000001 {V00}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0009: call [CORINFO_HELP_JIT_PINVOKE_BEGIN]
Generating: N031 ( 1, 4) [000037] Hc---------- t37 = CNS_INT(h) int 0x420368 ftn REG NA
/--* t37 int
Generating: N033 ( 3, 6) [000038] ------------ t38 = * IND int REG eax
IN000a: mov eax, dword ptr [(reloc 0x4000000000420368)]
/--* t38 int
Generating: N035 ( 6, 8) [000039] -c---------- t39 = * IND int REG NA
/--* t39 int control expr
Generating: N037 ( 26, 9) [000002] --CXG------- t2 = * CALL r2r_ind struct Vector2_3_4TestNative.CreateVector2FromFloats REG esi,edi $180
New Basic Block BB05 [0008] created.
Mark BB05 as label: codegen temp block
L_M61568_BB05:
G_M61568_IG03: ; offs=000022H, funclet=00, bbWeight=1
Mapped BB05 to G_M61568_IG04
Label: IG04, GCvars=0000000000000001 {V00}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Call: GCvars=0000000000000001 {V00}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN000b: call dword ptr [eax]Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2
IN000c: mov esi, eax
IN000d: mov edi, edx
Adjusting stack level from 8 to 0
Generating: N039 ( 3, 3) [000040] ------------ t40 = LCL_VAR_ADDR int V06 PInvokeFrame ecx REG ecx
IN000e: lea ecx, [V06 ebp-50H]
/--* t40 int
Generating: N041 (???,???) [000043] ------------ t43 = * PUTARG_REG int REG ecx
Generating: N043 ( 1, 4) [000044] Hc---------- t44 = CNS_INT(h) int 0x420230 ftn REG NA
/--* t44 int
Generating: N045 ( 3, 6) [000045] -c---------- t45 = * IND int REG NA
/--* t43 int arg0 in ecx
+--* t45 int control expr
Generating: N047 ( 17, 9) [000041] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END REG NA
Call: GCvars=0000000000000001 {V00}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN000f: call [CORINFO_HELP_JIT_PINVOKE_END]
/--* t2 struct
Generating: N049 ( 30, 12) [000005] DA-XG------- * STORE_LCL_VAR simd8 <System.Numerics.Vector2> V05 loc2 d:2 mm0 REG mm0
D:\git\runtime2\src\coreclr\jit\codegenxarch.cpp:1983
Assertion failed '!"Multireg store to SIMD reg not supported on X64 Windows"' in 'Vector2_3_4TestNative:CreateVector2FromFloats(float,float):System.Numerics.Vector2' during 'Generate code' (IL size 18)
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