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trylek/CG2-ReadFile-NGenDump.log

Created April 13, 2020 16:58
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ReadFile NGenDump from Crossgen2
Raw
CG2-ReadFile-NGenDump.log
D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\corerun.exe D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\crossgen2\crossgen2.dll @D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\framework-r2r.dll.rsp
<<<<
****** START compiling Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int (MethodHash=c1f39be0)
Generating code for Windows x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = true
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Jit invoked for ngen
IL to import:
IL_0000 02 ldarg.0
IL_0001 12 03 ldloca.s 0x3
IL_0003 28 01 00 00 0a call 0xA000001
IL_0008 02 ldarg.0
IL_0009 28 02 00 00 0a call 0xA000002
IL_000e 0c stloc.2
IL_000f 05 ldarg.3
IL_0010 13 05 stloc.s 0x5
IL_0012 11 05 ldloc.s 0x5
IL_0014 d3 conv.i
IL_0015 13 04 stloc.s 0x4
IL_0017 08 ldloc.2
IL_0018 03 ldarg.1
IL_0019 04 ldarg.2
IL_001a 11 04 ldloc.s 0x4
IL_001c fe 09 04 00 ldarg 0x4
IL_0020 28 04 00 00 0a call 0xA000004
IL_0025 28 05 00 00 0a call 0xA000005
IL_002a 28 06 00 00 0a call 0xA000006
IL_002f 0b stloc.1
IL_0030 07 ldloc.1
IL_0031 0a stloc.0
IL_0032 dd 0d 00 00 00 leave 13 (IL_0044)
IL_0037 09 ldloc.3
IL_0038 39 06 00 00 00 brfalse 6 (IL_0043)
IL_003d 02 ldarg.0
IL_003e 28 03 00 00 0a call 0xA000003
IL_0043 dc endfinally
IL_0044 06 ldloc.0
IL_0045 2a ret
lvaSetClass: setting class for V00 to (0000000000420030) [S.P.CoreLib]System.Runtime.InteropServices.SafeHandle
Arg #0 passed in register(s) rcx
Arg #1 passed in register(s) rdx
Arg #2 passed in register(s) r8
Arg #3 passed in register(s) r9
Setting lvPinned for V10
lvaGrabTemp returning 11 (V11 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 arg0 ref class-hnd
; V01 arg1 long
; V02 arg2 int
; V03 arg3 byref
; V04 arg4 long
; V05 loc0 int
; V06 loc1 int
; V07 loc2 long
; V08 loc3 bool
; V09 loc4 long
; V10 loc5 byref pinned
; V11 OutArgs lclBlk <na> "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 11
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 046h
1: 01h 01h V01 arg1 000h 046h
2: 02h 02h V02 arg2 000h 046h
3: 03h 03h V03 arg3 000h 046h
4: 04h 04h V04 arg4 000h 046h
5: 05h 05h V05 loc0 000h 046h
6: 06h 06h V06 loc1 000h 046h
7: 07h 07h V07 loc2 000h 046h
8: 08h 08h V08 loc3 000h 046h
9: 09h 09h V09 loc4 000h 046h
10: 0Ah 0Ah V10 loc5 000h 046h
New Basic Block BB01 [0000] created.
New scratch BB01
Debuggable code - Add new BB01 [0000] to perform initialization of variables
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE )
*************** In fgFindBasicBlocks() for Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int
Marked V05 as a single def local
Marked V06 as a single def local
Marked V07 as a single def local
Marked V09 as a single def local
Marked V10 as a single def local
Jump targets:
IL_0000
IL_0037
IL_0043
IL_0044
New Basic Block BB02 [0001] created.
BB02 [000..037)
New Basic Block BB03 [0002] created.
BB03 [037..03D)
New Basic Block BB04 [0003] created.
BB04 [03D..043)
New Basic Block BB05 [0004] created.
BB05 [043..044)
New Basic Block BB06 [0005] created.
BB06 [044..046)
EH clause #0:
Flags: 0x2 (finally)
TryOffset: 0x0
TryLength: 0x37
HandlerOffset: 0x37
HandlerLength: 0xd
ClassToken: 0x0
*************** After fgFindBasicBlocks() has created the EH table
*************** Exception Handling table
index eTry, eHnd
0 :: - Try at BB02..BB02 [000..037), Finally at BB03..BB05 [037..044)
*************** In fgNormalizeEH()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal
BB02 [0001] 1 0 1 [000..037)-> BB06 (leave ) T0 try { } keep try label
BB03 [0002] 1 0 1 [037..03D)-> BB05 ( cond ) H0 finally { keep label target
BB04 [0003] 1 0 1 [03D..043) H0
BB05 [0004] 2 0 1 [043..044) (finret) H0 }
BB06 [0005] 1 1 [044..046) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index eTry, eHnd
0 :: - Try at BB02..BB02 [000..037), Finally at BB03..BB05 [037..044)
No EH normalization performed.
INLINER: during 'prejit' result 'failed this callee' reason 'has exception handling' for 'n/a' calling 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
INLINER: Marking Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int as NOINLINE because of has exception handling
INLINER: during 'prejit' result 'failed this callee' reason 'has exception handling'
CLFLG_MINOPT set for method Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int
IL Code Size,Instr 70, 30, Basic Block count 6, Local Variable Num,Ref count 12, 19 for method Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int
OPTIONS: opts.MinOpts() == true
Basic block list for 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal
BB02 [0001] 1 0 1 [000..037)-> BB06 (leave ) T0 try { } keep try label
BB03 [0002] 1 0 1 [037..03D)-> BB05 ( cond ) H0 finally { keep label target
BB04 [0003] 1 0 1 [03D..043) H0
BB05 [0004] 2 0 1 [043..044) (finret) H0 }
BB06 [0005] 1 1 [044..046) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
Compiling 0 Kernel32::ReadFile, IL size = 70, hash=0xc1f39be0 MinOpts
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
*************** Starting PHASE Importation
*************** In impImport() for Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int
Marking leading BBF_INTERNAL block BB01 as BBF_IMPORTED
impImportBlockPending for BB02
impImportBlockPending for BB03
Importing BB02 (PC=000) of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldloca.s 3
[ 2] 3 (0x003) call 0A000001
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
STMT00001 (IL 0x000... ???)
[000004] --C-G------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
[000001] ------------ this in rcx +--* LCL_VAR ref V00 arg0
[000003] ------------ arg1 \--* ADDR byref
[000002] ------------ \--* LCL_VAR int V08 loc3
[ 0] 8 (0x008) ldarg.0
[ 1] 9 (0x009) call 0A000002
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
lvaGrabTemp returning 12 (V12 tmp1) called for impSpillStackEnsure.
STMT00002 (IL 0x008... ???)
[000008] -AC-G------- * ASG long
[000007] D------N---- +--* LCL_VAR long V12 tmp1
[000006] --C-G------- \--* CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
[000005] ------------ this in rcx \--* LCL_VAR ref V00 arg0
[ 1] 14 (0x00e) stloc.2
STMT00003 (IL 0x00E... ???)
[000011] -A---------- * ASG long
[000010] D------N---- +--* LCL_VAR long V07 loc2
[000009] ------------ \--* LCL_VAR long V12 tmp1
[ 0] 15 (0x00f) ldarg.3
[ 1] 16 (0x010) stloc.s 5
STMT00004 (IL 0x00F... ???)
[000014] -A---------- * ASG byref
[000013] D------N---- +--* LCL_VAR byref V10 loc5
[000012] ------------ \--* LCL_VAR byref V03 arg3
[ 0] 18 (0x012) ldloc.s 5
[ 1] 20 (0x014) conv.i
[ 1] 21 (0x015) stloc.s 4
STMT00005 (IL 0x012... ???)
[000018] -A---------- * ASG long
[000017] D------N---- +--* LCL_VAR long V09 loc4
[000016] ------------ \--* CAST long <- byref
[000015] ------------ \--* LCL_VAR byref V10 loc5
[ 0] 23 (0x017) ldloc.2
[ 1] 24 (0x018) ldarg.1
[ 2] 25 (0x019) ldarg.2
[ 3] 26 (0x01a) ldloc.s 4
[ 4] 28 (0x01c) ldarg 4
[ 5] 32 (0x020) call 0A000004
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
STMT00006 (IL 0x017... ???)
[000024] --C-G------- * CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError
[ 5] 37 (0x025) call 0A000005
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
Inline a CALLI PINVOKE call from method Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int
lvaGrabTemp returning 13 (V13 tmp2) called for impSpillStackEnsure.
STMT00007 (IL 0x025... ???)
[000027] -AC-G------- * ASG int
[000026] D------N---- +--* LCL_VAR int V13 tmp2
[000025] --C-G------- \--* CALL r2r_ind int Kernel32.ReadFile
[000019] ------------ arg0 +--* LCL_VAR long V07 loc2
[000020] ------------ arg1 +--* LCL_VAR long V01 arg1
[000021] ------------ arg2 +--* LCL_VAR int V02 arg2
[000022] ------------ arg3 +--* LCL_VAR long V09 loc4
[000023] ------------ arg4 \--* LCL_VAR long V04 arg4
[ 1] 42 (0x02a) call 0A000006
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
STMT00008 (IL 0x02A... ???)
[000029] --C-G------- * CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError
[ 1] 47 (0x02f) stloc.1
STMT00009 (IL 0x02F... ???)
[000031] -A---------- * ASG int
[000030] D------N---- +--* LCL_VAR int V06 loc1
[000028] ------------ \--* LCL_VAR int V13 tmp2
[ 0] 48 (0x030) ldloc.1
[ 1] 49 (0x031) stloc.0
STMT00010 (IL 0x030... ???)
[000034] -A---------- * ASG int
[000033] D------N---- +--* LCL_VAR int V05 loc0
[000032] ------------ \--* LCL_VAR int V06 loc1
[ 0] 50 (0x032) leave 0044
Before import CEE_LEAVE in BB02 (targetting BB06):
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal
BB02 [0001] 1 0 1 [000..037)-> BB06 (leave ) T0 try { } keep try label
BB03 [0002] 1 0 1 [037..03D)-> BB05 ( cond ) H0 finally { keep label target
BB04 [0003] 1 0 1 [03D..043) H0
BB05 [0004] 2 0 1 [043..044) (finret) H0 }
BB06 [0005] 1 1 [044..046) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index eTry, eHnd
0 :: - Try at BB02..BB02 [000..037), Finally at BB03..BB05 [037..044)
fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB02, jumpBlk=BB00, runRarely=false)
fgNewBBinRegion(jumpKind=8, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB02
New Basic Block BB07 [0006] created.
impImportLeave - jumping out of a finally-protected try (EH#0), convert block BB02 to BBJ_ALWAYS, add BBJ_CALLFINALLY block BB07
New Basic Block BB08 [0007] created.
impImportLeave - jumping out of a finally-protected try (EH#0), created step (BBJ_ALWAYS) block BB08
impImportLeave - final destination of step blocks set to BB06
impImportBlockPending for BB06
After import CEE_LEAVE:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal
BB02 [0001] 1 0 1 [000..037)-> BB07 (always) T0 try { } keep try label
BB07 [0006] 1 1 [???..???)-> BB03 (callf ) i internal
BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP
BB03 [0002] 1 0 1 [037..03D)-> BB05 ( cond ) H0 finally { keep label target
BB04 [0003] 1 0 1 [03D..043) H0
BB05 [0004] 2 0 1 [043..044) (finret) H0 }
BB06 [0005] 1 1 [044..046) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index eTry, eHnd
0 :: - Try at BB02..BB02 [000..037), Finally at BB03..BB05 [037..044)
STMT00011 (IL 0x032... ???)
[000035] ------------ * NOP void
impImportBlockPending for BB07
Importing BB06 (PC=068) of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
[ 0] 68 (0x044) ldloc.0
[ 1] 69 (0x045) ret
STMT00012 (IL 0x044... ???)
[000037] ------------ * RETURN int
[000036] ------------ \--* LCL_VAR int V05 loc0
Importing BB03 (PC=055) of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
[ 0] 55 (0x037) ldloc.3
[ 1] 56 (0x038) brfalse
STMT00013 (IL 0x037... ???)
[000041] ------------ * JTRUE void
[000040] ------------ \--* EQ int
[000038] ------------ +--* LCL_VAR int V08 loc3
[000039] ------------ \--* CNS_INT int 0
impImportBlockPending for BB04
impImportBlockPending for BB05
Importing BB05 (PC=067) of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
[ 0] 67 (0x043) endfinally
STMT00014 (IL 0x043... ???)
[000042] ------------ * RETFILT void
Importing BB04 (PC=061) of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
[ 0] 61 (0x03d) ldarg.0
[ 1] 62 (0x03e) call 0A000003
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
STMT00015 (IL 0x03D... ???)
[000044] --C-G------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
[000043] ------------ this in rcx \--* LCL_VAR ref V00 arg0
impImportBlockPending for BB05
After impImport() added block for try,catch,finally
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal
BB02 [0001] 1 0 1 [000..037)-> BB07 (always) T0 try { } keep i try label
BB07 [0006] 1 1 [???..???)-> BB03 (callf ) i internal
BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP
BB03 [0002] 1 0 1 [037..03D)-> BB05 ( cond ) H0 finally { keep i label target
BB04 [0003] 1 0 1 [03D..043) H0 i
BB05 [0004] 2 0 1 [043..044) (finret) H0 } i
BB06 [0005] 1 1 [044..046) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Importation
Trees after Importation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) i internal
BB02 [0001] 1 0 1 [000..037)-> BB07 (always) T0 try { } keep i try label
BB07 [0006] 1 1 [???..???)-> BB03 (callf ) i internal
BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP
BB03 [0002] 1 0 1 [037..03D)-> BB05 ( cond ) H0 finally { keep i label target
BB04 [0003] 1 0 1 [03D..043) H0 i
BB05 [0004] 2 0 1 [043..044) (finret) H0 } i
BB06 [0005] 1 1 [044..046) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
***** BB01
STMT00000 (IL ???... ???)
[000000] ------------ * NOP void
------------ BB02 [000..037) -> BB07 (always), preds={} succs={BB07}
***** BB02
STMT00001 (IL 0x000...0x00E)
[000004] --C-G------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
[000001] ------------ this in rcx +--* LCL_VAR ref V00 arg0
[000003] ------------ arg1 \--* ADDR byref
[000002] ------------ \--* LCL_VAR int V08 loc3
***** BB02
STMT00002 (IL 0x008... ???)
[000008] -AC-G------- * ASG long
[000007] D------N---- +--* LCL_VAR long V12 tmp1
[000006] --C-G------- \--* CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
[000005] ------------ this in rcx \--* LCL_VAR ref V00 arg0
***** BB02
STMT00003 (IL 0x00E... ???)
[000011] -A---------- * ASG long
[000010] D------N---- +--* LCL_VAR long V07 loc2
[000009] ------------ \--* LCL_VAR long V12 tmp1
***** BB02
STMT00004 (IL 0x00F...0x010)
[000014] -A---------- * ASG byref
[000013] D------N---- +--* LCL_VAR byref V10 loc5
[000012] ------------ \--* LCL_VAR byref V03 arg3
***** BB02
STMT00005 (IL 0x012...0x015)
[000018] -A---------- * ASG long
[000017] D------N---- +--* LCL_VAR long V09 loc4
[000016] ------------ \--* CAST long <- byref
[000015] ------------ \--* LCL_VAR byref V10 loc5
***** BB02
STMT00006 (IL 0x017...0x02F)
[000024] --C-G------- * CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError
***** BB02
STMT00007 (IL 0x025... ???)
[000027] -AC-G------- * ASG int
[000026] D------N---- +--* LCL_VAR int V13 tmp2
[000025] --C-G------- \--* CALL r2r_ind int Kernel32.ReadFile
[000019] ------------ arg0 +--* LCL_VAR long V07 loc2
[000020] ------------ arg1 +--* LCL_VAR long V01 arg1
[000021] ------------ arg2 +--* LCL_VAR int V02 arg2
[000022] ------------ arg3 +--* LCL_VAR long V09 loc4
[000023] ------------ arg4 \--* LCL_VAR long V04 arg4
***** BB02
STMT00008 (IL 0x02A... ???)
[000029] --C-G------- * CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError
***** BB02
STMT00009 (IL 0x02F... ???)
[000031] -A---------- * ASG int
[000030] D------N---- +--* LCL_VAR int V06 loc1
[000028] ------------ \--* LCL_VAR int V13 tmp2
***** BB02
STMT00010 (IL 0x030...0x031)
[000034] -A---------- * ASG int
[000033] D------N---- +--* LCL_VAR int V05 loc0
[000032] ------------ \--* LCL_VAR int V06 loc1
***** BB02
STMT00011 (IL 0x032...0x032)
[000035] ------------ * NOP void
------------ BB07 [???..???) -> BB03 (callf), preds={} succs={BB03}
------------ BB08 [???..???) -> BB06 (ALWAYS), preds={} succs={BB06}
------------ BB03 [037..03D) -> BB05 (cond), preds={} succs={BB04,BB05}
***** BB03
STMT00013 (IL 0x037...0x038)
[000041] ------------ * JTRUE void
[000040] ------------ \--* EQ int
[000038] ------------ +--* LCL_VAR int V08 loc3
[000039] ------------ \--* CNS_INT int 0
------------ BB04 [03D..043), preds={} succs={BB05}
***** BB04
STMT00015 (IL 0x03D...0x03E)
[000044] --C-G------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
[000043] ------------ this in rcx \--* LCL_VAR ref V00 arg0
------------ BB05 [043..044) (finret), preds={} succs={BB08}
***** BB05
STMT00014 (IL 0x043...0x043)
[000042] ------------ * RETFILT void
------------ BB06 [044..046) (return), preds={} succs={}
***** BB06
STMT00012 (IL 0x044...0x045)
[000037] ------------ * RETURN int
[000036] ------------ \--* LCL_VAR int V05 loc0
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Indirect call transform
-- no candidates to transform
*************** Finishing PHASE Indirect call transform [no changes]
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import
*************** Starting PHASE Morph - Init
New BlockSet epoch 1, # of blocks (including unused BB00): 9, bitset array size: 1 (short)
*************** In fgRemoveEmptyBlocks
*************** Finishing PHASE Morph - Init
*************** In fgDebugCheckBBlist
*************** Starting PHASE Morph - Inlining
*************** Finishing PHASE Morph - Inlining [no changes]
*************** Starting PHASE Allocate Objects
no newobjs in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
fgNewBBinRegion(jumpKind=4, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=true): inserting after BB06
New Basic Block BB09 [0008] created.
newReturnBB [BB09] created
lvaGrabTemp returning 14 (V14 tmp3) called for Single return block return value.
mergeReturns statement tree [000046] added to genReturnBB BB09 [0008]
[000046] ------------ * RETURN int
[000045] -------N---- \--* LCL_VAR int V14 tmp3
lvaGrabTemp returning 15 (V15 tmp4) (a long lifetime temp) called for Pinvoke FrameVar.
Local V15 should not be enregistered because: it is address exposed
*************** After fgAddInternal()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal
BB02 [0001] 1 0 1 [000..037)-> BB07 (always) T0 try { } keep i try label
BB07 [0006] 1 1 [???..???)-> BB03 (callf ) i internal
BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP
BB03 [0002] 1 0 1 [037..03D)-> BB05 ( cond ) H0 finally { keep i label target
BB04 [0003] 1 0 1 [03D..043) H0 i
BB05 [0004] 2 0 1 [043..044) (finret) H0 } i
BB06 [0005] 1 1 [044..046) (return) i
BB09 [0008] 1 1 [???..???) (return) keep internal target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index eTry, eHnd
0 :: - Try at BB02..BB02 [000..037), Finally at BB03..BB05 [037..044)
*************** Finishing PHASE Morph - Add internal blocks
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
Method compiled with minOpts, no removal.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty finally
Method compiled with minOpts, no removal.
*************** Finishing PHASE Remove empty finally [no changes]
*************** Starting PHASE Merge callfinally chains
Method compiled with minOpts, no merging.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
Method compiled with minOpts, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Compute preds
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal
BB02 [0001] 1 0 1 [000..037)-> BB07 (always) T0 try { } keep i try label
BB07 [0006] 1 1 [???..???)-> BB03 (callf ) i internal
BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP
BB03 [0002] 1 0 1 [037..03D)-> BB05 ( cond ) H0 finally { keep i label target
BB04 [0003] 1 0 1 [03D..043) H0 i
BB05 [0004] 2 0 1 [043..044) (finret) H0 } i
BB06 [0005] 1 1 [044..046) (return) i
BB09 [0008] 1 1 [???..???) (return) keep internal target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index eTry, eHnd
0 :: - Try at BB02..BB02 [000..037), Finally at BB03..BB05 [037..044)
Renumber BB07 to BB03
Renumber BB08 to BB04
Renumber BB03 to BB05
Renumber BB04 to BB06
Renumber BB05 to BB07
Renumber BB06 to BB08
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal
BB02 [0001] 1 0 1 [000..037)-> BB03 (always) T0 try { } keep i try label
BB03 [0006] 1 1 [???..???)-> BB05 (callf ) i internal
BB04 [0007] 0 1 [???..???)-> BB08 (ALWAYS) i internal KEEP
BB05 [0002] 1 0 1 [037..03D)-> BB07 ( cond ) H0 finally { keep i label target
BB06 [0003] 1 0 1 [03D..043) H0 i
BB07 [0004] 2 0 1 [043..044) (finret) H0 } i
BB08 [0005] 1 1 [044..046) (return) i
BB09 [0008] 1 1 [???..???) (return) keep internal target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index eTry, eHnd
0 :: - Try at BB02..BB02 [000..037), Finally at BB05..BB07 [037..044)
New BlockSet epoch 2, # of blocks (including unused BB00): 10, bitset array size: 1 (short)
*************** In fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal
BB02 [0001] 1 0 1 [000..037)-> BB03 (always) T0 try { } keep i try label
BB03 [0006] 1 1 [???..???)-> BB05 (callf ) i internal
BB04 [0007] 0 1 [???..???)-> BB08 (ALWAYS) i internal KEEP
BB05 [0002] 1 0 1 [037..03D)-> BB07 ( cond ) H0 finally { keep i label target
BB06 [0003] 1 0 1 [03D..043) H0 i
BB07 [0004] 2 0 1 [043..044) (finret) H0 } i
BB08 [0005] 1 1 [044..046) (return) i
BB09 [0008] 1 1 [???..???) (return) keep internal target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target KEEP
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 finally { keep i label target
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target
BB08 [0005] 1 BB04 1 [044..046) (return) i label target
BB09 [0008] 0 1 [???..???) (return) keep internal target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Compute preds
*************** Starting PHASE Morph - Promote Structs
*************** In fgResetImplicitByRefRefCount()
*************** In fgPromoteStructs()
promotion opt flag not enabled
*************** Finishing PHASE Morph - Promote Structs
*************** Starting PHASE Morph - Structs/AddrExp
*************** In fgMarkAddressExposedLocals()
LocalAddressVisitor visiting statement:
STMT00000 (IL ???... ???)
[000000] ------------ * NOP void
LocalAddressVisitor visiting statement:
STMT00001 (IL 0x000...0x00E)
[000004] --C-G------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
[000001] ------------ this in rcx +--* LCL_VAR ref V00 arg0
[000003] ------------ arg1 \--* ADDR byref
[000002] ------------ \--* LCL_VAR int V08 loc3
Local V08 should not be enregistered because: it is address exposed
Adding a quirk for the storage size of V08 of type boolLocalAddressVisitor modified statement:
STMT00001 (IL 0x000...0x00E)
[000004] --C-G------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
[000001] ------------ this in rcx +--* LCL_VAR ref V00 arg0
[000003] ------------ arg1 \--* LCL_VAR_ADDR byref V08 loc3
LocalAddressVisitor visiting statement:
STMT00002 (IL 0x008... ???)
[000008] -AC-G------- * ASG long
[000007] D------N---- +--* LCL_VAR long V12 tmp1
[000006] --C-G------- \--* CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
[000005] ------------ this in rcx \--* LCL_VAR ref V00 arg0
LocalAddressVisitor visiting statement:
STMT00003 (IL 0x00E... ???)
[000011] -A---------- * ASG long
[000010] D------N---- +--* LCL_VAR long V07 loc2
[000009] ------------ \--* LCL_VAR long V12 tmp1
LocalAddressVisitor visiting statement:
STMT00004 (IL 0x00F...0x010)
[000014] -A---------- * ASG byref
[000013] D------N---- +--* LCL_VAR byref V10 loc5
[000012] ------------ \--* LCL_VAR byref V03 arg3
LocalAddressVisitor visiting statement:
STMT00005 (IL 0x012...0x015)
[000018] -A---------- * ASG long
[000017] D------N---- +--* LCL_VAR long V09 loc4
[000016] ------------ \--* CAST long <- byref
[000015] ------------ \--* LCL_VAR byref V10 loc5
LocalAddressVisitor visiting statement:
STMT00006 (IL 0x017...0x02F)
[000024] --C-G------- * CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError
LocalAddressVisitor visiting statement:
STMT00007 (IL 0x025... ???)
[000027] -AC-G------- * ASG int
[000026] D------N---- +--* LCL_VAR int V13 tmp2
[000025] --C-G------- \--* CALL r2r_ind int Kernel32.ReadFile
[000019] ------------ arg0 +--* LCL_VAR long V07 loc2
[000020] ------------ arg1 +--* LCL_VAR long V01 arg1
[000021] ------------ arg2 +--* LCL_VAR int V02 arg2
[000022] ------------ arg3 +--* LCL_VAR long V09 loc4
[000023] ------------ arg4 \--* LCL_VAR long V04 arg4
LocalAddressVisitor visiting statement:
STMT00008 (IL 0x02A... ???)
[000029] --C-G------- * CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError
LocalAddressVisitor visiting statement:
STMT00009 (IL 0x02F... ???)
[000031] -A---------- * ASG int
[000030] D------N---- +--* LCL_VAR int V06 loc1
[000028] ------------ \--* LCL_VAR int V13 tmp2
LocalAddressVisitor visiting statement:
STMT00010 (IL 0x030...0x031)
[000034] -A---------- * ASG int
[000033] D------N---- +--* LCL_VAR int V05 loc0
[000032] ------------ \--* LCL_VAR int V06 loc1
LocalAddressVisitor visiting statement:
STMT00011 (IL 0x032...0x032)
[000035] ------------ * NOP void
LocalAddressVisitor visiting statement:
STMT00013 (IL 0x037...0x038)
[000041] ------------ * JTRUE void
[000040] ------------ \--* EQ int
[000038] ------------ +--* LCL_VAR int (AX) V08 loc3
[000039] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00015 (IL 0x03D...0x03E)
[000044] --C-G------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
[000043] ------------ this in rcx \--* LCL_VAR ref V00 arg0
LocalAddressVisitor visiting statement:
STMT00014 (IL 0x043...0x043)
[000042] ------------ * RETFILT void
LocalAddressVisitor visiting statement:
STMT00012 (IL 0x044...0x045)
[000037] ------------ * RETURN int
[000036] ------------ \--* LCL_VAR int V05 loc0
LocalAddressVisitor visiting statement:
STMT00016 (IL ???... ???)
[000046] ------------ * RETURN int
[000045] -------N---- \--* LCL_VAR int V14 tmp3
*************** Finishing PHASE Morph - Structs/AddrExp
*************** Starting PHASE Morph - ByRefs
*************** In fgRetypeImplicitByRefArgs()
*************** Finishing PHASE Morph - ByRefs
*************** Starting PHASE Morph - Global
*************** In fgMorphBlocks()
Morphing BB01 of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
fgMorphTree BB01, STMT00000 (before)
[000000] ------------ * NOP void
Morphing BB02 of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
fgMorphTree BB02, STMT00001 (before)
[000004] --C-G------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
[000001] ------------ this in rcx +--* LCL_VAR ref V00 arg0
[000003] ------------ arg1 \--* LCL_VAR_ADDR byref V08 loc3
Initializing arg info for 4.CALL:
ArgTable for 4.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 1.LCL_VAR ref, 1 reg: rcx, align=1]
fgArgTabEntry[arg 1 3.LCL_VAR_ADDR long, 1 reg: rdx, align=1]
Morphing args for 4.CALL:
argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rdx'):
[000003] -----+------ * LCL_VAR_ADDR long V08 loc3
Replaced with placeholder node:
[000047] ----------L- * ARGPLACE long
Deferred argument ('rcx'):
[000001] -----+------ * LCL_VAR ref V00 arg0
Replaced with placeholder node:
[000048] ----------L- * ARGPLACE ref
Shuffled argument table: rdx rcx
ArgTable for 4.CALL after fgMorphArgs:
fgArgTabEntry[arg 1 3.LCL_VAR_ADDR long, 1 reg: rdx, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 0 1.LCL_VAR ref, 1 reg: rcx, align=1, lateArgInx=1, processed]
fgMorphTree BB02, STMT00001 (after)
[000004] --CXG+------ * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
[000003] -----+------ arg1 in rdx +--* LCL_VAR_ADDR long V08 loc3
[000001] -----+------ this in rcx \--* LCL_VAR ref V00 arg0
fgMorphTree BB02, STMT00002 (before)
[000008] -AC-G------- * ASG long
[000007] D------N---- +--* LCL_VAR long V12 tmp1
[000006] --C-G------- \--* CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
[000005] ------------ this in rcx \--* LCL_VAR ref V00 arg0
Initializing arg info for 6.CALL:
ArgTable for 6.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 5.LCL_VAR ref, 1 reg: rcx, align=1]
Morphing args for 6.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000005] -----+------ * LCL_VAR ref V00 arg0
Replaced with placeholder node:
[000049] ----------L- * ARGPLACE ref
Shuffled argument table: rcx
ArgTable for 6.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 5.LCL_VAR ref, 1 reg: rcx, align=1, lateArgInx=0, processed]
fgMorphTree BB02, STMT00002 (after)
[000008] -ACXG+------ * ASG long
[000007] D----+-N---- +--* LCL_VAR long V12 tmp1
[000006] --CXG+------ \--* CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
[000005] -----+------ this in rcx \--* LCL_VAR ref V00 arg0
fgMorphTree BB02, STMT00003 (before)
[000011] -A---------- * ASG long
[000010] D------N---- +--* LCL_VAR long V07 loc2
[000009] ------------ \--* LCL_VAR long V12 tmp1
fgMorphTree BB02, STMT00004 (before)
[000014] -A---------- * ASG byref
[000013] D------N---- +--* LCL_VAR byref V10 loc5
[000012] ------------ \--* LCL_VAR byref V03 arg3
fgMorphTree BB02, STMT00005 (before)
[000018] -A---------- * ASG long
[000017] D------N---- +--* LCL_VAR long V09 loc4
[000016] ------------ \--* CAST long <- byref
[000015] ------------ \--* LCL_VAR byref V10 loc5
lvaGrabTemp returning 16 (V16 tmp5) called for Cast away GC.
fgMorphTree BB02, STMT00005 (after)
[000018] -A---+------ * ASG long
[000017] D----+-N---- +--* LCL_VAR long V09 loc4
[000054] -A---+------ \--* COMMA long
[000051] -A---+------ +--* ASG long
[000050] D----+-N---- | +--* LCL_VAR long V16 tmp5
[000015] -----+------ | \--* LCL_VAR byref V10 loc5
[000052] -----+------ \--* LCL_VAR long V16 tmp5
fgMorphTree BB02, STMT00006 (before)
[000024] --C-G------- * CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError
Initializing arg info for 24.CALL:
ArgTable for 24.CALL after fgInitArgInfo:
Morphing args for 24.CALL:
argSlots=0, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
ArgTable for 24.CALL after fgMorphArgs:
fgMorphTree BB02, STMT00007 (before)
[000027] -AC-G------- * ASG int
[000026] D------N---- +--* LCL_VAR int V13 tmp2
[000025] --C-G------- \--* CALL r2r_ind int Kernel32.ReadFile
[000019] ------------ arg0 +--* LCL_VAR long V07 loc2
[000020] ------------ arg1 +--* LCL_VAR long V01 arg1
[000021] ------------ arg2 +--* LCL_VAR int V02 arg2
[000022] ------------ arg3 +--* LCL_VAR long V09 loc4
[000023] ------------ arg4 \--* LCL_VAR long V04 arg4
Initializing arg info for 25.CALL:
ArgTable for 25.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 19.LCL_VAR long, 1 reg: rcx, align=1]
fgArgTabEntry[arg 1 20.LCL_VAR long, 1 reg: rdx, align=1]
fgArgTabEntry[arg 2 21.LCL_VAR int, 1 reg: r8, align=1]
fgArgTabEntry[arg 3 22.LCL_VAR long, 1 reg: r9, align=1]
fgArgTabEntry[arg 4 23.LCL_VAR long, numSlots=1, slotNum=4, align=1]
Morphing args for 25.CALL:
argSlots=5, preallocatedArgCount=5, nextSlotNum=5, outgoingArgSpaceSize=40
Sorting the arguments:
Deferred argument ('rcx'):
[000019] -----+------ * LCL_VAR long V07 loc2
Replaced with placeholder node:
[000055] ----------L- * ARGPLACE long
Deferred argument ('rdx'):
[000020] -----+------ * LCL_VAR long V01 arg1
Replaced with placeholder node:
[000056] ----------L- * ARGPLACE long
Deferred argument ('r8'):
[000021] -----+------ * LCL_VAR int V02 arg2
Replaced with placeholder node:
[000057] ----------L- * ARGPLACE int
Deferred argument ('r9'):
[000022] -----+------ * LCL_VAR long V09 loc4
Replaced with placeholder node:
[000058] ----------L- * ARGPLACE long
Shuffled argument table: rcx rdx r8 r9
ArgTable for 25.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 19.LCL_VAR long, 1 reg: rcx, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 20.LCL_VAR long, 1 reg: rdx, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 2 21.LCL_VAR int, 1 reg: r8, align=1, lateArgInx=2, processed]
fgArgTabEntry[arg 3 22.LCL_VAR long, 1 reg: r9, align=1, lateArgInx=3, processed]
fgArgTabEntry[arg 4 23.LCL_VAR long, numSlots=1, slotNum=4, align=1, processed]
fgMorphTree BB02, STMT00007 (after)
[000027] -ACXG+------ * ASG int
[000026] D----+-N---- +--* LCL_VAR int V13 tmp2
[000025] --CXG+------ \--* CALL r2r_ind int Kernel32.ReadFile
[000023] -----+------ arg4 out+20 +--* LCL_VAR long V04 arg4
[000019] -----+------ arg0 in rcx +--* LCL_VAR long V07 loc2
[000020] -----+------ arg1 in rdx +--* LCL_VAR long V01 arg1
[000021] -----+------ arg2 in r8 +--* LCL_VAR int V02 arg2
[000022] -----+------ arg3 in r9 \--* LCL_VAR long V09 loc4
fgMorphTree BB02, STMT00008 (before)
[000029] --C-G------- * CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError
Initializing arg info for 29.CALL:
ArgTable for 29.CALL after fgInitArgInfo:
Morphing args for 29.CALL:
argSlots=0, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
ArgTable for 29.CALL after fgMorphArgs:
fgMorphTree BB02, STMT00009 (before)
[000031] -A---------- * ASG int
[000030] D------N---- +--* LCL_VAR int V06 loc1
[000028] ------------ \--* LCL_VAR int V13 tmp2
fgMorphTree BB02, STMT00010 (before)
[000034] -A---------- * ASG int
[000033] D------N---- +--* LCL_VAR int V05 loc0
[000032] ------------ \--* LCL_VAR int V06 loc1
fgMorphTree BB02, STMT00011 (before)
[000035] ------------ * NOP void
Morphing BB03 of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
Morphing BB04 of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
Morphing BB05 of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
fgMorphTree BB05, STMT00013 (before)
[000041] ------------ * JTRUE void
[000040] ------------ \--* EQ int
[000038] ------------ +--* LCL_VAR int (AX) V08 loc3
[000039] ------------ \--* CNS_INT int 0
fgMorphTree BB05, STMT00013 (after)
[000041] ----G+------ * JTRUE void
[000040] J---G+-N---- \--* EQ int
[000059] ----G+------ +--* CAST int <- bool <- int
[000038] ----G+------ | \--* LCL_VAR int (AX) V08 loc3
[000039] -----+------ \--* CNS_INT int 0
Morphing BB06 of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
fgMorphTree BB06, STMT00015 (before)
[000044] --C-G------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
[000043] ------------ this in rcx \--* LCL_VAR ref V00 arg0
Initializing arg info for 44.CALL:
ArgTable for 44.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 43.LCL_VAR ref, 1 reg: rcx, align=1]
Morphing args for 44.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000043] -----+------ * LCL_VAR ref V00 arg0
Replaced with placeholder node:
[000060] ----------L- * ARGPLACE ref
Shuffled argument table: rcx
ArgTable for 44.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 43.LCL_VAR ref, 1 reg: rcx, align=1, lateArgInx=0, processed]
fgMorphTree BB06, STMT00015 (after)
[000044] --CXG+------ * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
[000043] -----+------ this in rcx \--* LCL_VAR ref V00 arg0
Morphing BB07 of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
fgMorphTree BB07, STMT00014 (before)
[000042] ------------ * RETFILT void
Morphing BB08 of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
fgMorphTree BB08, STMT00012 (before)
[000037] ------------ * RETURN int
[000036] ------------ \--* LCL_VAR int V05 loc0
morph BB08 to point at onereturn. New block is
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target
Morphing BB09 of 'Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int'
fgMorphTree BB09, STMT00016 (before)
[000046] ------------ * RETURN int
[000045] -------N---- \--* LCL_VAR int V14 tmp3
Method has EH, marking method as fully interruptible
*************** Finishing PHASE Morph - Global
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie
*************** Starting PHASE Mark GC poll blocks
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label gcsafe
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target KEEP
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 finally { keep i label target
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i gcsafe
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target
BB09 [0008] 1 BB08 1 [???..???) (return) keep internal target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index eTry, eHnd
0 :: - Try at BB02..BB02 [000..037), Finally at BB05..BB07 [037..044)
*************** After renumbering the basic blocks
=============== No blocks renumbered!
*************** Finishing PHASE Mark GC poll blocks
*************** Starting PHASE Compute edge weights (1, false)
*************** In fgComputeBlockAndEdgeWeights()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label gcsafe
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target KEEP
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 finally { keep i label target
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i gcsafe
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target
BB09 [0008] 1 BB08 1 [???..???) (return) keep internal target
-----------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
-- not optimizing, so not computing edge weights
*************** Finishing PHASE Compute edge weights (1, false)
*************** Starting PHASE Create EH funclets
*************** In fgCreateFunclets()
Relocating handler range BB05..BB07 (EH#0) to end of BBlist
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label gcsafe
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target KEEP
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 finally { keep i label target
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i gcsafe
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target
BB09 [0008] 1 BB08 1 [???..???) (return) keep internal target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index eTry, eHnd
0 :: - Try at BB02..BB02 [000..037), Finally at BB05..BB07 [037..044)
Relocated blocks [BB05..BB07] inserted after BB09 at the end of method
Create funclets: moved region
*************** Exception Handling table
index eTry, eHnd
0 :: - Try at BB02..BB02 [000..037), Finally at BB05..BB07 [037..044)
After fgCreateFunclets()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label gcsafe
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target KEEP
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target
BB09 [0008] 1 BB08 1 [???..???) (return) keep internal target
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 F finally { keep i label target flet
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i gcsafe
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table
index eTry, eHnd
0 :: - Try at BB02..BB02 [000..037), Finally at BB05..BB07 [037..044)
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Create EH funclets
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
lvaGrabTemp returning 17 (V17 tmp6) (a long lifetime temp) called for PSPSym.
Local V17 should not be enregistered because: it is address exposed
*** lvaComputeRefCounts ***
*************** Finishing PHASE Mark local vars
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has 12 tree nodes
*************** Finishing PHASE Set block order
*************** Starting PHASE Determine first cold block
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** Finishing PHASE Determine first cold block
Trees before Rationalize IR
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label gcsafe
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target KEEP
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target
BB09 [0008] 1 BB08 1 [???..???) (return) keep internal target
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 F finally { keep i label target flet
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i gcsafe
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
***** BB01
STMT00000 (IL ???... ???)
N001 ( 0, 0) [000000] ------------ * NOP void
------------ BB02 [000..037) -> BB03 (always), preds={BB01} succs={BB03}
***** BB02
STMT00001 (IL 0x000...0x00E)
N005 ( 20, 13) [000004] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
N003 ( 3, 3) [000003] ------------ arg1 in rdx +--* LCL_VAR_ADDR long V08 loc3
N004 ( 3, 2) [000001] ------------ this in rcx \--* LCL_VAR ref V00 arg0
***** BB02
STMT00002 (IL 0x008... ???)
N005 ( 21, 12) [000008] -ACXG---R--- * ASG long
N004 ( 3, 2) [000007] D------N---- +--* LCL_VAR long V12 tmp1
N003 ( 17, 9) [000006] --CXG------- \--* CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
N002 ( 3, 2) [000005] ------------ this in rcx \--* LCL_VAR ref V00 arg0
***** BB02
STMT00003 (IL 0x00E... ???)
N003 ( 7, 5) [000011] -A------R--- * ASG long
N002 ( 3, 2) [000010] D------N---- +--* LCL_VAR long V07 loc2
N001 ( 3, 2) [000009] ------------ \--* LCL_VAR long V12 tmp1
***** BB02
STMT00004 (IL 0x00F...0x010)
N003 ( 7, 5) [000014] -A------R--- * ASG byref
N002 ( 3, 2) [000013] D------N---- +--* LCL_VAR byref V10 loc5
N001 ( 3, 2) [000012] ------------ \--* LCL_VAR byref V03 arg3
***** BB02
STMT00005 (IL 0x012...0x015)
N007 ( 14, 10) [000018] -A------R--- * ASG long
N006 ( 3, 2) [000017] D------N---- +--* LCL_VAR long V09 loc4
N005 ( 10, 7) [000054] -A---------- \--* COMMA long
N003 ( 7, 5) [000051] -A------R--- +--* ASG long
N002 ( 3, 2) [000050] D------N---- | +--* LCL_VAR long V16 tmp5
N001 ( 3, 2) [000015] ------------ | \--* LCL_VAR byref V10 loc5
N004 ( 3, 2) [000052] ------------ \--* LCL_VAR long V16 tmp5
***** BB02
STMT00006 (IL 0x017...0x02F)
N001 ( 14, 5) [000024] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError
***** BB02
STMT00007 (IL 0x025... ???)
N012 ( 36, 22) [000027] -ACXG---R--- * ASG int
N011 ( 3, 2) [000026] D------N---- +--* LCL_VAR int V13 tmp2
N010 ( 32, 19) [000025] --CXG------- \--* CALL r2r_ind int Kernel32.ReadFile
N005 ( 3, 2) [000023] ------------ arg4 out+20 +--* LCL_VAR long V04 arg4
N006 ( 3, 2) [000019] ------------ arg0 in rcx +--* LCL_VAR long V07 loc2
N007 ( 3, 2) [000020] ------------ arg1 in rdx +--* LCL_VAR long V01 arg1
N008 ( 3, 2) [000021] ------------ arg2 in r8 +--* LCL_VAR int V02 arg2
N009 ( 3, 2) [000022] ------------ arg3 in r9 \--* LCL_VAR long V09 loc4
***** BB02
STMT00008 (IL 0x02A... ???)
N001 ( 14, 5) [000029] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError
***** BB02
STMT00009 (IL 0x02F... ???)
N003 ( 7, 5) [000031] -A------R--- * ASG int
N002 ( 3, 2) [000030] D------N---- +--* LCL_VAR int V06 loc1
N001 ( 3, 2) [000028] ------------ \--* LCL_VAR int V13 tmp2
***** BB02
STMT00010 (IL 0x030...0x031)
N003 ( 7, 5) [000034] -A------R--- * ASG int
N002 ( 3, 2) [000033] D------N---- +--* LCL_VAR int V05 loc0
N001 ( 3, 2) [000032] ------------ \--* LCL_VAR int V06 loc1
***** BB02
STMT00011 (IL 0x032...0x032)
N001 ( 0, 0) [000035] ------------ * NOP void
------------ BB03 [???..???) -> BB05 (callf), preds={BB02} succs={BB05}
------------ BB04 [???..???) -> BB08 (ALWAYS), preds={BB07} succs={BB08}
------------ BB08 [044..046) -> BB09 (always), preds={BB04} succs={BB09}
***** BB08
STMT00012 (IL 0x044...0x045)
N003 ( 7, 5) [000062] -A------R--- * ASG int
N002 ( 3, 2) [000061] D------N---- +--* LCL_VAR int V14 tmp3
N001 ( 3, 2) [000036] ------------ \--* LCL_VAR int V05 loc0
------------ BB09 [???..???) (return), preds={BB08} succs={}
***** BB09
STMT00016 (IL ???... ???)
N002 ( 4, 3) [000046] ------------ * RETURN int
N001 ( 3, 2) [000045] -------N---- \--* LCL_VAR int V14 tmp3
------------ BB05 [037..03D) -> BB07 (cond), preds={BB03} succs={BB06,BB07}
***** BB05
STMT00013 (IL 0x037...0x038)
N005 ( 8, 8) [000041] ----G------- * JTRUE void
N004 ( 6, 6) [000040] J---G--N---- \--* EQ int
N002 ( 4, 4) [000059] ----G------- +--* CAST int <- bool <- int
N001 ( 3, 2) [000038] ----G------- | \--* LCL_VAR int (AX) V08 loc3
N003 ( 1, 1) [000039] ------------ \--* CNS_INT int 0
------------ BB06 [03D..043), preds={BB05} succs={BB07}
***** BB06
STMT00015 (IL 0x03D...0x03E)
N003 ( 17, 9) [000044] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
N002 ( 3, 2) [000043] ------------ this in rcx \--* LCL_VAR ref V00 arg0
------------ BB07 [043..044) (finret), preds={BB05,BB06} succs={BB04}
***** BB07
STMT00014 (IL 0x043...0x043)
N001 ( 0, 0) [000042] ------------ * RETFILT void
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Rationalize IR
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 21, 12) [000008] DACXG------- * STORE_LCL_VAR long V12 tmp1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000011] DA---------- * STORE_LCL_VAR long V07 loc2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000014] DA---------- * STORE_LCL_VAR byref V10 loc5
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000051] DA---------- * STORE_LCL_VAR long V16 tmp5
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 14, 10) [000018] DA---------- * STORE_LCL_VAR long V09 loc4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N012 ( 36, 22) [000027] DACXG------- * STORE_LCL_VAR int V13 tmp2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000031] DA---------- * STORE_LCL_VAR int V06 loc1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000034] DA---------- * STORE_LCL_VAR int V05 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000062] DA---------- * STORE_LCL_VAR int V14 tmp3
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target LIR
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target LIR
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target LIR KEEP
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target LIR
BB09 [0008] 1 BB08 1 [???..???) (return) keep internal target LIR
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 F finally { keep i label target flet LIR
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i gcsafe LIR
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
N001 ( 0, 0) [000000] ------------ NOP void
------------ BB02 [000..037) -> BB03 (always), preds={BB01} succs={BB03}
[000063] ------------ IL_OFFSET void IL offset: 0x0
N003 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V08 loc3
N004 ( 3, 2) [000001] ------------ t1 = LCL_VAR ref V00 arg0
/--* t3 long arg1 in rdx
+--* t1 ref this in rcx
N005 ( 20, 13) [000004] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
[000064] ------------ IL_OFFSET void IL offset: 0x8
N002 ( 3, 2) [000005] ------------ t5 = LCL_VAR ref V00 arg0
/--* t5 ref this in rcx
N003 ( 17, 9) [000006] --CXG------- t6 = * CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
/--* t6 long
N005 ( 21, 12) [000008] DA-XG------- * STORE_LCL_VAR long V12 tmp1
[000065] ------------ IL_OFFSET void IL offset: 0xe
N001 ( 3, 2) [000009] ------------ t9 = LCL_VAR long V12 tmp1
/--* t9 long
N003 ( 7, 5) [000011] DA---------- * STORE_LCL_VAR long V07 loc2
[000066] ------------ IL_OFFSET void IL offset: 0xf
N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V03 arg3
/--* t12 byref
N003 ( 7, 5) [000014] DA---------- * STORE_LCL_VAR byref V10 loc5
[000067] ------------ IL_OFFSET void IL offset: 0x12
N001 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V10 loc5
/--* t15 byref
N003 ( 7, 5) [000051] DA---------- * STORE_LCL_VAR long V16 tmp5
N004 ( 3, 2) [000052] ------------ t52 = LCL_VAR long V16 tmp5
/--* t52 long
N007 ( 14, 10) [000018] DA---------- * STORE_LCL_VAR long V09 loc4
[000068] ------------ IL_OFFSET void IL offset: 0x17
N001 ( 14, 5) [000024] --CXG------- CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError
[000069] ------------ IL_OFFSET void IL offset: 0x25
N005 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V04 arg4
N006 ( 3, 2) [000019] ------------ t19 = LCL_VAR long V07 loc2
N007 ( 3, 2) [000020] ------------ t20 = LCL_VAR long V01 arg1
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR int V02 arg2
N009 ( 3, 2) [000022] ------------ t22 = LCL_VAR long V09 loc4
/--* t23 long arg4 out+20
+--* t19 long arg0 in rcx
+--* t20 long arg1 in rdx
+--* t21 int arg2 in r8
+--* t22 long arg3 in r9
N010 ( 32, 19) [000025] --CXG------- t25 = * CALL r2r_ind int Kernel32.ReadFile
/--* t25 int
N012 ( 36, 22) [000027] DA-XG------- * STORE_LCL_VAR int V13 tmp2
[000070] ------------ IL_OFFSET void IL offset: 0x2a
N001 ( 14, 5) [000029] --CXG------- CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError
[000071] ------------ IL_OFFSET void IL offset: 0x2f
N001 ( 3, 2) [000028] ------------ t28 = LCL_VAR int V13 tmp2
/--* t28 int
N003 ( 7, 5) [000031] DA---------- * STORE_LCL_VAR int V06 loc1
[000072] ------------ IL_OFFSET void IL offset: 0x30
N001 ( 3, 2) [000032] ------------ t32 = LCL_VAR int V06 loc1
/--* t32 int
N003 ( 7, 5) [000034] DA---------- * STORE_LCL_VAR int V05 loc0
[000073] ------------ IL_OFFSET void IL offset: 0x32
N001 ( 0, 0) [000035] ------------ NOP void
------------ BB03 [???..???) -> BB05 (callf), preds={BB02} succs={BB05}
------------ BB04 [???..???) -> BB08 (ALWAYS), preds={BB07} succs={BB08}
------------ BB08 [044..046) -> BB09 (always), preds={BB04} succs={BB09}
[000074] ------------ IL_OFFSET void IL offset: 0x44
N001 ( 3, 2) [000036] ------------ t36 = LCL_VAR int V05 loc0
/--* t36 int
N003 ( 7, 5) [000062] DA---------- * STORE_LCL_VAR int V14 tmp3
------------ BB09 [???..???) (return), preds={BB08} succs={}
N001 ( 3, 2) [000045] -------N---- t45 = LCL_VAR int V14 tmp3
/--* t45 int
N002 ( 4, 3) [000046] ------------ * RETURN int
------------ BB05 [037..03D) -> BB07 (cond), preds={BB03} succs={BB06,BB07}
[000075] ------------ IL_OFFSET void IL offset: 0x37
N001 ( 3, 2) [000038] ------------ t38 = LCL_VAR int (AX) V08 loc3
/--* t38 int
N002 ( 4, 4) [000059] ----G------- t59 = * CAST int <- bool <- int
N003 ( 1, 1) [000039] ------------ t39 = CNS_INT int 0
/--* t59 int
+--* t39 int
N004 ( 6, 6) [000040] J---G--N---- t40 = * EQ int
/--* t40 int
N005 ( 8, 8) [000041] ----G------- * JTRUE void
------------ BB06 [03D..043), preds={BB05} succs={BB07}
[000076] ------------ IL_OFFSET void IL offset: 0x3d
N002 ( 3, 2) [000043] ------------ t43 = LCL_VAR ref V00 arg0
/--* t43 ref this in rcx
N003 ( 17, 9) [000044] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
------------ BB07 [043..044) (finret), preds={BB05,BB06} succs={BB04}
[000077] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 0, 0) [000042] ------------ RETFILT void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Do 'simple' lowering
Bumping outgoingArgSpaceSize to 32 for call [000004]
outgoingArgSpaceSize 32 sufficient for call [000006], which needs 32
outgoingArgSpaceSize 32 sufficient for call [000024], which needs 32
Bumping outgoingArgSpaceSize to 40 for call [000025]
outgoingArgSpaceSize 40 sufficient for call [000029], which needs 32
outgoingArgSpaceSize 40 sufficient for call [000044], which needs 32
*************** Finishing PHASE Do 'simple' lowering
*************** In fgDebugCheckBBlist
Trees before Lowering nodeinfo
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target LIR
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target LIR
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target LIR KEEP
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target LIR
BB09 [0008] 1 BB08 1 [???..???) (return) keep internal target LIR
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 F finally { keep i label target flet LIR
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i gcsafe LIR
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
N001 ( 0, 0) [000000] ------------ NOP void
------------ BB02 [000..037) -> BB03 (always), preds={BB01} succs={BB03}
[000063] ------------ IL_OFFSET void IL offset: 0x0
N003 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V08 loc3
N004 ( 3, 2) [000001] ------------ t1 = LCL_VAR ref V00 arg0
/--* t3 long arg1 in rdx
+--* t1 ref this in rcx
N005 ( 20, 13) [000004] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
[000064] ------------ IL_OFFSET void IL offset: 0x8
N002 ( 3, 2) [000005] ------------ t5 = LCL_VAR ref V00 arg0
/--* t5 ref this in rcx
N003 ( 17, 9) [000006] --CXG------- t6 = * CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
/--* t6 long
N005 ( 21, 12) [000008] DA-XG------- * STORE_LCL_VAR long V12 tmp1
[000065] ------------ IL_OFFSET void IL offset: 0xe
N001 ( 3, 2) [000009] ------------ t9 = LCL_VAR long V12 tmp1
/--* t9 long
N003 ( 7, 5) [000011] DA---------- * STORE_LCL_VAR long V07 loc2
[000066] ------------ IL_OFFSET void IL offset: 0xf
N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V03 arg3
/--* t12 byref
N003 ( 7, 5) [000014] DA---------- * STORE_LCL_VAR byref V10 loc5
[000067] ------------ IL_OFFSET void IL offset: 0x12
N001 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V10 loc5
/--* t15 byref
N003 ( 7, 5) [000051] DA---------- * STORE_LCL_VAR long V16 tmp5
N004 ( 3, 2) [000052] ------------ t52 = LCL_VAR long V16 tmp5
/--* t52 long
N007 ( 14, 10) [000018] DA---------- * STORE_LCL_VAR long V09 loc4
[000068] ------------ IL_OFFSET void IL offset: 0x17
N001 ( 14, 5) [000024] --CXG------- CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError
[000069] ------------ IL_OFFSET void IL offset: 0x25
N005 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V04 arg4
N006 ( 3, 2) [000019] ------------ t19 = LCL_VAR long V07 loc2
N007 ( 3, 2) [000020] ------------ t20 = LCL_VAR long V01 arg1
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR int V02 arg2
N009 ( 3, 2) [000022] ------------ t22 = LCL_VAR long V09 loc4
/--* t23 long arg4 out+20
+--* t19 long arg0 in rcx
+--* t20 long arg1 in rdx
+--* t21 int arg2 in r8
+--* t22 long arg3 in r9
N010 ( 32, 19) [000025] --CXG------- t25 = * CALL r2r_ind int Kernel32.ReadFile
/--* t25 int
N012 ( 36, 22) [000027] DA-XG------- * STORE_LCL_VAR int V13 tmp2
[000070] ------------ IL_OFFSET void IL offset: 0x2a
N001 ( 14, 5) [000029] --CXG------- CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError
[000071] ------------ IL_OFFSET void IL offset: 0x2f
N001 ( 3, 2) [000028] ------------ t28 = LCL_VAR int V13 tmp2
/--* t28 int
N003 ( 7, 5) [000031] DA---------- * STORE_LCL_VAR int V06 loc1
[000072] ------------ IL_OFFSET void IL offset: 0x30
N001 ( 3, 2) [000032] ------------ t32 = LCL_VAR int V06 loc1
/--* t32 int
N003 ( 7, 5) [000034] DA---------- * STORE_LCL_VAR int V05 loc0
[000073] ------------ IL_OFFSET void IL offset: 0x32
N001 ( 0, 0) [000035] ------------ NOP void
------------ BB03 [???..???) -> BB05 (callf), preds={BB02} succs={BB05}
------------ BB04 [???..???) -> BB08 (ALWAYS), preds={BB07} succs={BB08}
------------ BB08 [044..046) -> BB09 (always), preds={BB04} succs={BB09}
[000074] ------------ IL_OFFSET void IL offset: 0x44
N001 ( 3, 2) [000036] ------------ t36 = LCL_VAR int V05 loc0
/--* t36 int
N003 ( 7, 5) [000062] DA---------- * STORE_LCL_VAR int V14 tmp3
------------ BB09 [???..???) (return), preds={BB08} succs={}
N001 ( 3, 2) [000045] -------N---- t45 = LCL_VAR int V14 tmp3
/--* t45 int
N002 ( 4, 3) [000046] ------------ * RETURN int
------------ BB05 [037..03D) -> BB07 (cond), preds={BB03} succs={BB06,BB07}
[000075] ------------ IL_OFFSET void IL offset: 0x37
N001 ( 3, 2) [000038] ------------ t38 = LCL_VAR int (AX) V08 loc3
/--* t38 int
N002 ( 4, 4) [000059] ----G------- t59 = * CAST int <- bool <- int
N003 ( 1, 1) [000039] ------------ t39 = CNS_INT int 0
/--* t59 int
+--* t39 int
N004 ( 6, 6) [000040] J---G--N---- t40 = * EQ int
/--* t40 int
N005 ( 8, 8) [000041] ----G------- * JTRUE void
------------ BB06 [03D..043), preds={BB05} succs={BB07}
[000076] ------------ IL_OFFSET void IL offset: 0x3d
N002 ( 3, 2) [000043] ------------ t43 = LCL_VAR ref V00 arg0
/--* t43 ref this in rcx
N003 ( 17, 9) [000044] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
------------ BB07 [043..044) (finret), preds={BB05,BB06} succs={BB04}
[000077] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 0, 0) [000042] ------------ RETFILT void
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Lowering nodeinfo
lowering call (before):
N003 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V08 loc3
N004 ( 3, 2) [000001] ------------ t1 = LCL_VAR ref V00 arg0
/--* t3 long arg1 in rdx
+--* t1 ref this in rcx
N005 ( 20, 13) [000004] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
objp:
======
lowering arg : N001 ( 0, 0) [000048] ----------L- * ARGPLACE ref
args:
======
lowering arg : N002 ( 0, 0) [000047] ----------L- * ARGPLACE long
late:
======
lowering arg : N003 ( 3, 3) [000003] ------------ * LCL_VAR_ADDR long V08 loc3
new node is : [000078] ------------ * PUTARG_REG long REG rdx
lowering arg : N004 ( 3, 2) [000001] ------------ * LCL_VAR ref V00 arg0
new node is : [000079] ------------ * PUTARG_REG ref REG rcx
results of lowering call:
N001 ( 3, 10) [000080] ------------ t80 = CNS_INT(h) long 0x420058 ftn
/--* t80 long
N002 ( 5, 12) [000081] ------------ t81 = * IND long
lowering call (after):
N003 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V08 loc3
/--* t3 long
[000078] ------------ t78 = * PUTARG_REG long REG rdx
N004 ( 3, 2) [000001] ------------ t1 = LCL_VAR ref V00 arg0
/--* t1 ref
[000079] ------------ t79 = * PUTARG_REG ref REG rcx
N001 ( 3, 10) [000080] -c---------- t80 = CNS_INT(h) long 0x420058 ftn
/--* t80 long
N002 ( 5, 12) [000081] -c---------- t81 = * IND long REG NA
/--* t78 long arg1 in rdx
+--* t79 ref this in rcx
+--* t81 long control expr
N005 ( 20, 13) [000004] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
lowering call (before):
N002 ( 3, 2) [000005] ------------ t5 = LCL_VAR ref V00 arg0
/--* t5 ref this in rcx
N003 ( 17, 9) [000006] --CXG------- t6 = * CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
objp:
======
lowering arg : N001 ( 0, 0) [000049] ----------L- * ARGPLACE ref
args:
======
late:
======
lowering arg : N002 ( 3, 2) [000005] ------------ * LCL_VAR ref V00 arg0
new node is : [000082] ------------ * PUTARG_REG ref REG rcx
results of lowering call:
N001 ( 3, 10) [000083] ------------ t83 = CNS_INT(h) long 0x420080 ftn
/--* t83 long
N002 ( 5, 12) [000084] ------------ t84 = * IND long
lowering call (after):
N002 ( 3, 2) [000005] ------------ t5 = LCL_VAR ref V00 arg0
/--* t5 ref
[000082] ------------ t82 = * PUTARG_REG ref REG rcx
N001 ( 3, 10) [000083] -c---------- t83 = CNS_INT(h) long 0x420080 ftn
/--* t83 long
N002 ( 5, 12) [000084] -c---------- t84 = * IND long REG NA
/--* t82 ref this in rcx
+--* t84 long control expr
N003 ( 17, 9) [000006] --CXG------- t6 = * CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
lowering call (before):
N001 ( 14, 5) [000024] --CXG------- CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError
objp:
======
args:
======
late:
======
results of lowering call:
N001 ( 3, 10) [000085] ------------ t85 = CNS_INT(h) long 0x4200A0 ftn
/--* t85 long
N002 ( 5, 12) [000086] ------------ t86 = * IND long
lowering call (after):
N001 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x4200A0 ftn
/--* t85 long
N002 ( 5, 12) [000086] -c---------- t86 = * IND long REG NA
/--* t86 long control expr
N001 ( 14, 5) [000024] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError
lowering call (before):
N005 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V04 arg4
N006 ( 3, 2) [000019] ------------ t19 = LCL_VAR long V07 loc2
N007 ( 3, 2) [000020] ------------ t20 = LCL_VAR long V01 arg1
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR int V02 arg2
N009 ( 3, 2) [000022] ------------ t22 = LCL_VAR long V09 loc4
/--* t23 long arg4 out+20
+--* t19 long arg0 in rcx
+--* t20 long arg1 in rdx
+--* t21 int arg2 in r8
+--* t22 long arg3 in r9
N010 ( 32, 19) [000025] --CXG------- t25 = * CALL r2r_ind int Kernel32.ReadFile
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000055] ----------L- * ARGPLACE long
lowering arg : N002 ( 0, 0) [000056] ----------L- * ARGPLACE long
lowering arg : N003 ( 0, 0) [000057] ----------L- * ARGPLACE int
lowering arg : N004 ( 0, 0) [000058] ----------L- * ARGPLACE long
lowering arg : N005 ( 3, 2) [000023] ------------ * LCL_VAR long V04 arg4
new node is : [000087] ------------ * PUTARG_STK [+0x20] void
late:
======
lowering arg : N006 ( 3, 2) [000019] ------------ * LCL_VAR long V07 loc2
new node is : [000088] ------------ * PUTARG_REG long REG rcx
lowering arg : N007 ( 3, 2) [000020] ------------ * LCL_VAR long V01 arg1
new node is : [000089] ------------ * PUTARG_REG long REG rdx
lowering arg : N008 ( 3, 2) [000021] ------------ * LCL_VAR int V02 arg2
new node is : [000090] ------------ * PUTARG_REG int REG r8
lowering arg : N009 ( 3, 2) [000022] ------------ * LCL_VAR long V09 loc4
new node is : [000091] ------------ * PUTARG_REG long REG r9
======= Inserting PInvoke call prolog
Initializing arg info for 94.CALL:
ArgTable for 94.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 93.LCL_VAR_ADDR long, 1 reg: rcx, align=1]
Morphing args for 94.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000093] ------------ * LCL_VAR_ADDR long V15 PInvokeFrame
Replaced with placeholder node:
[000095] ----------L- * ARGPLACE long
Shuffled argument table: rcx
ArgTable for 94.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 93.LCL_VAR_ADDR long, 1 reg: rcx, align=1, lateArgInx=0, processed]
lowering call (before):
N001 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR long V15 PInvokeFrame
/--* t93 long arg0 in rcx
N002 ( 17, 9) [000094] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
objp:
======
args:
======
lowering arg : ( 0, 0) [000095] ----------L- * ARGPLACE long
late:
======
lowering arg : N001 ( 3, 3) [000093] ------------ * LCL_VAR_ADDR long V15 PInvokeFrame
new node is : [000096] ------------ * PUTARG_REG long REG rcx
results of lowering call:
N001 ( 3, 10) [000097] ------------ t97 = CNS_INT(h) long 0x4200E8 ftn
/--* t97 long
N002 ( 5, 12) [000098] ------------ t98 = * IND long
lowering call (after):
N001 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR long V15 PInvokeFrame
/--* t93 long
[000096] ------------ t96 = * PUTARG_REG long REG rcx
N001 ( 3, 10) [000097] -c---------- t97 = CNS_INT(h) long 0x4200E8 ftn
/--* t97 long
N002 ( 5, 12) [000098] -c---------- t98 = * IND long REG NA
/--* t96 long arg0 in rcx
+--* t98 long control expr
N002 ( 17, 9) [000094] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
======= Inserting PInvoke call epilog
Initializing arg info for 103.CALL:
ArgTable for 103.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 102.LCL_VAR_ADDR long, 1 reg: rcx, align=1]
Morphing args for 103.CALL:
argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000102] ------------ * LCL_VAR_ADDR long V15 PInvokeFrame
Replaced with placeholder node:
[000104] ----------L- * ARGPLACE long
Shuffled argument table: rcx
ArgTable for 103.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 102.LCL_VAR_ADDR long, 1 reg: rcx, align=1, lateArgInx=0, processed]
results of lowering call:
N001 ( 3, 10) [000099] ------------ t99 = CNS_INT(h) long 0x4200F0 ftn
/--* t99 long
N002 ( 5, 12) [000100] ------------ t100 = * IND long
/--* t100 long
N003 ( 8, 14) [000101] ------------ t101 = * IND long
lowering call (after):
N005 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V04 arg4
/--* t23 long
[000087] ------------ * PUTARG_STK [+0x20] void
N006 ( 3, 2) [000019] ------------ t19 = LCL_VAR long V07 loc2
/--* t19 long
[000088] ------------ t88 = * PUTARG_REG long REG rcx
N007 ( 3, 2) [000020] ------------ t20 = LCL_VAR long V01 arg1
/--* t20 long
[000089] ------------ t89 = * PUTARG_REG long REG rdx
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR int V02 arg2
/--* t21 int
[000090] ------------ t90 = * PUTARG_REG int REG r8
N009 ( 3, 2) [000022] ------------ t22 = LCL_VAR long V09 loc4
/--* t22 long
[000091] ------------ t91 = * PUTARG_REG long REG r9
[000092] ------------ PINVOKE_PROLOG void
N001 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR long V15 PInvokeFrame
/--* t93 long
[000096] ------------ t96 = * PUTARG_REG long REG rcx
N001 ( 3, 10) [000097] -c---------- t97 = CNS_INT(h) long 0x4200E8 ftn
/--* t97 long
N002 ( 5, 12) [000098] -c---------- t98 = * IND long REG NA
/--* t96 long arg0 in rcx
+--* t98 long control expr
N002 ( 17, 9) [000094] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
N001 ( 3, 10) [000099] -c---------- t99 = CNS_INT(h) long 0x4200F0 ftn
/--* t99 long
N002 ( 5, 12) [000100] ------------ t100 = * IND long
/--* t100 long
N003 ( 8, 14) [000101] -c---------- t101 = * IND long REG NA
/--* t88 long arg0 in rcx
+--* t89 long arg1 in rdx
+--* t90 int arg2 in r8
+--* t91 long arg3 in r9
+--* t101 long control expr
N010 ( 32, 19) [000025] --CXG------- t25 = * CALL r2r_ind int Kernel32.ReadFile
lowering call (before):
N001 ( 3, 3) [000102] ------------ t102 = LCL_VAR_ADDR long V15 PInvokeFrame
/--* t102 long arg0 in rcx
N002 ( 17, 9) [000103] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END
objp:
======
args:
======
lowering arg : ( 0, 0) [000104] ----------L- * ARGPLACE long
late:
======
lowering arg : N001 ( 3, 3) [000102] ------------ * LCL_VAR_ADDR long V15 PInvokeFrame
new node is : [000105] ------------ * PUTARG_REG long REG rcx
results of lowering call:
N001 ( 3, 10) [000106] ------------ t106 = CNS_INT(h) long 0x4200F8 ftn
/--* t106 long
N002 ( 5, 12) [000107] ------------ t107 = * IND long
lowering call (after):
N001 ( 3, 3) [000102] ------------ t102 = LCL_VAR_ADDR long V15 PInvokeFrame
/--* t102 long
[000105] ------------ t105 = * PUTARG_REG long REG rcx
N001 ( 3, 10) [000106] -c---------- t106 = CNS_INT(h) long 0x4200F8 ftn
/--* t106 long
N002 ( 5, 12) [000107] -c---------- t107 = * IND long REG NA
/--* t105 long arg0 in rcx
+--* t107 long control expr
N002 ( 17, 9) [000103] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END
lowering call (before):
N001 ( 14, 5) [000029] --CXG------- CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError
objp:
======
args:
======
late:
======
results of lowering call:
N001 ( 3, 10) [000108] ------------ t108 = CNS_INT(h) long 0x4200C8 ftn
/--* t108 long
N002 ( 5, 12) [000109] ------------ t109 = * IND long
lowering call (after):
N001 ( 3, 10) [000108] -c---------- t108 = CNS_INT(h) long 0x4200C8 ftn
/--* t108 long
N002 ( 5, 12) [000109] -c---------- t109 = * IND long REG NA
/--* t109 long control expr
N001 ( 14, 5) [000029] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError
lowering GT_RETURN
N002 ( 4, 3) [000046] ------------ * RETURN int
============lowering call (before):
N002 ( 3, 2) [000043] ------------ t43 = LCL_VAR ref V00 arg0
/--* t43 ref this in rcx
N003 ( 17, 9) [000044] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
objp:
======
lowering arg : N001 ( 0, 0) [000060] ----------L- * ARGPLACE ref
args:
======
late:
======
lowering arg : N002 ( 3, 2) [000043] ------------ * LCL_VAR ref V00 arg0
new node is : [000110] ------------ * PUTARG_REG ref REG rcx
results of lowering call:
N001 ( 3, 10) [000111] ------------ t111 = CNS_INT(h) long 0x4200E0 ftn
/--* t111 long
N002 ( 5, 12) [000112] ------------ t112 = * IND long
lowering call (after):
N002 ( 3, 2) [000043] ------------ t43 = LCL_VAR ref V00 arg0
/--* t43 ref
[000110] ------------ t110 = * PUTARG_REG ref REG rcx
N001 ( 3, 10) [000111] -c---------- t111 = CNS_INT(h) long 0x4200E0 ftn
/--* t111 long
N002 ( 5, 12) [000112] -c---------- t112 = * IND long REG NA
/--* t110 ref this in rcx
+--* t112 long control expr
N003 ( 17, 9) [000044] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
Lower has completed modifying nodes.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target LIR
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target LIR
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target LIR KEEP
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target LIR
BB09 [0008] 1 BB08 1 [???..???) (return) keep internal target LIR
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 F finally { keep i label target flet LIR
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i gcsafe LIR
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
N001 ( 0, 0) [000000] ------------ NOP void
------------ BB02 [000..037) -> BB03 (always), preds={BB01} succs={BB03}
[000063] ------------ IL_OFFSET void IL offset: 0x0
N003 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V08 loc3
/--* t3 long
[000078] ------------ t78 = * PUTARG_REG long REG rdx
N004 ( 3, 2) [000001] ------------ t1 = LCL_VAR ref V00 arg0
/--* t1 ref
[000079] ------------ t79 = * PUTARG_REG ref REG rcx
N001 ( 3, 10) [000080] -c---------- t80 = CNS_INT(h) long 0x420058 ftn
/--* t80 long
N002 ( 5, 12) [000081] -c---------- t81 = * IND long REG NA
/--* t78 long arg1 in rdx
+--* t79 ref this in rcx
+--* t81 long control expr
N005 ( 20, 13) [000004] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
[000064] ------------ IL_OFFSET void IL offset: 0x8
N002 ( 3, 2) [000005] ------------ t5 = LCL_VAR ref V00 arg0
/--* t5 ref
[000082] ------------ t82 = * PUTARG_REG ref REG rcx
N001 ( 3, 10) [000083] -c---------- t83 = CNS_INT(h) long 0x420080 ftn
/--* t83 long
N002 ( 5, 12) [000084] -c---------- t84 = * IND long REG NA
/--* t82 ref this in rcx
+--* t84 long control expr
N003 ( 17, 9) [000006] --CXG------- t6 = * CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
/--* t6 long
N005 ( 21, 12) [000008] DA-XG------- * STORE_LCL_VAR long V12 tmp1
[000065] ------------ IL_OFFSET void IL offset: 0xe
N001 ( 3, 2) [000009] ------------ t9 = LCL_VAR long V12 tmp1
/--* t9 long
N003 ( 7, 5) [000011] DA---------- * STORE_LCL_VAR long V07 loc2
[000066] ------------ IL_OFFSET void IL offset: 0xf
N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V03 arg3
/--* t12 byref
N003 ( 7, 5) [000014] DA---------- * STORE_LCL_VAR byref V10 loc5
[000067] ------------ IL_OFFSET void IL offset: 0x12
N001 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V10 loc5
/--* t15 byref
N003 ( 7, 5) [000051] DA---------- * STORE_LCL_VAR long V16 tmp5
N004 ( 3, 2) [000052] ------------ t52 = LCL_VAR long V16 tmp5
/--* t52 long
N007 ( 14, 10) [000018] DA---------- * STORE_LCL_VAR long V09 loc4
[000068] ------------ IL_OFFSET void IL offset: 0x17
N001 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x4200A0 ftn
/--* t85 long
N002 ( 5, 12) [000086] -c---------- t86 = * IND long REG NA
/--* t86 long control expr
N001 ( 14, 5) [000024] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError
[000069] ------------ IL_OFFSET void IL offset: 0x25
N005 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V04 arg4
/--* t23 long
[000087] ------------ * PUTARG_STK [+0x20] void
N006 ( 3, 2) [000019] ------------ t19 = LCL_VAR long V07 loc2
/--* t19 long
[000088] ------------ t88 = * PUTARG_REG long REG rcx
N007 ( 3, 2) [000020] ------------ t20 = LCL_VAR long V01 arg1
/--* t20 long
[000089] ------------ t89 = * PUTARG_REG long REG rdx
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR int V02 arg2
/--* t21 int
[000090] ------------ t90 = * PUTARG_REG int REG r8
N009 ( 3, 2) [000022] ------------ t22 = LCL_VAR long V09 loc4
/--* t22 long
[000091] ------------ t91 = * PUTARG_REG long REG r9
[000092] ------------ PINVOKE_PROLOG void
N001 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR long V15 PInvokeFrame
/--* t93 long
[000096] ------------ t96 = * PUTARG_REG long REG rcx
N001 ( 3, 10) [000097] -c---------- t97 = CNS_INT(h) long 0x4200E8 ftn
/--* t97 long
N002 ( 5, 12) [000098] -c---------- t98 = * IND long REG NA
/--* t96 long arg0 in rcx
+--* t98 long control expr
N002 ( 17, 9) [000094] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
N001 ( 3, 10) [000099] -c---------- t99 = CNS_INT(h) long 0x4200F0 ftn
/--* t99 long
N002 ( 5, 12) [000100] ------------ t100 = * IND long
/--* t100 long
N003 ( 8, 14) [000101] -c---------- t101 = * IND long REG NA
/--* t88 long arg0 in rcx
+--* t89 long arg1 in rdx
+--* t90 int arg2 in r8
+--* t91 long arg3 in r9
+--* t101 long control expr
N010 ( 32, 19) [000025] --CXG------- t25 = * CALL r2r_ind int Kernel32.ReadFile
N001 ( 3, 3) [000102] ------------ t102 = LCL_VAR_ADDR long V15 PInvokeFrame
/--* t102 long
[000105] ------------ t105 = * PUTARG_REG long REG rcx
N001 ( 3, 10) [000106] -c---------- t106 = CNS_INT(h) long 0x4200F8 ftn
/--* t106 long
N002 ( 5, 12) [000107] -c---------- t107 = * IND long REG NA
/--* t105 long arg0 in rcx
+--* t107 long control expr
N002 ( 17, 9) [000103] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END
/--* t25 int
N012 ( 36, 22) [000027] DA-XG------- * STORE_LCL_VAR int V13 tmp2
[000070] ------------ IL_OFFSET void IL offset: 0x2a
N001 ( 3, 10) [000108] -c---------- t108 = CNS_INT(h) long 0x4200C8 ftn
/--* t108 long
N002 ( 5, 12) [000109] -c---------- t109 = * IND long REG NA
/--* t109 long control expr
N001 ( 14, 5) [000029] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError
[000071] ------------ IL_OFFSET void IL offset: 0x2f
N001 ( 3, 2) [000028] ------------ t28 = LCL_VAR int V13 tmp2
/--* t28 int
N003 ( 7, 5) [000031] DA---------- * STORE_LCL_VAR int V06 loc1
[000072] ------------ IL_OFFSET void IL offset: 0x30
N001 ( 3, 2) [000032] ------------ t32 = LCL_VAR int V06 loc1
/--* t32 int
N003 ( 7, 5) [000034] DA---------- * STORE_LCL_VAR int V05 loc0
[000073] ------------ IL_OFFSET void IL offset: 0x32
N001 ( 0, 0) [000035] ------------ NOP void
------------ BB03 [???..???) -> BB05 (callf), preds={BB02} succs={BB05}
------------ BB04 [???..???) -> BB08 (ALWAYS), preds={BB07} succs={BB08}
------------ BB08 [044..046) -> BB09 (always), preds={BB04} succs={BB09}
[000074] ------------ IL_OFFSET void IL offset: 0x44
N001 ( 3, 2) [000036] ------------ t36 = LCL_VAR int V05 loc0
/--* t36 int
N003 ( 7, 5) [000062] DA---------- * STORE_LCL_VAR int V14 tmp3
------------ BB09 [???..???) (return), preds={BB08} succs={}
N001 ( 3, 2) [000045] -------N---- t45 = LCL_VAR int V14 tmp3
/--* t45 int
N002 ( 4, 3) [000046] ------------ * RETURN int
------------ BB05 [037..03D) -> BB07 (cond), preds={BB03} succs={BB06,BB07}
[000075] ------------ IL_OFFSET void IL offset: 0x37
N001 ( 3, 2) [000038] ------------ t38 = LCL_VAR int (AX) V08 loc3
/--* t38 int
N002 ( 4, 4) [000059] ----G------- t59 = * CAST int <- bool <- int
N003 ( 1, 1) [000039] -c---------- t39 = CNS_INT int 0
/--* t59 int
+--* t39 int
N004 ( 6, 6) [000040] J---G--N---- * EQ void
N005 ( 8, 8) [000041] ----G------- * JTRUE void
------------ BB06 [03D..043), preds={BB05} succs={BB07}
[000076] ------------ IL_OFFSET void IL offset: 0x3d
N002 ( 3, 2) [000043] ------------ t43 = LCL_VAR ref V00 arg0
/--* t43 ref
[000110] ------------ t110 = * PUTARG_REG ref REG rcx
N001 ( 3, 10) [000111] -c---------- t111 = CNS_INT(h) long 0x4200E0 ftn
/--* t111 long
N002 ( 5, 12) [000112] -c---------- t112 = * IND long REG NA
/--* t110 ref this in rcx
+--* t112 long control expr
N003 ( 17, 9) [000044] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
------------ BB07 [043..044) (finret), preds={BB05,BB06} succs={BB04}
[000077] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 0, 0) [000042] ------------ RETFILT void
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 ref class-hnd
; V01 arg1 long
; V02 arg2 int
; V03 arg3 byref
; V04 arg4 long
; V05 loc0 int
; V06 loc1 int
; V07 loc2 long
; V08 loc3 bool do-not-enreg[X] addr-exposed ld-addr-op
; V09 loc4 long
; V10 loc5 byref pinned
; V11 OutArgs lclBlk <40> "OutgoingArgSpace"
; V12 tmp1 long "impSpillStackEnsure"
; V13 tmp2 int "impSpillStackEnsure"
; V14 tmp3 int "Single return block return value"
; V15 PInvokeFrame blk do-not-enreg[X] addr-exposed "Pinvoke FrameVar"
; V16 tmp5 long "Cast away GC"
; V17 PSPSym long do-not-enreg[X] addr-exposed "PSPSym"
In fgLocalVarLivenessInit
*************** In fgPerBlockLocalVarLiveness()
*************** In fgInterBlockLocalVarLiveness()
*************** In fgExtendDbgLifetimes()
Marking vars alive over their entire scope :
Local variable scopes = 11
VarNum LVNum Name Beg End
Sorted by enter scope:
0: 00h 00h V00 arg0 000h 046h <-- next enter scope
1: 01h 01h V01 arg1 000h 046h
2: 02h 02h V02 arg2 000h 046h
3: 03h 03h V03 arg3 000h 046h
4: 04h 04h V04 arg4 000h 046h
5: 05h 05h V05 loc0 000h 046h
6: 06h 06h V06 loc1 000h 046h
7: 07h 07h V07 loc2 000h 046h
8: 08h 08h V08 loc3 000h 046h
9: 09h 09h V09 loc4 000h 046h
10: 0Ah 0Ah V10 loc5 000h 046h
Sorted by exit scope:
0: 00h 00h V00 arg0 000h 046h <-- next exit scope
1: 01h 01h V01 arg1 000h 046h
2: 02h 02h V02 arg2 000h 046h
3: 03h 03h V03 arg3 000h 046h
4: 04h 04h V04 arg4 000h 046h
5: 05h 05h V05 loc0 000h 046h
6: 06h 06h V06 loc1 000h 046h
7: 07h 07h V07 loc2 000h 046h
8: 08h 08h V08 loc3 000h 046h
9: 09h 09h V09 loc4 000h 046h
10: 0Ah 0Ah V10 loc5 000h 046h
Scope info: block BB01 marking in scope: {}
Scope info: block BB02 marking in scope: {}
Scope info: block BB03 marking in scope: {}
Scope info: block BB04 marking in scope: {}
Scope info: block BB08 marking in scope: {}
Scope info: block BB09 marking in scope: {}
Scope info: block BB05 marking in scope: {}
Scope info: block BB06 marking in scope: {}
Scope info: block BB07 marking in scope: {}
Debug scopes:
BB01: {}
BB02: {}
BB03: {}
BB04: {}
BB08: {}
BB09: {}
BB05: {}
BB06: {}
BB07: {}
Scope info: block BB01 UNmarking in scope: {}
BB liveness after fgExtendDbgLifetimes():
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB02 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB03 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB04 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB08 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB09 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB05 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB06 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
BB07 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
*** lvaComputeRefCounts ***
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target LIR
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target LIR
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target LIR KEEP
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target LIR
BB09 [0008] 1 BB08 1 [???..???) (return) keep internal target LIR
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 F finally { keep i label target flet LIR
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i gcsafe LIR
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
N001 ( 0, 0) [000000] ------------ NOP void
------------ BB02 [000..037) -> BB03 (always), preds={BB01} succs={BB03}
[000063] ------------ IL_OFFSET void IL offset: 0x0
N003 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V08 loc3
/--* t3 long
[000078] ------------ t78 = * PUTARG_REG long REG rdx
N004 ( 3, 2) [000001] ------------ t1 = LCL_VAR ref V00 arg0
/--* t1 ref
[000079] ------------ t79 = * PUTARG_REG ref REG rcx
N001 ( 3, 10) [000080] -c---------- t80 = CNS_INT(h) long 0x420058 ftn
/--* t80 long
N002 ( 5, 12) [000081] -c---------- t81 = * IND long REG NA
/--* t78 long arg1 in rdx
+--* t79 ref this in rcx
+--* t81 long control expr
N005 ( 20, 13) [000004] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
[000064] ------------ IL_OFFSET void IL offset: 0x8
N002 ( 3, 2) [000005] ------------ t5 = LCL_VAR ref V00 arg0
/--* t5 ref
[000082] ------------ t82 = * PUTARG_REG ref REG rcx
N001 ( 3, 10) [000083] -c---------- t83 = CNS_INT(h) long 0x420080 ftn
/--* t83 long
N002 ( 5, 12) [000084] -c---------- t84 = * IND long REG NA
/--* t82 ref this in rcx
+--* t84 long control expr
N003 ( 17, 9) [000006] --CXG------- t6 = * CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
/--* t6 long
N005 ( 21, 12) [000008] DA-XG------- * STORE_LCL_VAR long V12 tmp1
[000065] ------------ IL_OFFSET void IL offset: 0xe
N001 ( 3, 2) [000009] ------------ t9 = LCL_VAR long V12 tmp1
/--* t9 long
N003 ( 7, 5) [000011] DA---------- * STORE_LCL_VAR long V07 loc2
[000066] ------------ IL_OFFSET void IL offset: 0xf
N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V03 arg3
/--* t12 byref
N003 ( 7, 5) [000014] DA---------- * STORE_LCL_VAR byref V10 loc5
[000067] ------------ IL_OFFSET void IL offset: 0x12
N001 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V10 loc5
/--* t15 byref
N003 ( 7, 5) [000051] DA---------- * STORE_LCL_VAR long V16 tmp5
N004 ( 3, 2) [000052] ------------ t52 = LCL_VAR long V16 tmp5
/--* t52 long
N007 ( 14, 10) [000018] DA---------- * STORE_LCL_VAR long V09 loc4
[000068] ------------ IL_OFFSET void IL offset: 0x17
N001 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x4200A0 ftn
/--* t85 long
N002 ( 5, 12) [000086] -c---------- t86 = * IND long REG NA
/--* t86 long control expr
N001 ( 14, 5) [000024] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError
[000069] ------------ IL_OFFSET void IL offset: 0x25
N005 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V04 arg4
/--* t23 long
[000087] ------------ * PUTARG_STK [+0x20] void
N006 ( 3, 2) [000019] ------------ t19 = LCL_VAR long V07 loc2
/--* t19 long
[000088] ------------ t88 = * PUTARG_REG long REG rcx
N007 ( 3, 2) [000020] ------------ t20 = LCL_VAR long V01 arg1
/--* t20 long
[000089] ------------ t89 = * PUTARG_REG long REG rdx
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR int V02 arg2
/--* t21 int
[000090] ------------ t90 = * PUTARG_REG int REG r8
N009 ( 3, 2) [000022] ------------ t22 = LCL_VAR long V09 loc4
/--* t22 long
[000091] ------------ t91 = * PUTARG_REG long REG r9
[000092] ------------ PINVOKE_PROLOG void
N001 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR long V15 PInvokeFrame
/--* t93 long
[000096] ------------ t96 = * PUTARG_REG long REG rcx
N001 ( 3, 10) [000097] -c---------- t97 = CNS_INT(h) long 0x4200E8 ftn
/--* t97 long
N002 ( 5, 12) [000098] -c---------- t98 = * IND long REG NA
/--* t96 long arg0 in rcx
+--* t98 long control expr
N002 ( 17, 9) [000094] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
N001 ( 3, 10) [000099] -c---------- t99 = CNS_INT(h) long 0x4200F0 ftn
/--* t99 long
N002 ( 5, 12) [000100] ------------ t100 = * IND long
/--* t100 long
N003 ( 8, 14) [000101] -c---------- t101 = * IND long REG NA
/--* t88 long arg0 in rcx
+--* t89 long arg1 in rdx
+--* t90 int arg2 in r8
+--* t91 long arg3 in r9
+--* t101 long control expr
N010 ( 32, 19) [000025] --CXG------- t25 = * CALL r2r_ind int Kernel32.ReadFile
N001 ( 3, 3) [000102] ------------ t102 = LCL_VAR_ADDR long V15 PInvokeFrame
/--* t102 long
[000105] ------------ t105 = * PUTARG_REG long REG rcx
N001 ( 3, 10) [000106] -c---------- t106 = CNS_INT(h) long 0x4200F8 ftn
/--* t106 long
N002 ( 5, 12) [000107] -c---------- t107 = * IND long REG NA
/--* t105 long arg0 in rcx
+--* t107 long control expr
N002 ( 17, 9) [000103] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END
/--* t25 int
N012 ( 36, 22) [000027] DA-XG------- * STORE_LCL_VAR int V13 tmp2
[000070] ------------ IL_OFFSET void IL offset: 0x2a
N001 ( 3, 10) [000108] -c---------- t108 = CNS_INT(h) long 0x4200C8 ftn
/--* t108 long
N002 ( 5, 12) [000109] -c---------- t109 = * IND long REG NA
/--* t109 long control expr
N001 ( 14, 5) [000029] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError
[000071] ------------ IL_OFFSET void IL offset: 0x2f
N001 ( 3, 2) [000028] ------------ t28 = LCL_VAR int V13 tmp2
/--* t28 int
N003 ( 7, 5) [000031] DA---------- * STORE_LCL_VAR int V06 loc1
[000072] ------------ IL_OFFSET void IL offset: 0x30
N001 ( 3, 2) [000032] ------------ t32 = LCL_VAR int V06 loc1
/--* t32 int
N003 ( 7, 5) [000034] DA---------- * STORE_LCL_VAR int V05 loc0
[000073] ------------ IL_OFFSET void IL offset: 0x32
N001 ( 0, 0) [000035] ------------ NOP void
------------ BB03 [???..???) -> BB05 (callf), preds={BB02} succs={BB05}
------------ BB04 [???..???) -> BB08 (ALWAYS), preds={BB07} succs={BB08}
------------ BB08 [044..046) -> BB09 (always), preds={BB04} succs={BB09}
[000074] ------------ IL_OFFSET void IL offset: 0x44
N001 ( 3, 2) [000036] ------------ t36 = LCL_VAR int V05 loc0
/--* t36 int
N003 ( 7, 5) [000062] DA---------- * STORE_LCL_VAR int V14 tmp3
------------ BB09 [???..???) (return), preds={BB08} succs={}
N001 ( 3, 2) [000045] -------N---- t45 = LCL_VAR int V14 tmp3
/--* t45 int
N002 ( 4, 3) [000046] ------------ * RETURN int
------------ BB05 [037..03D) -> BB07 (cond), preds={BB03} succs={BB06,BB07}
[000075] ------------ IL_OFFSET void IL offset: 0x37
N001 ( 3, 2) [000038] ------------ t38 = LCL_VAR int (AX) V08 loc3
/--* t38 int
N002 ( 4, 4) [000059] ----G------- t59 = * CAST int <- bool <- int
N003 ( 1, 1) [000039] -c---------- t39 = CNS_INT int 0
/--* t59 int
+--* t39 int
N004 ( 6, 6) [000040] J---G--N---- * EQ void
N005 ( 8, 8) [000041] ----G------- * JTRUE void
------------ BB06 [03D..043), preds={BB05} succs={BB07}
[000076] ------------ IL_OFFSET void IL offset: 0x3d
N002 ( 3, 2) [000043] ------------ t43 = LCL_VAR ref V00 arg0
/--* t43 ref
[000110] ------------ t110 = * PUTARG_REG ref REG rcx
N001 ( 3, 10) [000111] -c---------- t111 = CNS_INT(h) long 0x4200E0 ftn
/--* t111 long
N002 ( 5, 12) [000112] -c---------- t112 = * IND long REG NA
/--* t110 ref this in rcx
+--* t112 long control expr
N003 ( 17, 9) [000044] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
------------ BB07 [043..044) (finret), preds={BB05,BB06} succs={BB04}
[000077] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 0, 0) [000042] ------------ RETFILT void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Trees before Calculate stack level slots
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target LIR
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target LIR
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target LIR KEEP
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target LIR
BB09 [0008] 1 BB08 1 [???..???) (return) keep internal target LIR
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 F finally { keep i label target flet LIR
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i gcsafe LIR
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
N001 ( 0, 0) [000000] ------------ NOP void
------------ BB02 [000..037) -> BB03 (always), preds={BB01} succs={BB03}
[000063] ------------ IL_OFFSET void IL offset: 0x0
N003 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V08 loc3
/--* t3 long
[000078] ------------ t78 = * PUTARG_REG long REG rdx
N004 ( 3, 2) [000001] ------------ t1 = LCL_VAR ref V00 arg0
/--* t1 ref
[000079] ------------ t79 = * PUTARG_REG ref REG rcx
N001 ( 3, 10) [000080] -c---------- t80 = CNS_INT(h) long 0x420058 ftn
/--* t80 long
N002 ( 5, 12) [000081] -c---------- t81 = * IND long REG NA
/--* t78 long arg1 in rdx
+--* t79 ref this in rcx
+--* t81 long control expr
N005 ( 20, 13) [000004] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef
[000064] ------------ IL_OFFSET void IL offset: 0x8
N002 ( 3, 2) [000005] ------------ t5 = LCL_VAR ref V00 arg0
/--* t5 ref
[000082] ------------ t82 = * PUTARG_REG ref REG rcx
N001 ( 3, 10) [000083] -c---------- t83 = CNS_INT(h) long 0x420080 ftn
/--* t83 long
N002 ( 5, 12) [000084] -c---------- t84 = * IND long REG NA
/--* t82 ref this in rcx
+--* t84 long control expr
N003 ( 17, 9) [000006] --CXG------- t6 = * CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle
/--* t6 long
N005 ( 21, 12) [000008] DA-XG------- * STORE_LCL_VAR long V12 tmp1
[000065] ------------ IL_OFFSET void IL offset: 0xe
N001 ( 3, 2) [000009] ------------ t9 = LCL_VAR long V12 tmp1
/--* t9 long
N003 ( 7, 5) [000011] DA---------- * STORE_LCL_VAR long V07 loc2
[000066] ------------ IL_OFFSET void IL offset: 0xf
N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V03 arg3
/--* t12 byref
N003 ( 7, 5) [000014] DA---------- * STORE_LCL_VAR byref V10 loc5
[000067] ------------ IL_OFFSET void IL offset: 0x12
N001 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V10 loc5
/--* t15 byref
N003 ( 7, 5) [000051] DA---------- * STORE_LCL_VAR long V16 tmp5
N004 ( 3, 2) [000052] ------------ t52 = LCL_VAR long V16 tmp5
/--* t52 long
N007 ( 14, 10) [000018] DA---------- * STORE_LCL_VAR long V09 loc4
[000068] ------------ IL_OFFSET void IL offset: 0x17
N001 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x4200A0 ftn
/--* t85 long
N002 ( 5, 12) [000086] -c---------- t86 = * IND long REG NA
/--* t86 long control expr
N001 ( 14, 5) [000024] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError
[000069] ------------ IL_OFFSET void IL offset: 0x25
N005 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V04 arg4
/--* t23 long
[000087] ------------ * PUTARG_STK [+0x20] void
N006 ( 3, 2) [000019] ------------ t19 = LCL_VAR long V07 loc2
/--* t19 long
[000088] ------------ t88 = * PUTARG_REG long REG rcx
N007 ( 3, 2) [000020] ------------ t20 = LCL_VAR long V01 arg1
/--* t20 long
[000089] ------------ t89 = * PUTARG_REG long REG rdx
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR int V02 arg2
/--* t21 int
[000090] ------------ t90 = * PUTARG_REG int REG r8
N009 ( 3, 2) [000022] ------------ t22 = LCL_VAR long V09 loc4
/--* t22 long
[000091] ------------ t91 = * PUTARG_REG long REG r9
[000092] ------------ PINVOKE_PROLOG void
N001 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR long V15 PInvokeFrame
/--* t93 long
[000096] ------------ t96 = * PUTARG_REG long REG rcx
N001 ( 3, 10) [000097] -c---------- t97 = CNS_INT(h) long 0x4200E8 ftn
/--* t97 long
N002 ( 5, 12) [000098] -c---------- t98 = * IND long REG NA
/--* t96 long arg0 in rcx
+--* t98 long control expr
N002 ( 17, 9) [000094] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN
N001 ( 3, 10) [000099] -c---------- t99 = CNS_INT(h) long 0x4200F0 ftn
/--* t99 long
N002 ( 5, 12) [000100] ------------ t100 = * IND long
/--* t100 long
N003 ( 8, 14) [000101] -c---------- t101 = * IND long REG NA
/--* t88 long arg0 in rcx
+--* t89 long arg1 in rdx
+--* t90 int arg2 in r8
+--* t91 long arg3 in r9
+--* t101 long control expr
N010 ( 32, 19) [000025] --CXG------- t25 = * CALL r2r_ind int Kernel32.ReadFile
N001 ( 3, 3) [000102] ------------ t102 = LCL_VAR_ADDR long V15 PInvokeFrame
/--* t102 long
[000105] ------------ t105 = * PUTARG_REG long REG rcx
N001 ( 3, 10) [000106] -c---------- t106 = CNS_INT(h) long 0x4200F8 ftn
/--* t106 long
N002 ( 5, 12) [000107] -c---------- t107 = * IND long REG NA
/--* t105 long arg0 in rcx
+--* t107 long control expr
N002 ( 17, 9) [000103] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END
/--* t25 int
N012 ( 36, 22) [000027] DA-XG------- * STORE_LCL_VAR int V13 tmp2
[000070] ------------ IL_OFFSET void IL offset: 0x2a
N001 ( 3, 10) [000108] -c---------- t108 = CNS_INT(h) long 0x4200C8 ftn
/--* t108 long
N002 ( 5, 12) [000109] -c---------- t109 = * IND long REG NA
/--* t109 long control expr
N001 ( 14, 5) [000029] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError
[000071] ------------ IL_OFFSET void IL offset: 0x2f
N001 ( 3, 2) [000028] ------------ t28 = LCL_VAR int V13 tmp2
/--* t28 int
N003 ( 7, 5) [000031] DA---------- * STORE_LCL_VAR int V06 loc1
[000072] ------------ IL_OFFSET void IL offset: 0x30
N001 ( 3, 2) [000032] ------------ t32 = LCL_VAR int V06 loc1
/--* t32 int
N003 ( 7, 5) [000034] DA---------- * STORE_LCL_VAR int V05 loc0
[000073] ------------ IL_OFFSET void IL offset: 0x32
N001 ( 0, 0) [000035] ------------ NOP void
------------ BB03 [???..???) -> BB05 (callf), preds={BB02} succs={BB05}
------------ BB04 [???..???) -> BB08 (ALWAYS), preds={BB07} succs={BB08}
------------ BB08 [044..046) -> BB09 (always), preds={BB04} succs={BB09}
[000074] ------------ IL_OFFSET void IL offset: 0x44
N001 ( 3, 2) [000036] ------------ t36 = LCL_VAR int V05 loc0
/--* t36 int
N003 ( 7, 5) [000062] DA---------- * STORE_LCL_VAR int V14 tmp3
------------ BB09 [???..???) (return), preds={BB08} succs={}
N001 ( 3, 2) [000045] -------N---- t45 = LCL_VAR int V14 tmp3
/--* t45 int
N002 ( 4, 3) [000046] ------------ * RETURN int
------------ BB05 [037..03D) -> BB07 (cond), preds={BB03} succs={BB06,BB07}
[000075] ------------ IL_OFFSET void IL offset: 0x37
N001 ( 3, 2) [000038] ------------ t38 = LCL_VAR int (AX) V08 loc3
/--* t38 int
N002 ( 4, 4) [000059] ----G------- t59 = * CAST int <- bool <- int
N003 ( 1, 1) [000039] -c---------- t39 = CNS_INT int 0
/--* t59 int
+--* t39 int
N004 ( 6, 6) [000040] J---G--N---- * EQ void
N005 ( 8, 8) [000041] ----G------- * JTRUE void
------------ BB06 [03D..043), preds={BB05} succs={BB07}
[000076] ------------ IL_OFFSET void IL offset: 0x3d
N002 ( 3, 2) [000043] ------------ t43 = LCL_VAR ref V00 arg0
/--* t43 ref
[000110] ------------ t110 = * PUTARG_REG ref REG rcx
N001 ( 3, 10) [000111] -c---------- t111 = CNS_INT(h) long 0x4200E0 ftn
/--* t111 long
N002 ( 5, 12) [000112] -c---------- t112 = * IND long REG NA
/--* t110 ref this in rcx
+--* t112 long control expr
N003 ( 17, 9) [000044] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease
------------ BB07 [043..044) (finret), preds={BB05,BB06} succs={BB04}
[000077] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 0, 0) [000042] ------------ RETFILT void
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots [no changes]
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{}
{}
{}
{}
BB02 use def in out
{}
{}
{}
{}
BB03 use def in out
{}
{}
{}
{}
BB04 use def in out
{}
{}
{}
{}
BB08 use def in out
{}
{}
{}
{}
BB09 use def in out
{}
{}
{}
{}
BB05 use def in out
{}
{}
{}
{}
BB06 use def in out
{}
{}
{}
{}
BB07 use def in out
{}
{}
{}
{}
EH Vars: {}
Finally Vars: {}
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 )
BB02( 1 )
BB03( 1 )
BB05( 1 ) EH-in
BB06( 1 )
BB07( 1 ) EH-out
BB04( 1 ) EH-in EH-out
BB08( 1 ) EH-in
BB09( 1 )
BB01 [???..???), preds={} succs={BB02}
=====
N001. NOP
BB02 [000..037) -> BB03 (always), preds={BB01} succs={BB03}
=====
N000. IL_OFFSET IL offset: 0x0
N003. t3 = LCL_VAR_ADDR V08 loc3
N000. t78 = PUTARG_REG; t3
N004. t1 = V00 MEM
N000. t79 = PUTARG_REG; t1
N001. CNS_INT(h) 0x420058 ftn
N002. IND
N005. CALL r2r_ind; t78,t79
N000. IL_OFFSET IL offset: 0x8
N002. t5 = V00 MEM
N000. t82 = PUTARG_REG; t5
N001. CNS_INT(h) 0x420080 ftn
N002. IND
N003. t6 = CALL r2r_ind; t82
N005. V12 MEM; t6
N000. IL_OFFSET IL offset: 0xe
N001. t9 = V12 MEM
N003. V07 MEM; t9
N000. IL_OFFSET IL offset: 0xf
N001. t12 = V03 MEM
N003. V10 MEM; t12
N000. IL_OFFSET IL offset: 0x12
N001. t15 = V10 MEM
N003. V16 MEM; t15
N004. t52 = V16 MEM
N007. V09 MEM; t52
N000. IL_OFFSET IL offset: 0x17
N001. CNS_INT(h) 0x4200A0 ftn
N002. IND
N001. CALL r2r_ind
N000. IL_OFFSET IL offset: 0x25
N005. t23 = V04 MEM
N000. PUTARG_STK [+0x20]; t23
N006. t19 = V07 MEM
N000. t88 = PUTARG_REG; t19
N007. t20 = V01 MEM
N000. t89 = PUTARG_REG; t20
N008. t21 = V02 MEM
N000. t90 = PUTARG_REG; t21
N009. t22 = V09 MEM
N000. t91 = PUTARG_REG; t22
N000. PINVOKE_PROLOG
N001. t93 = LCL_VAR_ADDR V15 PInvokeFrame
N000. t96 = PUTARG_REG; t93
N001. CNS_INT(h) 0x4200E8 ftn
N002. IND
N002. CALL help; t96
N001. CNS_INT(h) 0x4200F0 ftn
N002. t100 = IND
N003. t101 = IND ; t100
N010. t25 = CALL r2r_ind; t88,t89,t90,t91,t101
N001. t102 = LCL_VAR_ADDR V15 PInvokeFrame
N000. t105 = PUTARG_REG; t102
N001. CNS_INT(h) 0x4200F8 ftn
N002. IND
N002. CALL help; t105
N012. V13 MEM; t25
N000. IL_OFFSET IL offset: 0x2a
N001. CNS_INT(h) 0x4200C8 ftn
N002. IND
N001. CALL r2r_ind
N000. IL_OFFSET IL offset: 0x2f
N001. t28 = V13 MEM
N003. V06 MEM; t28
N000. IL_OFFSET IL offset: 0x30
N001. t32 = V06 MEM
N003. V05 MEM; t32
N000. IL_OFFSET IL offset: 0x32
N001. NOP
BB03 [???..???) -> BB05 (callf), preds={BB02} succs={BB05}
=====
BB05 [037..03D) -> BB07 (cond), preds={BB03} succs={BB06,BB07}
=====
N000. IL_OFFSET IL offset: 0x37
N001. t38 = V08 MEM
N002. t59 = CAST ; t38
N003. CNS_INT 0
N004. EQ ; t59
N005. JTRUE
BB06 [03D..043), preds={BB05} succs={BB07}
=====
N000. IL_OFFSET IL offset: 0x3d
N002. t43 = V00 MEM
N000. t110 = PUTARG_REG; t43
N001. CNS_INT(h) 0x4200E0 ftn
N002. IND
N003. CALL r2r_ind; t110
BB07 [043..044) (finret), preds={BB05,BB06} succs={BB04}
=====
N000. IL_OFFSET IL offset: 0x43
N001. RETFILT
BB04 [???..???) -> BB08 (ALWAYS), preds={BB07} succs={BB08}
=====
BB08 [044..046) -> BB09 (always), preds={BB04} succs={BB09}
=====
N000. IL_OFFSET IL offset: 0x44
N001. t36 = V05 MEM
N003. V14 MEM; t36
BB09 [???..???) (return), preds={BB08} succs={}
=====
N001. t45 = V14 MEM
N002. RETURN ; t45
buildIntervals second part ========
Int arg V00 in reg rcx
Int arg V01 in reg rdx
Int arg V02 in reg r8
Int arg V03 in reg r9
NEW BLOCK BB01
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N002 ( 0, 0) [000000] ------------ * NOP void REG NA
NEW BLOCK BB02
Setting BB01 as the predecessor for determining incoming variable registers of BB02
<RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
DefList: { }
N006 (???,???) [000063] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
DefList: { }
N008 ( 3, 3) [000003] ------------ * LCL_VAR_ADDR long V08 loc3 NA REG NA
Interval 0: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #2 @9 RefTypeDef <Ivl:0> LCL_VAR_ADDR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N008.t3. LCL_VAR_ADDR }
N010 (???,???) [000078] ------------ * PUTARG_REG long REG rdx
<RefPosition #3 @10 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #4 @10 RefTypeUse <Ivl:0> BB02 regmask=[rdx] minReg=1 last fixed>
Interval 1: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #5 @11 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #6 @11 RefTypeDef <Ivl:1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed>
DefList: { N010.t78. PUTARG_REG }
N012 ( 3, 2) [000001] ------------ * LCL_VAR ref V00 arg0 NA REG NA
Interval 2: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #7 @13 RefTypeDef <Ivl:2> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N010.t78. PUTARG_REG; N012.t1. LCL_VAR }
N014 (???,???) [000079] ------------ * PUTARG_REG ref REG rcx
<RefPosition #8 @14 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #9 @14 RefTypeUse <Ivl:2> BB02 regmask=[rcx] minReg=1 last fixed>
Interval 3: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #10 @15 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #11 @15 RefTypeDef <Ivl:3> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
DefList: { N010.t78. PUTARG_REG; N014.t79. PUTARG_REG }
N016 ( 3, 10) [000080] -c---------- * CNS_INT(h) long 0x420058 ftn REG NA
Contained
DefList: { N010.t78. PUTARG_REG; N014.t79. PUTARG_REG }
N018 ( 5, 12) [000081] -c---------- * IND long REG NA
Contained
DefList: { N010.t78. PUTARG_REG; N014.t79. PUTARG_REG }
N020 ( 20, 13) [000004] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef REG NA
<RefPosition #12 @20 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #13 @20 RefTypeUse <Ivl:1> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #14 @20 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #15 @20 RefTypeUse <Ivl:3> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #16 @21 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #17 @21 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #18 @21 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #19 @21 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #20 @21 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #21 @21 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1>
<RefPosition #22 @21 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1>
DefList: { }
N022 (???,???) [000064] ------------ * IL_OFFSET void IL offset: 0x8 REG NA
DefList: { }
N024 ( 3, 2) [000005] ------------ * LCL_VAR ref V00 arg0 NA REG NA
Interval 4: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #23 @25 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N024.t5. LCL_VAR }
N026 (???,???) [000082] ------------ * PUTARG_REG ref REG rcx
<RefPosition #24 @26 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #25 @26 RefTypeUse <Ivl:4> BB02 regmask=[rcx] minReg=1 last fixed>
Interval 5: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #26 @27 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #27 @27 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
DefList: { N026.t82. PUTARG_REG }
N028 ( 3, 10) [000083] -c---------- * CNS_INT(h) long 0x420080 ftn REG NA
Contained
DefList: { N026.t82. PUTARG_REG }
N030 ( 5, 12) [000084] -c---------- * IND long REG NA
Contained
DefList: { N026.t82. PUTARG_REG }
N032 ( 17, 9) [000006] --CXG------- * CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle REG NA
<RefPosition #28 @32 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #29 @32 RefTypeUse <Ivl:5> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #30 @33 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #31 @33 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #32 @33 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #33 @33 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #34 @33 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #35 @33 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1>
<RefPosition #36 @33 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1>
Interval 6: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #37 @33 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #38 @33 RefTypeDef <Ivl:6> CALL BB02 regmask=[rax] minReg=1 fixed>
DefList: { N032.t6. CALL }
N034 ( 21, 12) [000008] DA-XG------- * STORE_LCL_VAR long V12 tmp1 NA REG NA
<RefPosition #39 @34 RefTypeUse <Ivl:6> BB02 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N036 (???,???) [000065] ------------ * IL_OFFSET void IL offset: 0xe REG NA
DefList: { }
N038 ( 3, 2) [000009] ------------ * LCL_VAR long V12 tmp1 NA REG NA
Interval 7: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #40 @39 RefTypeDef <Ivl:7> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N038.t9. LCL_VAR }
N040 ( 7, 5) [000011] DA---------- * STORE_LCL_VAR long V07 loc2 NA REG NA
<RefPosition #41 @40 RefTypeUse <Ivl:7> BB02 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N042 (???,???) [000066] ------------ * IL_OFFSET void IL offset: 0xf REG NA
DefList: { }
N044 ( 3, 2) [000012] ------------ * LCL_VAR byref V03 arg3 NA REG NA
Interval 8: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #42 @45 RefTypeDef <Ivl:8> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N044.t12. LCL_VAR }
N046 ( 7, 5) [000014] DA---------- * STORE_LCL_VAR byref V10 loc5 NA REG NA
<RefPosition #43 @46 RefTypeUse <Ivl:8> BB02 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N048 (???,???) [000067] ------------ * IL_OFFSET void IL offset: 0x12 REG NA
DefList: { }
N050 ( 3, 2) [000015] ------------ * LCL_VAR byref V10 loc5 NA REG NA
Interval 9: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #44 @51 RefTypeDef <Ivl:9> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N050.t15. LCL_VAR }
N052 ( 7, 5) [000051] DA---------- * STORE_LCL_VAR long V16 tmp5 NA REG NA
<RefPosition #45 @52 RefTypeUse <Ivl:9> BB02 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N054 ( 3, 2) [000052] ------------ * LCL_VAR long V16 tmp5 NA REG NA
Interval 10: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #46 @55 RefTypeDef <Ivl:10> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N054.t52. LCL_VAR }
N056 ( 14, 10) [000018] DA---------- * STORE_LCL_VAR long V09 loc4 NA REG NA
<RefPosition #47 @56 RefTypeUse <Ivl:10> BB02 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N058 (???,???) [000068] ------------ * IL_OFFSET void IL offset: 0x17 REG NA
DefList: { }
N060 ( 3, 10) [000085] -c---------- * CNS_INT(h) long 0x4200A0 ftn REG NA
Contained
DefList: { }
N062 ( 5, 12) [000086] -c---------- * IND long REG NA
Contained
DefList: { }
N064 ( 14, 5) [000024] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError REG NA
<RefPosition #48 @65 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #49 @65 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #50 @65 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #51 @65 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #52 @65 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #53 @65 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1>
<RefPosition #54 @65 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1>
DefList: { }
N066 (???,???) [000069] ------------ * IL_OFFSET void IL offset: 0x25 REG NA
DefList: { }
N068 ( 3, 2) [000023] ------------ * LCL_VAR long V04 arg4 NA REG NA
Interval 11: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #55 @69 RefTypeDef <Ivl:11> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N068.t23. LCL_VAR }
N070 (???,???) [000087] ------------ * PUTARG_STK [+0x20] void REG NA
<RefPosition #56 @70 RefTypeUse <Ivl:11> BB02 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N072 ( 3, 2) [000019] ------------ * LCL_VAR long V07 loc2 NA REG NA
Interval 12: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #57 @73 RefTypeDef <Ivl:12> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N072.t19. LCL_VAR }
N074 (???,???) [000088] ------------ * PUTARG_REG long REG rcx
<RefPosition #58 @74 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #59 @74 RefTypeUse <Ivl:12> BB02 regmask=[rcx] minReg=1 last fixed>
Interval 13: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #60 @75 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #61 @75 RefTypeDef <Ivl:13> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
DefList: { N074.t88. PUTARG_REG }
N076 ( 3, 2) [000020] ------------ * LCL_VAR long V01 arg1 NA REG NA
Interval 14: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #62 @77 RefTypeDef <Ivl:14> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N074.t88. PUTARG_REG; N076.t20. LCL_VAR }
N078 (???,???) [000089] ------------ * PUTARG_REG long REG rdx
<RefPosition #63 @78 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #64 @78 RefTypeUse <Ivl:14> BB02 regmask=[rdx] minReg=1 last fixed>
Interval 15: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #65 @79 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #66 @79 RefTypeDef <Ivl:15> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed>
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG }
N080 ( 3, 2) [000021] ------------ * LCL_VAR int V02 arg2 NA REG NA
Interval 16: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #67 @81 RefTypeDef <Ivl:16> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N080.t21. LCL_VAR }
N082 (???,???) [000090] ------------ * PUTARG_REG int REG r8
<RefPosition #68 @82 RefTypeFixedReg <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #69 @82 RefTypeUse <Ivl:16> BB02 regmask=[r8] minReg=1 last fixed>
Interval 17: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #70 @83 RefTypeFixedReg <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #71 @83 RefTypeDef <Ivl:17> PUTARG_REG BB02 regmask=[r8] minReg=1 fixed>
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N082.t90. PUTARG_REG }
N084 ( 3, 2) [000022] ------------ * LCL_VAR long V09 loc4 NA REG NA
Interval 18: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #72 @85 RefTypeDef <Ivl:18> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N082.t90. PUTARG_REG; N084.t22. LCL_VAR }
N086 (???,???) [000091] ------------ * PUTARG_REG long REG r9
<RefPosition #73 @86 RefTypeFixedReg <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #74 @86 RefTypeUse <Ivl:18> BB02 regmask=[r9] minReg=1 last fixed>
Interval 19: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #75 @87 RefTypeFixedReg <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #76 @87 RefTypeDef <Ivl:19> PUTARG_REG BB02 regmask=[r9] minReg=1 fixed>
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N082.t90. PUTARG_REG; N086.t91. PUTARG_REG }
N088 (???,???) [000092] ------------ * PINVOKE_PROLOG void REG NA
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N082.t90. PUTARG_REG; N086.t91. PUTARG_REG }
N090 ( 3, 3) [000093] ------------ * LCL_VAR_ADDR long V15 PInvokeFrame NA REG NA
Interval 20: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #77 @91 RefTypeDef <Ivl:20> LCL_VAR_ADDR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N082.t90. PUTARG_REG; N086.t91. PUTARG_REG; N090.t93. LCL_VAR_ADDR }
N092 (???,???) [000096] ------------ * PUTARG_REG long REG rcx
<RefPosition #78 @92 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #79 @92 RefTypeUse <Ivl:20> BB02 regmask=[rcx] minReg=1 last fixed>
Interval 21: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #80 @93 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #81 @93 RefTypeDef <Ivl:21> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N082.t90. PUTARG_REG; N086.t91. PUTARG_REG; N092.t96. PUTARG_REG }
N094 ( 3, 10) [000097] -c---------- * CNS_INT(h) long 0x4200E8 ftn REG NA
Contained
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N082.t90. PUTARG_REG; N086.t91. PUTARG_REG; N092.t96. PUTARG_REG }
N096 ( 5, 12) [000098] -c---------- * IND long REG NA
Contained
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N082.t90. PUTARG_REG; N086.t91. PUTARG_REG; N092.t96. PUTARG_REG }
N098 ( 17, 9) [000094] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN REG NA
<RefPosition #82 @98 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #83 @98 RefTypeUse <Ivl:21> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #84 @99 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #85 @99 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #86 @99 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #87 @99 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #88 @99 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #89 @99 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1>
<RefPosition #90 @99 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1>
<RefPosition #91 @99 RefTypeKillGCRefs CALL BB02 regmask=[rax rbx rsi rdi r10-r15] minReg=1>
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N082.t90. PUTARG_REG; N086.t91. PUTARG_REG }
N100 ( 3, 10) [000099] -c---------- * CNS_INT(h) long 0x4200F0 ftn REG NA
Contained
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N082.t90. PUTARG_REG; N086.t91. PUTARG_REG }
N102 ( 5, 12) [000100] ------------ * IND long REG NA
Interval 22: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #92 @103 RefTypeDef <Ivl:22> IND BB02 regmask=[allIntButFP] minReg=1>
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N082.t90. PUTARG_REG; N086.t91. PUTARG_REG; N102.t100. IND }
N104 ( 8, 14) [000101] -c---------- * IND long REG NA
Contained
DefList: { N074.t88. PUTARG_REG; N078.t89. PUTARG_REG; N082.t90. PUTARG_REG; N086.t91. PUTARG_REG; N102.t100. IND }
N106 ( 32, 19) [000025] --CXG------- * CALL r2r_ind int Kernel32.ReadFile REG NA
<RefPosition #93 @106 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #94 @106 RefTypeUse <Ivl:13> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #95 @106 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #96 @106 RefTypeUse <Ivl:15> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #97 @106 RefTypeFixedReg <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #98 @106 RefTypeUse <Ivl:17> BB02 regmask=[r8] minReg=1 last fixed>
<RefPosition #99 @106 RefTypeFixedReg <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #100 @106 RefTypeUse <Ivl:19> BB02 regmask=[r9] minReg=1 last fixed>
<RefPosition #101 @106 RefTypeUse <Ivl:22> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #102 @107 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #103 @107 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #104 @107 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #105 @107 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #106 @107 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #107 @107 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1>
<RefPosition #108 @107 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1>
<RefPosition #109 @107 RefTypeKillGCRefs CALL BB02 regmask=[rax rbx rsi rdi r10-r15] minReg=1>
Interval 23: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #110 @107 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #111 @107 RefTypeDef <Ivl:23> CALL BB02 regmask=[rax] minReg=1 fixed>
DefList: { N106.t25. CALL }
N108 ( 3, 3) [000102] ------------ * LCL_VAR_ADDR long V15 PInvokeFrame NA REG NA
Interval 24: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #112 @109 RefTypeDef <Ivl:24> LCL_VAR_ADDR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N106.t25. CALL; N108.t102. LCL_VAR_ADDR }
N110 (???,???) [000105] ------------ * PUTARG_REG long REG rcx
<RefPosition #113 @110 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #114 @110 RefTypeUse <Ivl:24> BB02 regmask=[rcx] minReg=1 last fixed>
Interval 25: long RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #115 @111 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #116 @111 RefTypeDef <Ivl:25> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
DefList: { N106.t25. CALL; N110.t105. PUTARG_REG }
N112 ( 3, 10) [000106] -c---------- * CNS_INT(h) long 0x4200F8 ftn REG NA
Contained
DefList: { N106.t25. CALL; N110.t105. PUTARG_REG }
N114 ( 5, 12) [000107] -c---------- * IND long REG NA
Contained
DefList: { N106.t25. CALL; N110.t105. PUTARG_REG }
N116 ( 17, 9) [000103] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END REG NA
<RefPosition #117 @116 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #118 @116 RefTypeUse <Ivl:25> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #119 @117 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #120 @117 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #121 @117 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #122 @117 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #123 @117 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #124 @117 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1>
<RefPosition #125 @117 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1>
DefList: { N106.t25. CALL }
N118 ( 36, 22) [000027] DA-XG------- * STORE_LCL_VAR int V13 tmp2 NA REG NA
<RefPosition #126 @118 RefTypeUse <Ivl:23> BB02 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N120 (???,???) [000070] ------------ * IL_OFFSET void IL offset: 0x2a REG NA
DefList: { }
N122 ( 3, 10) [000108] -c---------- * CNS_INT(h) long 0x4200C8 ftn REG NA
Contained
DefList: { }
N124 ( 5, 12) [000109] -c---------- * IND long REG NA
Contained
DefList: { }
N126 ( 14, 5) [000029] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError REG NA
<RefPosition #127 @127 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #128 @127 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #129 @127 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #130 @127 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #131 @127 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #132 @127 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1>
<RefPosition #133 @127 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1>
DefList: { }
N128 (???,???) [000071] ------------ * IL_OFFSET void IL offset: 0x2f REG NA
DefList: { }
N130 ( 3, 2) [000028] ------------ * LCL_VAR int V13 tmp2 NA REG NA
Interval 26: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #134 @131 RefTypeDef <Ivl:26> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N130.t28. LCL_VAR }
N132 ( 7, 5) [000031] DA---------- * STORE_LCL_VAR int V06 loc1 NA REG NA
<RefPosition #135 @132 RefTypeUse <Ivl:26> BB02 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N134 (???,???) [000072] ------------ * IL_OFFSET void IL offset: 0x30 REG NA
DefList: { }
N136 ( 3, 2) [000032] ------------ * LCL_VAR int V06 loc1 NA REG NA
Interval 27: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #136 @137 RefTypeDef <Ivl:27> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
DefList: { N136.t32. LCL_VAR }
N138 ( 7, 5) [000034] DA---------- * STORE_LCL_VAR int V05 loc0 NA REG NA
<RefPosition #137 @138 RefTypeUse <Ivl:27> BB02 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N140 (???,???) [000073] ------------ * IL_OFFSET void IL offset: 0x32 REG NA
DefList: { }
N142 ( 0, 0) [000035] ------------ * NOP void REG NA
NEW BLOCK BB03
Setting BB02 as the predecessor for determining incoming variable registers of BB03
<RefPosition #138 @144 RefTypeBB BB03 regmask=[] minReg=1>
NEW BLOCK BB05
Incoming EH boundary; <RefPosition #139 @146 RefTypeBB BB05 regmask=[] minReg=1>
DefList: { }
N148 (???,???) [000075] ------------ * IL_OFFSET void IL offset: 0x37 REG NA
DefList: { }
N150 ( 3, 2) [000038] ------------ * LCL_VAR int (AX) V08 loc3 NA REG NA
Interval 28: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #140 @151 RefTypeDef <Ivl:28> LCL_VAR BB05 regmask=[allIntButFP] minReg=1>
DefList: { N150.t38. LCL_VAR }
N152 ( 4, 4) [000059] ----G------- * CAST int <- bool <- int REG NA
<RefPosition #141 @152 RefTypeUse <Ivl:28> BB05 regmask=[allIntButFP] minReg=1 last>
Interval 29: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #142 @153 RefTypeDef <Ivl:29> CAST BB05 regmask=[allIntButFP] minReg=1>
DefList: { N152.t59. CAST }
N154 ( 1, 1) [000039] -c---------- * CNS_INT int 0 REG NA
Contained
DefList: { N152.t59. CAST }
N156 ( 6, 6) [000040] J---G--N---- * EQ void REG NA
<RefPosition #143 @156 RefTypeUse <Ivl:29> BB05 regmask=[allIntButFP] minReg=1 last>
DefList: { }
N158 ( 8, 8) [000041] ----G------- * JTRUE void REG NA
NEW BLOCK BB06
Setting BB05 as the predecessor for determining incoming variable registers of BB06
<RefPosition #144 @160 RefTypeBB BB06 regmask=[] minReg=1>
DefList: { }
N162 (???,???) [000076] ------------ * IL_OFFSET void IL offset: 0x3d REG NA
DefList: { }
N164 ( 3, 2) [000043] ------------ * LCL_VAR ref V00 arg0 NA REG NA
Interval 30: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #145 @165 RefTypeDef <Ivl:30> LCL_VAR BB06 regmask=[allIntButFP] minReg=1>
DefList: { N164.t43. LCL_VAR }
N166 (???,???) [000110] ------------ * PUTARG_REG ref REG rcx
<RefPosition #146 @166 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #147 @166 RefTypeUse <Ivl:30> BB06 regmask=[rcx] minReg=1 last fixed>
Interval 31: ref RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #148 @167 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #149 @167 RefTypeDef <Ivl:31> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
DefList: { N166.t110. PUTARG_REG }
N168 ( 3, 10) [000111] -c---------- * CNS_INT(h) long 0x4200E0 ftn REG NA
Contained
DefList: { N166.t110. PUTARG_REG }
N170 ( 5, 12) [000112] -c---------- * IND long REG NA
Contained
DefList: { N166.t110. PUTARG_REG }
N172 ( 17, 9) [000044] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease REG NA
<RefPosition #150 @172 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #151 @172 RefTypeUse <Ivl:31> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #152 @173 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1>
<RefPosition #153 @173 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #154 @173 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1>
<RefPosition #155 @173 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1>
<RefPosition #156 @173 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1>
<RefPosition #157 @173 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1>
<RefPosition #158 @173 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1>
NEW BLOCK BB07
Setting BB05 as the predecessor for determining incoming variable registers of BB07
<RefPosition #159 @174 RefTypeBB BB07 regmask=[] minReg=1>
DefList: { }
N176 (???,???) [000077] ------------ * IL_OFFSET void IL offset: 0x43 REG NA
DefList: { }
N178 ( 0, 0) [000042] ------------ * RETFILT void REG NA
NEW BLOCK BB04
Incoming EH boundary; <RefPosition #160 @180 RefTypeBB BB04 regmask=[] minReg=1>
NEW BLOCK BB08
Incoming EH boundary; <RefPosition #161 @182 RefTypeBB BB08 regmask=[] minReg=1>
DefList: { }
N184 (???,???) [000074] ------------ * IL_OFFSET void IL offset: 0x44 REG NA
DefList: { }
N186 ( 3, 2) [000036] ------------ * LCL_VAR int V05 loc0 NA REG NA
Interval 32: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #162 @187 RefTypeDef <Ivl:32> LCL_VAR BB08 regmask=[allIntButFP] minReg=1>
DefList: { N186.t36. LCL_VAR }
N188 ( 7, 5) [000062] DA---------- * STORE_LCL_VAR int V14 tmp3 NA REG NA
<RefPosition #163 @188 RefTypeUse <Ivl:32> BB08 regmask=[allIntButFP] minReg=1 last>
NEW BLOCK BB09
Setting BB08 as the predecessor for determining incoming variable registers of BB09
<RefPosition #164 @190 RefTypeBB BB09 regmask=[] minReg=1>
DefList: { }
N192 ( 3, 2) [000045] -------N---- * LCL_VAR int V14 tmp3 NA REG NA
Interval 33: int RefPositions {} physReg:NA Preferences=[allIntButFP]
<RefPosition #165 @193 RefTypeDef <Ivl:33> LCL_VAR BB09 regmask=[allIntButFP] minReg=1>
DefList: { N192.t45. LCL_VAR }
N194 ( 4, 3) [000046] ------------ * RETURN int REG NA
<RefPosition #166 @194 RefTypeFixedReg <Reg:rax> BB09 regmask=[rax] minReg=1>
<RefPosition #167 @194 RefTypeUse <Ivl:33> BB09 regmask=[rax] minReg=1 last fixed>
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: long RefPositions {#2@9 #4@10} physReg:NA Preferences=[rdx]
Interval 1: long RefPositions {#6@11 #13@20} physReg:NA Preferences=[rdx]
Interval 2: ref RefPositions {#7@13 #9@14} physReg:NA Preferences=[rcx]
Interval 3: ref RefPositions {#11@15 #15@20} physReg:NA Preferences=[rcx]
Interval 4: ref RefPositions {#23@25 #25@26} physReg:NA Preferences=[rcx]
Interval 5: ref RefPositions {#27@27 #29@32} physReg:NA Preferences=[rcx]
Interval 6: long RefPositions {#38@33 #39@34} physReg:NA Preferences=[rax]
Interval 7: long RefPositions {#40@39 #41@40} physReg:NA Preferences=[allIntButFP]
Interval 8: byref RefPositions {#42@45 #43@46} physReg:NA Preferences=[allIntButFP]
Interval 9: byref RefPositions {#44@51 #45@52} physReg:NA Preferences=[allIntButFP]
Interval 10: long RefPositions {#46@55 #47@56} physReg:NA Preferences=[allIntButFP]
Interval 11: long RefPositions {#55@69 #56@70} physReg:NA Preferences=[allIntButFP]
Interval 12: long RefPositions {#57@73 #59@74} physReg:NA Preferences=[rcx]
Interval 13: long RefPositions {#61@75 #94@106} physReg:NA Preferences=[rcx]
Interval 14: long RefPositions {#62@77 #64@78} physReg:NA Preferences=[rdx]
Interval 15: long RefPositions {#66@79 #96@106} physReg:NA Preferences=[rdx]
Interval 16: int RefPositions {#67@81 #69@82} physReg:NA Preferences=[r8]
Interval 17: int RefPositions {#71@83 #98@106} physReg:NA Preferences=[r8]
Interval 18: long RefPositions {#72@85 #74@86} physReg:NA Preferences=[r9]
Interval 19: long RefPositions {#76@87 #100@106} physReg:NA Preferences=[r9]
Interval 20: long RefPositions {#77@91 #79@92} physReg:NA Preferences=[rcx]
Interval 21: long RefPositions {#81@93 #83@98} physReg:NA Preferences=[rcx]
Interval 22: long RefPositions {#92@103 #101@106} physReg:NA Preferences=[allIntButFP]
Interval 23: int RefPositions {#111@107 #126@118} physReg:NA Preferences=[rax]
Interval 24: long RefPositions {#112@109 #114@110} physReg:NA Preferences=[rcx]
Interval 25: long RefPositions {#116@111 #118@116} physReg:NA Preferences=[rcx]
Interval 26: int RefPositions {#134@131 #135@132} physReg:NA Preferences=[allIntButFP]
Interval 27: int RefPositions {#136@137 #137@138} physReg:NA Preferences=[allIntButFP]
Interval 28: int RefPositions {#140@151 #141@152} physReg:NA Preferences=[allIntButFP]
Interval 29: int RefPositions {#142@153 #143@156} physReg:NA Preferences=[allIntButFP]
Interval 30: ref RefPositions {#145@165 #147@166} physReg:NA Preferences=[rcx]
Interval 31: ref RefPositions {#149@167 #151@172} physReg:NA Preferences=[rcx]
Interval 32: int RefPositions {#162@187 #163@188} physReg:NA Preferences=[allIntButFP]
Interval 33: int RefPositions {#165@193 #167@194} physReg:NA Preferences=[rax]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #2 @9 RefTypeDef <Ivl:0> LCL_VAR_ADDR BB02 regmask=[rdx] minReg=1>
<RefPosition #3 @10 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #4 @10 RefTypeUse <Ivl:0> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #5 @11 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #6 @11 RefTypeDef <Ivl:1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed>
<RefPosition #7 @13 RefTypeDef <Ivl:2> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #8 @14 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #9 @14 RefTypeUse <Ivl:2> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #10 @15 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #11 @15 RefTypeDef <Ivl:3> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #12 @20 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #13 @20 RefTypeUse <Ivl:1> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #14 @20 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #15 @20 RefTypeUse <Ivl:3> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #16 @21 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #17 @21 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #18 @21 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #19 @21 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #20 @21 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #21 @21 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #22 @21 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #23 @25 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #24 @26 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #25 @26 RefTypeUse <Ivl:4> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #26 @27 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #27 @27 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #28 @32 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #29 @32 RefTypeUse <Ivl:5> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #30 @33 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #31 @33 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #32 @33 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #33 @33 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #34 @33 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #35 @33 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #36 @33 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #37 @33 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #38 @33 RefTypeDef <Ivl:6> CALL BB02 regmask=[rax] minReg=1 fixed>
<RefPosition #39 @34 RefTypeUse <Ivl:6> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #40 @39 RefTypeDef <Ivl:7> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #41 @40 RefTypeUse <Ivl:7> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #42 @45 RefTypeDef <Ivl:8> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #43 @46 RefTypeUse <Ivl:8> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #44 @51 RefTypeDef <Ivl:9> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #45 @52 RefTypeUse <Ivl:9> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #46 @55 RefTypeDef <Ivl:10> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #47 @56 RefTypeUse <Ivl:10> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #48 @65 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #49 @65 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #50 @65 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #51 @65 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #52 @65 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #53 @65 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #54 @65 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #55 @69 RefTypeDef <Ivl:11> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #56 @70 RefTypeUse <Ivl:11> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #57 @73 RefTypeDef <Ivl:12> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #58 @74 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #59 @74 RefTypeUse <Ivl:12> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #60 @75 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #61 @75 RefTypeDef <Ivl:13> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #62 @77 RefTypeDef <Ivl:14> LCL_VAR BB02 regmask=[rdx] minReg=1>
<RefPosition #63 @78 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #64 @78 RefTypeUse <Ivl:14> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #65 @79 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #66 @79 RefTypeDef <Ivl:15> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed>
<RefPosition #67 @81 RefTypeDef <Ivl:16> LCL_VAR BB02 regmask=[r8] minReg=1>
<RefPosition #68 @82 RefTypeFixedReg <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #69 @82 RefTypeUse <Ivl:16> BB02 regmask=[r8] minReg=1 last fixed>
<RefPosition #70 @83 RefTypeFixedReg <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #71 @83 RefTypeDef <Ivl:17> PUTARG_REG BB02 regmask=[r8] minReg=1 fixed>
<RefPosition #72 @85 RefTypeDef <Ivl:18> LCL_VAR BB02 regmask=[r9] minReg=1>
<RefPosition #73 @86 RefTypeFixedReg <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #74 @86 RefTypeUse <Ivl:18> BB02 regmask=[r9] minReg=1 last fixed>
<RefPosition #75 @87 RefTypeFixedReg <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #76 @87 RefTypeDef <Ivl:19> PUTARG_REG BB02 regmask=[r9] minReg=1 fixed>
<RefPosition #77 @91 RefTypeDef <Ivl:20> LCL_VAR_ADDR BB02 regmask=[rcx] minReg=1>
<RefPosition #78 @92 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #79 @92 RefTypeUse <Ivl:20> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #80 @93 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #81 @93 RefTypeDef <Ivl:21> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #82 @98 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #83 @98 RefTypeUse <Ivl:21> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #84 @99 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #85 @99 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #86 @99 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #87 @99 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #88 @99 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #89 @99 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #90 @99 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #91 @99 RefTypeKillGCRefs CALL BB02 regmask=[rax rbx rsi rdi r10-r15] minReg=1>
<RefPosition #92 @103 RefTypeDef <Ivl:22> IND BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #93 @106 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #94 @106 RefTypeUse <Ivl:13> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #95 @106 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #96 @106 RefTypeUse <Ivl:15> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #97 @106 RefTypeFixedReg <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #98 @106 RefTypeUse <Ivl:17> BB02 regmask=[r8] minReg=1 last fixed>
<RefPosition #99 @106 RefTypeFixedReg <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #100 @106 RefTypeUse <Ivl:19> BB02 regmask=[r9] minReg=1 last fixed>
<RefPosition #101 @106 RefTypeUse <Ivl:22> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #102 @107 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #103 @107 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #104 @107 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #105 @107 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #106 @107 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #107 @107 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #108 @107 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #109 @107 RefTypeKillGCRefs CALL BB02 regmask=[rax rbx rsi rdi r10-r15] minReg=1>
<RefPosition #110 @107 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #111 @107 RefTypeDef <Ivl:23> CALL BB02 regmask=[rax] minReg=1 fixed>
<RefPosition #112 @109 RefTypeDef <Ivl:24> LCL_VAR_ADDR BB02 regmask=[rcx] minReg=1>
<RefPosition #113 @110 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #114 @110 RefTypeUse <Ivl:24> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #115 @111 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #116 @111 RefTypeDef <Ivl:25> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #117 @116 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #118 @116 RefTypeUse <Ivl:25> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #119 @117 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #120 @117 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #121 @117 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #122 @117 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #123 @117 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #124 @117 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #125 @117 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #126 @118 RefTypeUse <Ivl:23> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #127 @127 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #128 @127 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #129 @127 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #130 @127 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #131 @127 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #132 @127 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #133 @127 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #134 @131 RefTypeDef <Ivl:26> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #135 @132 RefTypeUse <Ivl:26> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #136 @137 RefTypeDef <Ivl:27> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #137 @138 RefTypeUse <Ivl:27> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #138 @144 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #139 @146 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #140 @151 RefTypeDef <Ivl:28> LCL_VAR BB05 regmask=[allIntButFP] minReg=1>
<RefPosition #141 @152 RefTypeUse <Ivl:28> BB05 regmask=[allIntButFP] minReg=1 last>
<RefPosition #142 @153 RefTypeDef <Ivl:29> CAST BB05 regmask=[allIntButFP] minReg=1>
<RefPosition #143 @156 RefTypeUse <Ivl:29> BB05 regmask=[allIntButFP] minReg=1 last regOptional>
<RefPosition #144 @160 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #145 @165 RefTypeDef <Ivl:30> LCL_VAR BB06 regmask=[rcx] minReg=1>
<RefPosition #146 @166 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #147 @166 RefTypeUse <Ivl:30> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #148 @167 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #149 @167 RefTypeDef <Ivl:31> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #150 @172 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #151 @172 RefTypeUse <Ivl:31> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #152 @173 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #153 @173 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #154 @173 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #155 @173 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #156 @173 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #157 @173 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #158 @173 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #159 @174 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #160 @180 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #161 @182 RefTypeBB BB08 regmask=[] minReg=1>
<RefPosition #162 @187 RefTypeDef <Ivl:32> LCL_VAR BB08 regmask=[allIntButFP] minReg=1>
<RefPosition #163 @188 RefTypeUse <Ivl:32> BB08 regmask=[allIntButFP] minReg=1 last>
<RefPosition #164 @190 RefTypeBB BB09 regmask=[] minReg=1>
<RefPosition #165 @193 RefTypeDef <Ivl:33> LCL_VAR BB09 regmask=[rax] minReg=1>
<RefPosition #166 @194 RefTypeFixedReg <Reg:rax> BB09 regmask=[rax] minReg=1>
<RefPosition #167 @194 RefTypeUse <Ivl:33> BB09 regmask=[rax] minReg=1 last fixed>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [???..???), preds={} succs={BB02}
=====
N002. NOP
BB02 [000..037) -> BB03 (always), preds={BB01} succs={BB03}
=====
N006. IL_OFFSET IL offset: 0x0
N008. LCL_VAR_ADDR V08 loc3 NA
Def:<I0>(#2)
N010. PUTARG_REG
Use:<I0>(#4) Fixed:rdx(#3) *
Def:<I1>(#6) rdx
N012. V00 MEM
Def:<I2>(#7)
N014. PUTARG_REG
Use:<I2>(#9) Fixed:rcx(#8) *
Def:<I3>(#11) rcx
N016. CNS_INT(h) 0x420058 ftn
N018. IND
N020. CALL r2r_ind
Use:<I1>(#13) Fixed:rdx(#12) *
Use:<I3>(#15) Fixed:rcx(#14) *
Kill: rax rcx rdx r8 r9 r10 r11
N022. IL_OFFSET IL offset: 0x8
N024. V00 MEM
Def:<I4>(#23)
N026. PUTARG_REG
Use:<I4>(#25) Fixed:rcx(#24) *
Def:<I5>(#27) rcx
N028. CNS_INT(h) 0x420080 ftn
N030. IND
N032. CALL r2r_ind
Use:<I5>(#29) Fixed:rcx(#28) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I6>(#38) rax
N034. V12 MEM
Use:<I6>(#39) *
N036. IL_OFFSET IL offset: 0xe
N038. V12 MEM
Def:<I7>(#40)
N040. V07 MEM
Use:<I7>(#41) *
N042. IL_OFFSET IL offset: 0xf
N044. V03 MEM
Def:<I8>(#42)
N046. V10 MEM
Use:<I8>(#43) *
N048. IL_OFFSET IL offset: 0x12
N050. V10 MEM
Def:<I9>(#44)
N052. V16 MEM
Use:<I9>(#45) *
N054. V16 MEM
Def:<I10>(#46)
N056. V09 MEM
Use:<I10>(#47) *
N058. IL_OFFSET IL offset: 0x17
N060. CNS_INT(h) 0x4200A0 ftn
N062. IND
N064. CALL r2r_ind
Kill: rax rcx rdx r8 r9 r10 r11
N066. IL_OFFSET IL offset: 0x25
N068. V04 MEM
Def:<I11>(#55)
N070. PUTARG_STK [+0x20]
Use:<I11>(#56) *
N072. V07 MEM
Def:<I12>(#57)
N074. PUTARG_REG
Use:<I12>(#59) Fixed:rcx(#58) *
Def:<I13>(#61) rcx
N076. V01 MEM
Def:<I14>(#62)
N078. PUTARG_REG
Use:<I14>(#64) Fixed:rdx(#63) *
Def:<I15>(#66) rdx
N080. V02 MEM
Def:<I16>(#67)
N082. PUTARG_REG
Use:<I16>(#69) Fixed:r8(#68) *
Def:<I17>(#71) r8
N084. V09 MEM
Def:<I18>(#72)
N086. PUTARG_REG
Use:<I18>(#74) Fixed:r9(#73) *
Def:<I19>(#76) r9
N088. PINVOKE_PROLOG
N090. LCL_VAR_ADDR V15 PInvokeFrame NA
Def:<I20>(#77)
N092. PUTARG_REG
Use:<I20>(#79) Fixed:rcx(#78) *
Def:<I21>(#81) rcx
N094. CNS_INT(h) 0x4200E8 ftn
N096. IND
N098. CALL help
Use:<I21>(#83) Fixed:rcx(#82) *
Kill: rax rcx rdx r8 r9 r10 r11
N100. CNS_INT(h) 0x4200F0 ftn
N102. IND
N104. IND
N106. CALL r2r_ind
N108. LCL_VAR_ADDR V15 PInvokeFrame NA
N110. PUTARG_REG
N112. CNS_INT(h) 0x4200F8 ftn
N114. IND
N116. CALL help
N118. V13 MEM
N120. IL_OFFSET IL offset: 0x2a
N122. CNS_INT(h) 0x4200C8 ftn
N124. IND
N126. CALL r2r_ind
N128. IL_OFFSET IL offset: 0x2f
N130. V13 MEM
N132. V06 MEM
N134. IL_OFFSET IL offset: 0x30
N136. V06 MEM
N138. V05 MEM
N140. IL_OFFSET IL offset: 0x32
N142. NOP
N148. IL_OFFSET IL offset: 0x37
N150. V08 MEM
N152. CAST
N154. CNS_INT 0
N156. EQ
N158. JTRUE
N162. IL_OFFSET IL offset: 0x3d
N164. V00 MEM
N166. PUTARG_REG
N168. CNS_INT(h) 0x4200E0 ftn
N170. IND
N172. CALL r2r_ind
N176. IL_OFFSET IL offset: 0x43
N178. RETFILT
N184. IL_OFFSET IL offset: 0x44
N186. V05 MEM
N188. V14 MEM
N192. V14 MEM
N194. RETURN
Linear scan intervals after buildIntervals:
Interval 0: long RefPositions {#2@9 #4@10} physReg:NA Preferences=[rdx]
Interval 1: long RefPositions {#6@11 #13@20} physReg:NA Preferences=[rdx]
Interval 2: ref RefPositions {#7@13 #9@14} physReg:NA Preferences=[rcx]
Interval 3: ref RefPositions {#11@15 #15@20} physReg:NA Preferences=[rcx]
Interval 4: ref RefPositions {#23@25 #25@26} physReg:NA Preferences=[rcx]
Interval 5: ref RefPositions {#27@27 #29@32} physReg:NA Preferences=[rcx]
Interval 6: long RefPositions {#38@33 #39@34} physReg:NA Preferences=[rax]
Interval 7: long RefPositions {#40@39 #41@40} physReg:NA Preferences=[allIntButFP]
Interval 8: byref RefPositions {#42@45 #43@46} physReg:NA Preferences=[allIntButFP]
Interval 9: byref RefPositions {#44@51 #45@52} physReg:NA Preferences=[allIntButFP]
Interval 10: long RefPositions {#46@55 #47@56} physReg:NA Preferences=[allIntButFP]
Interval 11: long RefPositions {#55@69 #56@70} physReg:NA Preferences=[allIntButFP]
Interval 12: long RefPositions {#57@73 #59@74} physReg:NA Preferences=[rcx]
Interval 13: long RefPositions {#61@75 #94@106} physReg:NA Preferences=[rcx]
Interval 14: long RefPositions {#62@77 #64@78} physReg:NA Preferences=[rdx]
Interval 15: long RefPositions {#66@79 #96@106} physReg:NA Preferences=[rdx]
Interval 16: int RefPositions {#67@81 #69@82} physReg:NA Preferences=[r8]
Interval 17: int RefPositions {#71@83 #98@106} physReg:NA Preferences=[r8]
Interval 18: long RefPositions {#72@85 #74@86} physReg:NA Preferences=[r9]
Interval 19: long RefPositions {#76@87 #100@106} physReg:NA Preferences=[r9]
Interval 20: long RefPositions {#77@91 #79@92} physReg:NA Preferences=[rcx]
Interval 21: long RefPositions {#81@93 #83@98} physReg:NA Preferences=[rcx]
Interval 22: long RefPositions {#92@103 #101@106} physReg:NA Preferences=[allIntButFP]
Interval 23: int RefPositions {#111@107 #126@118} physReg:NA Preferences=[rax]
Interval 24: long RefPositions {#112@109 #114@110} physReg:NA Preferences=[rcx]
Interval 25: long RefPositions {#116@111 #118@116} physReg:NA Preferences=[rcx]
Interval 26: int RefPositions {#134@131 #135@132} physReg:NA Preferences=[allIntButFP]
Interval 27: int RefPositions {#136@137 #137@138} physReg:NA Preferences=[allIntButFP]
Interval 28: int RefPositions {#140@151 #141@152} physReg:NA Preferences=[allIntButFP]
Interval 29: int RefPositions {#142@153 #143@156} physReg:NA Preferences=[allIntButFP]
Interval 30: ref RefPositions {#145@165 #147@166} physReg:NA Preferences=[rcx]
Interval 31: ref RefPositions {#149@167 #151@172} physReg:NA Preferences=[rcx]
Interval 32: int RefPositions {#162@187 #163@188} physReg:NA Preferences=[allIntButFP]
Interval 33: int RefPositions {#165@193 #167@194} physReg:NA Preferences=[rax]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: long RefPositions {#2@9 #4@10} physReg:NA Preferences=[rdx]
Interval 1: long RefPositions {#6@11 #13@20} physReg:NA Preferences=[rdx]
Interval 2: ref RefPositions {#7@13 #9@14} physReg:NA Preferences=[rcx]
Interval 3: ref RefPositions {#11@15 #15@20} physReg:NA Preferences=[rcx]
Interval 4: ref RefPositions {#23@25 #25@26} physReg:NA Preferences=[rcx]
Interval 5: ref RefPositions {#27@27 #29@32} physReg:NA Preferences=[rcx]
Interval 6: long RefPositions {#38@33 #39@34} physReg:NA Preferences=[rax]
Interval 7: long RefPositions {#40@39 #41@40} physReg:NA Preferences=[allIntButFP]
Interval 8: byref RefPositions {#42@45 #43@46} physReg:NA Preferences=[allIntButFP]
Interval 9: byref RefPositions {#44@51 #45@52} physReg:NA Preferences=[allIntButFP]
Interval 10: long RefPositions {#46@55 #47@56} physReg:NA Preferences=[allIntButFP]
Interval 11: long RefPositions {#55@69 #56@70} physReg:NA Preferences=[allIntButFP]
Interval 12: long RefPositions {#57@73 #59@74} physReg:NA Preferences=[rcx]
Interval 13: long RefPositions {#61@75 #94@106} physReg:NA Preferences=[rcx]
Interval 14: long RefPositions {#62@77 #64@78} physReg:NA Preferences=[rdx]
Interval 15: long RefPositions {#66@79 #96@106} physReg:NA Preferences=[rdx]
Interval 16: int RefPositions {#67@81 #69@82} physReg:NA Preferences=[r8]
Interval 17: int RefPositions {#71@83 #98@106} physReg:NA Preferences=[r8]
Interval 18: long RefPositions {#72@85 #74@86} physReg:NA Preferences=[r9]
Interval 19: long RefPositions {#76@87 #100@106} physReg:NA Preferences=[r9]
Interval 20: long RefPositions {#77@91 #79@92} physReg:NA Preferences=[rcx]
Interval 21: long RefPositions {#81@93 #83@98} physReg:NA Preferences=[rcx]
Interval 22: long RefPositions {#92@103 #101@106} physReg:NA Preferences=[allIntButFP]
Interval 23: int RefPositions {#111@107 #126@118} physReg:NA Preferences=[rax]
Interval 24: long RefPositions {#112@109 #114@110} physReg:NA Preferences=[rcx]
Interval 25: long RefPositions {#116@111 #118@116} physReg:NA Preferences=[rcx]
Interval 26: int RefPositions {#134@131 #135@132} physReg:NA Preferences=[allIntButFP]
Interval 27: int RefPositions {#136@137 #137@138} physReg:NA Preferences=[allIntButFP]
Interval 28: int RefPositions {#140@151 #141@152} physReg:NA Preferences=[allIntButFP]
Interval 29: int RefPositions {#142@153 #143@156} physReg:NA Preferences=[allIntButFP]
Interval 30: ref RefPositions {#145@165 #147@166} physReg:NA Preferences=[rcx]
Interval 31: ref RefPositions {#149@167 #151@172} physReg:NA Preferences=[rcx]
Interval 32: int RefPositions {#162@187 #163@188} physReg:NA Preferences=[allIntButFP]
Interval 33: int RefPositions {#165@193 #167@194} physReg:NA Preferences=[rax]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #2 @9 RefTypeDef <Ivl:0> LCL_VAR_ADDR BB02 regmask=[rdx] minReg=1>
<RefPosition #3 @10 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #4 @10 RefTypeUse <Ivl:0> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #5 @11 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #6 @11 RefTypeDef <Ivl:1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed>
<RefPosition #7 @13 RefTypeDef <Ivl:2> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #8 @14 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #9 @14 RefTypeUse <Ivl:2> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #10 @15 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #11 @15 RefTypeDef <Ivl:3> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #12 @20 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #13 @20 RefTypeUse <Ivl:1> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #14 @20 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #15 @20 RefTypeUse <Ivl:3> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #16 @21 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #17 @21 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #18 @21 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #19 @21 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #20 @21 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #21 @21 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #22 @21 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #23 @25 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #24 @26 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #25 @26 RefTypeUse <Ivl:4> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #26 @27 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #27 @27 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #28 @32 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #29 @32 RefTypeUse <Ivl:5> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #30 @33 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #31 @33 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #32 @33 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #33 @33 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #34 @33 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #35 @33 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #36 @33 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #37 @33 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #38 @33 RefTypeDef <Ivl:6> CALL BB02 regmask=[rax] minReg=1 fixed>
<RefPosition #39 @34 RefTypeUse <Ivl:6> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #40 @39 RefTypeDef <Ivl:7> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #41 @40 RefTypeUse <Ivl:7> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #42 @45 RefTypeDef <Ivl:8> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #43 @46 RefTypeUse <Ivl:8> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #44 @51 RefTypeDef <Ivl:9> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #45 @52 RefTypeUse <Ivl:9> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #46 @55 RefTypeDef <Ivl:10> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #47 @56 RefTypeUse <Ivl:10> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #48 @65 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #49 @65 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #50 @65 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #51 @65 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #52 @65 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #53 @65 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #54 @65 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #55 @69 RefTypeDef <Ivl:11> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #56 @70 RefTypeUse <Ivl:11> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #57 @73 RefTypeDef <Ivl:12> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #58 @74 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #59 @74 RefTypeUse <Ivl:12> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #60 @75 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #61 @75 RefTypeDef <Ivl:13> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #62 @77 RefTypeDef <Ivl:14> LCL_VAR BB02 regmask=[rdx] minReg=1>
<RefPosition #63 @78 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #64 @78 RefTypeUse <Ivl:14> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #65 @79 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #66 @79 RefTypeDef <Ivl:15> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed>
<RefPosition #67 @81 RefTypeDef <Ivl:16> LCL_VAR BB02 regmask=[r8] minReg=1>
<RefPosition #68 @82 RefTypeFixedReg <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #69 @82 RefTypeUse <Ivl:16> BB02 regmask=[r8] minReg=1 last fixed>
<RefPosition #70 @83 RefTypeFixedReg <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #71 @83 RefTypeDef <Ivl:17> PUTARG_REG BB02 regmask=[r8] minReg=1 fixed>
<RefPosition #72 @85 RefTypeDef <Ivl:18> LCL_VAR BB02 regmask=[r9] minReg=1>
<RefPosition #73 @86 RefTypeFixedReg <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #74 @86 RefTypeUse <Ivl:18> BB02 regmask=[r9] minReg=1 last fixed>
<RefPosition #75 @87 RefTypeFixedReg <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #76 @87 RefTypeDef <Ivl:19> PUTARG_REG BB02 regmask=[r9] minReg=1 fixed>
<RefPosition #77 @91 RefTypeDef <Ivl:20> LCL_VAR_ADDR BB02 regmask=[rcx] minReg=1>
<RefPosition #78 @92 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #79 @92 RefTypeUse <Ivl:20> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #80 @93 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #81 @93 RefTypeDef <Ivl:21> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #82 @98 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #83 @98 RefTypeUse <Ivl:21> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #84 @99 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #85 @99 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #86 @99 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #87 @99 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #88 @99 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #89 @99 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #90 @99 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #91 @99 RefTypeKillGCRefs CALL BB02 regmask=[rax rbx rsi rdi r10-r15] minReg=1>
<RefPosition #92 @103 RefTypeDef <Ivl:22> IND BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #93 @106 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #94 @106 RefTypeUse <Ivl:13> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #95 @106 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #96 @106 RefTypeUse <Ivl:15> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #97 @106 RefTypeFixedReg <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #98 @106 RefTypeUse <Ivl:17> BB02 regmask=[r8] minReg=1 last fixed>
<RefPosition #99 @106 RefTypeFixedReg <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #100 @106 RefTypeUse <Ivl:19> BB02 regmask=[r9] minReg=1 last fixed>
<RefPosition #101 @106 RefTypeUse <Ivl:22> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #102 @107 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #103 @107 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #104 @107 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #105 @107 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #106 @107 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #107 @107 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #108 @107 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #109 @107 RefTypeKillGCRefs CALL BB02 regmask=[rax rbx rsi rdi r10-r15] minReg=1>
<RefPosition #110 @107 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #111 @107 RefTypeDef <Ivl:23> CALL BB02 regmask=[rax] minReg=1 fixed>
<RefPosition #112 @109 RefTypeDef <Ivl:24> LCL_VAR_ADDR BB02 regmask=[rcx] minReg=1>
<RefPosition #113 @110 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #114 @110 RefTypeUse <Ivl:24> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #115 @111 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #116 @111 RefTypeDef <Ivl:25> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #117 @116 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #118 @116 RefTypeUse <Ivl:25> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #119 @117 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #120 @117 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #121 @117 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #122 @117 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #123 @117 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #124 @117 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #125 @117 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #126 @118 RefTypeUse <Ivl:23> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #127 @127 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #128 @127 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #129 @127 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #130 @127 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #131 @127 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #132 @127 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #133 @127 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #134 @131 RefTypeDef <Ivl:26> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #135 @132 RefTypeUse <Ivl:26> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #136 @137 RefTypeDef <Ivl:27> LCL_VAR BB02 regmask=[allIntButFP] minReg=1>
<RefPosition #137 @138 RefTypeUse <Ivl:27> BB02 regmask=[allIntButFP] minReg=1 last>
<RefPosition #138 @144 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #139 @146 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #140 @151 RefTypeDef <Ivl:28> LCL_VAR BB05 regmask=[allIntButFP] minReg=1>
<RefPosition #141 @152 RefTypeUse <Ivl:28> BB05 regmask=[allIntButFP] minReg=1 last>
<RefPosition #142 @153 RefTypeDef <Ivl:29> CAST BB05 regmask=[allIntButFP] minReg=1>
<RefPosition #143 @156 RefTypeUse <Ivl:29> BB05 regmask=[allIntButFP] minReg=1 last regOptional>
<RefPosition #144 @160 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #145 @165 RefTypeDef <Ivl:30> LCL_VAR BB06 regmask=[rcx] minReg=1>
<RefPosition #146 @166 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #147 @166 RefTypeUse <Ivl:30> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #148 @167 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #149 @167 RefTypeDef <Ivl:31> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #150 @172 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #151 @172 RefTypeUse <Ivl:31> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #152 @173 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #153 @173 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #154 @173 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #155 @173 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #156 @173 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #157 @173 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #158 @173 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #159 @174 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #160 @180 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #161 @182 RefTypeBB BB08 regmask=[] minReg=1>
<RefPosition #162 @187 RefTypeDef <Ivl:32> LCL_VAR BB08 regmask=[allIntButFP] minReg=1>
<RefPosition #163 @188 RefTypeUse <Ivl:32> BB08 regmask=[allIntButFP] minReg=1 last>
<RefPosition #164 @190 RefTypeBB BB09 regmask=[] minReg=1>
<RefPosition #165 @193 RefTypeDef <Ivl:33> LCL_VAR BB09 regmask=[rax] minReg=1>
<RefPosition #166 @194 RefTypeFixedReg <Reg:rax> BB09 regmask=[rax] minReg=1>
<RefPosition #167 @194 RefTypeUse <Ivl:33> BB09 regmask=[rax] minReg=1 last fixed>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
Columns are only printed up to the last modifed register, which may increase during allocation,
in which case additional columns will appear.
Registers which are not marked modified have ---- in their column.
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
| | | | | | | | | |
0.#0 BB1 PredBB0 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
4.#1 BB2 PredBB1 | | | | | | | | | |
9.#2 I0 Def Alloc rdx | | |I0 a| | | | | | |
10.#3 rdx Fixd Keep rdx | | |I0 a| | | | | | |
10.#4 I0 Use * Keep rdx | | |I0 a| | | | | | |
11.#5 rdx Fixd Keep rdx | | | | | | | | | |
11.#6 I1 Def Alloc rdx | | |I1 a| | | | | | |
13.#7 I2 Def Alloc rcx | |I2 a|I1 a| | | | | | |
14.#8 rcx Fixd Keep rcx | |I2 a|I1 a| | | | | | |
14.#9 I2 Use * Keep rcx | |I2 a|I1 a| | | | | | |
15.#10 rcx Fixd Keep rcx | | |I1 a| | | | | | |
15.#11 I3 Def Alloc rcx | |I3 a|I1 a| | | | | | |
20.#12 rdx Fixd Keep rdx | |I3 a|I1 a| | | | | | |
20.#13 I1 Use * Keep rdx | |I3 a|I1 a| | | | | | |
20.#14 rcx Fixd Keep rcx | |I3 a|I1 a| | | | | | |
20.#15 I3 Use * Keep rcx | |I3 a|I1 a| | | | | | |
21.#16 rax Kill Keep rax | | | | | | | | | |
21.#17 rcx Kill Keep rcx | | | | | | | | | |
21.#18 rdx Kill Keep rdx | | | | | | | | | |
21.#19 r8 Kill Keep r8 | | | | | | | | | |
21.#20 r9 Kill Keep r9 | | | | | | | | | |
21.#21 r10 Kill Keep r10 | | | | | | | | | |
21.#22 r11 Kill Keep r11 | | | | | | | | | |
25.#23 I4 Def Alloc rcx | |I4 a| | | | | | | |
26.#24 rcx Fixd Keep rcx | |I4 a| | | | | | | |
26.#25 I4 Use * Keep rcx | |I4 a| | | | | | | |
27.#26 rcx Fixd Keep rcx | | | | | | | | | |
27.#27 I5 Def Alloc rcx | |I5 a| | | | | | | |
32.#28 rcx Fixd Keep rcx | |I5 a| | | | | | | |
32.#29 I5 Use * Keep rcx | |I5 a| | | | | | | |
33.#30 rax Kill Keep rax | | | | | | | | | |
33.#31 rcx Kill Keep rcx | | | | | | | | | |
33.#32 rdx Kill Keep rdx | | | | | | | | | |
33.#33 r8 Kill Keep r8 | | | | | | | | | |
33.#34 r9 Kill Keep r9 | | | | | | | | | |
33.#35 r10 Kill Keep r10 | | | | | | | | | |
33.#36 r11 Kill Keep r11 | | | | | | | | | |
33.#37 rax Fixd Keep rax | | | | | | | | | |
33.#38 I6 Def Alloc rax |I6 a| | | | | | | | |
34.#39 I6 Use * Keep rax |I6 a| | | | | | | | |
39.#40 I7 Def Alloc rax |I7 a| | | | | | | | |
40.#41 I7 Use * Keep rax |I7 a| | | | | | | | |
45.#42 I8 Def Alloc rax |I8 a| | | | | | | | |
46.#43 I8 Use * Keep rax |I8 a| | | | | | | | |
51.#44 I9 Def Alloc rax |I9 a| | | | | | | | |
52.#45 I9 Use * Keep rax |I9 a| | | | | | | | |
55.#46 I10 Def Alloc rax |I10a| | | | | | | | |
56.#47 I10 Use * Keep rax |I10a| | | | | | | | |
65.#48 rax Kill Keep rax | | | | | | | | | |
65.#49 rcx Kill Keep rcx | | | | | | | | | |
65.#50 rdx Kill Keep rdx | | | | | | | | | |
65.#51 r8 Kill Keep r8 | | | | | | | | | |
65.#52 r9 Kill Keep r9 | | | | | | | | | |
65.#53 r10 Kill Keep r10 | | | | | | | | | |
65.#54 r11 Kill Keep r11 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
69.#55 I11 Def Alloc rcx | |I11a| | | | | | | |
70.#56 I11 Use * Keep rcx | |I11a| | | | | | | |
73.#57 I12 Def Alloc rcx | |I12a| | | | | | | |
74.#58 rcx Fixd Keep rcx | |I12a| | | | | | | |
74.#59 I12 Use * Keep rcx | |I12a| | | | | | | |
75.#60 rcx Fixd Keep rcx | | | | | | | | | |
75.#61 I13 Def Alloc rcx | |I13a| | | | | | | |
77.#62 I14 Def Alloc rdx | |I13a|I14a| | | | | | |
78.#63 rdx Fixd Keep rdx | |I13a|I14a| | | | | | |
78.#64 I14 Use * Keep rdx | |I13a|I14a| | | | | | |
79.#65 rdx Fixd Keep rdx | |I13a| | | | | | | |
79.#66 I15 Def Alloc rdx | |I13a|I15a| | | | | | |
81.#67 I16 Def Alloc r8 | |I13a|I15a| | | | |I16a| |
82.#68 r8 Fixd Keep r8 | |I13a|I15a| | | | |I16a| |
82.#69 I16 Use * Keep r8 | |I13a|I15a| | | | |I16a| |
83.#70 r8 Fixd Keep r8 | |I13a|I15a| | | | | | |
83.#71 I17 Def Alloc r8 | |I13a|I15a| | | | |I17a| |
85.#72 I18 Def Alloc r9 | |I13a|I15a| | | | |I17a|I18a|
86.#73 r9 Fixd Keep r9 | |I13a|I15a| | | | |I17a|I18a|
86.#74 I18 Use * Keep r9 | |I13a|I15a| | | | |I17a|I18a|
87.#75 r9 Fixd Keep r9 | |I13a|I15a| | | | |I17a| |
87.#76 I19 Def Alloc r9 | |I13a|I15a| | | | |I17a|I19a|
91.#77 I20 Def Spill rcx | | |I15a| | | | |I17a|I19a|
Steal rcx | |I20a|I15a| | | | |I17a|I19a|
92.#78 rcx Fixd Keep rcx | |I20a|I15a| | | | |I17a|I19a|
92.#79 I20 Use * Keep rcx | |I20a|I15a| | | | |I17a|I19a|
93.#80 rcx Fixd Keep rcx | | |I15a| | | | |I17a|I19a|
93.#81 I21 Def Alloc rcx | |I21a|I15a| | | | |I17a|I19a|
98.#82 rcx Fixd Keep rcx | |I21a|I15a| | | | |I17a|I19a|
98.#83 I21 Use * Keep rcx | |I21a|I15a| | | | |I17a|I19a|
99.#84 rax Kill Keep rax | | |I15a| | | | |I17a|I19a|
99.#85 rcx Kill Keep rcx | | |I15a| | | | |I17a|I19a|
99.#86 rdx Kill Spill rdx | | | | | | | |I17a|I19a|
Keep rdx | | | | | | | |I17a|I19a|
99.#87 r8 Kill Spill r8 | | | | | | | | |I19a|
Keep r8 | | | | | | | | |I19a|
99.#88 r9 Kill Spill r9 | | | | | | | | | |
Keep r9 | | | | | | | | | |
99.#89 r10 Kill Keep r10 | | | | | | | | | |
99.#90 r11 Kill Keep r11 | | | | | | | | | |
99.#91 KlGC None | | | | | | | | | |
103.#92 I22 Def Alloc rax |I22a| | | | | | | | |
106.#93 rcx Fixd Keep rcx |I22a| | | | | | | | |
106.#94 I13 Use * ReLod NA |I22a| | | | | | | | |
Alloc rcx |I22a|I13a| | | | | | | |
106.#95 rdx Fixd Keep rdx |I22a|I13a| | | | | | | |
106.#96 I15 Use * ReLod NA |I22a|I13a| | | | | | | |
Alloc rdx |I22a|I13a|I15a| | | | | | |
106.#97 r8 Fixd Keep r8 |I22a|I13a|I15a| | | | | | |
106.#98 I17 Use * ReLod NA |I22a|I13a|I15a| | | | | | |
Alloc r8 |I22a|I13a|I15a| | | | |I17a| |
106.#99 r9 Fixd Keep r9 |I22a|I13a|I15a| | | | |I17a| |
106.#100 I19 Use * ReLod NA |I22a|I13a|I15a| | | | |I17a| |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
Alloc r9 |I22a|I13a|I15a| | | | |I17a|I19a|
106.#101 I22 Use * Keep rax |I22a|I13a|I15a| | | | |I17a|I19a|
107.#102 rax Kill Keep rax | | | | | | | | | |
107.#103 rcx Kill Keep rcx | | | | | | | | | |
107.#104 rdx Kill Keep rdx | | | | | | | | | |
107.#105 r8 Kill Keep r8 | | | | | | | | | |
107.#106 r9 Kill Keep r9 | | | | | | | | | |
107.#107 r10 Kill Keep r10 | | | | | | | | | |
107.#108 r11 Kill Keep r11 | | | | | | | | | |
107.#109 KlGC None | | | | | | | | | |
107.#110 rax Fixd Keep rax | | | | | | | | | |
107.#111 I23 Def Alloc rsi | | | | | |I23a| | | |
109.#112 I24 Def Alloc rcx | |I24a| | | |I23a| | | |
110.#113 rcx Fixd Keep rcx | |I24a| | | |I23a| | | |
110.#114 I24 Use * Keep rcx | |I24a| | | |I23a| | | |
111.#115 rcx Fixd Keep rcx | | | | | |I23a| | | |
111.#116 I25 Def Alloc rcx | |I25a| | | |I23a| | | |
116.#117 rcx Fixd Keep rcx | |I25a| | | |I23a| | | |
116.#118 I25 Use * Keep rcx | |I25a| | | |I23a| | | |
117.#119 rax Kill Keep rax | | | | | |I23a| | | |
117.#120 rcx Kill Keep rcx | | | | | |I23a| | | |
117.#121 rdx Kill Keep rdx | | | | | |I23a| | | |
117.#122 r8 Kill Keep r8 | | | | | |I23a| | | |
117.#123 r9 Kill Keep r9 | | | | | |I23a| | | |
117.#124 r10 Kill Keep r10 | | | | | |I23a| | | |
117.#125 r11 Kill Keep r11 | | | | | |I23a| | | |
118.#126 I23 Use * Keep rsi | | | | | |I23a| | | |
127.#127 rax Kill Keep rax | | | | | | | | | |
127.#128 rcx Kill Keep rcx | | | | | | | | | |
127.#129 rdx Kill Keep rdx | | | | | | | | | |
127.#130 r8 Kill Keep r8 | | | | | | | | | |
127.#131 r9 Kill Keep r9 | | | | | | | | | |
127.#132 r10 Kill Keep r10 | | | | | | | | | |
127.#133 r11 Kill Keep r11 | | | | | | | | | |
131.#134 I26 Def Alloc rcx | |I26a| | | | | | | |
132.#135 I26 Use * Keep rcx | |I26a| | | | | | | |
137.#136 I27 Def Alloc rcx | |I27a| | | | | | | |
138.#137 I27 Use * Keep rcx | |I27a| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
144.#138 BB3 PredBB2 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
146.#139 BB5 PredBB0 | | | | | | | | | |
151.#140 I28 Def Alloc rcx | |I28a| | | | | | | |
152.#141 I28 Use * Keep rcx | |I28a| | | | | | | |
153.#142 I29 Def Alloc rcx | |I29a| | | | | | | |
156.#143 I29 Use * Keep rcx | |I29a| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
160.#144 BB6 PredBB5 | | | | | | | | | |
165.#145 I30 Def Alloc rcx | |I30a| | | | | | | |
166.#146 rcx Fixd Keep rcx | |I30a| | | | | | | |
166.#147 I30 Use * Keep rcx | |I30a| | | | | | | |
167.#148 rcx Fixd Keep rcx | | | | | | | | | |
167.#149 I31 Def Alloc rcx | |I31a| | | | | | | |
172.#150 rcx Fixd Keep rcx | |I31a| | | | | | | |
172.#151 I31 Use * Keep rcx | |I31a| | | | | | | |
173.#152 rax Kill Keep rax | | | | | | | | | |
173.#153 rcx Kill Keep rcx | | | | | | | | | |
173.#154 rdx Kill Keep rdx | | | | | | | | | |
173.#155 r8 Kill Keep r8 | | | | | | | | | |
173.#156 r9 Kill Keep r9 | | | | | | | | | |
173.#157 r10 Kill Keep r10 | | | | | | | | | |
173.#158 r11 Kill Keep r11 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
174.#159 BB7 PredBB5 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
180.#160 BB4 PredBB0 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
182.#161 BB8 PredBB0 | | | | | | | | | |
187.#162 I32 Def Alloc rax |I32a| | | | | | | | |
188.#163 I32 Use * Keep rax |I32a| | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
190.#164 BB9 PredBB8 | | | | | | | | | |
193.#165 I33 Def Alloc rax |I33a| | | | | | | | |
194.#166 rax Fixd Keep rax |I33a| | | | | | | | |
194.#167 I33 Use * Keep rax | | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #2 @9 RefTypeDef <Ivl:0> LCL_VAR_ADDR BB02 regmask=[rdx] minReg=1>
<RefPosition #3 @10 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #4 @10 RefTypeUse <Ivl:0> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #5 @11 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #6 @11 RefTypeDef <Ivl:1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed>
<RefPosition #7 @13 RefTypeDef <Ivl:2> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #8 @14 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #9 @14 RefTypeUse <Ivl:2> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #10 @15 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #11 @15 RefTypeDef <Ivl:3> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #12 @20 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #13 @20 RefTypeUse <Ivl:1> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #14 @20 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #15 @20 RefTypeUse <Ivl:3> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #16 @21 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #17 @21 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #18 @21 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #19 @21 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #20 @21 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #21 @21 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #22 @21 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #23 @25 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #24 @26 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #25 @26 RefTypeUse <Ivl:4> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #26 @27 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #27 @27 RefTypeDef <Ivl:5> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #28 @32 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #29 @32 RefTypeUse <Ivl:5> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #30 @33 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #31 @33 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #32 @33 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #33 @33 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #34 @33 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #35 @33 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #36 @33 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #37 @33 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #38 @33 RefTypeDef <Ivl:6> CALL BB02 regmask=[rax] minReg=1 fixed>
<RefPosition #39 @34 RefTypeUse <Ivl:6> BB02 regmask=[rax] minReg=1 last>
<RefPosition #40 @39 RefTypeDef <Ivl:7> LCL_VAR BB02 regmask=[rax] minReg=1>
<RefPosition #41 @40 RefTypeUse <Ivl:7> BB02 regmask=[rax] minReg=1 last>
<RefPosition #42 @45 RefTypeDef <Ivl:8> LCL_VAR BB02 regmask=[rax] minReg=1>
<RefPosition #43 @46 RefTypeUse <Ivl:8> BB02 regmask=[rax] minReg=1 last>
<RefPosition #44 @51 RefTypeDef <Ivl:9> LCL_VAR BB02 regmask=[rax] minReg=1>
<RefPosition #45 @52 RefTypeUse <Ivl:9> BB02 regmask=[rax] minReg=1 last>
<RefPosition #46 @55 RefTypeDef <Ivl:10> LCL_VAR BB02 regmask=[rax] minReg=1>
<RefPosition #47 @56 RefTypeUse <Ivl:10> BB02 regmask=[rax] minReg=1 last>
<RefPosition #48 @65 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #49 @65 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #50 @65 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #51 @65 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #52 @65 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #53 @65 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #54 @65 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #55 @69 RefTypeDef <Ivl:11> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #56 @70 RefTypeUse <Ivl:11> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #57 @73 RefTypeDef <Ivl:12> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #58 @74 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #59 @74 RefTypeUse <Ivl:12> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #60 @75 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #61 @75 RefTypeDef <Ivl:13> PUTARG_REG BB02 regmask=[rcx] minReg=1 spillAfter fixed>
<RefPosition #62 @77 RefTypeDef <Ivl:14> LCL_VAR BB02 regmask=[rdx] minReg=1>
<RefPosition #63 @78 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #64 @78 RefTypeUse <Ivl:14> BB02 regmask=[rdx] minReg=1 last fixed>
<RefPosition #65 @79 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #66 @79 RefTypeDef <Ivl:15> PUTARG_REG BB02 regmask=[rdx] minReg=1 spillAfter fixed>
<RefPosition #67 @81 RefTypeDef <Ivl:16> LCL_VAR BB02 regmask=[r8] minReg=1>
<RefPosition #68 @82 RefTypeFixedReg <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #69 @82 RefTypeUse <Ivl:16> BB02 regmask=[r8] minReg=1 last fixed>
<RefPosition #70 @83 RefTypeFixedReg <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #71 @83 RefTypeDef <Ivl:17> PUTARG_REG BB02 regmask=[r8] minReg=1 spillAfter fixed>
<RefPosition #72 @85 RefTypeDef <Ivl:18> LCL_VAR BB02 regmask=[r9] minReg=1>
<RefPosition #73 @86 RefTypeFixedReg <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #74 @86 RefTypeUse <Ivl:18> BB02 regmask=[r9] minReg=1 last fixed>
<RefPosition #75 @87 RefTypeFixedReg <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #76 @87 RefTypeDef <Ivl:19> PUTARG_REG BB02 regmask=[r9] minReg=1 spillAfter fixed>
<RefPosition #77 @91 RefTypeDef <Ivl:20> LCL_VAR_ADDR BB02 regmask=[rcx] minReg=1>
<RefPosition #78 @92 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #79 @92 RefTypeUse <Ivl:20> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #80 @93 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #81 @93 RefTypeDef <Ivl:21> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #82 @98 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #83 @98 RefTypeUse <Ivl:21> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #84 @99 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #85 @99 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #86 @99 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #87 @99 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #88 @99 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #89 @99 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #90 @99 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #91 @99 RefTypeKillGCRefs CALL BB02 regmask=[rax rbx rsi rdi r10-r15] minReg=1>
<RefPosition #92 @103 RefTypeDef <Ivl:22> IND BB02 regmask=[rax] minReg=1>
<RefPosition #93 @106 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #94 @106 RefTypeUse <Ivl:13> BB02 regmask=[rcx] minReg=1 last reload fixed>
<RefPosition #95 @106 RefTypeFixedReg <Reg:rdx> BB02 regmask=[rdx] minReg=1>
<RefPosition #96 @106 RefTypeUse <Ivl:15> BB02 regmask=[rdx] minReg=1 last reload fixed>
<RefPosition #97 @106 RefTypeFixedReg <Reg:r8 > BB02 regmask=[r8] minReg=1>
<RefPosition #98 @106 RefTypeUse <Ivl:17> BB02 regmask=[r8] minReg=1 last reload fixed>
<RefPosition #99 @106 RefTypeFixedReg <Reg:r9 > BB02 regmask=[r9] minReg=1>
<RefPosition #100 @106 RefTypeUse <Ivl:19> BB02 regmask=[r9] minReg=1 last reload fixed>
<RefPosition #101 @106 RefTypeUse <Ivl:22> BB02 regmask=[rax] minReg=1 last>
<RefPosition #102 @107 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #103 @107 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #104 @107 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #105 @107 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #106 @107 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #107 @107 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #108 @107 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #109 @107 RefTypeKillGCRefs CALL BB02 regmask=[rax rbx rsi rdi r10-r15] minReg=1>
<RefPosition #110 @107 RefTypeFixedReg <Reg:rax> BB02 regmask=[rax] minReg=1>
<RefPosition #111 @107 RefTypeDef <Ivl:23> CALL BB02 regmask=[rsi] minReg=1 fixed>
<RefPosition #112 @109 RefTypeDef <Ivl:24> LCL_VAR_ADDR BB02 regmask=[rcx] minReg=1>
<RefPosition #113 @110 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #114 @110 RefTypeUse <Ivl:24> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #115 @111 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #116 @111 RefTypeDef <Ivl:25> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed>
<RefPosition #117 @116 RefTypeFixedReg <Reg:rcx> BB02 regmask=[rcx] minReg=1>
<RefPosition #118 @116 RefTypeUse <Ivl:25> BB02 regmask=[rcx] minReg=1 last fixed>
<RefPosition #119 @117 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #120 @117 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #121 @117 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #122 @117 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #123 @117 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #124 @117 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #125 @117 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #126 @118 RefTypeUse <Ivl:23> BB02 regmask=[rsi] minReg=1 last>
<RefPosition #127 @127 RefTypeKill <Reg:rax> BB02 regmask=[rax] minReg=1 last>
<RefPosition #128 @127 RefTypeKill <Reg:rcx> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #129 @127 RefTypeKill <Reg:rdx> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #130 @127 RefTypeKill <Reg:r8 > BB02 regmask=[r8] minReg=1 last>
<RefPosition #131 @127 RefTypeKill <Reg:r9 > BB02 regmask=[r9] minReg=1 last>
<RefPosition #132 @127 RefTypeKill <Reg:r10> BB02 regmask=[r10] minReg=1 last>
<RefPosition #133 @127 RefTypeKill <Reg:r11> BB02 regmask=[r11] minReg=1 last>
<RefPosition #134 @131 RefTypeDef <Ivl:26> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #135 @132 RefTypeUse <Ivl:26> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #136 @137 RefTypeDef <Ivl:27> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #137 @138 RefTypeUse <Ivl:27> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #138 @144 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #139 @146 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #140 @151 RefTypeDef <Ivl:28> LCL_VAR BB05 regmask=[rcx] minReg=1>
<RefPosition #141 @152 RefTypeUse <Ivl:28> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #142 @153 RefTypeDef <Ivl:29> CAST BB05 regmask=[rcx] minReg=1>
<RefPosition #143 @156 RefTypeUse <Ivl:29> BB05 regmask=[rcx] minReg=1 last regOptional>
<RefPosition #144 @160 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #145 @165 RefTypeDef <Ivl:30> LCL_VAR BB06 regmask=[rcx] minReg=1>
<RefPosition #146 @166 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #147 @166 RefTypeUse <Ivl:30> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #148 @167 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #149 @167 RefTypeDef <Ivl:31> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed>
<RefPosition #150 @172 RefTypeFixedReg <Reg:rcx> BB06 regmask=[rcx] minReg=1>
<RefPosition #151 @172 RefTypeUse <Ivl:31> BB06 regmask=[rcx] minReg=1 last fixed>
<RefPosition #152 @173 RefTypeKill <Reg:rax> BB06 regmask=[rax] minReg=1 last>
<RefPosition #153 @173 RefTypeKill <Reg:rcx> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #154 @173 RefTypeKill <Reg:rdx> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #155 @173 RefTypeKill <Reg:r8 > BB06 regmask=[r8] minReg=1 last>
<RefPosition #156 @173 RefTypeKill <Reg:r9 > BB06 regmask=[r9] minReg=1 last>
<RefPosition #157 @173 RefTypeKill <Reg:r10> BB06 regmask=[r10] minReg=1 last>
<RefPosition #158 @173 RefTypeKill <Reg:r11> BB06 regmask=[r11] minReg=1 last>
<RefPosition #159 @174 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #160 @180 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #161 @182 RefTypeBB BB08 regmask=[] minReg=1>
<RefPosition #162 @187 RefTypeDef <Ivl:32> LCL_VAR BB08 regmask=[rax] minReg=1>
<RefPosition #163 @188 RefTypeUse <Ivl:32> BB08 regmask=[rax] minReg=1 last>
<RefPosition #164 @190 RefTypeBB BB09 regmask=[] minReg=1>
<RefPosition #165 @193 RefTypeDef <Ivl:33> LCL_VAR BB09 regmask=[rax] minReg=1>
<RefPosition #166 @194 RefTypeFixedReg <Reg:rax> BB09 regmask=[rax] minReg=1>
<RefPosition #167 @194 RefTypeUse <Ivl:33> BB09 regmask=[rax] minReg=1 last fixed>
Active intervals at end of allocation:
Max spill for long is 1
Max spill for long is 2
Max spill for int is 1
Max spill for long is 3
Max spill for long is 3
Max spill for long is 3
Max spill for int is 1
Max spill for long is 3
Trees after linear scan register allocator (LSRA)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target LIR
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target LIR
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target LIR KEEP
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target LIR
BB09 [0008] 1 BB08 1 [???..???) (return) keep internal target LIR
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 F finally { keep i label target flet LIR
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i gcsafe LIR
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [???..???), preds={} succs={BB02}
N002 ( 0, 0) [000000] ------------ NOP void REG NA
------------ BB02 [000..037) -> BB03 (always), preds={BB01} succs={BB03}
N006 (???,???) [000063] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N008 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V08 loc3 rdx REG rdx
/--* t3 long
N010 (???,???) [000078] ------------ t78 = * PUTARG_REG long REG rdx
N012 ( 3, 2) [000001] ------------ t1 = LCL_VAR ref V00 arg0 rcx REG rcx
/--* t1 ref
N014 (???,???) [000079] ------------ t79 = * PUTARG_REG ref REG rcx
N016 ( 3, 10) [000080] -c---------- t80 = CNS_INT(h) long 0x420058 ftn REG NA
/--* t80 long
N018 ( 5, 12) [000081] -c---------- t81 = * IND long REG NA
/--* t78 long arg1 in rdx
+--* t79 ref this in rcx
+--* t81 long control expr
N020 ( 20, 13) [000004] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef REG NA
N022 (???,???) [000064] ------------ IL_OFFSET void IL offset: 0x8 REG NA
N024 ( 3, 2) [000005] ------------ t5 = LCL_VAR ref V00 arg0 rcx REG rcx
/--* t5 ref
N026 (???,???) [000082] ------------ t82 = * PUTARG_REG ref REG rcx
N028 ( 3, 10) [000083] -c---------- t83 = CNS_INT(h) long 0x420080 ftn REG NA
/--* t83 long
N030 ( 5, 12) [000084] -c---------- t84 = * IND long REG NA
/--* t82 ref this in rcx
+--* t84 long control expr
N032 ( 17, 9) [000006] --CXG------- t6 = * CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle REG rax
/--* t6 long
N034 ( 21, 12) [000008] DA-XG------- * STORE_LCL_VAR long V12 tmp1 NA REG NA
N036 (???,???) [000065] ------------ IL_OFFSET void IL offset: 0xe REG NA
N038 ( 3, 2) [000009] ------------ t9 = LCL_VAR long V12 tmp1 rax REG rax
/--* t9 long
N040 ( 7, 5) [000011] DA---------- * STORE_LCL_VAR long V07 loc2 NA REG NA
N042 (???,???) [000066] ------------ IL_OFFSET void IL offset: 0xf REG NA
N044 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V03 arg3 rax REG rax
/--* t12 byref
N046 ( 7, 5) [000014] DA---------- * STORE_LCL_VAR byref V10 loc5 NA REG NA
N048 (???,???) [000067] ------------ IL_OFFSET void IL offset: 0x12 REG NA
N050 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V10 loc5 rax REG rax
/--* t15 byref
N052 ( 7, 5) [000051] DA---------- * STORE_LCL_VAR long V16 tmp5 NA REG NA
N054 ( 3, 2) [000052] ------------ t52 = LCL_VAR long V16 tmp5 rax REG rax
/--* t52 long
N056 ( 14, 10) [000018] DA---------- * STORE_LCL_VAR long V09 loc4 NA REG NA
N058 (???,???) [000068] ------------ IL_OFFSET void IL offset: 0x17 REG NA
N060 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x4200A0 ftn REG NA
/--* t85 long
N062 ( 5, 12) [000086] -c---------- t86 = * IND long REG NA
/--* t86 long control expr
N064 ( 14, 5) [000024] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError REG NA
N066 (???,???) [000069] ------------ IL_OFFSET void IL offset: 0x25 REG NA
N068 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V04 arg4 rcx REG rcx
/--* t23 long
N070 (???,???) [000087] ------------ * PUTARG_STK [+0x20] void REG NA
N072 ( 3, 2) [000019] ------------ t19 = LCL_VAR long V07 loc2 rcx REG rcx
/--* t19 long
N074 (???,???) [000088] -----------Z t88 = * PUTARG_REG long REG rcx
N076 ( 3, 2) [000020] ------------ t20 = LCL_VAR long V01 arg1 rdx REG rdx
/--* t20 long
N078 (???,???) [000089] -----------Z t89 = * PUTARG_REG long REG rdx
N080 ( 3, 2) [000021] ------------ t21 = LCL_VAR int V02 arg2 r8 REG r8
/--* t21 int
N082 (???,???) [000090] -----------Z t90 = * PUTARG_REG int REG r8
N084 ( 3, 2) [000022] ------------ t22 = LCL_VAR long V09 loc4 r9 REG r9
/--* t22 long
N086 (???,???) [000091] -----------Z t91 = * PUTARG_REG long REG r9
N088 (???,???) [000092] ------------ PINVOKE_PROLOG void REG NA
N090 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR long V15 PInvokeFrame rcx REG rcx
/--* t93 long
N092 (???,???) [000096] ------------ t96 = * PUTARG_REG long REG rcx
N094 ( 3, 10) [000097] -c---------- t97 = CNS_INT(h) long 0x4200E8 ftn REG NA
/--* t97 long
N096 ( 5, 12) [000098] -c---------- t98 = * IND long REG NA
/--* t96 long arg0 in rcx
+--* t98 long control expr
N098 ( 17, 9) [000094] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN REG NA
N100 ( 3, 10) [000099] -c---------- t99 = CNS_INT(h) long 0x4200F0 ftn REG NA
/--* t99 long
N102 ( 5, 12) [000100] ------------ t100 = * IND long REG rax
/--* t100 long
N104 ( 8, 14) [000101] -c---------- t101 = * IND long REG NA
/--* t88 long arg0 in rcx
+--* t89 long arg1 in rdx
+--* t90 int arg2 in r8
+--* t91 long arg3 in r9
+--* t101 long control expr
N106 ( 32, 19) [000025] --CXG------- t25 = * CALL r2r_ind int Kernel32.ReadFile REG rsi
N108 ( 3, 3) [000102] ------------ t102 = LCL_VAR_ADDR long V15 PInvokeFrame rcx REG rcx
/--* t102 long
N110 (???,???) [000105] ------------ t105 = * PUTARG_REG long REG rcx
N112 ( 3, 10) [000106] -c---------- t106 = CNS_INT(h) long 0x4200F8 ftn REG NA
/--* t106 long
N114 ( 5, 12) [000107] -c---------- t107 = * IND long REG NA
/--* t105 long arg0 in rcx
+--* t107 long control expr
N116 ( 17, 9) [000103] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END REG NA
/--* t25 int
N118 ( 36, 22) [000027] DA-XG------- * STORE_LCL_VAR int V13 tmp2 NA REG NA
N120 (???,???) [000070] ------------ IL_OFFSET void IL offset: 0x2a REG NA
N122 ( 3, 10) [000108] -c---------- t108 = CNS_INT(h) long 0x4200C8 ftn REG NA
/--* t108 long
N124 ( 5, 12) [000109] -c---------- t109 = * IND long REG NA
/--* t109 long control expr
N126 ( 14, 5) [000029] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError REG NA
N128 (???,???) [000071] ------------ IL_OFFSET void IL offset: 0x2f REG NA
N130 ( 3, 2) [000028] ------------ t28 = LCL_VAR int V13 tmp2 rcx REG rcx
/--* t28 int
N132 ( 7, 5) [000031] DA---------- * STORE_LCL_VAR int V06 loc1 NA REG NA
N134 (???,???) [000072] ------------ IL_OFFSET void IL offset: 0x30 REG NA
N136 ( 3, 2) [000032] ------------ t32 = LCL_VAR int V06 loc1 rcx REG rcx
/--* t32 int
N138 ( 7, 5) [000034] DA---------- * STORE_LCL_VAR int V05 loc0 NA REG NA
N140 (???,???) [000073] ------------ IL_OFFSET void IL offset: 0x32 REG NA
N142 ( 0, 0) [000035] ------------ NOP void REG NA
------------ BB03 [???..???) -> BB05 (callf), preds={BB02} succs={BB05}
------------ BB04 [???..???) -> BB08 (ALWAYS), preds={BB07} succs={BB08}
------------ BB08 [044..046) -> BB09 (always), preds={BB04} succs={BB09}
N184 (???,???) [000074] ------------ IL_OFFSET void IL offset: 0x44 REG NA
N186 ( 3, 2) [000036] ------------ t36 = LCL_VAR int V05 loc0 rax REG rax
/--* t36 int
N188 ( 7, 5) [000062] DA---------- * STORE_LCL_VAR int V14 tmp3 NA REG NA
------------ BB09 [???..???) (return), preds={BB08} succs={}
N192 ( 3, 2) [000045] -------N---- t45 = LCL_VAR int V14 tmp3 rax REG rax
/--* t45 int
N194 ( 4, 3) [000046] ------------ * RETURN int REG NA
------------ BB05 [037..03D) -> BB07 (cond), preds={BB03} succs={BB06,BB07}
N148 (???,???) [000075] ------------ IL_OFFSET void IL offset: 0x37 REG NA
N150 ( 3, 2) [000038] ------------ t38 = LCL_VAR int (AX) V08 loc3 rcx REG rcx
/--* t38 int
N152 ( 4, 4) [000059] ----G------- t59 = * CAST int <- bool <- int REG rcx
N154 ( 1, 1) [000039] -c---------- t39 = CNS_INT int 0 REG NA
/--* t59 int
+--* t39 int
N156 ( 6, 6) [000040] J---G--N---- * EQ void REG NA
N158 ( 8, 8) [000041] ----G------- * JTRUE void REG NA
------------ BB06 [03D..043), preds={BB05} succs={BB07}
N162 (???,???) [000076] ------------ IL_OFFSET void IL offset: 0x3d REG NA
N164 ( 3, 2) [000043] ------------ t43 = LCL_VAR ref V00 arg0 rcx REG rcx
/--* t43 ref
N166 (???,???) [000110] ------------ t110 = * PUTARG_REG ref REG rcx
N168 ( 3, 10) [000111] -c---------- t111 = CNS_INT(h) long 0x4200E0 ftn REG NA
/--* t111 long
N170 ( 5, 12) [000112] -c---------- t112 = * IND long REG NA
/--* t110 ref this in rcx
+--* t112 long control expr
N172 ( 17, 9) [000044] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease REG NA
------------ BB07 [043..044) (finret), preds={BB05,BB06} succs={BB04}
N176 (???,???) [000077] ------------ IL_OFFSET void IL offset: 0x43 REG NA
N178 ( 0, 0) [000042] ------------ RETFILT void REG NA
-------------------------------------------------------------------------------------------------------------------
Final allocation
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
0.#0 BB1 PredBB0 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
4.#1 BB2 PredBB1 | | | | | | | | | |
9.#2 I0 Def Alloc rdx | | |I0 a| | | | | | |
10.#3 rdx Fixd Keep rdx | | |I0 a| | | | | | |
10.#4 I0 Use * Keep rdx | | |I0 i| | | | | | |
11.#5 rdx Fixd Keep rdx | | | | | | | | | |
11.#6 I1 Def Alloc rdx | | |I1 a| | | | | | |
13.#7 I2 Def Alloc rcx | |I2 a|I1 a| | | | | | |
14.#8 rcx Fixd Keep rcx | |I2 a|I1 a| | | | | | |
14.#9 I2 Use * Keep rcx | |I2 i|I1 a| | | | | | |
15.#10 rcx Fixd Keep rcx | | |I1 a| | | | | | |
15.#11 I3 Def Alloc rcx | |I3 a|I1 a| | | | | | |
20.#12 rdx Fixd Keep rdx | |I3 a|I1 a| | | | | | |
20.#13 I1 Use * Keep rdx | |I3 a|I1 i| | | | | | |
20.#14 rcx Fixd Keep rcx | |I3 a| | | | | | | |
20.#15 I3 Use * Keep rcx | |I3 i| | | | | | | |
21.#16 rax Kill Keep rax | | | | | | | | | |
21.#17 rcx Kill Keep rcx | | | | | | | | | |
21.#18 rdx Kill Keep rdx | | | | | | | | | |
21.#19 r8 Kill Keep r8 | | | | | | | | | |
21.#20 r9 Kill Keep r9 | | | | | | | | | |
21.#21 r10 Kill Keep r10 | | | | | | | | | |
21.#22 r11 Kill Keep r11 | | | | | | | | | |
25.#23 I4 Def Alloc rcx | |I4 a| | | | | | | |
26.#24 rcx Fixd Keep rcx | |I4 a| | | | | | | |
26.#25 I4 Use * Keep rcx | |I4 i| | | | | | | |
27.#26 rcx Fixd Keep rcx | | | | | | | | | |
27.#27 I5 Def Alloc rcx | |I5 a| | | | | | | |
32.#28 rcx Fixd Keep rcx | |I5 a| | | | | | | |
32.#29 I5 Use * Keep rcx | |I5 i| | | | | | | |
33.#30 rax Kill Keep rax | | | | | | | | | |
33.#31 rcx Kill Keep rcx | | | | | | | | | |
33.#32 rdx Kill Keep rdx | | | | | | | | | |
33.#33 r8 Kill Keep r8 | | | | | | | | | |
33.#34 r9 Kill Keep r9 | | | | | | | | | |
33.#35 r10 Kill Keep r10 | | | | | | | | | |
33.#36 r11 Kill Keep r11 | | | | | | | | | |
33.#37 rax Fixd Keep rax | | | | | | | | | |
33.#38 I6 Def Alloc rax |I6 a| | | | | | | | |
34.#39 I6 Use * Keep rax |I6 i| | | | | | | | |
39.#40 I7 Def Alloc rax |I7 a| | | | | | | | |
40.#41 I7 Use * Keep rax |I7 i| | | | | | | | |
45.#42 I8 Def Alloc rax |I8 a| | | | | | | | |
46.#43 I8 Use * Keep rax |I8 i| | | | | | | | |
51.#44 I9 Def Alloc rax |I9 a| | | | | | | | |
52.#45 I9 Use * Keep rax |I9 i| | | | | | | | |
55.#46 I10 Def Alloc rax |I10a| | | | | | | | |
56.#47 I10 Use * Keep rax |I10i| | | | | | | | |
65.#48 rax Kill Keep rax | | | | | | | | | |
65.#49 rcx Kill Keep rcx | | | | | | | | | |
65.#50 rdx Kill Keep rdx | | | | | | | | | |
65.#51 r8 Kill Keep r8 | | | | | | | | | |
65.#52 r9 Kill Keep r9 | | | | | | | | | |
65.#53 r10 Kill Keep r10 | | | | | | | | | |
65.#54 r11 Kill Keep r11 | | | | | | | | | |
69.#55 I11 Def Alloc rcx | |I11a| | | | | | | |
70.#56 I11 Use * Keep rcx | |I11i| | | | | | | |
73.#57 I12 Def Alloc rcx | |I12a| | | | | | | |
74.#58 rcx Fixd Keep rcx | |I12a| | | | | | | |
74.#59 I12 Use * Keep rcx | |I12i| | | | | | | |
75.#60 rcx Fixd Keep rcx | | | | | | | | | |
75.#61 I13 Def Alloc rcx | | | | | | | | | |
Spill rcx | | | | | | | | | |
77.#62 I14 Def Alloc rdx | | |I14a| | | | | | |
78.#63 rdx Fixd Keep rdx | | |I14a| | | | | | |
78.#64 I14 Use * Keep rdx | | |I14i| | | | | | |
79.#65 rdx Fixd Keep rdx | | | | | | | | | |
79.#66 I15 Def Alloc rdx | | | | | | | | | |
Spill rdx | | | | | | | | | |
81.#67 I16 Def Alloc r8 | | | | | | | |I16a| |
82.#68 r8 Fixd Keep r8 | | | | | | | |I16a| |
82.#69 I16 Use * Keep r8 | | | | | | | |I16i| |
83.#70 r8 Fixd Keep r8 | | | | | | | | | |
83.#71 I17 Def Alloc r8 | | | | | | | | | |
Spill r8 | | | | | | | | | |
85.#72 I18 Def Alloc r9 | | | | | | | | |I18a|
86.#73 r9 Fixd Keep r9 | | | | | | | | |I18a|
86.#74 I18 Use * Keep r9 | | | | | | | | |I18i|
87.#75 r9 Fixd Keep r9 | | | | | | | | | |
87.#76 I19 Def Alloc r9 | | | | | | | | | |
Spill r9 | | | | | | | | | |
91.#77 I20 Def Alloc rcx | |I20a| | | | | | | |
92.#78 rcx Fixd Keep rcx | |I20a| | | | | | | |
92.#79 I20 Use * Keep rcx | |I20i| | | | | | | |
93.#80 rcx Fixd Keep rcx | | | | | | | | | |
93.#81 I21 Def Alloc rcx | |I21a| | | | | | | |
98.#82 rcx Fixd Keep rcx | |I21a| | | | | | | |
98.#83 I21 Use * Keep rcx | |I21i| | | | | | | |
99.#84 rax Kill Keep rax | | | | | | | | | |
99.#85 rcx Kill Keep rcx | | | | | | | | | |
99.#86 rdx Kill Keep rdx | | | | | | | | | |
99.#87 r8 Kill Keep r8 | | | | | | | | | |
99.#88 r9 Kill Keep r9 | | | | | | | | | |
99.#89 r10 Kill Keep r10 | | | | | | | | | |
99.#90 r11 Kill Keep r11 | | | | | | | | | |
| | | | | | | | | |
103.#92 I22 Def Alloc rax |I22a| | | | | | | | |
106.#93 rcx Fixd Keep rcx |I22a| | | | | | | | |
106.#94 I13 Use * ReLod rcx |I22a|I13a| | | | | | | |
Keep rcx |I22a|I13i| | | | | | | |
106.#95 rdx Fixd Keep rdx |I22a| | | | | | | | |
106.#96 I15 Use * ReLod rdx |I22a| |I15a| | | | | | |
Keep rdx |I22a| |I15i| | | | | | |
106.#97 r8 Fixd Keep r8 |I22a| | | | | | | | |
106.#98 I17 Use * ReLod r8 |I22a| | | | | | |I17a| |
Keep r8 |I22a| | | | | | |I17i| |
106.#99 r9 Fixd Keep r9 |I22a| | | | | | | | |
106.#100 I19 Use * ReLod r9 |I22a| | | | | | | |I19a|
Keep r9 |I22a| | | | | | | |I19i|
106.#101 I22 Use * Keep rax |I22i| | | | | | | | |
107.#102 rax Kill Keep rax | | | | | | | | | |
107.#103 rcx Kill Keep rcx | | | | | | | | | |
107.#104 rdx Kill Keep rdx | | | | | | | | | |
107.#105 r8 Kill Keep r8 | | | | | | | | | |
107.#106 r9 Kill Keep r9 | | | | | | | | | |
107.#107 r10 Kill Keep r10 | | | | | | | | | |
107.#108 r11 Kill Keep r11 | | | | | | | | | |
| | | | | | | | | |
107.#110 rax Fixd Keep rax | | | | | | | | | |
107.#111 I23 Def Alloc rsi | | | | | |I23a| | | |
109.#112 I24 Def Alloc rcx | |I24a| | | |I23a| | | |
110.#113 rcx Fixd Keep rcx | |I24a| | | |I23a| | | |
110.#114 I24 Use * Keep rcx | |I24i| | | |I23a| | | |
111.#115 rcx Fixd Keep rcx | | | | | |I23a| | | |
111.#116 I25 Def Alloc rcx | |I25a| | | |I23a| | | |
116.#117 rcx Fixd Keep rcx | |I25a| | | |I23a| | | |
116.#118 I25 Use * Keep rcx | |I25i| | | |I23a| | | |
117.#119 rax Kill Keep rax | | | | | |I23a| | | |
117.#120 rcx Kill Keep rcx | | | | | |I23a| | | |
117.#121 rdx Kill Keep rdx | | | | | |I23a| | | |
117.#122 r8 Kill Keep r8 | | | | | |I23a| | | |
117.#123 r9 Kill Keep r9 | | | | | |I23a| | | |
117.#124 r10 Kill Keep r10 | | | | | |I23a| | | |
117.#125 r11 Kill Keep r11 | | | | | |I23a| | | |
118.#126 I23 Use * Keep rsi | | | | | |I23i| | | |
127.#127 rax Kill Keep rax | | | | | | | | | |
127.#128 rcx Kill Keep rcx | | | | | | | | | |
127.#129 rdx Kill Keep rdx | | | | | | | | | |
127.#130 r8 Kill Keep r8 | | | | | | | | | |
127.#131 r9 Kill Keep r9 | | | | | | | | | |
127.#132 r10 Kill Keep r10 | | | | | | | | | |
127.#133 r11 Kill Keep r11 | | | | | | | | | |
131.#134 I26 Def Alloc rcx | |I26a| | | | | | | |
132.#135 I26 Use * Keep rcx | |I26i| | | | | | | |
137.#136 I27 Def Alloc rcx | |I27a| | | | | | | |
138.#137 I27 Use * Keep rcx | |I27i| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
144.#138 BB3 PredBB2 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
146.#139 BB5 PredBB0 | | | | | | | | | |
151.#140 I28 Def Alloc rcx | |I28a| | | | | | | |
152.#141 I28 Use * Keep rcx | |I28i| | | | | | | |
153.#142 I29 Def Alloc rcx | |I29a| | | | | | | |
156.#143 I29 Use * Keep rcx | |I29i| | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
160.#144 BB6 PredBB5 | | | | | | | | | |
165.#145 I30 Def Alloc rcx | |I30a| | | | | | | |
166.#146 rcx Fixd Keep rcx | |I30a| | | | | | | |
166.#147 I30 Use * Keep rcx | |I30i| | | | | | | |
167.#148 rcx Fixd Keep rcx | | | | | | | | | |
167.#149 I31 Def Alloc rcx | |I31a| | | | | | | |
172.#150 rcx Fixd Keep rcx | |I31a| | | | | | | |
172.#151 I31 Use * Keep rcx | |I31i| | | | | | | |
173.#152 rax Kill Keep rax | | | | | | | | | |
173.#153 rcx Kill Keep rcx | | | | | | | | | |
173.#154 rdx Kill Keep rdx | | | | | | | | | |
173.#155 r8 Kill Keep r8 | | | | | | | | | |
173.#156 r9 Kill Keep r9 | | | | | | | | | |
173.#157 r10 Kill Keep r10 | | | | | | | | | |
173.#158 r11 Kill Keep r11 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
174.#159 BB7 PredBB5 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
180.#160 BB4 PredBB0 | | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
182.#161 BB8 PredBB0 | | | | | | | | | |
187.#162 I32 Def Alloc rax |I32a| | | | | | | | |
188.#163 I32 Use * Keep rax |I32i| | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
190.#164 BB9 PredBB8 | | | | | | | | | |
193.#165 I33 Def Alloc rax |I33a| | | | | | | | |
194.#166 rax Fixd Keep rax |I33a| | | | | | | | |
194.#167 I33 Use * Keep rax |I33i| | | | | | | | |
Recording the maximum number of concurrent spills:
int: 1
pre-allocated temp #1, slot 0, size = 4
long: 3
pre-allocated temp #2, slot 1, size = 8
pre-allocated temp #3, slot 1, size = 8
pre-allocated temp #4, slot 1, size = 8
----------
LSRA Stats
----------
BB02 [ 100]: SpillCount = 4, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0
Total Tracked Vars: 0
Total Reg Cand Vars: 0
Total number of Intervals: 33
Total number of RefPositions: 167
Total Spill Count: 4 Weighted: 400
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 4
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [???..???), preds={} succs={BB02}
=====
N002. NOP
BB02 [000..037) -> BB03 (always), preds={BB01} succs={BB03}
=====
N006. IL_OFFSET IL offset: 0x0
N008. rdx = LCL_VAR_ADDR V08 loc3 rdx
N010. rdx = PUTARG_REG; rdx
N012. rcx = V00 MEM
N014. rcx = PUTARG_REG; rcx
N016. CNS_INT(h) 0x420058 ftn
N018. IND
N020. CALL r2r_ind; rdx,rcx
N022. IL_OFFSET IL offset: 0x8
N024. rcx = V00 MEM
N026. rcx = PUTARG_REG; rcx
N028. CNS_INT(h) 0x420080 ftn
N030. IND
N032. rax = CALL r2r_ind; rcx
N034. V12 MEM; rax
N036. IL_OFFSET IL offset: 0xe
N038. rax = V12 MEM
N040. V07 MEM; rax
N042. IL_OFFSET IL offset: 0xf
N044. rax = V03 MEM
N046. V10 MEM; rax
N048. IL_OFFSET IL offset: 0x12
N050. rax = V10 MEM
N052. V16 MEM; rax
N054. rax = V16 MEM
N056. V09 MEM; rax
N058. IL_OFFSET IL offset: 0x17
N060. CNS_INT(h) 0x4200A0 ftn
N062. IND
N064. CALL r2r_ind
N066. IL_OFFSET IL offset: 0x25
N068. rcx = V04 MEM
N070. PUTARG_STK [+0x20]; rcx
N072. rcx = V07 MEM
S N074. rcx = PUTARG_REG; rcx
N076. rdx = V01 MEM
S N078. rdx = PUTARG_REG; rdx
N080. r8 = V02 MEM
S N082. r8 = PUTARG_REG; r8
N084. r9 = V09 MEM
S N086. r9 = PUTARG_REG; r9
N088. PINVOKE_PROLOG
N090. rcx = LCL_VAR_ADDR V15 PInvokeFrame rcx
N092. rcx = PUTARG_REG; rcx
N094. CNS_INT(h) 0x4200E8 ftn
N096. IND
N098. CALL help; rcx
N100. CNS_INT(h) 0x4200F0 ftn
N102. rax = IND
N104. STK = IND ; rax
N106. rsi = CALL r2r_ind; rcx,rdx,r8,r9,STK
N108. rcx = LCL_VAR_ADDR V15 PInvokeFrame rcx
N110. rcx = PUTARG_REG; rcx
N112. CNS_INT(h) 0x4200F8 ftn
N114. IND
N116. CALL help; rcx
N118. V13 MEM; rsi
N120. IL_OFFSET IL offset: 0x2a
N122. CNS_INT(h) 0x4200C8 ftn
N124. IND
N126. CALL r2r_ind
N128. IL_OFFSET IL offset: 0x2f
N130. rcx = V13 MEM
N132. V06 MEM; rcx
N134. IL_OFFSET IL offset: 0x30
N136. rcx = V06 MEM
N138. V05 MEM; rcx
N140. IL_OFFSET IL offset: 0x32
N142. NOP
BB03 [???..???) -> BB05 (callf), preds={BB02} succs={BB05}
=====
BB05 [037..03D) -> BB07 (cond), preds={BB03} succs={BB06,BB07}
=====
N148. IL_OFFSET IL offset: 0x37
N150. rcx = V08 MEM
N152. rcx = CAST ; rcx
N154. CNS_INT 0
N156. EQ ; rcx
N158. JTRUE
BB06 [03D..043), preds={BB05} succs={BB07}
=====
N162. IL_OFFSET IL offset: 0x3d
N164. rcx = V00 MEM
N166. rcx = PUTARG_REG; rcx
N168. CNS_INT(h) 0x4200E0 ftn
N170. IND
N172. CALL r2r_ind; rcx
BB07 [043..044) (finret), preds={BB05,BB06} succs={BB04}
=====
N176. IL_OFFSET IL offset: 0x43
N178. RETFILT
BB04 [???..???) -> BB08 (ALWAYS), preds={BB07} succs={BB08}
=====
BB08 [044..046) -> BB09 (always), preds={BB04} succs={BB09}
=====
N184. IL_OFFSET IL offset: 0x44
N186. rax = V05 MEM
N188. V14 MEM; rax
BB09 [???..???) (return), preds={BB08} succs={}
=====
N192. rax = V14 MEM
N194. RETURN ; rax
*************** Finishing PHASE Linear scan register alloc
*************** In genGenerateCode()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [???..???) keep i internal label target LIR
BB02 [0001] 1 0 BB01 1 [000..037)-> BB03 (always) T0 try { } keep i try label gcsafe LIR
BB03 [0006] 1 BB02 1 [???..???)-> BB05 (callf ) i internal label target LIR
BB04 [0007] 1 BB07 1 [???..???)-> BB08 (ALWAYS) i internal label target LIR KEEP
BB08 [0005] 1 BB04 1 [044..046)-> BB09 (always) i label target LIR
BB09 [0008] 1 BB08 1 [???..???) (return) keep internal target LIR
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow
BB05 [0002] 2 0 BB03 1 [037..03D)-> BB07 ( cond ) H0 F finally { keep i label target flet LIR
BB06 [0003] 1 0 BB05 1 [03D..043) H0 i gcsafe LIR
BB07 [0004] 2 0 BB05,BB06 1 [043..044) (finret) H0 } i label target LIR
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Modified regs: [rax rcx rdx rsi r8-r11]
Marking regs modified: [rbx rsi rdi r12-r15] ([rax rcx rdx rsi r8-r11] => [rax rcx rdx rbx rsi rdi r8-r15])
Callee-saved registers pushed: 7 [rbx rsi rdi r12-r15]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V05 loc0, size=4, stkOffs=-0x4c
Assign V06 loc1, size=4, stkOffs=-0x50
Assign V07 loc2, size=8, stkOffs=-0x58
Assign V08 loc3, size=8, stkOffs=-0x60
Assign V09 loc4, size=8, stkOffs=-0x68
Assign V10 loc5, size=8, stkOffs=-0x70
Assign V12 tmp1, size=8, stkOffs=-0x78
Assign V13 tmp2, size=4, stkOffs=-0x7c
Assign V14 tmp3, size=4, stkOffs=-0x80
Assign V16 tmp5, size=8, stkOffs=-0x88
Pad V15 PInvokeFrame, size=88, stkOffs=-0xa8, pad=4
Assign V15 PInvokeFrame, size=88, stkOffs=-0x100
Assign V17 PSPSym, size=8, stkOffs=-0x108
Assign V11 OutArgs, size=40, stkOffs=-0x130
--- delta bump 8 for RA
--- delta bump 8 for FP
--- delta bump 0 for RBP frame
--- virtual stack offset to actual stack offset delta is 16
-- V00 was 0, now 16
-- V01 was 8, now 24
-- V02 was 16, now 32
-- V03 was 24, now 40
-- V04 was 32, now 48
-- V05 was -76, now -60
-- V06 was -80, now -64
-- V07 was -88, now -72
-- V08 was -96, now -80
-- V09 was -104, now -88
-- V10 was -112, now -96
-- V11 was -304, now -288
-- V12 was -120, now -104
-- V13 was -124, now -108
-- V14 was -128, now -112
-- V15 was -256, now -240
-- V16 was -136, now -120
-- V17 was -264, now -248
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 1, 1 ) ref -> [rbp+0x10] class-hnd
; V01 arg1 [V01 ] ( 1, 1 ) long -> [rbp+0x18]
; V02 arg2 [V02 ] ( 1, 1 ) int -> [rbp+0x20]
; V03 arg3 [V03 ] ( 1, 1 ) byref -> [rbp+0x28]
; V04 arg4 [V04 ] ( 1, 1 ) long -> [rbp+0x30]
; V05 loc0 [V05 ] ( 1, 1 ) int -> [rbp-0x3C] must-init
; V06 loc1 [V06 ] ( 1, 1 ) int -> [rbp-0x40] must-init
; V07 loc2 [V07 ] ( 1, 1 ) long -> [rbp-0x48] must-init
; V08 loc3 [V08 ] ( 1, 1 ) bool -> [rbp-0x50] do-not-enreg[X] must-init addr-exposed ld-addr-op
; V09 loc4 [V09 ] ( 1, 1 ) long -> [rbp-0x58] must-init
; V10 loc5 [V10 ] ( 1, 1 ) byref -> [rbp-0x60] must-init pinned
; V11 OutArgs [V11 ] ( 1, 1 ) lclBlk (40) [rsp+0x00] "OutgoingArgSpace"
; V12 tmp1 [V12 ] ( 1, 1 ) long -> [rbp-0x68] "impSpillStackEnsure"
; V13 tmp2 [V13 ] ( 1, 1 ) int -> [rbp-0x6C] "impSpillStackEnsure"
; V14 tmp3 [V14 ] ( 1, 1 ) int -> [rbp-0x70] "Single return block return value"
; V15 PInvokeFrame [V15 ] ( 1, 1 ) blk (88) [rbp-0xF0] do-not-enreg[X] addr-exposed "Pinvoke FrameVar"
; V16 tmp5 [V16 ] ( 1, 1 ) long -> [rbp-0x78] "Cast away GC"
; V17 PSPSym [V17 ] ( 1, 1 ) long -> [rbp-0xF8] do-not-enreg[X] addr-exposed "PSPSym"
; TEMP_01 int -> [rbp-0x7C]
; TEMP_04 long -> [rbp-0x84]
; TEMP_03 long -> [rbp-0x8C]
; TEMP_02 long -> [rbp-0x94]
;
; Lcl frame size = 232
Setting stack level from -572662307 to 0
=============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x00000000.40030070: keep i internal label target LIR
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M25631_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB01, IL range [???..???)
Scope info: ignoring block beginning
Generating: N002 ( 0, 0) [000000] ------------ NOP void REG NA
Scope info: end block BB01, IL range [???..???)
Scope info: ignoring block end
=============== Generating BB02 [000..037) -> BB03 (always), preds={BB01} succs={BB03} flags=0x00000004.40090130: keep i try label gcsafe LIR
BB02 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M25631_BB02:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB02, IL range [000..037)
Scope info: opening scope, LVnum=0 [000..046)
Scope info: >> new scope, VarNum=0, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=1 [000..046)
Scope info: >> new scope, VarNum=1, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=2 [000..046)
Scope info: >> new scope, VarNum=2, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=3 [000..046)
Scope info: >> new scope, VarNum=3, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=4 [000..046)
Scope info: >> new scope, VarNum=4, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=5 [000..046)
Scope info: >> new scope, VarNum=5, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=6 [000..046)
Scope info: >> new scope, VarNum=6, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=7 [000..046)
Scope info: >> new scope, VarNum=7, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=8 [000..046)
Scope info: >> new scope, VarNum=8, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=9 [000..046)
Scope info: >> new scope, VarNum=9, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: opening scope, LVnum=10 [000..046)
Scope info: >> new scope, VarNum=10, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
Scope info: open scopes =
0 (V00 arg0) [000..046)
1 (V01 arg1) [000..046)
2 (V02 arg2) [000..046)
3 (V03 arg3) [000..046)
4 (V04 arg4) [000..046)
5 (V05 loc0) [000..046)
6 (V06 loc1) [000..046)
7 (V07 loc2) [000..046)
8 (V08 loc3) [000..046)
9 (V09 loc4) [000..046)
10 (V10 loc5) [000..046)
Added IP mapping: 0x0000 STACK_EMPTY (G_M25631_IG02,ins#0,ofs#0) label
Generating: N006 (???,???) [000063] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N008 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V08 loc3 rdx REG rdx
IN0001: lea rdx, [V08 rbp-50H]
/--* t3 long
Generating: N010 (???,???) [000078] ------------ t78 = * PUTARG_REG long REG rdx
Generating: N012 ( 3, 2) [000001] ------------ t1 = LCL_VAR ref V00 arg0 rcx REG rcx
IN0002: mov rcx, gword ptr [V00 rbp+10H]
GC regs: 00000000 {} => 00000002 {rcx}
/--* t1 ref
Generating: N014 (???,???) [000079] ------------ t79 = * PUTARG_REG ref REG rcx
GC regs: 00000002 {rcx} => 00000000 {}
GC regs: 00000000 {} => 00000002 {rcx}
Generating: N016 ( 3, 10) [000080] -c---------- t80 = CNS_INT(h) long 0x420058 ftn REG NA
/--* t80 long
Generating: N018 ( 5, 12) [000081] -c---------- t81 = * IND long REG NA
/--* t78 long arg1 in rdx
+--* t79 ref this in rcx
+--* t81 long control expr
Generating: N020 ( 20, 13) [000004] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousAddRef REG NA
GC regs: 00000002 {rcx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x0003 CALL_INSTRUCTION (G_M25631_IG02,ins#2,ofs#8)
IN0003: call [System.Runtime.InteropServices.SafeHandle:DangerousAddRef(byref):this]
Added IP mapping: 0x0008 STACK_EMPTY (G_M25631_IG02,ins#3,ofs#14)
Generating: N022 (???,???) [000064] ------------ IL_OFFSET void IL offset: 0x8 REG NA
Generating: N024 ( 3, 2) [000005] ------------ t5 = LCL_VAR ref V00 arg0 rcx REG rcx
IN0004: mov rcx, gword ptr [V00 rbp+10H]
GC regs: 00000000 {} => 00000002 {rcx}
/--* t5 ref
Generating: N026 (???,???) [000082] ------------ t82 = * PUTARG_REG ref REG rcx
GC regs: 00000002 {rcx} => 00000000 {}
GC regs: 00000000 {} => 00000002 {rcx}
Generating: N028 ( 3, 10) [000083] -c---------- t83 = CNS_INT(h) long 0x420080 ftn REG NA
/--* t83 long
Generating: N030 ( 5, 12) [000084] -c---------- t84 = * IND long REG NA
/--* t82 ref this in rcx
+--* t84 long control expr
Generating: N032 ( 17, 9) [000006] --CXG------- t6 = * CALL r2r_ind long System.Runtime.InteropServices.SafeHandle.DangerousGetHandle REG rax
GC regs: 00000002 {rcx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x0009 CALL_INSTRUCTION (G_M25631_IG02,ins#4,ofs#18)
IN0005: call [System.Runtime.InteropServices.SafeHandle:DangerousGetHandle():long:this]
/--* t6 long
Generating: N034 ( 21, 12) [000008] DA-XG------- * STORE_LCL_VAR long V12 tmp1 NA REG NA
IN0006: mov qword ptr [V12 rbp-68H], rax
Added IP mapping: 0x000E (G_M25631_IG02,ins#6,ofs#28)
Generating: N036 (???,???) [000065] ------------ IL_OFFSET void IL offset: 0xe REG NA
Generating: N038 ( 3, 2) [000009] ------------ t9 = LCL_VAR long V12 tmp1 rax REG rax
IN0007: mov rax, qword ptr [V12 rbp-68H]
/--* t9 long
Generating: N040 ( 7, 5) [000011] DA---------- * STORE_LCL_VAR long V07 loc2 NA REG NA
IN0008: mov qword ptr [V07 rbp-48H], rax
Added IP mapping: 0x000F STACK_EMPTY (G_M25631_IG02,ins#8,ofs#36)
Generating: N042 (???,???) [000066] ------------ IL_OFFSET void IL offset: 0xf REG NA
Generating: N044 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V03 arg3 rax REG rax
IN0009: mov rax, bword ptr [V03 rbp+28H]
Byref regs: 00000000 {} => 00000001 {rax}
/--* t12 byref
Generating: N046 ( 7, 5) [000014] DA---------- * STORE_LCL_VAR byref V10 loc5 NA REG NA
Byref regs: 00000001 {rax} => 00000000 {}
IN000a: mov bword ptr [V10 rbp-60H], rax
Added IP mapping: 0x0012 STACK_EMPTY (G_M25631_IG02,ins#10,ofs#44)
Generating: N048 (???,???) [000067] ------------ IL_OFFSET void IL offset: 0x12 REG NA
Generating: N050 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V10 loc5 rax REG rax
IN000b: mov rax, bword ptr [V10 rbp-60H]
Byref regs: 00000000 {} => 00000001 {rax}
/--* t15 byref
Generating: N052 ( 7, 5) [000051] DA---------- * STORE_LCL_VAR long V16 tmp5 NA REG NA
Byref regs: 00000001 {rax} => 00000000 {}
IN000c: mov qword ptr [V16 rbp-78H], rax
Generating: N054 ( 3, 2) [000052] ------------ t52 = LCL_VAR long V16 tmp5 rax REG rax
IN000d: mov rax, qword ptr [V16 rbp-78H]
/--* t52 long
Generating: N056 ( 14, 10) [000018] DA---------- * STORE_LCL_VAR long V09 loc4 NA REG NA
IN000e: mov qword ptr [V09 rbp-58H], rax
Added IP mapping: 0x0017 STACK_EMPTY (G_M25631_IG02,ins#14,ofs#60)
Generating: N058 (???,???) [000068] ------------ IL_OFFSET void IL offset: 0x17 REG NA
Generating: N060 ( 3, 10) [000085] -c---------- t85 = CNS_INT(h) long 0x4200A0 ftn REG NA
/--* t85 long
Generating: N062 ( 5, 12) [000086] -c---------- t86 = * IND long REG NA
/--* t86 long control expr
Generating: N064 ( 14, 5) [000024] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.ClearLastError REG NA
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x0020 CALL_INSTRUCTION (G_M25631_IG02,ins#14,ofs#60)
IN000f: call [System.StubHelpers.StubHelpers:ClearLastError()]
Added IP mapping: 0x0025 (G_M25631_IG02,ins#15,ofs#66)
Generating: N066 (???,???) [000069] ------------ IL_OFFSET void IL offset: 0x25 REG NA
Generating: N068 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V04 arg4 rcx REG rcx
IN0010: mov rcx, qword ptr [V04 rbp+30H]
/--* t23 long
Generating: N070 (???,???) [000087] ------------ * PUTARG_STK [+0x20] void REG NA
IN0011: mov qword ptr [V11+0x20 rsp+20H], rcx
Generating: N072 ( 3, 2) [000019] ------------ t19 = LCL_VAR long V07 loc2 rcx REG rcx
IN0012: mov rcx, qword ptr [V07 rbp-48H]
/--* t19 long
Generating: N074 (???,???) [000088] -----------Z t88 = * PUTARG_REG long REG rcx
reused temp #4, slot 1, size = 8
The register rcx spilled with [000088]
IN0013: mov qword ptr [TEMP_04 rbp-84H], rcx
Generating: N076 ( 3, 2) [000020] ------------ t20 = LCL_VAR long V01 arg1 rdx REG rdx
IN0014: mov rdx, qword ptr [V01 rbp+18H]
/--* t20 long
Generating: N078 (???,???) [000089] -----------Z t89 = * PUTARG_REG long REG rdx
reused temp #3, slot 1, size = 8
The register rdx spilled with [000089]
IN0015: mov qword ptr [TEMP_03 rbp-8CH], rdx
Generating: N080 ( 3, 2) [000021] ------------ t21 = LCL_VAR int V02 arg2 r8 REG r8
IN0016: mov r8d, dword ptr [V02 rbp+20H]
/--* t21 int
Generating: N082 (???,???) [000090] -----------Z t90 = * PUTARG_REG int REG r8
reused temp #1, slot 0, size = 4
The register r8 spilled with [000090]
IN0017: mov dword ptr [TEMP_01 rbp-7CH], r8d
Generating: N084 ( 3, 2) [000022] ------------ t22 = LCL_VAR long V09 loc4 r9 REG r9
IN0018: mov r9, qword ptr [V09 rbp-58H]
/--* t22 long
Generating: N086 (???,???) [000091] -----------Z t91 = * PUTARG_REG long REG r9
reused temp #2, slot 1, size = 8
The register r9 spilled with [000091]
IN0019: mov qword ptr [TEMP_02 rbp-94H], r9
Generating: N088 (???,???) [000092] ------------ PINVOKE_PROLOG void REG NA
Generating: N090 ( 3, 3) [000093] ------------ t93 = LCL_VAR_ADDR long V15 PInvokeFrame rcx REG rcx
IN001a: lea rcx, [V15 rbp-F0H]
/--* t93 long
Generating: N092 (???,???) [000096] ------------ t96 = * PUTARG_REG long REG rcx
Generating: N094 ( 3, 10) [000097] -c---------- t97 = CNS_INT(h) long 0x4200E8 ftn REG NA
/--* t97 long
Generating: N096 ( 5, 12) [000098] -c---------- t98 = * IND long REG NA
/--* t96 long arg0 in rcx
+--* t98 long control expr
Generating: N098 ( 17, 9) [000094] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_BEGIN REG NA
New Basic Block BB10 [0009] created.
L_M25631_BB10:
G_M25631_IG02: ; offs=000000H, funclet=00, bbWeight=1
Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN001b: call [CORINFO_HELP_JIT_PINVOKE_BEGIN]
Generating: N100 ( 3, 10) [000099] -c---------- t99 = CNS_INT(h) long 0x4200F0 ftn REG NA
/--* t99 long
Generating: N102 ( 5, 12) [000100] ------------ t100 = * IND long REG rax
IN001c: mov rax, qword ptr [(reloc 0x4200f0)]
/--* t100 long
Generating: N104 ( 8, 14) [000101] -c---------- t101 = * IND long REG NA
/--* t88 long arg0 in rcx
+--* t89 long arg1 in rdx
+--* t90 int arg2 in r8
+--* t91 long arg3 in r9
+--* t101 long control expr
Generating: N106 ( 32, 19) [000025] --CXG------- t25 = * CALL r2r_ind int Kernel32.ReadFile REG rsi
Tree-Node marked unspilled from [000088]
IN001d: mov rcx, qword ptr [TEMP_04 rbp-84H]
release temp #4, slot 1, size = 8
Tree-Node marked unspilled from [000089]
IN001e: mov rdx, qword ptr [TEMP_03 rbp-8CH]
release temp #3, slot 1, size = 8
Tree-Node marked unspilled from [000090]
IN001f: mov r8d, dword ptr [TEMP_01 rbp-7CH]
release temp #1, slot 0, size = 4
Tree-Node marked unspilled from [000091]
IN0020: mov r9, qword ptr [TEMP_02 rbp-94H]
release temp #2, slot 1, size = 8
New Basic Block BB11 [0010] created.
L_M25631_BB11:
G_M25631_IG03: ; offs=00007BH, funclet=00, bbWeight=1
Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x0025 CALL_INSTRUCTION (G_M25631_IG04,ins#0,ofs#0)
IN0021: call qword ptr [rax]Kernel32:ReadFile(long,long,int,long,long):int
IN0022: mov esi, eax
Generating: N108 ( 3, 3) [000102] ------------ t102 = LCL_VAR_ADDR long V15 PInvokeFrame rcx REG rcx
IN0023: lea rcx, [V15 rbp-F0H]
/--* t102 long
Generating: N110 (???,???) [000105] ------------ t105 = * PUTARG_REG long REG rcx
Generating: N112 ( 3, 10) [000106] -c---------- t106 = CNS_INT(h) long 0x4200F8 ftn REG NA
/--* t106 long
Generating: N114 ( 5, 12) [000107] -c---------- t107 = * IND long REG NA
/--* t105 long arg0 in rcx
+--* t107 long control expr
Generating: N116 ( 17, 9) [000103] --C-G------- * CALL help void HELPER.CORINFO_HELP_JIT_PINVOKE_END REG NA
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0024: call [CORINFO_HELP_JIT_PINVOKE_END]
/--* t25 int
Generating: N118 ( 36, 22) [000027] DA-XG------- * STORE_LCL_VAR int V13 tmp2 NA REG NA
IN0025: mov dword ptr [V13 rbp-6CH], esi
Added IP mapping: 0x002A (G_M25631_IG04,ins#5,ofs#20)
Generating: N120 (???,???) [000070] ------------ IL_OFFSET void IL offset: 0x2a REG NA
Generating: N122 ( 3, 10) [000108] -c---------- t108 = CNS_INT(h) long 0x4200C8 ftn REG NA
/--* t108 long
Generating: N124 ( 5, 12) [000109] -c---------- t109 = * IND long REG NA
/--* t109 long control expr
Generating: N126 ( 14, 5) [000029] --CXG------- * CALL r2r_ind void System.StubHelpers.StubHelpers.SetLastError REG NA
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x002A CALL_INSTRUCTION (G_M25631_IG04,ins#5,ofs#20)
IN0026: call [System.StubHelpers.StubHelpers:SetLastError()]
Added IP mapping: 0x002F (G_M25631_IG04,ins#6,ofs#26)
Generating: N128 (???,???) [000071] ------------ IL_OFFSET void IL offset: 0x2f REG NA
Generating: N130 ( 3, 2) [000028] ------------ t28 = LCL_VAR int V13 tmp2 rcx REG rcx
IN0027: mov ecx, dword ptr [V13 rbp-6CH]
/--* t28 int
Generating: N132 ( 7, 5) [000031] DA---------- * STORE_LCL_VAR int V06 loc1 NA REG NA
IN0028: mov dword ptr [V06 rbp-40H], ecx
Added IP mapping: 0x0030 STACK_EMPTY (G_M25631_IG04,ins#8,ofs#32)
Generating: N134 (???,???) [000072] ------------ IL_OFFSET void IL offset: 0x30 REG NA
Generating: N136 ( 3, 2) [000032] ------------ t32 = LCL_VAR int V06 loc1 rcx REG rcx
IN0029: mov ecx, dword ptr [V06 rbp-40H]
/--* t32 int
Generating: N138 ( 7, 5) [000034] DA---------- * STORE_LCL_VAR int V05 loc0 NA REG NA
IN002a: mov dword ptr [V05 rbp-3CH], ecx
Added IP mapping: 0x0032 STACK_EMPTY (G_M25631_IG04,ins#10,ofs#38)
Generating: N140 (???,???) [000073] ------------ IL_OFFSET void IL offset: 0x32 REG NA
Generating: N142 ( 0, 0) [000035] ------------ NOP void REG NA
IN002b: nop
Scope info: end block BB02, IL range [000..037)
Scope info: open scopes =
0 (V00 arg0) [000..046)
1 (V01 arg1) [000..046)
2 (V02 arg2) [000..046)
3 (V03 arg3) [000..046)
4 (V04 arg4) [000..046)
5 (V05 loc0) [000..046)
6 (V06 loc1) [000..046)
7 (V07 loc2) [000..046)
8 (V08 loc3) [000..046)
9 (V09 loc4) [000..046)
10 (V10 loc5) [000..046)
IN002c: jmp L_M25631_BB03
=============== Generating BB03 [???..???) -> BB05 (callf), preds={BB02} succs={BB05} flags=0x00000000.40030060: i internal label target LIR
BB03 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M25631_BB03:
G_M25631_IG04: ; offs=0000A1H, funclet=00, bbWeight=1
Label: IG05, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB03, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: NO_MAP STACK_EMPTY (G_M25631_IG05,ins#0,ofs#0) label
Scope info: end block BB03, IL range [???..???)
Scope info: ignoring block end
IN002d: mov rcx, rsp
IN002e: call L_M25631_BB05
G_M25631_IG05: ; offs=0000CDH, funclet=00, bbWeight=1
IN002f: nop
=============== Generating BB08 [044..046) -> BB09 (always), preds={BB04} succs={BB09} flags=0x00000000.40030020: i label target LIR
BB08 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M25631_BB08:
G_M25631_IG06: ; offs=0000D5H, funclet=00, bbWeight=1
Label: IG07, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB08, IL range [044..046)
Scope info: found offset hole. lastOffs=55, currOffs=68
Scope info: open scopes =
0 (V00 arg0) [000..046)
1 (V01 arg1) [000..046)
2 (V02 arg2) [000..046)
3 (V03 arg3) [000..046)
4 (V04 arg4) [000..046)
5 (V05 loc0) [000..046)
6 (V06 loc1) [000..046)
7 (V07 loc2) [000..046)
8 (V08 loc3) [000..046)
9 (V09 loc4) [000..046)
10 (V10 loc5) [000..046)
Added IP mapping: 0x0044 STACK_EMPTY (G_M25631_IG07,ins#0,ofs#0) label
Generating: N184 (???,???) [000074] ------------ IL_OFFSET void IL offset: 0x44 REG NA
Generating: N186 ( 3, 2) [000036] ------------ t36 = LCL_VAR int V05 loc0 rax REG rax
IN0030: mov eax, dword ptr [V05 rbp-3CH]
/--* t36 int
Generating: N188 ( 7, 5) [000062] DA---------- * STORE_LCL_VAR int V14 tmp3 NA REG NA
IN0031: mov dword ptr [V14 rbp-70H], eax
Scope info: end block BB08, IL range [044..046)
Scope info: ending scope, LVnum=0 [000..046)
Scope info: ending scope, LVnum=1 [000..046)
Scope info: ending scope, LVnum=2 [000..046)
Scope info: ending scope, LVnum=3 [000..046)
Scope info: ending scope, LVnum=4 [000..046)
Scope info: ending scope, LVnum=5 [000..046)
Scope info: ending scope, LVnum=6 [000..046)
Scope info: ending scope, LVnum=7 [000..046)
Scope info: ending scope, LVnum=8 [000..046)
Scope info: ending scope, LVnum=9 [000..046)
Scope info: ending scope, LVnum=10 [000..046)
Scope info: open scopes =
<none>
IN0032: jmp L_M25631_BB09
=============== Generating BB09 [???..???) (return), preds={BB08} succs={} flags=0x00000000.40020050: keep internal target LIR
BB09 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M25631_BB09:
G_M25631_IG07: ; offs=0000D6H, funclet=00, bbWeight=1
Label: IG08, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB09, IL range [???..???)
Scope info: ignoring block beginning
Added IP mapping: NO_MAP STACK_EMPTY (G_M25631_IG08,ins#0,ofs#0) label
Generating: N192 ( 3, 2) [000045] -------N---- t45 = LCL_VAR int V14 tmp3 rax REG rax
IN0033: mov eax, dword ptr [V14 rbp-70H]
/--* t45 int
Generating: N194 ( 4, 3) [000046] ------------ * RETURN int REG NA
Scope info: end block BB09, IL range [???..???)
Scope info: ignoring block end
Added IP mapping: EPILOG STACK_EMPTY (G_M25631_IG08,ins#1,ofs#3) label
Reserving epilog IG for block BB09
G_M25631_IG08: ; offs=0000E1H, funclet=00, bbWeight=1
*************** After placeholder IG creation
G_M25631_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M25631_IG02: ; offs=000000H, size=007BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG03: ; offs=00007BH, size=0026H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG04: ; offs=0000A1H, size=002CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG05: ; offs=0000CDH, size=0008H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG06: ; offs=0000D5H, size=0001H, nogc, extend
G_M25631_IG07: ; offs=0000D6H, size=000BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG08: ; offs=0000E1H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG09: ; epilog placeholder, next placeholder=<END>, BB09 [0008], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M25631_IG10: ; offs=0001E4H, size=0000H, gcrefRegs=00000000 {} <-- Current IG
=============== Generating BB05 [037..03D) -> BB07 (cond), preds={BB03} succs={BB06,BB07} flags=0x00000000.40030230: keep i label target flet LIR
BB05 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M25631_BB05:
Label: IG10, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: found beginning of funclet region at block BB05; ignoring following blocks
Reserving funclet prolog IG for block BB05
Added IP mapping: PROLOG STACK_EMPTY (G_M25631_IG10,ins#0,ofs#256) label
*************** After placeholder IG creation
G_M25631_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M25631_IG02: ; offs=000000H, size=007BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG03: ; offs=00007BH, size=0026H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG04: ; offs=0000A1H, size=002CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG05: ; offs=0000CDH, size=0008H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG06: ; offs=0000D5H, size=0001H, nogc, extend
G_M25631_IG07: ; offs=0000D6H, size=000BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG08: ; offs=0000E1H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG09: ; epilog placeholder, next placeholder=IG10 , BB09 [0008], epilog, extend <-- First placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M25631_IG10: ; func=01, funclet prolog placeholder, next placeholder=<END>, BB05 [0002], funclet prolog <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M25631_IG11: ; offs=0002E4H, size=0000H, gcrefRegs=00000000 {} <-- Current IG
Added IP mapping: 0x0037 STACK_EMPTY (G_M25631_IG11,ins#0,ofs#0) label
Generating: N148 (???,???) [000075] ------------ IL_OFFSET void IL offset: 0x37 REG NA
Generating: N150 ( 3, 2) [000038] ------------ t38 = LCL_VAR int (AX) V08 loc3 rcx REG rcx
IN0034: mov ecx, dword ptr [V08 rbp-50H]
/--* t38 int
Generating: N152 ( 4, 4) [000059] ----G------- t59 = * CAST int <- bool <- int REG rcx
IN0035: movzx rcx, cl
Generating: N154 ( 1, 1) [000039] -c---------- t39 = CNS_INT int 0 REG NA
/--* t59 int
+--* t39 int
Generating: N156 ( 6, 6) [000040] J---G--N---- * EQ void REG NA
IN0036: test ecx, ecx
Generating: N158 ( 8, 8) [000041] ----G------- * JTRUE void REG NA
IN0037: je L_M25631_BB07
=============== Generating BB06 [03D..043), preds={BB05} succs={BB07} flags=0x00000004.40080020: i gcsafe LIR
BB06 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M25631_BB06:
Added IP mapping: 0x003D STACK_EMPTY (G_M25631_IG11,ins#4,ofs#14) label
Generating: N162 (???,???) [000076] ------------ IL_OFFSET void IL offset: 0x3d REG NA
Generating: N164 ( 3, 2) [000043] ------------ t43 = LCL_VAR ref V00 arg0 rcx REG rcx
IN0038: mov rcx, gword ptr [V00 rbp+10H]
GC regs: 00000000 {} => 00000002 {rcx}
/--* t43 ref
Generating: N166 (???,???) [000110] ------------ t110 = * PUTARG_REG ref REG rcx
GC regs: 00000002 {rcx} => 00000000 {}
GC regs: 00000000 {} => 00000002 {rcx}
Generating: N168 ( 3, 10) [000111] -c---------- t111 = CNS_INT(h) long 0x4200E0 ftn REG NA
/--* t111 long
Generating: N170 ( 5, 12) [000112] -c---------- t112 = * IND long REG NA
/--* t110 ref this in rcx
+--* t112 long control expr
Generating: N172 ( 17, 9) [000044] --CXG------- * CALL r2r_ind void System.Runtime.InteropServices.SafeHandle.DangerousRelease REG NA
GC regs: 00000002 {rcx} => 00000000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x003E CALL_INSTRUCTION (G_M25631_IG11,ins#5,ofs#18)
IN0039: call [System.Runtime.InteropServices.SafeHandle:DangerousRelease():this]
=============== Generating BB07 [043..044) (finret), preds={BB05,BB06} succs={BB04} flags=0x00000000.40030020: i label target LIR
BB07 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M25631_BB07:
G_M25631_IG11: ; offs=0002E4H, funclet=01, bbWeight=1
Label: IG12, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Added IP mapping: 0x0043 STACK_EMPTY (G_M25631_IG12,ins#0,ofs#0) label
Generating: N176 (???,???) [000077] ------------ IL_OFFSET void IL offset: 0x43 REG NA
Generating: N178 ( 0, 0) [000042] ------------ RETFILT void REG NA
IN003a: nop
Reserving funclet epilog IG for block BB07
G_M25631_IG12: ; offs=0002FCH, funclet=01, bbWeight=1
Added IP mapping: EPILOG STACK_EMPTY (G_M25631_IG13,ins#0,ofs#256) label
*************** After placeholder IG creation
G_M25631_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M25631_IG02: ; offs=000000H, size=007BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG03: ; offs=00007BH, size=0026H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG04: ; offs=0000A1H, size=002CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG05: ; offs=0000CDH, size=0008H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG06: ; offs=0000D5H, size=0001H, nogc, extend
G_M25631_IG07: ; offs=0000D6H, size=000BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG08: ; offs=0000E1H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG09: ; epilog placeholder, next placeholder=IG10 , BB09 [0008], epilog, extend <-- First placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M25631_IG10: ; func=01, funclet prolog placeholder, next placeholder=IG13 , BB05 [0002], funclet prolog
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M25631_IG11: ; offs=0002E4H, size=0018H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M25631_IG12: ; offs=0002FCH, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG13: ; funclet epilog placeholder, next placeholder=<END>, BB07 [0004], funclet epilog, extend <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Liveness not changing: 0000000000000000 {}
4 tmps used
# compCycleEstimate = 183, compSizeEstimate = 112 Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 1, 1 ) ref -> [rbp+0x10] class-hnd
; V01 arg1 [V01 ] ( 1, 1 ) long -> [rbp+0x18]
; V02 arg2 [V02 ] ( 1, 1 ) int -> [rbp+0x20]
; V03 arg3 [V03 ] ( 1, 1 ) byref -> [rbp+0x28]
; V04 arg4 [V04 ] ( 1, 1 ) long -> [rbp+0x30]
; V05 loc0 [V05 ] ( 1, 1 ) int -> [rbp-0x3C] must-init
; V06 loc1 [V06 ] ( 1, 1 ) int -> [rbp-0x40] must-init
; V07 loc2 [V07 ] ( 1, 1 ) long -> [rbp-0x48] must-init
; V08 loc3 [V08 ] ( 1, 1 ) bool -> [rbp-0x50] do-not-enreg[X] must-init addr-exposed ld-addr-op
; V09 loc4 [V09 ] ( 1, 1 ) long -> [rbp-0x58] must-init
; V10 loc5 [V10 ] ( 1, 1 ) byref -> [rbp-0x60] must-init pinned
; V11 OutArgs [V11 ] ( 1, 1 ) lclBlk (40) [rsp+0x00] "OutgoingArgSpace"
; V12 tmp1 [V12 ] ( 1, 1 ) long -> [rbp-0x68] "impSpillStackEnsure"
; V13 tmp2 [V13 ] ( 1, 1 ) int -> [rbp-0x6C] "impSpillStackEnsure"
; V14 tmp3 [V14 ] ( 1, 1 ) int -> [rbp-0x70] "Single return block return value"
; V15 PInvokeFrame [V15 ] ( 1, 1 ) blk (88) [rbp-0xF0] do-not-enreg[X] addr-exposed "Pinvoke FrameVar"
; V16 tmp5 [V16 ] ( 1, 1 ) long -> [rbp-0x78] "Cast away GC"
; V17 PSPSym [V17 ] ( 1, 1 ) long -> [rbp-0xF8] do-not-enreg[X] addr-exposed "PSPSym"
; TEMP_01 int -> [rbp-0x7C]
; TEMP_02 long -> [rbp-0x94]
; TEMP_03 long -> [rbp-0x8C]
; TEMP_04 long -> [rbp-0x84]
;
; Lcl frame size = 232
*************** Before prolog / epilog generation
G_M25631_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M25631_IG02: ; offs=000000H, size=007BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG03: ; offs=00007BH, size=0026H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG04: ; offs=0000A1H, size=002CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG05: ; offs=0000CDH, size=0008H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG06: ; offs=0000D5H, size=0001H, nogc, extend
G_M25631_IG07: ; offs=0000D6H, size=000BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG08: ; offs=0000E1H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG09: ; epilog placeholder, next placeholder=IG10 , BB09 [0008], epilog, extend <-- First placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M25631_IG10: ; func=01, funclet prolog placeholder, next placeholder=IG13 , BB05 [0002], funclet prolog
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M25631_IG11: ; offs=0002E4H, size=0018H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M25631_IG12: ; offs=0002FCH, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG13: ; funclet epilog placeholder, next placeholder=<END>, BB07 [0004], funclet epilog, extend <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M25631_IG01,ins#0,ofs#0) label
__prolog:
Found 12 lvMustInit int-sized stack slots, frame offsets 96 through 56
IN003b: push rbp
IN003c: push r15
IN003d: push r14
IN003e: push r13
IN003f: push r12
IN0040: push rdi
IN0041: push rsi
IN0042: push rbx
IN0043: sub rsp, 232
IN0044: lea rbp, [rsp+120H]
Notify VM instruction set (SSE42) must be supported.
IN0045: xorps xmm4, xmm4
IN0046: movaps xmmword ptr [rbp-60H], xmm4
IN0047: movaps xmmword ptr [rbp-50H], xmm4
IN0048: xor rax, rax
IN0049: mov qword ptr [rbp-40H], rax
IN004a: mov qword ptr [V17 rbp-F8H], rsp
*************** In genFnPrologCalleeRegArgs() for int regs
IN004b: mov gword ptr [V00 rbp+10H], rcx
IN004c: mov qword ptr [V01 rbp+18H], rdx
IN004d: mov dword ptr [V02 rbp+20H], r8d
IN004e: mov bword ptr [V03 rbp+28H], r9
*************** In genEnregisterIncomingStackArgs()
G_M25631_IG01: ; offs=000000H, funclet=00, bbWeight=1
Funclet prolog / epilog info
Function InitialSP-to-FP delta: 288
SP delta: 56
PSP slot Initial SP offset: 40
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN004f: lea rsp, [rbp-38H]
IN0050: pop rbx
IN0051: pop rsi
IN0052: pop rdi
IN0053: pop r12
IN0054: pop r13
IN0055: pop r14
IN0056: pop r15
IN0057: pop rbp
IN0058: ret
G_M25631_IG09: ; offs=0000E4H, funclet=00, bbWeight=1
*************** In genFuncletProlog()
IN0059: push rbp
IN005a: push r15
IN005b: push r14
IN005c: push r13
IN005d: push r12
IN005e: push rdi
IN005f: push rsi
IN0060: push rbx
IN0061: sub rsp, 56
IN0062: mov rbp, qword ptr [rcx+40]
Marking regs modified: [rbp] ([rax rcx rdx rbx rsi rdi r8-r15] => [rax rcx rdx rbx rbp rsi rdi r8-r15])
IN0063: mov qword ptr [rsp+28H], rbp
IN0064: lea rbp, [rbp+120H]
Removing modified regs: [rbp] ([rax rcx rdx rbx rbp rsi rdi r8-r15] => [rax rcx rdx rbx rsi rdi r8-r15])
G_M25631_IG10: ; offs=0001E4H, funclet=01, bbWeight=1
*************** In genFuncletEpilog()
IN0065: add rsp, 56
IN0066: pop rbx
IN0067: pop rsi
IN0068: pop rdi
IN0069: pop r12
IN006a: pop r13
IN006b: pop r14
IN006c: pop r15
IN006d: pop rbp
IN006e: ret
G_M25631_IG13: ; offs=0002FDH, funclet=01, bbWeight=1
0 prologs, 1 epilogs, 1 funclet prologs, 1 funclet epilogs
*************** After prolog / epilog generation
G_M25631_IG01: ; func=00, offs=000000H, size=0043H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M25631_IG02: ; offs=000043H, size=007BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG03: ; offs=0000BEH, size=0026H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG04: ; offs=0000E4H, size=002CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG05: ; offs=000110H, size=0008H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG06: ; offs=000118H, size=0001H, nogc, extend
G_M25631_IG07: ; offs=000119H, size=000BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG08: ; offs=000124H, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG09: ; offs=000127H, size=0011H, epilog, nogc, extend
G_M25631_IG10: ; func=01, offs=000138H, size=0020H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, funclet prolog, nogc
G_M25631_IG11: ; offs=000158H, size=0018H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M25631_IG12: ; offs=000170H, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M25631_IG13: ; offs=000171H, size=0011H, funclet epilog, nogc, extend
*************** In emitJumpDistBind()
Binding: IN002c: 000000 jmp L_M25631_BB03
Binding L_M25631_BB03to G_M25631_IG05
Estimate of fwd jump [F0ADD4AC/044]: 010B -> 0110 = 0003
Shrinking jump [F0ADD4AC/044]
Adjusted offset of BB05 from 0110 to 010D
Binding: IN002e: 000000 call L_M25631_BB05
Binding L_M25631_BB05to G_M25631_IG10
Adjusted offset of BB06 from 0118 to 0115
Adjusted offset of BB07 from 0119 to 0116
Binding: IN0032: 000000 jmp L_M25631_BB09
Binding L_M25631_BB09to G_M25631_IG08
Estimate of fwd jump [F0ADD81C/050]: 011C -> 0121 = 0003
Shrinking jump [F0ADD81C/050]
Adjusted offset of BB08 from 0124 to 011E
Adjusted offset of BB09 from 0127 to 0121
Adjusted offset of BB10 from 0138 to 0132
Adjusted offset of BB11 from 0158 to 0152
Binding: IN0037: 000000 je L_M25631_BB07
Binding L_M25631_BB07to G_M25631_IG12
Estimate of fwd jump [F0ADDDC4/055]: 015A -> 016A = 000E
Shrinking jump [F0ADDDC4/055]
Adjusted offset of BB12 from 0170 to 0166
Adjusted offset of BB13 from 0171 to 0167
Total shrinkage = 10, min extra jump size = 4294967295
*************** Finishing PHASE Generate code
*************** Starting PHASE Emit code
Hot code size = 0x178 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x18)
reserveUnwindInfo(isFunclet=TRUE, isColdCode=FALSE, unwindSize=0x16)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M25631_IG01: ; func=00, offs=000000H, size=0043H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN003b: 000000 55 push rbp
IN003c: 000001 4157 push r15
IN003d: 000003 4156 push r14
IN003e: 000005 4155 push r13
IN003f: 000007 4154 push r12
IN0040: 000009 57 push rdi
IN0041: 00000A 56 push rsi
IN0042: 00000B 53 push rbx
IN0043: 00000C 4881ECE8000000 sub rsp, 232
IN0044: 000013 488DAC2420010000 lea rbp, [rsp+120H]
IN0045: 00001B 0F57E4 xorps xmm4, xmm4
IN0046: 00001E 0F2965A0 movaps xmmword ptr [rbp-60H], xmm4
IN0047: 000022 0F2965B0 movaps xmmword ptr [rbp-50H], xmm4
IN0048: 000026 33C0 xor rax, rax
IN0049: 000028 488945C0 mov qword ptr [rbp-40H], rax
IN004a: 00002C 4889A508FFFFFF mov qword ptr [rbp-F8H], rsp
IN004b: 000033 48894D10 mov gword ptr [rbp+10H], rcx
IN004c: 000037 48895518 mov qword ptr [rbp+18H], rdx
IN004d: 00003B 44894520 mov dword ptr [rbp+20H], r8d
IN004e: 00003F 4C894D28 mov bword ptr [rbp+28H], r9
;; bbWeight=1 PerfScore 21.33
G_M25631_IG02: ; func=00, offs=000043H, size=007BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 000043 488D55B0 lea rdx, [rbp-50H]
gcrReg +[rcx]
IN0002: 000047 488B4D10 mov rcx, gword ptr [rbp+10H]
New gcrReg live regs=00000000 {}
gcrReg -[rcx]
[F0ADF0A8] ptr arg pop 0
IN0003: 00004B FF1500000000 call [System.Runtime.InteropServices.SafeHandle:DangerousAddRef(byref):this]
gcrReg +[rcx]
IN0004: 000051 488B4D10 mov rcx, gword ptr [rbp+10H]
New gcrReg live regs=00000000 {}
gcrReg -[rcx]
[F0ADF158] ptr arg pop 0
IN0005: 000055 FF1500000000 call [System.Runtime.InteropServices.SafeHandle:DangerousGetHandle():long:this]
IN0006: 00005B 48894598 mov qword ptr [rbp-68H], rax
IN0007: 00005F 488B4598 mov rax, qword ptr [rbp-68H]
IN0008: 000063 488945B8 mov qword ptr [rbp-48H], rax
byrReg +[rax]
IN0009: 000067 488B4528 mov rax, bword ptr [rbp+28H]
IN000a: 00006B 488945A0 mov bword ptr [rbp-60H], rax
IN000b: 00006F 488B45A0 mov rax, bword ptr [rbp-60H]
IN000c: 000073 48894588 mov qword ptr [rbp-78H], rax
byrReg -[rax]
IN000d: 000077 488B4588 mov rax, qword ptr [rbp-78H]
IN000e: 00007B 488945A8 mov qword ptr [rbp-58H], rax
[F0ADF208] ptr arg pop 0
IN000f: 00007F FF1500000000 call [System.StubHelpers.StubHelpers:ClearLastError()]
IN0010: 000085 488B4D30 mov rcx, qword ptr [rbp+30H]
IN0011: 000089 48894C2420 mov qword ptr [rsp+20H], rcx
IN0012: 00008E 488B4DB8 mov rcx, qword ptr [rbp-48H]
IN0013: 000092 48898D7CFFFFFF mov qword ptr [rbp-84H], rcx
IN0014: 000099 488B5518 mov rdx, qword ptr [rbp+18H]
IN0015: 00009D 48899574FFFFFF mov qword ptr [rbp-8CH], rdx
IN0016: 0000A4 448B4520 mov r8d, dword ptr [rbp+20H]
IN0017: 0000A8 44894584 mov dword ptr [rbp-7CH], r8d
IN0018: 0000AC 4C8B4DA8 mov r9, qword ptr [rbp-58H]
IN0019: 0000B0 4C898D6CFFFFFF mov qword ptr [rbp-94H], r9
IN001a: 0000B7 488D8D10FFFFFF lea rcx, [rbp-F0H]
;; bbWeight=1 PerfScore 31.00
G_M25631_IG03: ; func=00, offs=0000BEH, size=0026H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
[F0ADF258] ptr arg pop 0
IN001b: 0000BE FF1500000000 call [CORINFO_HELP_JIT_PINVOKE_BEGIN]
IN001c: 0000C4 488B0500000000 mov rax, qword ptr [(reloc 0x4200f0)]
IN001d: 0000CB 488B8D7CFFFFFF mov rcx, qword ptr [rbp-84H]
IN001e: 0000D2 488B9574FFFFFF mov rdx, qword ptr [rbp-8CH]
IN001f: 0000D9 448B4584 mov r8d, dword ptr [rbp-7CH]
IN0020: 0000DD 4C8B8D6CFFFFFF mov r9, qword ptr [rbp-94H]
;; bbWeight=1 PerfScore 9.00
G_M25631_IG04: ; func=00, offs=0000E4H, size=0029H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
[F0ADF278] ptr arg pop 0
IN0021: 0000E4 FF10 call qword ptr [rax]Kernel32:ReadFile(long,long,int,long,long):int
IN0022: 0000E6 8BF0 mov esi, eax
IN0023: 0000E8 488D8D10FFFFFF lea rcx, [rbp-F0H]
[F0ADF2F0] ptr arg pop 0
IN0024: 0000EF FF1500000000 call [CORINFO_HELP_JIT_PINVOKE_END]
IN0025: 0000F5 897594 mov dword ptr [rbp-6CH], esi
[F0ADF310] ptr arg pop 0
IN0026: 0000F8 FF1500000000 call [System.StubHelpers.StubHelpers:SetLastError()]
IN0027: 0000FE 8B4D94 mov ecx, dword ptr [rbp-6CH]
IN0028: 000101 894DC0 mov dword ptr [rbp-40H], ecx
IN0029: 000104 8B4DC0 mov ecx, dword ptr [rbp-40H]
IN002a: 000107 894DC4 mov dword ptr [rbp-3CH], ecx
IN002b: 00010A 90 nop
IN002c: 00010B EB00 jmp SHORT G_M25631_IG05
;; bbWeight=1 PerfScore 17.00
G_M25631_IG05: ; func=00, offs=00010DH, size=0008H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN002d: 00010D 488BCC mov rcx, rsp
IN002e: 000110 E81D000000 call G_M25631_IG10
;; bbWeight=1 PerfScore 1.25
G_M25631_IG06: ; func=00, offs=000115H, size=0001H, nogc, extend
IN002f: 000115 90 nop
;; bbWeight=1 PerfScore 0.25
G_M25631_IG07: ; func=00, offs=000116H, size=0008H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0030: 000116 8B45C4 mov eax, dword ptr [rbp-3CH]
IN0031: 000119 894590 mov dword ptr [rbp-70H], eax
IN0032: 00011C EB00 jmp SHORT G_M25631_IG08
;; bbWeight=1 PerfScore 4.00
G_M25631_IG08: ; func=00, offs=00011EH, size=0003H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0033: 00011E 8B4590 mov eax, dword ptr [rbp-70H]
;; bbWeight=1 PerfScore 1.00
G_M25631_IG09: ; func=00, offs=000121H, size=0011H, epilog, nogc, extend
IN004f: 000121 488D65C8 lea rsp, [rbp-38H]
IN0050: 000125 5B pop rbx
IN0051: 000126 5E pop rsi
IN0052: 000127 5F pop rdi
IN0053: 000128 415C pop r12
IN0054: 00012A 415D pop r13
IN0055: 00012C 415E pop r14
IN0056: 00012E 415F pop r15
IN0057: 000130 5D pop rbp
IN0058: 000131 C3 ret
;; bbWeight=1 PerfScore 5.50
G_M25631_IG10: ; func=01, offs=000132H, size=0020H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, funclet prolog, nogc
IN0059: 000132 55 push rbp
IN005a: 000133 4157 push r15
IN005b: 000135 4156 push r14
IN005c: 000137 4155 push r13
IN005d: 000139 4154 push r12
IN005e: 00013B 57 push rdi
IN005f: 00013C 56 push rsi
IN0060: 00013D 53 push rbx
IN0061: 00013E 4883EC38 sub rsp, 56
IN0062: 000142 488B6928 mov rbp, qword ptr [rcx+40]
IN0063: 000146 48896C2428 mov qword ptr [rsp+28H], rbp
IN0064: 00014B 488DAD20010000 lea rbp, [rbp+120H]
;; bbWeight=1 PerfScore 11.75
G_M25631_IG11: ; func=01, offs=000152H, size=0014H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, isz
IN0034: 000152 8B4DB0 mov ecx, dword ptr [rbp-50H]
IN0035: 000155 0FB6C9 movzx rcx, cl
IN0036: 000158 85C9 test ecx, ecx
IN0037: 00015A 740A je SHORT G_M25631_IG12
gcrReg +[rcx]
IN0038: 00015C 488B4D10 mov rcx, gword ptr [rbp+10H]
New gcrReg live regs=00000000 {}
gcrReg -[rcx]
[F0ADF3B8] ptr arg pop 0
IN0039: 000160 FF1500000000 call [System.Runtime.InteropServices.SafeHandle:DangerousRelease():this]
;; bbWeight=1 PerfScore 6.50
G_M25631_IG12: ; func=01, offs=000166H, size=0001H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN003a: 000166 90 nop
;; bbWeight=1 PerfScore 0.25
G_M25631_IG13: ; func=01, offs=000167H, size=0011H, funclet epilog, nogc, extend
IN0065: 000167 4883C438 add rsp, 56
IN0066: 00016B 5B pop rbx
IN0067: 00016C 5E pop rsi
IN0068: 00016D 5F pop rdi
IN0069: 00016E 415C pop r12
IN006a: 000170 415D pop r13
IN006b: 000172 415E pop r14
IN006c: 000174 415F pop r15
IN006d: 000176 5D pop rbp
IN006e: 000177 C3 ret
;; bbWeight=1 PerfScore 5.25Allocated method code size = 376 , actual size = 376
; Total bytes of code 376, prolog size 67, PerfScore 151.68, (MethodHash=c1f39be0) for method Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int
; ============================================================
*************** After end code gen, before unwindEmit()
G_M25631_IG01: ; func=00, offs=000000H, size=0043H, bbWeight=1 PerfScore 21.33, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN003b: 000000 push rbp
IN003c: 000001 push r15
IN003d: 000003 push r14
IN003e: 000005 push r13
IN003f: 000007 push r12
IN0040: 000009 push rdi
IN0041: 00000A push rsi
IN0042: 00000B push rbx
IN0043: 00000C sub rsp, 232
IN0044: 000013 lea rbp, [rsp+120H]
IN0045: 00001B xorps xmm4, xmm4
IN0046: 00001E movaps xmmword ptr [rbp-60H], xmm4
IN0047: 000022 movaps xmmword ptr [rbp-50H], xmm4
IN0048: 000026 xor rax, rax
IN0049: 000028 mov qword ptr [rbp-40H], rax
IN004a: 00002C mov qword ptr [V17 rbp-F8H], rsp
IN004b: 000033 mov gword ptr [V00 rbp+10H], rcx
IN004c: 000037 mov qword ptr [V01 rbp+18H], rdx
IN004d: 00003B mov dword ptr [V02 rbp+20H], r8d
IN004e: 00003F mov bword ptr [V03 rbp+28H], r9
G_M25631_IG02: ; offs=000043H, size=007BH, bbWeight=1 PerfScore 31.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 000043 lea rdx, [V08 rbp-50H]
IN0002: 000047 mov rcx, gword ptr [V00 rbp+10H]
IN0003: 00004B call [System.Runtime.InteropServices.SafeHandle:DangerousAddRef(byref):this]
IN0004: 000051 mov rcx, gword ptr [V00 rbp+10H]
IN0005: 000055 call [System.Runtime.InteropServices.SafeHandle:DangerousGetHandle():long:this]
IN0006: 00005B mov qword ptr [V12 rbp-68H], rax
IN0007: 00005F mov rax, qword ptr [V12 rbp-68H]
IN0008: 000063 mov qword ptr [V07 rbp-48H], rax
IN0009: 000067 mov rax, bword ptr [V03 rbp+28H]
IN000a: 00006B mov bword ptr [V10 rbp-60H], rax
IN000b: 00006F mov rax, bword ptr [V10 rbp-60H]
IN000c: 000073 mov qword ptr [V16 rbp-78H], rax
IN000d: 000077 mov rax, qword ptr [V16 rbp-78H]
IN000e: 00007B mov qword ptr [V09 rbp-58H], rax
IN000f: 00007F call [System.StubHelpers.StubHelpers:ClearLastError()]
IN0010: 000085 mov rcx, qword ptr [V04 rbp+30H]
IN0011: 000089 mov qword ptr [V11+0x20 rsp+20H], rcx
IN0012: 00008E mov rcx, qword ptr [V07 rbp-48H]
IN0013: 000092 mov qword ptr [TEMP_04 rbp-84H], rcx
IN0014: 000099 mov rdx, qword ptr [V01 rbp+18H]
IN0015: 00009D mov qword ptr [TEMP_03 rbp-8CH], rdx
IN0016: 0000A4 mov r8d, dword ptr [V02 rbp+20H]
IN0017: 0000A8 mov dword ptr [TEMP_01 rbp-7CH], r8d
IN0018: 0000AC mov r9, qword ptr [V09 rbp-58H]
IN0019: 0000B0 mov qword ptr [TEMP_02 rbp-94H], r9
IN001a: 0000B7 lea rcx, [V15 rbp-F0H]
G_M25631_IG03: ; offs=0000BEH, size=0026H, bbWeight=1 PerfScore 9.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN001b: 0000BE call [CORINFO_HELP_JIT_PINVOKE_BEGIN]
IN001c: 0000C4 mov rax, qword ptr [(reloc 0x4200f0)]
IN001d: 0000CB mov rcx, qword ptr [TEMP_04 rbp-84H]
IN001e: 0000D2 mov rdx, qword ptr [TEMP_03 rbp-8CH]
IN001f: 0000D9 mov r8d, dword ptr [TEMP_01 rbp-7CH]
IN0020: 0000DD mov r9, qword ptr [TEMP_02 rbp-94H]
G_M25631_IG04: ; offs=0000E4H, size=0029H, bbWeight=1 PerfScore 17.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0021: 0000E4 call qword ptr [rax]Kernel32:ReadFile(long,long,int,long,long):int
IN0022: 0000E6 mov esi, eax
IN0023: 0000E8 lea rcx, [V15 rbp-F0H]
IN0024: 0000EF call [CORINFO_HELP_JIT_PINVOKE_END]
IN0025: 0000F5 mov dword ptr [V13 rbp-6CH], esi
IN0026: 0000F8 call [System.StubHelpers.StubHelpers:SetLastError()]
IN0027: 0000FE mov ecx, dword ptr [V13 rbp-6CH]
IN0028: 000101 mov dword ptr [V06 rbp-40H], ecx
IN0029: 000104 mov ecx, dword ptr [V06 rbp-40H]
IN002a: 000107 mov dword ptr [V05 rbp-3CH], ecx
IN002b: 00010A nop
IN002c: 00010B jmp SHORT G_M25631_IG05
G_M25631_IG05: ; offs=00010DH, size=0008H, bbWeight=1 PerfScore 1.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN002d: 00010D mov rcx, rsp
IN002e: 000110 call G_M25631_IG10
G_M25631_IG06: ; offs=000115H, size=0001H, bbWeight=1 PerfScore 0.25, nogc, extend
IN002f: 000115 nop
G_M25631_IG07: ; offs=000116H, size=0008H, bbWeight=1 PerfScore 4.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0030: 000116 mov eax, dword ptr [V05 rbp-3CH]
IN0031: 000119 mov dword ptr [V14 rbp-70H], eax
IN0032: 00011C jmp SHORT G_M25631_IG08
G_M25631_IG08: ; offs=00011EH, size=0003H, bbWeight=1 PerfScore 1.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0033: 00011E mov eax, dword ptr [V14 rbp-70H]
G_M25631_IG09: ; offs=000121H, size=0011H, bbWeight=1 PerfScore 5.50, epilog, nogc, extend
IN004f: 000121 lea rsp, [rbp-38H]
IN0050: 000125 pop rbx
IN0051: 000126 pop rsi
IN0052: 000127 pop rdi
IN0053: 000128 pop r12
IN0054: 00012A pop r13
IN0055: 00012C pop r14
IN0056: 00012E pop r15
IN0057: 000130 pop rbp
IN0058: 000131 ret
G_M25631_IG10: ; func=01, offs=000132H, size=0020H, bbWeight=1 PerfScore 11.75, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, funclet prolog, nogc
IN0059: 000132 push rbp
IN005a: 000133 push r15
IN005b: 000135 push r14
IN005c: 000137 push r13
IN005d: 000139 push r12
IN005e: 00013B push rdi
IN005f: 00013C push rsi
IN0060: 00013D push rbx
IN0061: 00013E sub rsp, 56
IN0062: 000142 mov rbp, qword ptr [rcx+40]
IN0063: 000146 mov qword ptr [rsp+28H], rbp
IN0064: 00014B lea rbp, [rbp+120H]
G_M25631_IG11: ; offs=000152H, size=0014H, bbWeight=1 PerfScore 6.50, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, isz
IN0034: 000152 mov ecx, dword ptr [V08 rbp-50H]
IN0035: 000155 movzx rcx, cl
IN0036: 000158 test ecx, ecx
IN0037: 00015A je SHORT G_M25631_IG12
IN0038: 00015C mov rcx, gword ptr [V00 rbp+10H]
IN0039: 000160 call [System.Runtime.InteropServices.SafeHandle:DangerousRelease():this]
G_M25631_IG12: ; offs=000166H, size=0001H, bbWeight=1 PerfScore 0.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN003a: 000166 nop
G_M25631_IG13: ; offs=000167H, size=0011H, bbWeight=1 PerfScore 5.25, funclet epilog, nogc, extend
IN0065: 000167 add rsp, 56
IN0066: 00016B pop rbx
IN0067: 00016C pop rsi
IN0068: 00016D pop rdi
IN0069: 00016E pop r12
IN006a: 000170 pop r13
IN006b: 000172 pop r14
IN006c: 000174 pop r15
IN006d: 000176 pop rbp
IN006e: 000177 ret
*************** Finishing PHASE Emit code
*************** Starting PHASE Emit GC+EH tables
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x000132 (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x13
CountOfUnwindCodes: 10
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x13 UnwindOp: UWOP_ALLOC_LARGE (1) OpInfo: 0 - Scaled small
Size: 29 * 8 = 232 = 0x000E8
CodeOffset: 0x0C UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3)
CodeOffset: 0x0B UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rsi (6)
CodeOffset: 0x0A UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rdi (7)
CodeOffset: 0x09 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r12 (12)
CodeOffset: 0x07 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r13 (13)
CodeOffset: 0x05 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14)
CodeOffset: 0x03 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r15 (15)
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
allocUnwindInfo(pHotCode=0x0000017980AC6BE8, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x132, unwindSize=0x18, pUnwindBlock=0x00000179F0AB71D8, funKind=0 (main function))
Unwind Info:
>> Start offset : 0x000132 (not in unwind data)
>> End offset : 0x000178 (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x10
CountOfUnwindCodes: 9
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x10 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 6 * 8 + 8 = 56 = 0x38
CodeOffset: 0x0C UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3)
CodeOffset: 0x0B UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rsi (6)
CodeOffset: 0x0A UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rdi (7)
CodeOffset: 0x09 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r12 (12)
CodeOffset: 0x07 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r13 (13)
CodeOffset: 0x05 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14)
CodeOffset: 0x03 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r15 (15)
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
allocUnwindInfo(pHotCode=0x0000017980AC6BE8, pColdCode=0x0000000000000000, startOffset=0x132, endOffset=0x178, unwindSize=0x16, pUnwindBlock=0x00000179F0AB7412, funKind=1 (handler))
*************** In genIPmappingGen()
IP mapping count : 27
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000043 ( STACK_EMPTY )
IL offs 0x0003 : 0x0000004B ( CALL_INSTRUCTION )
IL offs 0x0008 : 0x00000051 ( STACK_EMPTY )
IL offs 0x0009 : 0x00000055 ( CALL_INSTRUCTION )
IL offs 0x000E : 0x0000005F
IL offs 0x000F : 0x00000067 ( STACK_EMPTY )
IL offs 0x0012 : 0x0000006F ( STACK_EMPTY )
IL offs 0x0017 : 0x0000007F ( STACK_EMPTY )
IL offs 0x0020 : 0x0000007F ( CALL_INSTRUCTION )
IL offs 0x0025 : 0x00000085
IL offs 0x0025 : 0x000000E4 ( CALL_INSTRUCTION )
IL offs 0x002A : 0x000000F8
IL offs 0x002A : 0x000000F8 ( CALL_INSTRUCTION )
IL offs 0x002F : 0x000000FE
IL offs 0x0030 : 0x00000104 ( STACK_EMPTY )
IL offs 0x0032 : 0x0000010A ( STACK_EMPTY )
IL offs NO_MAP : 0x0000010D ( STACK_EMPTY )
IL offs 0x0044 : 0x00000116 ( STACK_EMPTY )
IL offs NO_MAP : 0x0000011E ( STACK_EMPTY )
IL offs EPILOG : 0x00000121 ( STACK_EMPTY )
IL offs PROLOG : 0x00000132 ( STACK_EMPTY )
IL offs 0x0037 : 0x00000152 ( STACK_EMPTY )
IL offs 0x003D : 0x0000015C ( STACK_EMPTY )
IL offs 0x003E : 0x00000160 ( CALL_INSTRUCTION )
IL offs 0x0043 : 0x00000166 ( STACK_EMPTY )
IL offs EPILOG : 0x00000167 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 16
*************** Variable debug info
16 live ranges
0( UNKNOWN) : From 00000000h to 00000043h, in rcx
1( UNKNOWN) : From 00000000h to 00000043h, in rdx
2( UNKNOWN) : From 00000000h to 00000043h, in r8
3( UNKNOWN) : From 00000000h to 00000043h, in r9
4( UNKNOWN) : From 00000000h to 00000043h, in rsp[40] (1 slot)
0( UNKNOWN) : From 00000043h to 0000011Ch, in rbp[16] (1 slot)
1( UNKNOWN) : From 00000043h to 0000011Ch, in rbp[24] (1 slot)
2( UNKNOWN) : From 00000043h to 0000011Ch, in rbp[32] (1 slot)
3( UNKNOWN) : From 00000043h to 0000011Ch, in rbp[40] (1 slot)
4( UNKNOWN) : From 00000043h to 0000011Ch, in rbp[48] (1 slot)
5( UNKNOWN) : From 00000043h to 0000011Ch, in rbp[-60] (1 slot)
6( UNKNOWN) : From 00000043h to 0000011Ch, in rbp[-64] (1 slot)
7( UNKNOWN) : From 00000043h to 0000011Ch, in rbp[-72] (1 slot)
8( UNKNOWN) : From 00000043h to 0000011Ch, in rbp[-80] (1 slot)
9( UNKNOWN) : From 00000043h to 0000011Ch, in rbp[-88] (1 slot)
10( UNKNOWN) : From 00000043h to 0000011Ch, in rbp[-96] (1 slot)
*************** EH table for Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int
1 EH table entries, 0 duplicate clauses, 1 cloned finallys, 2 total EH entries reported to VM
setEHcount(cEH=2)
EH#0: try [0043..010D) handled by [0132..0178) (finally)
EH#1: try [010D..010D) handled by [010D..0116) (finally) cloned finally
*************** In gcInfoBlockHdrSave()
Set code length to 376.
Set ReturnKind to Scalar.
Set stack base register to rbp.
Set PSPSym stack slot to 40.
Set WantsReportOnlyLeaf.
Set Outgoing stack arg area size to 40.
Stack slot id for offset 16 (0x10) (frame) (untracked) = 0.
Stack slot id for offset 40 (0x28) (frame) (byref, untracked) = 1.
Stack slot id for offset -96 (0xffffffa0) (frame) (byref, pinned, untracked) = 2.
Register slot id for reg rcx = 3.
Register slot id for reg rax (byref) = 4.
Set state of slot 3 at instr offset 0x4b to Live.
Set state of slot 3 at instr offset 0x51 to Dead.
Set state of slot 3 at instr offset 0x55 to Live.
Set state of slot 3 at instr offset 0x5b to Dead.
Set state of slot 4 at instr offset 0x6b to Live.
Set state of slot 4 at instr offset 0x7b to Dead.
Set state of slot 3 at instr offset 0x160 to Live.
Set state of slot 3 at instr offset 0x166 to Dead.
Defining interruptible range: [0x43, 0x115).
Defining interruptible range: [0x116, 0x121).
Defining interruptible range: [0x152, 0x167).
*************** Finishing PHASE Emit GC+EH tables
Method code size: 376
Allocations for Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int (MethodHash=c1f39be0)
count: 1053, size: 79744, max = 2640
allocateMemory: 131072, nraUsed: 82472
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 0 | 0.00%
ASTNode | 14736 | 18.48%
InstDesc | 10304 | 12.92%
ImpStack | 384 | 0.48%
BasicBlock | 4416 | 5.54%
fgArgInfo | 616 | 0.77%
fgArgInfoPtrArr | 184 | 0.23%
FlowList | 288 | 0.36%
TreeStatementList | 0 | 0.00%
SiScope | 1064 | 1.33%
DominatorMemory | 0 | 0.00%
LSRA | 3160 | 3.96%
LSRA_Interval | 2720 | 3.41%
LSRA_RefPosition | 10752 | 13.48%
Reachability | 0 | 0.00%
SSA | 0 | 0.00%
ValueNumber | 0 | 0.00%
LvaTable | 2640 | 3.31%
UnwindInfo | 32 | 0.04%
hashBv | 360 | 0.45%
bitset | 152 | 0.19%
FixedBitVect | 16 | 0.02%
Generic | 1660 | 2.08%
LocalAddressVisitor | 0 | 0.00%
FieldSeqStore | 0 | 0.00%
ZeroOffsetFieldMap | 40 | 0.05%
ArrayInfoMap | 0 | 0.00%
MemoryPhiArg | 0 | 0.00%
CSE | 0 | 0.00%
GC | 3004 | 3.77%
CorSig | 624 | 0.78%
Inlining | 216 | 0.27%
ArrayStack | 0 | 0.00%
DebugInfo | 1304 | 1.64%
DebugOnly | 19253 | 24.14%
Codegen | 1176 | 1.47%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 643 | 0.81%
RangeCheck | 0 | 0.00%
CopyProp | 0 | 0.00%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 0 | 0.00%
ClassLayout | 0 | 0.00%
TailMergeThrows | 0 | 0.00%
EarlyProp | 0 | 0.00%
****** DONE compiling Kernel32:ReadFile([S.P.CoreLib]System.Runtime.InteropServices.SafeHandle,long,int,byref,long):int
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\framework-r2r.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Dia2Lib.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\dotnet-Microsoft.XmlSerializer.Generator.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\ILCompiler.Reflection.ReadyToRun.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.CSharp.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Diagnostics.FastSerialization.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Diagnostics.NETCore.Client.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Diagnostics.Tools.RuntimeClient.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Diagnostics.Tracing.TraceEvent.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Caching.Abstractions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Caching.Memory.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Configuration.Abstractions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Configuration.Binder.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Configuration.CommandLine.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Configuration.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Configuration.EnvironmentVariables.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Configuration.FileExtensions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Configuration.Ini.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Configuration.Json.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Configuration.UserSecrets.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Configuration.Xml.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.DependencyInjection.Abstractions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.DependencyInjection.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.DependencyModel.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.FileProviders.Abstractions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.FileProviders.Composite.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.FileProviders.Physical.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.FileSystemGlobbing.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Hosting.Abstractions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Hosting.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Http.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Logging.Abstractions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Logging.Configuration.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Logging.Console.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Logging.Debug.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Logging.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Logging.EventLog.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Logging.EventSource.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Logging.TraceSource.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Options.ConfigurationExtensions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Options.DataAnnotations.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Options.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Extensions.Primitives.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.VisualBasic.Core.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.VisualBasic.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Win32.Primitives.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Win32.Registry.AccessControl.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Win32.Registry.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Microsoft.Win32.SystemEvents.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\mscorlib.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\netstandard.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Newtonsoft.Json.Bson.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\Newtonsoft.Json.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\OSExtensions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\runincontext.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.AppContext.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Buffers.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.CodeDom.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Collections.Concurrent.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Collections.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Collections.Immutable.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Collections.NonGeneric.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Collections.Specialized.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ComponentModel.Annotations.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ComponentModel.Composition.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ComponentModel.Composition.Registration.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ComponentModel.DataAnnotations.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ComponentModel.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ComponentModel.EventBasedAsync.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ComponentModel.Primitives.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ComponentModel.TypeConverter.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Composition.AttributedModel.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Composition.Convention.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Composition.Hosting.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Composition.Runtime.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Composition.TypedParts.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Configuration.ConfigurationManager.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Configuration.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Console.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Core.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Data.Common.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Data.DataSetExtensions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Data.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Data.Odbc.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Data.OleDb.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Diagnostics.Contracts.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Diagnostics.Debug.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Diagnostics.DiagnosticSource.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Diagnostics.EventLog.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Diagnostics.FileVersionInfo.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Diagnostics.PerformanceCounter.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Diagnostics.Process.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Diagnostics.StackTrace.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Diagnostics.TextWriterTraceListener.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Diagnostics.Tools.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Diagnostics.TraceSource.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Diagnostics.Tracing.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.DirectoryServices.AccountManagement.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.DirectoryServices.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.DirectoryServices.Protocols.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Drawing.Common.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Drawing.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Drawing.Primitives.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Dynamic.Runtime.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Globalization.Calendars.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Globalization.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Globalization.Extensions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.Compression.Brotli.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.Compression.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.Compression.FileSystem.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.Compression.ZipFile.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.FileSystem.AccessControl.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.FileSystem.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.FileSystem.DriveInfo.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.FileSystem.Primitives.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.FileSystem.Watcher.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.IsolatedStorage.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.MemoryMappedFiles.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.Packaging.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.Pipelines.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.Pipes.AccessControl.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.Pipes.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.Ports.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.IO.UnmanagedMemoryStream.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Linq.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Linq.Expressions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Linq.Parallel.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Linq.Queryable.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Management.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Memory.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.Http.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.Http.Json.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.Http.WinHttpHandler.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.HttpListener.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.Mail.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.NameResolution.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.NetworkInformation.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.Ping.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.Primitives.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.Requests.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.Security.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.ServicePoint.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.Sockets.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.WebClient.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.WebHeaderCollection.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.WebProxy.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.WebSockets.Client.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.WebSockets.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Net.WebSockets.WebSocketProtocol.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Numerics.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Numerics.Tensors.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Numerics.Vectors.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ObjectModel.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Private.CoreLib.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Private.DataContractSerialization.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Private.Uri.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Private.Xml.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Private.Xml.Linq.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Reflection.Context.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Reflection.DispatchProxy.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Reflection.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Reflection.Emit.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Reflection.Emit.ILGeneration.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Reflection.Emit.Lightweight.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Reflection.Extensions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Reflection.Metadata.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Reflection.MetadataLoadContext.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Reflection.Primitives.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Reflection.TypeExtensions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Resources.Extensions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Resources.Reader.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Resources.ResourceManager.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Resources.Writer.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.Caching.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.CompilerServices.Unsafe.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.CompilerServices.VisualC.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.Extensions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.Handles.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.InteropServices.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.InteropServices.RuntimeInformation.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.InteropServices.WindowsRuntime.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.Intrinsics.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.Intrinsics.Experimental.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.Loader.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.Numerics.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.Serialization.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.Serialization.Formatters.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.Serialization.Json.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.Serialization.Primitives.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.Serialization.Xml.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Runtime.WindowsRuntime.UI.Xaml.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.AccessControl.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Claims.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Cryptography.Algorithms.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Cryptography.Cng.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Cryptography.Csp.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Cryptography.Encoding.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Cryptography.OpenSsl.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Cryptography.Pkcs.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Cryptography.Primitives.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Cryptography.ProtectedData.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Cryptography.X509Certificates.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Cryptography.Xml.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Permissions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Principal.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.Principal.Windows.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Security.SecureString.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ServiceModel.Syndication.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ServiceModel.Web.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ServiceProcess.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ServiceProcess.ServiceController.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Text.Encoding.CodePages.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Text.Encoding.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Text.Encoding.Extensions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Text.Encodings.Web.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Text.Json.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Text.RegularExpressions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Threading.AccessControl.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Threading.Channels.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Threading.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Threading.Overlapped.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Threading.Tasks.Dataflow.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Threading.Tasks.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Threading.Tasks.Extensions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Threading.Tasks.Parallel.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Threading.Thread.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Threading.ThreadPool.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Threading.Timer.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Transactions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Transactions.Local.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Utf8String.Experimental.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.ValueTuple.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Web.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Web.HttpUtility.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Windows.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Windows.Extensions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Xml.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Xml.Linq.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Xml.ReaderWriter.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Xml.Serialization.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Xml.XDocument.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Xml.XmlDocument.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Xml.XmlSerializer.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Xml.XPath.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\System.Xml.XPath.XDocument.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\TraceReloggerLib.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\WindowsBase.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\xunit.abstractions.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\xunit.assert.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\xunit.console.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\xunit.core.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\xunit.execution.dotnet.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\xunit.performance.core.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\xunit.performance.execution.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\xunit.performance.metrics.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\xunit.runner.reporters.netcoreapp10.dll
Emitting R2R PE file: D:\git\runtime5\artifacts\tests\coreclr\Windows_NT.x64.Checked\Tests\Core_Root\CPAOT-chk.out\xunit.runner.utility.netcoreapp10.dll
>>>>
1 / 1 (100%, 0 failed): succeeded in 23052 msecs
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