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trylek/indexer-slow.log

Created September 1, 2020 23:38
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Perf regression caused by fix for expanding generic dictionaries - slow version
Raw
indexer-slow.log
****** START compiling System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this (MethodHash=992e2e63)
Generating code for Windows x64
OPTIONS: Tier-0 compilation (set COMPlus_TieredCompilation=0 to disable)
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
IL to import:
IL_0000 12 00 ldloca.s 0x0
IL_0002 fe 15 3a 00 00 1b initobj 0x1B00003A
IL_0008 12 01 ldloca.s 0x1
IL_000a 02 ldarg.0
IL_000b 7b 59 08 00 0a ldfld 0xA000859
IL_0010 28 a9 05 00 0a call 0xA0005A9
IL_0015 16 ldc.i4.0
IL_0016 0c stloc.2
IL_0017 2b 12 br.s 18 (IL_002b)
IL_0019 12 01 ldloca.s 0x1
IL_001b 08 ldloc.2
IL_001c 28 0b 08 00 0a call 0xA00080B
IL_0021 fe 15 3a 00 00 1b initobj 0x1B00003A
IL_0027 08 ldloc.2
IL_0028 17 ldc.i4.1
IL_0029 58 add
IL_002a 0c stloc.2
IL_002b 08 ldloc.2
IL_002c 12 01 ldloca.s 0x1
IL_002e 28 70 08 00 0a call 0xA000870
IL_0033 32 e4 blt.s -28 (IL_0019)
IL_0035 06 ldloc.0
IL_0036 2a ret
lvaSetClass: setting class for V00 to (00007FF9F0F4EC18) System.Collections.IndexerSet`1[__Canon]
'this' passed in register rcx
lvaSetClass: setting class for V01 to (00007FF9F09E0FD8) System.__Canon
lvaGrabTemp returning 4 (V04 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 ref class-hnd
; V02 loc1 struct <System.Span`1[__Canon], 16>
; V03 loc2 int
; V04 OutArgs lclBlk <na> "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 4
VarNum LVNum Name Beg End
0: 00h 00h V00 this 000h 037h
1: 01h 01h V01 loc0 000h 037h
2: 02h 02h V02 loc1 000h 037h
3: 03h 03h V03 loc2 000h 037h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this
Jump targets:
IL_0019
IL_002b
New Basic Block BB01 [0000] created.
BB01 [000..019)
New Basic Block BB02 [0001] created.
BB02 [019..02B)
New Basic Block BB03 [0002] created.
BB03 [02B..035)
New Basic Block BB04 [0003] created.
BB04 [035..037)
****
**** JIT Tier0 jit request switching to Tier1 because of loop
****
Notify VM instruction set (AVX) must be supported.
****** START compiling System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this (MethodHash=992e2e63)
Generating code for Windows x64
OPTIONS: Tier-0 compilation, switched to FullOpts
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
IL Code Size,Instr 55, 0, Basic Block count 4, Local Variable Num,Ref count 5, 0 for method System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this
OPTIONS: opts.MinOpts() == false
Basic block list for 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..019)-> BB03 (always)
BB02 [0001] 1 1 [019..02B) bwd bwd-target
BB03 [0002] 2 1 [02B..035)-> BB02 ( cond ) bwd
BB04 [0003] 1 1 [035..037) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Pre-import
*************** Finishing PHASE Pre-import
*************** Starting PHASE Importation
*************** In impImport() for System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
[ 0] 0 (0x000) ldloca.s 0
[ 1] 2 (0x002) initobj 1B00003A
STMT00000 (IL 0x000... ???)
[000004] IA---------- * ASG struct (init)
[000003] -------N---- +--* BLK struct<8>
[000001] ------------ | \--* ADDR byref
[000000] -------N---- | \--* LCL_VAR ref V01 loc0
[000002] ------------ \--* CNS_INT int 0
[ 0] 8 (0x008) ldloca.s 1
[ 1] 10 (0x00a) ldarg.0
[ 2] 11 (0x00b) ldfld 0A000859
[ 2] 16 (0x010) call 0A0005A9
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
lvaGrabTemp returning 5 (V05 tmp1) called for impRuntimeLookup slot.
lvaGrabTemp returning 6 (V06 tmp2) called for impAppendStmt.
STMT00002 (IL 0x008... ???)
[000015] -A-XG------- * ASG ref
[000014] D------N---- +--* LCL_VAR ref V06 tmp2
[000008] ---XG------- \--* FIELD ref _array
[000007] ------------ \--* LCL_VAR ref V00 this
Marked V06 as a single def temp
Querying runtime about current class of field System.Collections.IndexerSet`1[System.__Canon]._array (declared as System.__Canon[])
Field's current class not available
lvaSetClass: setting class for V06 to (00007FF9F109F808) System.__Canon[]
STMT00001 (IL 0x008... ???)
[000013] -A-X-------- * ASG long
[000012] D------N---- +--* LCL_VAR long V05 tmp1
[000011] #--X-------- \--* IND long
[000010] !----------- \--* LCL_VAR ref V00 this
lvaGrabTemp returning 7 (V07 tmp3) called for impRuntimeLookup indirectOffset.
STMT00003 (IL ???... ???)
[000024] -A---------- * ASG long
[000023] D------N---- +--* LCL_VAR long V07 tmp3
[000022] n----------- \--* IND long
[000021] #----------- \--* IND long
[000020] ------------ \--* ADD long
[000018] ------------ +--* LCL_VAR long V05 tmp1
[000019] ------------ \--* CNS_INT long 56
lvaGrabTemp returning 8 (V08 tmp4) called for spilling Runtime Lookup tree.
STMT00004 (IL ???... ???)
[000044] -AC-G------- * ASG long
[000043] D------N---- +--* LCL_VAR long V08 tmp4
[000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000033] ------------ arg0 +--* EQ int
[000029] n----------- | +--* IND long
[000028] ------------ | | \--* ADD long
[000025] ------------ | | +--* LCL_VAR long V07 tmp3
[000027] ------------ | | \--* CNS_INT long 96
[000032] ------------ | \--* CNS_INT long 0
[000042] ------------ arg1 +--* LE int
[000040] ------------ | +--* IND long
[000039] ------------ | | \--* ADD long
[000026] ------------ | | +--* LCL_VAR long V07 tmp3
[000038] ------------ | | \--* CNS_INT long 8
[000041] ------------ | \--* CNS_INT long 96
[000034] n----------- arg2 +--* IND long
[000035] ------------ | \--* ADD long
[000036] ------------ | +--* LCL_VAR long V07 tmp3
[000037] ------------ | \--* CNS_INT long 96
[000017] ------------ arg3 +--* LCL_VAR long V05 tmp1
[000030] ------------ arg4 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
STMT00005 (IL ???... ???)
[000009] I-C-G------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor (exactContextHnd=0x00007FF9F129E501)
[000006] ------------ this in rcx +--* ADDR byref
[000005] -------N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000046] ------------ arg1 +--* RUNTIMELOOKUP long 0x7ff9f129e500 class
[000045] ------------ | \--* LCL_VAR long V08 tmp4
[000016] ------------ arg2 \--* LCL_VAR ref V06 tmp2
[ 0] 21 (0x015) ldc.i4.0 0
[ 1] 22 (0x016) stloc.2
STMT00006 (IL 0x015... ???)
[000049] -A---------- * ASG int
[000048] D------N---- +--* LCL_VAR int V03 loc2
[000047] ------------ \--* CNS_INT int 0
[ 0] 23 (0x017) br.s
impImportBlockPending for BB03
Importing BB03 (PC=043) of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
[ 0] 43 (0x02b) ldloc.2
[ 1] 44 (0x02c) ldloca.s 1
[ 2] 46 (0x02e) call 0A000870
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
lvaGrabTemp returning 9 (V09 tmp5) called for impRuntimeLookup slot.
STMT00007 (IL 0x02B... ???)
[000057] -A-X-------- * ASG long
[000056] D------N---- +--* LCL_VAR long V09 tmp5
[000055] #--X-------- \--* IND long
[000054] !----------- \--* LCL_VAR ref V00 this
lvaGrabTemp returning 10 (V10 tmp6) called for impRuntimeLookup indirectOffset.
STMT00008 (IL ???... ???)
[000065] -A---------- * ASG long
[000064] D------N---- +--* LCL_VAR long V10 tmp6
[000063] n----------- \--* IND long
[000062] #----------- \--* IND long
[000061] ------------ \--* ADD long
[000059] ------------ +--* LCL_VAR long V09 tmp5
[000060] ------------ \--* CNS_INT long 56
lvaGrabTemp returning 11 (V11 tmp7) called for spilling Runtime Lookup tree.
STMT00009 (IL ???... ???)
[000085] -AC-G------- * ASG long
[000084] D------N---- +--* LCL_VAR long V11 tmp7
[000072] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000074] ------------ arg0 +--* EQ int
[000070] n----------- | +--* IND long
[000069] ------------ | | \--* ADD long
[000066] ------------ | | +--* LCL_VAR long V10 tmp6
[000068] ------------ | | \--* CNS_INT long 96
[000073] ------------ | \--* CNS_INT long 0
[000083] ------------ arg1 +--* LE int
[000081] ------------ | +--* IND long
[000080] ------------ | | \--* ADD long
[000067] ------------ | | +--* LCL_VAR long V10 tmp6
[000079] ------------ | | \--* CNS_INT long 8
[000082] ------------ | \--* CNS_INT long 96
[000075] n----------- arg2 +--* IND long
[000076] ------------ | \--* ADD long
[000077] ------------ | +--* LCL_VAR long V10 tmp6
[000078] ------------ | \--* CNS_INT long 96
[000058] ------------ arg3 +--* LCL_VAR long V09 tmp5
[000071] ------------ arg4 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
STMT00010 (IL ???... ???)
[000053] I-C-G------- * CALL int System.Span`1[__Canon][System.__Canon].get_Length (exactContextHnd=0x00007FF9F129E501)
[000052] ------------ this in rcx +--* ADDR byref
[000051] -------N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000087] ------------ arg1 \--* RUNTIMELOOKUP long 0x7ff9f129e500 class
[000086] ------------ \--* LCL_VAR long V11 tmp7
[ 2] 51 (0x033) blt.s
STMT00011 (IL ???... ???)
[000090] --C--------- * JTRUE void
[000089] --C--------- \--* LT int
[000050] ------------ +--* LCL_VAR int V03 loc2
[000088] --C--------- \--* RET_EXPR int (inl return from call [000053])
impImportBlockPending for BB04
impImportBlockPending for BB02
Importing BB02 (PC=025) of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
[ 0] 25 (0x019) ldloca.s 1
[ 1] 27 (0x01b) ldloc.2
[ 2] 28 (0x01c) call 0A00080B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0
impIntrinsic: Expanding Span<T>.get_Item, T=System.__Canon, sizeof(T)=8
with ptr-to-span
[000092] ------------ * ADDR byref
[000091] -------N---- \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
and index
[000093] ------------ * LCL_VAR int V03 loc2
[ 1] 33 (0x021) initobj 1B00003A
STMT00012 (IL 0x019... ???)
[000107] IA-X-------- * ASG struct (init)
[000106] ---X---N---- +--* BLK struct<8>
[000104] ---X-------- | \--* COMMA byref
[000098] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000093] ------------ | | +--* LCL_VAR int V03 loc2
[000097] ------------ | | \--* FIELD int _length
[000092] ------------ | | \--* ADDR byref
[000091] -------N---- | | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000103] ------------ | \--* ADD byref
[000102] ------------ | +--* FIELD byref _pointer
[000096] ------------ | | \--* ADDR byref
[000095] -------N---- | | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000101] ------------ | \--* MUL long
[000099] ------------ | +--* CAST long <- int
[000094] ------------ | | \--* LCL_VAR int V03 loc2
[000100] ------------ | \--* CNS_INT int 8
[000105] ------------ \--* CNS_INT int 0
[ 0] 39 (0x027) ldloc.2
[ 1] 40 (0x028) ldc.i4.1 1
[ 2] 41 (0x029) add
[ 1] 42 (0x02a) stloc.2
STMT00013 (IL 0x027... ???)
[000112] -A---------- * ASG int
[000111] D------N---- +--* LCL_VAR int V03 loc2
[000110] ------------ \--* ADD int
[000108] ------------ +--* LCL_VAR int V03 loc2
[000109] ------------ \--* CNS_INT int 1
impImportBlockPending for BB03
Importing BB04 (PC=053) of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
[ 0] 53 (0x035) ldloc.0
[ 1] 54 (0x036) ret
STMT00014 (IL 0x035... ???)
[000114] ------------ * RETURN ref
[000113] ------------ \--* LCL_VAR ref V01 loc0
*************** Finishing PHASE Importation
Trees after Importation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..019)-> BB03 (always) i
BB02 [0001] 1 1 [019..02B) i bwd bwd-target
BB03 [0002] 2 1 [02B..035)-> BB02 ( cond ) i bwd
BB04 [0003] 1 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..019) -> BB03 (always), preds={} succs={BB03}
***** BB01
STMT00000 (IL 0x000...0x003)
[000004] IA---------- * ASG struct (init)
[000003] -------N---- +--* BLK struct<8>
[000001] ------------ | \--* ADDR byref
[000000] -------N---- | \--* LCL_VAR ref V01 loc0
[000002] ------------ \--* CNS_INT int 0
***** BB01
STMT00002 (IL 0x008...0x016)
[000015] -A-XG------- * ASG ref
[000014] D------N---- +--* LCL_VAR ref V06 tmp2
[000008] ---XG------- \--* FIELD ref _array
[000007] ------------ \--* LCL_VAR ref V00 this
***** BB01
STMT00001 (IL 0x008... ???)
[000013] -A-X-------- * ASG long
[000012] D------N---- +--* LCL_VAR long V05 tmp1
[000011] #--X-------- \--* IND long
[000010] !----------- \--* LCL_VAR ref V00 this
***** BB01
STMT00003 (IL ???... ???)
[000024] -A---------- * ASG long
[000023] D------N---- +--* LCL_VAR long V07 tmp3
[000022] n----------- \--* IND long
[000021] #----------- \--* IND long
[000020] ------------ \--* ADD long
[000018] ------------ +--* LCL_VAR long V05 tmp1
[000019] ------------ \--* CNS_INT long 56
***** BB01
STMT00004 (IL ???... ???)
[000044] -AC-G------- * ASG long
[000043] D------N---- +--* LCL_VAR long V08 tmp4
[000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000033] ------------ arg0 +--* EQ int
[000029] n----------- | +--* IND long
[000028] ------------ | | \--* ADD long
[000025] ------------ | | +--* LCL_VAR long V07 tmp3
[000027] ------------ | | \--* CNS_INT long 96
[000032] ------------ | \--* CNS_INT long 0
[000042] ------------ arg1 +--* LE int
[000040] ------------ | +--* IND long
[000039] ------------ | | \--* ADD long
[000026] ------------ | | +--* LCL_VAR long V07 tmp3
[000038] ------------ | | \--* CNS_INT long 8
[000041] ------------ | \--* CNS_INT long 96
[000034] n----------- arg2 +--* IND long
[000035] ------------ | \--* ADD long
[000036] ------------ | +--* LCL_VAR long V07 tmp3
[000037] ------------ | \--* CNS_INT long 96
[000017] ------------ arg3 +--* LCL_VAR long V05 tmp1
[000030] ------------ arg4 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
***** BB01
STMT00005 (IL ???... ???)
[000009] I-C-G------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor (exactContextHnd=0x00007FF9F129E501)
[000006] ------------ this in rcx +--* ADDR byref
[000005] -------N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000046] ------------ arg1 +--* RUNTIMELOOKUP long 0x7ff9f129e500 class
[000045] ------------ | \--* LCL_VAR long V08 tmp4
[000016] ------------ arg2 \--* LCL_VAR ref V06 tmp2
***** BB01
STMT00006 (IL 0x015... ???)
[000049] -A---------- * ASG int
[000048] D------N---- +--* LCL_VAR int V03 loc2
[000047] ------------ \--* CNS_INT int 0
------------ BB02 [019..02B), preds={} succs={BB03}
***** BB02
STMT00012 (IL 0x019...0x022)
[000107] IA-X-------- * ASG struct (init)
[000106] ---X---N---- +--* BLK struct<8>
[000104] ---X-------- | \--* COMMA byref
[000098] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000093] ------------ | | +--* LCL_VAR int V03 loc2
[000097] ------------ | | \--* FIELD int _length
[000092] ------------ | | \--* ADDR byref
[000091] -------N---- | | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000103] ------------ | \--* ADD byref
[000102] ------------ | +--* FIELD byref _pointer
[000096] ------------ | | \--* ADDR byref
[000095] -------N---- | | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000101] ------------ | \--* MUL long
[000099] ------------ | +--* CAST long <- int
[000094] ------------ | | \--* LCL_VAR int V03 loc2
[000100] ------------ | \--* CNS_INT int 8
[000105] ------------ \--* CNS_INT int 0
***** BB02
STMT00013 (IL 0x027...0x02A)
[000112] -A---------- * ASG int
[000111] D------N---- +--* LCL_VAR int V03 loc2
[000110] ------------ \--* ADD int
[000108] ------------ +--* LCL_VAR int V03 loc2
[000109] ------------ \--* CNS_INT int 1
------------ BB03 [02B..035) -> BB02 (cond), preds={} succs={BB04,BB02}
***** BB03
STMT00007 (IL 0x02B...0x033)
[000057] -A-X-------- * ASG long
[000056] D------N---- +--* LCL_VAR long V09 tmp5
[000055] #--X-------- \--* IND long
[000054] !----------- \--* LCL_VAR ref V00 this
***** BB03
STMT00008 (IL ???... ???)
[000065] -A---------- * ASG long
[000064] D------N---- +--* LCL_VAR long V10 tmp6
[000063] n----------- \--* IND long
[000062] #----------- \--* IND long
[000061] ------------ \--* ADD long
[000059] ------------ +--* LCL_VAR long V09 tmp5
[000060] ------------ \--* CNS_INT long 56
***** BB03
STMT00009 (IL ???... ???)
[000085] -AC-G------- * ASG long
[000084] D------N---- +--* LCL_VAR long V11 tmp7
[000072] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000074] ------------ arg0 +--* EQ int
[000070] n----------- | +--* IND long
[000069] ------------ | | \--* ADD long
[000066] ------------ | | +--* LCL_VAR long V10 tmp6
[000068] ------------ | | \--* CNS_INT long 96
[000073] ------------ | \--* CNS_INT long 0
[000083] ------------ arg1 +--* LE int
[000081] ------------ | +--* IND long
[000080] ------------ | | \--* ADD long
[000067] ------------ | | +--* LCL_VAR long V10 tmp6
[000079] ------------ | | \--* CNS_INT long 8
[000082] ------------ | \--* CNS_INT long 96
[000075] n----------- arg2 +--* IND long
[000076] ------------ | \--* ADD long
[000077] ------------ | +--* LCL_VAR long V10 tmp6
[000078] ------------ | \--* CNS_INT long 96
[000058] ------------ arg3 +--* LCL_VAR long V09 tmp5
[000071] ------------ arg4 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
***** BB03
STMT00010 (IL ???... ???)
[000053] I-C-G------- * CALL int System.Span`1[__Canon][System.__Canon].get_Length (exactContextHnd=0x00007FF9F129E501)
[000052] ------------ this in rcx +--* ADDR byref
[000051] -------N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000087] ------------ arg1 \--* RUNTIMELOOKUP long 0x7ff9f129e500 class
[000086] ------------ \--* LCL_VAR long V11 tmp7
***** BB03
STMT00011 (IL ???... ???)
[000090] --C--------- * JTRUE void
[000089] --C--------- \--* LT int
[000050] ------------ +--* LCL_VAR int V03 loc2
[000088] --C--------- \--* RET_EXPR int (inl return from call [000053])
------------ BB04 [035..037) (return), preds={} succs={}
***** BB04
STMT00014 (IL 0x035...0x036)
[000114] ------------ * RETURN ref
[000113] ------------ \--* LCL_VAR ref V01 loc0
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Indirect call transform
*** ExpRuntimeLookup: transformingSTMT00004
New Basic Block BB05 [0004] created.
BB03 previous predecessor was BB01, now is BB05
New Basic Block BB06 [0005] created.
New Basic Block BB07 [0006] created.
New Basic Block BB08 [0007] created.
New Basic Block BB09 [0008] created.
Removing statement STMT00004 (IL ???... ???)
[000044] -AC-G------- * ASG long
[000043] D------N---- +--* LCL_VAR long V08 tmp4
[000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000017] ------------ arg0 +--* LCL_VAR long V05 tmp1
[000030] ------------ arg1 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
in BB01 as useless:
*** ExpRuntimeLookup: transformingSTMT00009
New Basic Block BB10 [0009] created.
BB04 previous predecessor was BB03, now is BB10
BB02 previous predecessor was BB03, now is BB10
New Basic Block BB11 [0010] created.
New Basic Block BB12 [0011] created.
New Basic Block BB13 [0012] created.
New Basic Block BB14 [0013] created.
Removing statement STMT00009 (IL ???... ???)
[000085] -AC-G------- * ASG long
[000084] D------N---- +--* LCL_VAR long V11 tmp7
[000072] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000058] ------------ arg0 +--* LCL_VAR long V09 tmp5
[000071] ------------ arg1 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
in BB03 as useless:
-- 2 calls transformed
*************** Finishing PHASE Indirect call transform
Trees after Indirect call transform
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015) i
BB06 [0005] 0 1 [???..???)-> BB09 ( cond ) i
BB07 [0006] 0 0.80 [???..???)-> BB09 ( cond ) i
BB08 [0007] 0 0.80 [???..???)-> BB05 (always) i
BB09 [0008] 0 0.20 [???..???) i
BB05 [0004] 1 1 [015..019)-> BB03 (always) i label target
BB02 [0001] 1 1 [019..02B) i bwd bwd-target
BB03 [0002] 2 1 [02B..???) i bwd
BB11 [0010] 0 1 [???..???)-> BB14 ( cond ) i
BB12 [0011] 0 0.80 [???..???)-> BB14 ( cond ) i
BB13 [0012] 0 0.80 [???..???)-> BB10 (always) i
BB14 [0013] 0 0.20 [???..???) i
BB10 [0009] 1 1 [???..035)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015), preds={} succs={BB06}
***** BB01
STMT00000 (IL 0x000...0x003)
[000004] IA---------- * ASG struct (init)
[000003] -------N---- +--* BLK struct<8>
[000001] ------------ | \--* ADDR byref
[000000] -------N---- | \--* LCL_VAR ref V01 loc0
[000002] ------------ \--* CNS_INT int 0
***** BB01
STMT00002 (IL 0x008...0x016)
[000015] -A-XG------- * ASG ref
[000014] D------N---- +--* LCL_VAR ref V06 tmp2
[000008] ---XG------- \--* FIELD ref _array
[000007] ------------ \--* LCL_VAR ref V00 this
***** BB01
STMT00001 (IL 0x008... ???)
[000013] -A-X-------- * ASG long
[000012] D------N---- +--* LCL_VAR long V05 tmp1
[000011] #--X-------- \--* IND long
[000010] !----------- \--* LCL_VAR ref V00 this
***** BB01
STMT00003 (IL ???... ???)
[000024] -A---------- * ASG long
[000023] D------N---- +--* LCL_VAR long V07 tmp3
[000022] n----------- \--* IND long
[000021] #----------- \--* IND long
[000020] ------------ \--* ADD long
[000018] ------------ +--* LCL_VAR long V05 tmp1
[000019] ------------ \--* CNS_INT long 56
------------ BB06 [???..???) -> BB09 (cond), preds={} succs={BB07,BB09}
***** BB06
STMT00015 (IL ???... ???)
[000115] ------------ * JTRUE void
[000042] ------------ \--* LE int
[000040] ------------ +--* IND long
[000039] ------------ | \--* ADD long
[000026] ------------ | +--* LCL_VAR long V07 tmp3
[000038] ------------ | \--* CNS_INT long 8
[000041] ------------ \--* CNS_INT long 96
------------ BB07 [???..???) -> BB09 (cond), preds={} succs={BB08,BB09}
***** BB07
STMT00016 (IL ???... ???)
[000116] ------------ * JTRUE void
[000033] ------------ \--* EQ int
[000029] n----------- +--* IND long
[000028] ------------ | \--* ADD long
[000025] ------------ | +--* LCL_VAR long V07 tmp3
[000027] ------------ | \--* CNS_INT long 96
[000032] ------------ \--* CNS_INT long 0
------------ BB08 [???..???) -> BB05 (always), preds={} succs={BB05}
***** BB08
STMT00017 (IL ???... ???)
[000118] -A---------- * ASG long
[000117] D------N---- +--* LCL_VAR long V08 tmp4
[000034] n----------- \--* IND long
[000035] ------------ \--* ADD long
[000036] ------------ +--* LCL_VAR long V07 tmp3
[000037] ------------ \--* CNS_INT long 96
------------ BB09 [???..???), preds={} succs={BB05}
***** BB09
STMT00018 (IL ???... ???)
[000120] -AC-G------- * ASG long
[000119] D------N---- +--* LCL_VAR long V08 tmp4
[000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000017] ------------ arg0 +--* LCL_VAR long V05 tmp1
[000030] ------------ arg1 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB05 [015..019) -> BB03 (always), preds={} succs={BB03}
***** BB05
STMT00005 (IL ???... ???)
[000009] I-C-G------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor (exactContextHnd=0x00007FF9F129E501)
[000006] ------------ this in rcx +--* ADDR byref
[000005] -------N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000046] ------------ arg1 +--* RUNTIMELOOKUP long 0x7ff9f129e500 class
[000045] ------------ | \--* LCL_VAR long V08 tmp4
[000016] ------------ arg2 \--* LCL_VAR ref V06 tmp2
***** BB05
STMT00006 (IL 0x015... ???)
[000049] -A---------- * ASG int
[000048] D------N---- +--* LCL_VAR int V03 loc2
[000047] ------------ \--* CNS_INT int 0
------------ BB02 [019..02B), preds={} succs={BB03}
***** BB02
STMT00012 (IL 0x019...0x022)
[000107] IA-X-------- * ASG struct (init)
[000106] ---X---N---- +--* BLK struct<8>
[000104] ---X-------- | \--* COMMA byref
[000098] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000093] ------------ | | +--* LCL_VAR int V03 loc2
[000097] ------------ | | \--* FIELD int _length
[000092] ------------ | | \--* ADDR byref
[000091] -------N---- | | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000103] ------------ | \--* ADD byref
[000102] ------------ | +--* FIELD byref _pointer
[000096] ------------ | | \--* ADDR byref
[000095] -------N---- | | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000101] ------------ | \--* MUL long
[000099] ------------ | +--* CAST long <- int
[000094] ------------ | | \--* LCL_VAR int V03 loc2
[000100] ------------ | \--* CNS_INT int 8
[000105] ------------ \--* CNS_INT int 0
***** BB02
STMT00013 (IL 0x027...0x02A)
[000112] -A---------- * ASG int
[000111] D------N---- +--* LCL_VAR int V03 loc2
[000110] ------------ \--* ADD int
[000108] ------------ +--* LCL_VAR int V03 loc2
[000109] ------------ \--* CNS_INT int 1
------------ BB03 [02B..???), preds={} succs={BB11}
***** BB03
STMT00007 (IL 0x02B...0x033)
[000057] -A-X-------- * ASG long
[000056] D------N---- +--* LCL_VAR long V09 tmp5
[000055] #--X-------- \--* IND long
[000054] !----------- \--* LCL_VAR ref V00 this
***** BB03
STMT00008 (IL ???... ???)
[000065] -A---------- * ASG long
[000064] D------N---- +--* LCL_VAR long V10 tmp6
[000063] n----------- \--* IND long
[000062] #----------- \--* IND long
[000061] ------------ \--* ADD long
[000059] ------------ +--* LCL_VAR long V09 tmp5
[000060] ------------ \--* CNS_INT long 56
------------ BB11 [???..???) -> BB14 (cond), preds={} succs={BB12,BB14}
***** BB11
STMT00019 (IL ???... ???)
[000121] ------------ * JTRUE void
[000083] ------------ \--* LE int
[000081] ------------ +--* IND long
[000080] ------------ | \--* ADD long
[000067] ------------ | +--* LCL_VAR long V10 tmp6
[000079] ------------ | \--* CNS_INT long 8
[000082] ------------ \--* CNS_INT long 96
------------ BB12 [???..???) -> BB14 (cond), preds={} succs={BB13,BB14}
***** BB12
STMT00020 (IL ???... ???)
[000122] ------------ * JTRUE void
[000074] ------------ \--* EQ int
[000070] n----------- +--* IND long
[000069] ------------ | \--* ADD long
[000066] ------------ | +--* LCL_VAR long V10 tmp6
[000068] ------------ | \--* CNS_INT long 96
[000073] ------------ \--* CNS_INT long 0
------------ BB13 [???..???) -> BB10 (always), preds={} succs={BB10}
***** BB13
STMT00021 (IL ???... ???)
[000124] -A---------- * ASG long
[000123] D------N---- +--* LCL_VAR long V11 tmp7
[000075] n----------- \--* IND long
[000076] ------------ \--* ADD long
[000077] ------------ +--* LCL_VAR long V10 tmp6
[000078] ------------ \--* CNS_INT long 96
------------ BB14 [???..???), preds={} succs={BB10}
***** BB14
STMT00022 (IL ???... ???)
[000126] -AC-G------- * ASG long
[000125] D------N---- +--* LCL_VAR long V11 tmp7
[000072] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000058] ------------ arg0 +--* LCL_VAR long V09 tmp5
[000071] ------------ arg1 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB10 [???..035) -> BB02 (cond), preds={} succs={BB04,BB02}
***** BB10
STMT00010 (IL ???... ???)
[000053] I-C-G------- * CALL int System.Span`1[__Canon][System.__Canon].get_Length (exactContextHnd=0x00007FF9F129E501)
[000052] ------------ this in rcx +--* ADDR byref
[000051] -------N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000087] ------------ arg1 \--* RUNTIMELOOKUP long 0x7ff9f129e500 class
[000086] ------------ \--* LCL_VAR long V11 tmp7
***** BB10
STMT00011 (IL ???... ???)
[000090] --C--------- * JTRUE void
[000089] --C--------- \--* LT int
[000050] ------------ +--* LCL_VAR int V03 loc2
[000088] --C--------- \--* RET_EXPR int (inl return from call [000053])
------------ BB04 [035..037) (return), preds={} succs={}
***** BB04
STMT00014 (IL 0x035...0x036)
[000114] ------------ * RETURN ref
[000113] ------------ \--* LCL_VAR ref V01 loc0
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Finishing PHASE Expand patchpoints [no changes]
*************** Starting PHASE Post-import
*************** Finishing PHASE Post-import
*************** Starting PHASE Morph - Init
New BlockSet epoch 1, # of blocks (including unused BB00): 15, bitset array size: 1 (short)
*************** In fgRemoveEmptyBlocks
*************** Finishing PHASE Morph - Init
*************** In fgDebugCheckBBlist
*************** Starting PHASE Morph - Inlining
Querying runtime about current class of field System.Collections.IndexerSet`1[System.__Canon]._array (declared as System.__Canon[])
Field's current class not available
Expanding INLINE_CANDIDATE in statement STMT00005 in BB05:
STMT00005 (IL ???... ???)
[000009] I-C-G------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor (exactContextHnd=0x00007FF9F129E501)
[000006] ------------ this in rcx +--* ADDR byref
[000005] -------N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000046] ------------ arg1 +--* RUNTIMELOOKUP long 0x7ff9f129e500 class
[000045] ------------ | \--* LCL_VAR long V08 tmp4
[000016] ------------ arg2 \--* LCL_VAR ref V06 tmp2
thisArg: is a constant is byref to a struct local
[000006] ------------ * ADDR byref
[000005] -------N---- \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
Argument #1: is a local var
[000016] ------------ * LCL_VAR ref V06 tmp2
INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this set to 0x00007FF9F129E501:
Invoking compiler for the inlinee method System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this :
IL to import:
IL_0000 03 ldarg.1
IL_0001 2d 08 brtrue.s 8 (IL_000b)
IL_0003 02 ldarg.0
IL_0004 fe 15 b2 00 00 1b initobj 0x1B0000B2
IL_000a 2a ret
IL_000b d0 15 00 00 1b ldtoken 0x1B000015
IL_0010 28 87 07 00 06 call 0x6000787
IL_0015 28 d0 07 00 06 call 0x60007D0
IL_001a 2d 1c brtrue.s 28 (IL_0038)
IL_001c 03 ldarg.1
IL_001d 6f 91 04 00 06 callvirt 0x6000491
IL_0022 d0 40 00 00 1b ldtoken 0x1B000040
IL_0027 28 87 07 00 06 call 0x6000787
IL_002c 28 89 07 00 06 call 0x6000789
IL_0031 2c 05 brfalse.s 5 (IL_0038)
IL_0033 28 d9 18 00 06 call 0x60018D9
IL_0038 02 ldarg.0
IL_0039 03 ldarg.1
IL_003a 28 1e 01 00 2b call 0x2B00011E
IL_003f 73 ad 01 00 0a newobj 0xA0001AD
IL_0044 7d b5 01 00 0a stfld 0xA0001B5
IL_0049 02 ldarg.0
IL_004a 03 ldarg.1
IL_004b 8e ldlen
IL_004c 69 conv.i4
IL_004d 7d b9 01 00 0a stfld 0xA0001B9
IL_0052 2a ret
INLINER impTokenLookupContextHandle for System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this is 0x00007FF9F129E501.
*************** In fgFindBasicBlocks() for System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this
Jump targets:
IL_000b
IL_0038
New Basic Block BB15 [0014] created.
BB15 [000..003)
New Basic Block BB16 [0015] created.
BB16 [003..00B)
New Basic Block BB17 [0016] created.
BB17 [00B..01C)
New Basic Block BB18 [0017] created.
BB18 [01C..033)
New Basic Block BB19 [0018] created.
BB19 [033..038)
New Basic Block BB20 [0019] created.
BB20 [038..053)
Basic block list for 'System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB15 [0014] 1 1 [000..003)-> BB17 ( cond )
BB16 [0015] 1 1 [003..00B) (return)
BB17 [0016] 1 1 [00B..01C)-> BB20 ( cond )
BB18 [0017] 1 1 [01C..033)-> BB20 ( cond )
BB19 [0018] 1 1 [033..038)
BB20 [0019] 3 1 [038..053) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Inline @[000009] Starting PHASE Pre-import
*************** Inline @[000009] Finishing PHASE Pre-import
*************** Inline @[000009] Starting PHASE Importation
*************** In impImport() for System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this
impImportBlockPending for BB15
Importing BB15 (PC=000) of 'System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this'
[ 0] 0 (0x000) ldarg.1
[ 1] 1 (0x001) brtrue.s
[000129] ------------ * JTRUE void
[000128] ------------ \--* NE int
[000016] ------------ +--* LCL_VAR ref V06 tmp2
[000127] ------------ \--* CNS_INT ref null
impImportBlockPending for BB16
impImportBlockPending for BB17
Importing BB17 (PC=011) of 'System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this'
[ 0] 11 (0x00b) ldtoken
** Note: inlinee IL was partially imported -- imported 3 of 83 bytes of method IL
*************** Inline @[000009] Finishing PHASE Importation
Trees after Importation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB15 [0014] 1 1 [000..003)-> BB17 ( cond ) i
BB16 [0015] 1 1 [003..00B) (return)
BB17 [0016] 1 1 [00B..01C)-> BB20 ( cond )
BB18 [0017] 1 1 [01C..033)-> BB20 ( cond )
BB19 [0018] 1 1 [033..038)
BB20 [0019] 3 1 [038..053) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB15 [000..003) -> BB17 (cond), preds={} succs={BB16,BB17}
***** BB15
[000129] ------------ * JTRUE void
[000128] ------------ \--* NE int
[000016] ------------ +--* LCL_VAR ref V06 tmp2
[000127] ------------ \--* CNS_INT ref null
------------ BB16 [003..00B) (return), preds={} succs={}
------------ BB17 [00B..01C) -> BB20 (cond), preds={} succs={BB18,BB20}
------------ BB18 [01C..033) -> BB20 (cond), preds={} succs={BB19,BB20}
------------ BB19 [033..038), preds={} succs={BB20}
------------ BB20 [038..053) (return), preds={} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** Inline @[000009] Starting PHASE Indirect call transform
-- no candidates to transform
*************** Inline @[000009] Finishing PHASE Indirect call transform [no changes]
*************** Inline @[000009] Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Inline @[000009] Finishing PHASE Expand patchpoints [no changes]
*************** Inline @[000009] Starting PHASE Post-import
*************** Inline @[000009] Finishing PHASE Post-import
INLINER: during 'fgInline' result 'failed this call site' reason 'runtime dictionary lookup' for 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this' calling 'System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this'
INLINER: during 'fgInline' result 'failed this call site' reason 'runtime dictionary lookup'
Expanding INLINE_CANDIDATE in statement STMT00010 in BB10:
STMT00010 (IL ???... ???)
[000053] I-C-G------- * CALL int System.Span`1[__Canon][System.__Canon].get_Length (exactContextHnd=0x00007FF9F129E501)
[000052] ------------ this in rcx +--* ADDR byref
[000051] -------N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000087] ------------ arg1 \--* RUNTIMELOOKUP long 0x7ff9f129e500 class
[000086] ------------ \--* LCL_VAR long V11 tmp7
thisArg: is a constant is byref to a struct local
[000052] ------------ * ADDR byref
[000051] -------N---- \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
INLINER: inlineInfo.tokenLookupContextHandle for System.Span`1[__Canon][System.__Canon]:get_Length():int:this set to 0x00007FF9F129E501:
Invoking compiler for the inlinee method System.Span`1[__Canon][System.__Canon]:get_Length():int:this :
IL to import:
IL_0000 02 ldarg.0
IL_0001 7b b9 01 00 0a ldfld 0xA0001B9
IL_0006 2a ret
INLINER impTokenLookupContextHandle for System.Span`1[__Canon][System.__Canon]:get_Length():int:this is 0x00007FF9F129E501.
*************** In fgFindBasicBlocks() for System.Span`1[__Canon][System.__Canon]:get_Length():int:this
Jump targets:
none
New Basic Block BB21 [0020] created.
BB21 [000..007)
Basic block list for 'System.Span`1[__Canon][System.__Canon]:get_Length():int:this'
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB21 [0020] 1 1 [000..007) (return)
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Inline @[000053] Starting PHASE Pre-import
*************** Inline @[000053] Finishing PHASE Pre-import
*************** Inline @[000053] Starting PHASE Importation
*************** In impImport() for System.Span`1[__Canon][System.__Canon]:get_Length():int:this
impImportBlockPending for BB21
Importing BB21 (PC=000) of 'System.Span`1[__Canon][System.__Canon]:get_Length():int:this'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) ldfld 0A0001B9
[ 1] 6 (0x006) ret
Inlinee Return expression (before normalization) =>
[000132] ------------ * FIELD int _length
[000130] ------------ \--* ADDR byref
[000131] -------N---- \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
Inlinee Return expression (after normalization) =>
[000132] ------------ * FIELD int _length
[000130] ------------ \--* ADDR byref
[000131] -------N---- \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL
*************** Inline @[000053] Finishing PHASE Importation
Trees after Importation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB21 [0020] 1 1 [000..007) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB21 [000..007) (return), preds={} succs={}
-------------------------------------------------------------------------------------------------------------------
*************** Inline @[000053] Starting PHASE Indirect call transform
-- no candidates to transform
*************** Inline @[000053] Finishing PHASE Indirect call transform [no changes]
*************** Inline @[000053] Starting PHASE Expand patchpoints
-- no patchpoints to transform
*************** Inline @[000053] Finishing PHASE Expand patchpoints [no changes]
*************** Inline @[000053] Starting PHASE Post-import
*************** In fgRemoveEmptyBlocks
*************** Inline @[000053] Finishing PHASE Post-import
----------- Statements (and blocks) added due to the inlining of call [000053] -----------
Arguments setup:
Inlinee method body:fgInlineAppendStatements: no gc ref inline locals.
Return expression for call at [000053] is
[000132] ------------ * FIELD int _length
[000130] ------------ \--* ADDR byref
[000131] -------N---- \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
Successfully inlined System.Span`1[__Canon][System.__Canon]:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size]
--------------------------------------------------------------------------------------------
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this' calling 'System.Span`1[__Canon][System.__Canon]:get_Length():int:this'
INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size'
Replacing the return expression placeholder [000088] with [000132]
[000088] --C--------- * RET_EXPR int (inl return from call [000132])
Inserting the inline return expression
[000132] ------------ * FIELD int _length
[000130] ------------ \--* ADDR byref
[000131] -------N---- \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
**************** Inline Tree
Inlines into 0600164E System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this
[0 IL=0016 TR=000009 060013F3] [FAILED: runtime dictionary lookup] System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this
[1 IL=0046 TR=000053 060013F8] [below ALWAYS_INLINE size] System.Span`1[__Canon][System.__Canon]:get_Length():int:this
Budget: initialTime=225, finalTime=211, initialBudget=2250, currentBudget=2250
Budget: initialSize=1385, finalSize=1385
*************** Finishing PHASE Morph - Inlining
Trees after Morph - Inlining
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015) i
BB06 [0005] 0 1 [???..???)-> BB09 ( cond ) i
BB07 [0006] 0 0.80 [???..???)-> BB09 ( cond ) i
BB08 [0007] 0 0.80 [???..???)-> BB05 (always) i
BB09 [0008] 0 0.20 [???..???) i
BB05 [0004] 1 1 [015..019)-> BB03 (always) i label target
BB02 [0001] 1 1 [019..02B) i bwd bwd-target
BB03 [0002] 2 1 [02B..???) i bwd
BB11 [0010] 0 1 [???..???)-> BB14 ( cond ) i
BB12 [0011] 0 0.80 [???..???)-> BB14 ( cond ) i
BB13 [0012] 0 0.80 [???..???)-> BB10 (always) i
BB14 [0013] 0 0.20 [???..???) i
BB10 [0009] 1 1 [???..035)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015), preds={} succs={BB06}
***** BB01
STMT00000 (IL 0x000...0x003)
[000004] IA---------- * ASG struct (init)
[000003] -------N---- +--* BLK struct<8>
[000001] ------------ | \--* ADDR byref
[000000] -------N---- | \--* LCL_VAR ref V01 loc0
[000002] ------------ \--* CNS_INT int 0
***** BB01
STMT00002 (IL 0x008...0x016)
[000015] -A-XG------- * ASG ref
[000014] D------N---- +--* LCL_VAR ref V06 tmp2
[000008] ---XG------- \--* FIELD ref _array
[000007] ------------ \--* LCL_VAR ref V00 this
***** BB01
STMT00001 (IL 0x008... ???)
[000013] -A-X-------- * ASG long
[000012] D------N---- +--* LCL_VAR long V05 tmp1
[000011] #--X-------- \--* IND long
[000010] !----------- \--* LCL_VAR ref V00 this
***** BB01
STMT00003 (IL ???... ???)
[000024] -A---------- * ASG long
[000023] D------N---- +--* LCL_VAR long V07 tmp3
[000022] n----------- \--* IND long
[000021] #----------- \--* IND long
[000020] ------------ \--* ADD long
[000018] ------------ +--* LCL_VAR long V05 tmp1
[000019] ------------ \--* CNS_INT long 56
------------ BB06 [???..???) -> BB09 (cond), preds={} succs={BB07,BB09}
***** BB06
STMT00015 (IL ???... ???)
[000115] ------------ * JTRUE void
[000042] ------------ \--* LE int
[000040] ------------ +--* IND long
[000039] ------------ | \--* ADD long
[000026] ------------ | +--* LCL_VAR long V07 tmp3
[000038] ------------ | \--* CNS_INT long 8
[000041] ------------ \--* CNS_INT long 96
------------ BB07 [???..???) -> BB09 (cond), preds={} succs={BB08,BB09}
***** BB07
STMT00016 (IL ???... ???)
[000116] ------------ * JTRUE void
[000033] ------------ \--* EQ int
[000029] n----------- +--* IND long
[000028] ------------ | \--* ADD long
[000025] ------------ | +--* LCL_VAR long V07 tmp3
[000027] ------------ | \--* CNS_INT long 96
[000032] ------------ \--* CNS_INT long 0
------------ BB08 [???..???) -> BB05 (always), preds={} succs={BB05}
***** BB08
STMT00017 (IL ???... ???)
[000118] -A---------- * ASG long
[000117] D------N---- +--* LCL_VAR long V08 tmp4
[000034] n----------- \--* IND long
[000035] ------------ \--* ADD long
[000036] ------------ +--* LCL_VAR long V07 tmp3
[000037] ------------ \--* CNS_INT long 96
------------ BB09 [???..???), preds={} succs={BB05}
***** BB09
STMT00018 (IL ???... ???)
[000120] -AC-G------- * ASG long
[000119] D------N---- +--* LCL_VAR long V08 tmp4
[000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000017] ------------ arg0 +--* LCL_VAR long V05 tmp1
[000030] ------------ arg1 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB05 [015..019) -> BB03 (always), preds={} succs={BB03}
***** BB05
STMT00005 (IL ???... ???)
[000009] --C-G------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor
[000006] ------------ this in rcx +--* ADDR byref
[000005] -------N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000046] ------------ arg1 +--* RUNTIMELOOKUP long 0x7ff9f129e500 class
[000045] ------------ | \--* LCL_VAR long V08 tmp4
[000016] ------------ arg2 \--* LCL_VAR ref V06 tmp2
***** BB05
STMT00006 (IL 0x015... ???)
[000049] -A---------- * ASG int
[000048] D------N---- +--* LCL_VAR int V03 loc2
[000047] ------------ \--* CNS_INT int 0
------------ BB02 [019..02B), preds={} succs={BB03}
***** BB02
STMT00012 (IL 0x019...0x022)
[000107] IA-X-------- * ASG struct (init)
[000106] ---X---N---- +--* BLK struct<8>
[000104] ---X-------- | \--* COMMA byref
[000098] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000093] ------------ | | +--* LCL_VAR int V03 loc2
[000097] ------------ | | \--* FIELD int _length
[000092] ------------ | | \--* ADDR byref
[000091] -------N---- | | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000103] ------------ | \--* ADD byref
[000102] ------------ | +--* FIELD byref _pointer
[000096] ------------ | | \--* ADDR byref
[000095] -------N---- | | \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
[000101] ------------ | \--* MUL long
[000099] ------------ | +--* CAST long <- int
[000094] ------------ | | \--* LCL_VAR int V03 loc2
[000100] ------------ | \--* CNS_INT int 8
[000105] ------------ \--* CNS_INT int 0
***** BB02
STMT00013 (IL 0x027...0x02A)
[000112] -A---------- * ASG int
[000111] D------N---- +--* LCL_VAR int V03 loc2
[000110] ------------ \--* ADD int
[000108] ------------ +--* LCL_VAR int V03 loc2
[000109] ------------ \--* CNS_INT int 1
------------ BB03 [02B..???), preds={} succs={BB11}
***** BB03
STMT00007 (IL 0x02B...0x033)
[000057] -A-X-------- * ASG long
[000056] D------N---- +--* LCL_VAR long V09 tmp5
[000055] #--X-------- \--* IND long
[000054] !----------- \--* LCL_VAR ref V00 this
***** BB03
STMT00008 (IL ???... ???)
[000065] -A---------- * ASG long
[000064] D------N---- +--* LCL_VAR long V10 tmp6
[000063] n----------- \--* IND long
[000062] #----------- \--* IND long
[000061] ------------ \--* ADD long
[000059] ------------ +--* LCL_VAR long V09 tmp5
[000060] ------------ \--* CNS_INT long 56
------------ BB11 [???..???) -> BB14 (cond), preds={} succs={BB12,BB14}
***** BB11
STMT00019 (IL ???... ???)
[000121] ------------ * JTRUE void
[000083] ------------ \--* LE int
[000081] ------------ +--* IND long
[000080] ------------ | \--* ADD long
[000067] ------------ | +--* LCL_VAR long V10 tmp6
[000079] ------------ | \--* CNS_INT long 8
[000082] ------------ \--* CNS_INT long 96
------------ BB12 [???..???) -> BB14 (cond), preds={} succs={BB13,BB14}
***** BB12
STMT00020 (IL ???... ???)
[000122] ------------ * JTRUE void
[000074] ------------ \--* EQ int
[000070] n----------- +--* IND long
[000069] ------------ | \--* ADD long
[000066] ------------ | +--* LCL_VAR long V10 tmp6
[000068] ------------ | \--* CNS_INT long 96
[000073] ------------ \--* CNS_INT long 0
------------ BB13 [???..???) -> BB10 (always), preds={} succs={BB10}
***** BB13
STMT00021 (IL ???... ???)
[000124] -A---------- * ASG long
[000123] D------N---- +--* LCL_VAR long V11 tmp7
[000075] n----------- \--* IND long
[000076] ------------ \--* ADD long
[000077] ------------ +--* LCL_VAR long V10 tmp6
[000078] ------------ \--* CNS_INT long 96
------------ BB14 [???..???), preds={} succs={BB10}
***** BB14
STMT00022 (IL ???... ???)
[000126] -AC-G------- * ASG long
[000125] D------N---- +--* LCL_VAR long V11 tmp7
[000072] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000058] ------------ arg0 +--* LCL_VAR long V09 tmp5
[000071] ------------ arg1 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB10 [???..035) -> BB02 (cond), preds={} succs={BB04,BB02}
***** BB10
STMT00011 (IL ???... ???)
[000090] --C--------- * JTRUE void
[000089] --C--------- \--* LT int
[000050] ------------ +--* LCL_VAR int V03 loc2
[000132] ------------ \--* FIELD int _length
[000130] ------------ \--* ADDR byref
[000131] -------N---- \--* LCL_VAR struct<System.Span`1[__Canon], 16> V02 loc1
------------ BB04 [035..037) (return), preds={} succs={}
***** BB04
STMT00014 (IL 0x035...0x036)
[000114] ------------ * RETURN ref
[000113] ------------ \--* LCL_VAR ref V01 loc0
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Allocate Objects
no newobjs in this method; punting
*************** Finishing PHASE Allocate Objects [no changes]
*************** Starting PHASE Morph - Add internal blocks
*************** After fgAddInternal()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015) i
BB06 [0005] 0 1 [???..???)-> BB09 ( cond ) i
BB07 [0006] 0 0.80 [???..???)-> BB09 ( cond ) i
BB08 [0007] 0 0.80 [???..???)-> BB05 (always) i
BB09 [0008] 0 0.20 [???..???) i
BB05 [0004] 1 1 [015..019)-> BB03 (always) i label target
BB02 [0001] 1 1 [019..02B) i bwd bwd-target
BB03 [0002] 2 1 [02B..???) i bwd
BB11 [0010] 0 1 [???..???)-> BB14 ( cond ) i
BB12 [0011] 0 0.80 [???..???)-> BB14 ( cond ) i
BB13 [0012] 0 0.80 [???..???)-> BB10 (always) i
BB14 [0013] 0 0.20 [???..???) i
BB10 [0009] 1 1 [???..035)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** Finishing PHASE Morph - Add internal blocks
*************** Starting PHASE Remove empty try
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty try [no changes]
*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.
*************** Finishing PHASE Remove empty finally [no changes]
*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.
*************** Finishing PHASE Merge callfinally chains [no changes]
*************** Starting PHASE Clone finally
No EH in this method, no cloning.
*************** Finishing PHASE Clone finally [no changes]
*************** Starting PHASE Compute preds
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015) i
BB06 [0005] 0 1 [???..???)-> BB09 ( cond ) i
BB07 [0006] 0 0.80 [???..???)-> BB09 ( cond ) i
BB08 [0007] 0 0.80 [???..???)-> BB05 (always) i
BB09 [0008] 0 0.20 [???..???) i
BB05 [0004] 1 1 [015..019)-> BB03 (always) i label target
BB02 [0001] 1 1 [019..02B) i bwd bwd-target
BB03 [0002] 2 1 [02B..???) i bwd
BB11 [0010] 0 1 [???..???)-> BB14 ( cond ) i
BB12 [0011] 0 0.80 [???..???)-> BB14 ( cond ) i
BB13 [0012] 0 0.80 [???..???)-> BB10 (always) i
BB14 [0013] 0 0.20 [???..???) i
BB10 [0009] 1 1 [???..035)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB06 to BB02
Renumber BB07 to BB03
Renumber BB08 to BB04
Renumber BB09 to BB05
Renumber BB05 to BB06
Renumber BB02 to BB07
Renumber BB03 to BB08
Renumber BB11 to BB09
Renumber BB12 to BB10
Renumber BB13 to BB11
Renumber BB14 to BB12
Renumber BB10 to BB13
Renumber BB04 to BB14
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015) i
BB02 [0005] 0 1 [???..???)-> BB05 ( cond ) i
BB03 [0006] 0 0.80 [???..???)-> BB05 ( cond ) i
BB04 [0007] 0 0.80 [???..???)-> BB06 (always) i
BB05 [0008] 0 0.20 [???..???) i
BB06 [0004] 1 1 [015..019)-> BB08 (always) i label target
BB07 [0001] 1 1 [019..02B) i bwd bwd-target
BB08 [0002] 2 1 [02B..???) i bwd
BB09 [0010] 0 1 [???..???)-> BB12 ( cond ) i
BB10 [0011] 0 0.80 [???..???)-> BB12 ( cond ) i
BB11 [0012] 0 0.80 [???..???)-> BB13 (always) i
BB12 [0013] 0 0.20 [???..???) i
BB13 [0009] 1 1 [???..035)-> BB07 ( cond ) i label target bwd
BB14 [0003] 1 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 2, # of blocks (including unused BB00): 15, bitset array size: 1 (short)
*************** In fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015) i
BB02 [0005] 0 1 [???..???)-> BB05 ( cond ) i
BB03 [0006] 0 0.80 [???..???)-> BB05 ( cond ) i
BB04 [0007] 0 0.80 [???..???)-> BB06 (always) i
BB05 [0008] 0 0.20 [???..???) i
BB06 [0004] 1 1 [015..019)-> BB08 (always) i label target
BB07 [0001] 1 1 [019..02B) i bwd bwd-target
BB08 [0002] 2 1 [02B..???) i bwd
BB09 [0010] 0 1 [???..???)-> BB12 ( cond ) i
BB10 [0011] 0 0.80 [???..???)-> BB12 ( cond ) i
BB11 [0012] 0 0.80 [???..???)-> BB13 (always) i
BB12 [0013] 0 0.20 [???..???) i
BB13 [0009] 1 1 [???..035)-> BB07 ( cond ) i label target bwd
BB14 [0003] 1 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015) i label target
BB02 [0005] 1 BB01 1 [???..???)-> BB05 ( cond ) i
BB03 [0006] 1 BB02 0.80 [???..???)-> BB05 ( cond ) i
BB04 [0007] 1 BB03 0.80 [???..???)-> BB06 (always) i
BB05 [0008] 2 BB02,BB03 0.20 [???..???) i label target
BB06 [0004] 2 BB04,BB05 1 [015..019)-> BB08 (always) i label target
BB07 [0001] 1 BB13 1 [019..02B) i label target bwd bwd-target
BB08 [0002] 2 BB06,BB07 1 [02B..???) i label target bwd
BB09 [0010] 1 BB08 1 [???..???)-> BB12 ( cond ) i
BB10 [0011] 1 BB09 0.80 [???..???)-> BB12 ( cond ) i
BB11 [0012] 1 BB10 0.80 [???..???)-> BB13 (always) i
BB12 [0013] 2 BB09,BB10 0.20 [???..???) i label target
BB13 [0009] 2 BB11,BB12 1 [???..035)-> BB07 ( cond ) i label target bwd
BB14 [0003] 1 BB13 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Compute preds
*************** Starting PHASE Merge throw blocks
*************** In fgTailMergeThrows
Method does not have multiple noreturn calls.
*************** Finishing PHASE Merge throw blocks [no changes]
*************** Starting PHASE Update flow graph early pass
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015) i label target
BB02 [0005] 1 BB01 1 [???..???)-> BB05 ( cond ) i
BB03 [0006] 1 BB02 0.80 [???..???)-> BB05 ( cond ) i
BB04 [0007] 1 BB03 0.80 [???..???)-> BB06 (always) i
BB05 [0008] 2 BB02,BB03 0.20 [???..???) i label target
BB06 [0004] 2 BB04,BB05 1 [015..019)-> BB08 (always) i label target
BB07 [0001] 1 BB13 1 [019..02B) i label target bwd bwd-target
BB08 [0002] 2 BB06,BB07 1 [02B..???) i label target bwd
BB09 [0010] 1 BB08 1 [???..???)-> BB12 ( cond ) i
BB10 [0011] 1 BB09 0.80 [???..???)-> BB12 ( cond ) i
BB11 [0012] 1 BB10 0.80 [???..???)-> BB13 (always) i
BB12 [0013] 2 BB09,BB10 0.20 [???..???) i label target
BB13 [0009] 2 BB11,BB12 1 [???..035)-> BB07 ( cond ) i label target bwd
BB14 [0003] 1 BB13 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
Compacting blocks BB01 and BB02:
*************** In fgDebugCheckBBlist
Compacting blocks BB08 and BB09:
*************** In fgDebugCheckBBlist
After updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB05 ( cond ) i label target
BB03 [0006] 1 BB01 0.80 [???..???)-> BB05 ( cond ) i
BB04 [0007] 1 BB03 0.80 [???..???)-> BB06 (always) i
BB05 [0008] 2 BB01,BB03 0.20 [???..???) i label target
BB06 [0004] 2 BB04,BB05 1 [015..019)-> BB08 (always) i label target
BB07 [0001] 1 BB13 1 [019..02B) i label target bwd bwd-target
BB08 [0002] 2 BB06,BB07 1 [02B..???)-> BB12 ( cond ) i label target bwd
BB10 [0011] 1 BB08 0.80 [???..???)-> BB12 ( cond ) i
BB11 [0012] 1 BB10 0.80 [???..???)-> BB13 (always) i
BB12 [0013] 2 BB08,BB10 0.20 [???..???) i label target
BB13 [0009] 2 BB11,BB12 1 [???..035)-> BB07 ( cond ) i label target bwd
BB14 [0003] 1 BB13 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Update flow graph early pass
*************** Starting PHASE Morph - Promote Structs
*************** In fgResetImplicitByRefRefCount()
*************** In fgPromoteStructs()
lvaTable before fgPromoteStructs
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 ref ld-addr-op class-hnd
; V02 loc1 struct <System.Span`1[__Canon], 16> ld-addr-op
; V03 loc2 int
; V04 OutArgs lclBlk <na> "OutgoingArgSpace"
; V05 tmp1 long "impRuntimeLookup slot"
; V06 tmp2 ref class-hnd "impAppendStmt"
; V07 tmp3 long "impRuntimeLookup indirectOffset"
; V08 tmp4 long "spilling Runtime Lookup tree"
; V09 tmp5 long "impRuntimeLookup slot"
; V10 tmp6 long "impRuntimeLookup indirectOffset"
; V11 tmp7 long "spilling Runtime Lookup tree"
Promoting struct local V02 (System.Span`1[__Canon]):
lvaGrabTemp returning 12 (V12 tmp8) (a long lifetime temp) called for field V02._pointer (fldOffset=0x0).
lvaGrabTemp returning 13 (V13 tmp9) (a long lifetime temp) called for field V02._length (fldOffset=0x8).
lvaTable after fgPromoteStructs
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 ref ld-addr-op class-hnd
; V02 loc1 struct <System.Span`1[__Canon], 16> ld-addr-op
; V03 loc2 int
; V04 OutArgs lclBlk <na> "OutgoingArgSpace"
; V05 tmp1 long "impRuntimeLookup slot"
; V06 tmp2 ref class-hnd "impAppendStmt"
; V07 tmp3 long "impRuntimeLookup indirectOffset"
; V08 tmp4 long "spilling Runtime Lookup tree"
; V09 tmp5 long "impRuntimeLookup slot"
; V10 tmp6 long "impRuntimeLookup indirectOffset"
; V11 tmp7 long "spilling Runtime Lookup tree"
; V12 tmp8 byref V02._pointer(offs=0x00) P-INDEP "field V02._pointer (fldOffset=0x0)"
; V13 tmp9 int V02._length(offs=0x08) P-INDEP "field V02._length (fldOffset=0x8)"
*************** Finishing PHASE Morph - Promote Structs
*************** Starting PHASE Morph - Structs/AddrExp
*************** In fgMarkAddressExposedLocals()
LocalAddressVisitor visiting statement:
STMT00000 (IL 0x000...0x003)
[000004] IA---------- * ASG struct (init)
[000003] -------N---- +--* BLK struct<8>
[000001] ------------ | \--* ADDR byref
[000000] -------N---- | \--* LCL_VAR ref V01 loc0
[000002] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00002 (IL 0x008...0x016)
[000015] -A-XG------- * ASG ref
[000014] D------N---- +--* LCL_VAR ref V06 tmp2
[000008] ---XG------- \--* FIELD ref _array
[000007] ------------ \--* LCL_VAR ref V00 this
LocalAddressVisitor visiting statement:
STMT00001 (IL 0x008... ???)
[000013] -A-X-------- * ASG long
[000012] D------N---- +--* LCL_VAR long V05 tmp1
[000011] #--X-------- \--* IND long
[000010] !----------- \--* LCL_VAR ref V00 this
LocalAddressVisitor visiting statement:
STMT00003 (IL ???... ???)
[000024] -A---------- * ASG long
[000023] D------N---- +--* LCL_VAR long V07 tmp3
[000022] n----------- \--* IND long
[000021] #----------- \--* IND long
[000020] ------------ \--* ADD long
[000018] ------------ +--* LCL_VAR long V05 tmp1
[000019] ------------ \--* CNS_INT long 56
LocalAddressVisitor visiting statement:
STMT00015 (IL ???... ???)
[000115] ------------ * JTRUE void
[000042] ------------ \--* LE int
[000040] ------------ +--* IND long
[000039] ------------ | \--* ADD long
[000026] ------------ | +--* LCL_VAR long V07 tmp3
[000038] ------------ | \--* CNS_INT long 8
[000041] ------------ \--* CNS_INT long 96
LocalAddressVisitor visiting statement:
STMT00016 (IL ???... ???)
[000116] ------------ * JTRUE void
[000033] ------------ \--* EQ int
[000029] n----------- +--* IND long
[000028] ------------ | \--* ADD long
[000025] ------------ | +--* LCL_VAR long V07 tmp3
[000027] ------------ | \--* CNS_INT long 96
[000032] ------------ \--* CNS_INT long 0
LocalAddressVisitor visiting statement:
STMT00017 (IL ???... ???)
[000118] -A---------- * ASG long
[000117] D------N---- +--* LCL_VAR long V08 tmp4
[000034] n----------- \--* IND long
[000035] ------------ \--* ADD long
[000036] ------------ +--* LCL_VAR long V07 tmp3
[000037] ------------ \--* CNS_INT long 96
LocalAddressVisitor visiting statement:
STMT00018 (IL ???... ???)
[000120] -AC-G------- * ASG long
[000119] D------N---- +--* LCL_VAR long V08 tmp4
[000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000017] ------------ arg0 +--* LCL_VAR long V05 tmp1
[000030] ------------ arg1 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
LocalAddressVisitor visiting statement:
STMT00005 (IL ???... ???)
[000009] --C-G------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor
[000006] ------------ this in rcx +--* ADDR byref
[000005] -------N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9
[000046] ------------ arg1 +--* RUNTIMELOOKUP long 0x7ff9f129e500 class
[000045] ------------ | \--* LCL_VAR long V08 tmp4
[000016] ------------ arg2 \--* LCL_VAR ref V06 tmp2
Local V12 should not be enregistered because: it is address exposed
Local V13 should not be enregistered because: it is address exposed
Local V02 should not be enregistered because: it is address exposed
LocalAddressVisitor visiting statement:
STMT00006 (IL 0x015... ???)
[000049] -A---------- * ASG int
[000048] D------N---- +--* LCL_VAR int V03 loc2
[000047] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00012 (IL 0x019...0x022)
[000107] IA-X-------- * ASG struct (init)
[000106] ---X---N---- +--* BLK struct<8>
[000104] ---X-------- | \--* COMMA byref
[000098] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000093] ------------ | | +--* LCL_VAR int V03 loc2
[000097] ------------ | | \--* FIELD int _length
[000092] ------------ | | \--* ADDR byref
[000091] -------N---- | | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| | \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| | \--* int V02._length (offs=0x08) -> V13 tmp9
[000103] ------------ | \--* ADD byref
[000102] ------------ | +--* FIELD byref _pointer
[000096] ------------ | | \--* ADDR byref
[000095] -------N---- | | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| | \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| | \--* int V02._length (offs=0x08) -> V13 tmp9
[000101] ------------ | \--* MUL long
[000099] ------------ | +--* CAST long <- int
[000094] ------------ | | \--* LCL_VAR int V03 loc2
[000100] ------------ | \--* CNS_INT int 8
[000105] ------------ \--* CNS_INT int 0
Replacing the field in promoted struct with local var V13
Replacing the field in promoted struct with local var V12
LocalAddressVisitor modified statement:
STMT00012 (IL 0x019...0x022)
[000107] IA-X-------- * ASG struct (init)
[000106] ---X---N---- +--* BLK struct<8>
[000104] ---X-------- | \--* COMMA byref
[000098] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000093] ------------ | | +--* LCL_VAR int V03 loc2
[000097] ------------ | | \--* LCL_VAR int (AX) V13 tmp9
[000103] ------------ | \--* ADD byref
[000102] ------------ | +--* LCL_VAR byref (AX) V12 tmp8
[000101] ------------ | \--* MUL long
[000099] ------------ | +--* CAST long <- int
[000094] ------------ | | \--* LCL_VAR int V03 loc2
[000100] ------------ | \--* CNS_INT int 8
[000105] ------------ \--* CNS_INT int 0
LocalAddressVisitor visiting statement:
STMT00013 (IL 0x027...0x02A)
[000112] -A---------- * ASG int
[000111] D------N---- +--* LCL_VAR int V03 loc2
[000110] ------------ \--* ADD int
[000108] ------------ +--* LCL_VAR int V03 loc2
[000109] ------------ \--* CNS_INT int 1
LocalAddressVisitor visiting statement:
STMT00007 (IL 0x02B...0x033)
[000057] -A-X-------- * ASG long
[000056] D------N---- +--* LCL_VAR long V09 tmp5
[000055] #--X-------- \--* IND long
[000054] !----------- \--* LCL_VAR ref V00 this
LocalAddressVisitor visiting statement:
STMT00008 (IL ???... ???)
[000065] -A---------- * ASG long
[000064] D------N---- +--* LCL_VAR long V10 tmp6
[000063] n----------- \--* IND long
[000062] #----------- \--* IND long
[000061] ------------ \--* ADD long
[000059] ------------ +--* LCL_VAR long V09 tmp5
[000060] ------------ \--* CNS_INT long 56
LocalAddressVisitor visiting statement:
STMT00019 (IL ???... ???)
[000121] ------------ * JTRUE void
[000083] ------------ \--* LE int
[000081] ------------ +--* IND long
[000080] ------------ | \--* ADD long
[000067] ------------ | +--* LCL_VAR long V10 tmp6
[000079] ------------ | \--* CNS_INT long 8
[000082] ------------ \--* CNS_INT long 96
LocalAddressVisitor visiting statement:
STMT00020 (IL ???... ???)
[000122] ------------ * JTRUE void
[000074] ------------ \--* EQ int
[000070] n----------- +--* IND long
[000069] ------------ | \--* ADD long
[000066] ------------ | +--* LCL_VAR long V10 tmp6
[000068] ------------ | \--* CNS_INT long 96
[000073] ------------ \--* CNS_INT long 0
LocalAddressVisitor visiting statement:
STMT00021 (IL ???... ???)
[000124] -A---------- * ASG long
[000123] D------N---- +--* LCL_VAR long V11 tmp7
[000075] n----------- \--* IND long
[000076] ------------ \--* ADD long
[000077] ------------ +--* LCL_VAR long V10 tmp6
[000078] ------------ \--* CNS_INT long 96
LocalAddressVisitor visiting statement:
STMT00022 (IL ???... ???)
[000126] -AC-G------- * ASG long
[000125] D------N---- +--* LCL_VAR long V11 tmp7
[000072] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000058] ------------ arg0 +--* LCL_VAR long V09 tmp5
[000071] ------------ arg1 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
LocalAddressVisitor visiting statement:
STMT00011 (IL ???... ???)
[000090] --C--------- * JTRUE void
[000089] --C--------- \--* LT int
[000050] ------------ +--* LCL_VAR int V03 loc2
[000132] ------------ \--* FIELD int _length
[000130] ------------ \--* ADDR byref
[000131] -------N---- \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
\--* byref V02._pointer (offs=0x00) -> V12 tmp8
\--* int V02._length (offs=0x08) -> V13 tmp9
Replacing the field in promoted struct with local var V13
LocalAddressVisitor modified statement:
STMT00011 (IL ???... ???)
[000090] --C--------- * JTRUE void
[000089] --C--------- \--* LT int
[000050] ------------ +--* LCL_VAR int V03 loc2
[000132] ------------ \--* LCL_VAR int (AX) V13 tmp9
LocalAddressVisitor visiting statement:
STMT00014 (IL 0x035...0x036)
[000114] ------------ * RETURN ref
[000113] ------------ \--* LCL_VAR ref V01 loc0
*************** Finishing PHASE Morph - Structs/AddrExp
*************** Starting PHASE Morph - ByRefs
*************** In fgRetypeImplicitByRefArgs()
*************** Finishing PHASE Morph - ByRefs
*************** Starting PHASE Morph - Global
*************** In fgMorphBlocks()
Morphing BB01 of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
fgMorphTree BB01, STMT00000 (before)
[000004] IA---------- * ASG struct (init)
[000003] -------N---- +--* BLK struct<8>
[000001] ------------ | \--* ADDR byref
[000000] -------N---- | \--* LCL_VAR ref V01 loc0
[000002] ------------ \--* CNS_INT int 0
fgMorphBlkNode for dst tree, before:
[000003] n----+-N---- * BLK struct<8>
[000001] -----+------ \--* ADDR byref
[000000] D----+-N---- \--* LCL_VAR ref V01 loc0
fgMorphBlkNode after:
[000003] n----+-N---- * BLK struct<8>
[000001] -----+------ \--* ADDR byref
[000000] D----+-N---- \--* LCL_VAR ref V01 loc0
fgMorphInitBlock:fgMorphOneAsgBlock (after):
[000004] -A---------- * ASG ref
[000000] D----+-N---- +--* LCL_VAR ref V01 loc0
[000002] -----+------ \--* CNS_INT ref null
using oneAsgTree.
GenTreeNode creates assertion:
[000004] -A---------- * ASG ref
In BB01 New Local Constant Assertion: V01 == null index=#01, mask=0000000000000001
fgMorphTree BB01, STMT00000 (after)
[000004] -A---+------ * ASG ref
[000000] D----+-N---- +--* LCL_VAR ref V01 loc0
[000002] -----+------ \--* CNS_INT ref null
fgMorphTree BB01, STMT00002 (before)
[000015] -A-XG------- * ASG ref
[000014] D------N---- +--* LCL_VAR ref V06 tmp2
[000008] ---XG------- \--* FIELD ref _array
[000007] ------------ \--* LCL_VAR ref V00 this
Final value of Compiler::fgMorphField after calling fgMorphSmpOp:
[000008] ---XG------- * IND ref
[000135] -----+------ \--* ADD byref
[000007] -----+------ +--* LCL_VAR ref V00 this
[000134] -----+------ \--* CNS_INT long 16 field offset Fseq[_array]
GenTreeNode creates assertion:
[000008] ---XG------- * IND ref
In BB01 New Local Constant Assertion: V00 != null index=#02, mask=0000000000000002
fgMorphTree BB01, STMT00002 (after)
[000015] -A-XG+------ * ASG ref
[000014] D----+-N---- +--* LCL_VAR ref V06 tmp2
[000008] ---XG+------ \--* IND ref
[000135] -----+------ \--* ADD byref
[000007] -----+------ +--* LCL_VAR ref V00 this
[000134] -----+------ \--* CNS_INT long 16 field offset Fseq[_array]
fgMorphTree BB01, STMT00001 (before)
[000013] -A-X-------- * ASG long
[000012] D------N---- +--* LCL_VAR long V05 tmp1
[000011] #--X-------- \--* IND long
[000010] !----------- \--* LCL_VAR ref V00 this
Non-null prop for index #02 in BB01:
[000011] #--X-------- * IND long
fgMorphTree BB01, STMT00003 (before)
[000024] -A---------- * ASG long
[000023] D------N---- +--* LCL_VAR long V07 tmp3
[000022] n----------- \--* IND long
[000021] #----------- \--* IND long
[000020] ------------ \--* ADD long
[000018] ------------ +--* LCL_VAR long V05 tmp1
[000019] ------------ \--* CNS_INT long 56
fgMorphTree BB01, STMT00015 (before)
[000115] ------------ * JTRUE void
[000042] ------------ \--* LE int
[000040] ------------ +--* IND long
[000039] ------------ | \--* ADD long
[000026] ------------ | +--* LCL_VAR long V07 tmp3
[000038] ------------ | \--* CNS_INT long 8
[000041] ------------ \--* CNS_INT long 96
Morphing BB03 of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
fgMorphTree BB03, STMT00016 (before)
[000116] ------------ * JTRUE void
[000033] ------------ \--* EQ int
[000029] n----------- +--* IND long
[000028] ------------ | \--* ADD long
[000025] ------------ | +--* LCL_VAR long V07 tmp3
[000027] ------------ | \--* CNS_INT long 96
[000032] ------------ \--* CNS_INT long 0
Morphing BB04 of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
fgMorphTree BB04, STMT00017 (before)
[000118] -A---------- * ASG long
[000117] D------N---- +--* LCL_VAR long V08 tmp4
[000034] n----------- \--* IND long
[000035] ------------ \--* ADD long
[000036] ------------ +--* LCL_VAR long V07 tmp3
[000037] ------------ \--* CNS_INT long 96
Morphing BB05 of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
fgMorphTree BB05, STMT00018 (before)
[000120] -AC-G------- * ASG long
[000119] D------N---- +--* LCL_VAR long V08 tmp4
[000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000017] ------------ arg0 +--* LCL_VAR long V05 tmp1
[000030] ------------ arg1 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
Initializing arg info for 31.CALL:
ArgTable for 31.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 17.LCL_VAR long (By ref), 1 reg: rcx, align=1]
fgArgTabEntry[arg 1 30.CNS_INT long (By ref), 1 reg: rdx, align=1]
Morphing args for 31.CALL:
argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000017] -----+------ * LCL_VAR long V05 tmp1
Replaced with placeholder node:
[000136] ----------L- * ARGPLACE long
Deferred argument ('rdx'):
[000030] -----+------ * CNS_INT(h) long 0x7ff9f1337fe8 token
Replaced with placeholder node:
[000137] ----------L- * ARGPLACE long
Shuffled argument table: rcx rdx
ArgTable for 31.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 17.LCL_VAR long (By ref), 1 reg: rcx, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 30.CNS_INT long (By ref), 1 reg: rdx, align=1, lateArgInx=1, processed]
fgMorphTree BB05, STMT00018 (after)
[000120] -AC-G+------ * ASG long
[000119] D----+-N---- +--* LCL_VAR long V08 tmp4
[000031] --C-G+------ \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000017] -----+------ arg0 in rcx +--* LCL_VAR long V05 tmp1
[000030] -----+------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
Morphing BB06 of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
fgMorphTree BB06, STMT00005 (before)
[000009] --C-G------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor
[000006] ------------ this in rcx +--* ADDR byref
[000005] -------N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9
[000046] ------------ arg1 +--* RUNTIMELOOKUP long 0x7ff9f129e500 class
[000045] ------------ | \--* LCL_VAR long V08 tmp4
[000016] ------------ arg2 \--* LCL_VAR ref V06 tmp2
Initializing arg info for 9.CALL:
ArgTable for 9.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 6.ADDR byref (By ref), 1 reg: rcx, align=1]
fgArgTabEntry[arg 1 46.RUNTIMELOOKUP long (By ref), 1 reg: rdx, align=1]
fgArgTabEntry[arg 2 16.LCL_VAR ref (By ref), 1 reg: r8, align=1]
Morphing args for 9.CALL:
argSlots=3, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000006] -----+------ * ADDR byref
[000005] ----G+-N---- \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
\--* byref V02._pointer (offs=0x00) -> V12 tmp8
\--* int V02._length (offs=0x08) -> V13 tmp9
Replaced with placeholder node:
[000138] ----------L- * ARGPLACE byref
Deferred argument ('rdx'):
[000045] -----+------ * LCL_VAR long V08 tmp4
Replaced with placeholder node:
[000139] ----------L- * ARGPLACE long
Deferred argument ('r8'):
[000016] -----+------ * LCL_VAR ref V06 tmp2
Replaced with placeholder node:
[000140] ----------L- * ARGPLACE ref
Shuffled argument table: rcx rdx r8
ArgTable for 9.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 6.ADDR byref (By ref), 1 reg: rcx, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 45.LCL_VAR long (By ref), 1 reg: rdx, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 2 16.LCL_VAR ref (By ref), 1 reg: r8, align=1, lateArgInx=2, processed]
fgMorphTree BB06, STMT00005 (after)
[000009] --CXG+------ * CALL void System.Span`1[__Canon][System.__Canon]..ctor
[000006] -----+------ this in rcx +--* ADDR byref
[000005] ----G+-N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9
[000045] -----+------ arg1 in rdx +--* LCL_VAR long V08 tmp4
[000016] -----+------ arg2 in r8 \--* LCL_VAR ref V06 tmp2
fgMorphTree BB06, STMT00006 (before)
[000049] -A---------- * ASG int
[000048] D------N---- +--* LCL_VAR int V03 loc2
[000047] ------------ \--* CNS_INT int 0
GenTreeNode creates assertion:
[000049] -A---------- * ASG int
In BB06 New Local Constant Assertion: V03 == 0 index=#01, mask=0000000000000001
Morphing BB07 of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
fgMorphTree BB07, STMT00012 (before)
[000107] IA-X-------- * ASG struct (init)
[000106] ---X---N---- +--* BLK struct<8>
[000104] ---X-------- | \--* COMMA byref
[000098] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void
[000093] ------------ | | +--* LCL_VAR int V03 loc2
[000097] ------------ | | \--* LCL_VAR int (AX) V13 tmp9
[000103] ------------ | \--* ADD byref
[000102] ------------ | +--* LCL_VAR byref (AX) V12 tmp8
[000101] ------------ | \--* MUL long
[000099] ------------ | +--* CAST long <- int
[000094] ------------ | | \--* LCL_VAR int V03 loc2
[000100] ------------ | \--* CNS_INT int 8
[000105] ------------ \--* CNS_INT int 0
fgMorphBlkNode for dst tree, before:
[000106] ---XG+-N---- * BLK struct<8>
[000104] ---XG+------ \--* COMMA byref
[000098] ---XG+------ +--* ARR_BOUNDS_CHECK_Rng void
[000093] -----+------ | +--* LCL_VAR int V03 loc2
[000097] ----G+------ | \--* LCL_VAR int (AX) V13 tmp9
[000103] ----G+------ \--* ADD byref
[000102] ----G+------ +--* LCL_VAR byref (AX) V12 tmp8
[000101] -----+------ \--* LSH long
[000099] -----+------ +--* CAST long <- int
[000094] -----+------ | \--* LCL_VAR int V03 loc2
[000100] -----+------ \--* CNS_INT int 3
fgMorphBlkNode after:
[000106] ---XG+-N---- * BLK struct<8>
[000104] ---XG+------ \--* COMMA byref
[000098] ---XG+------ +--* ARR_BOUNDS_CHECK_Rng void
[000093] -----+------ | +--* LCL_VAR int V03 loc2
[000097] ----G+------ | \--* LCL_VAR int (AX) V13 tmp9
[000103] ----G+------ \--* ADD byref
[000102] ----G+------ +--* LCL_VAR byref (AX) V12 tmp8
[000101] -----+------ \--* LSH long
[000099] -----+------ +--* CAST long <- int
[000094] -----+------ | \--* LCL_VAR int V03 loc2
[000100] -----+------ \--* CNS_INT int 3
fgMorphInitBlock:
fgMorphTree BB07, STMT00012 (after)
[000107] IA-XG+------ * ASG struct (init)
[000106] ---XG+-N---- +--* BLK struct<8>
[000104] ---XG+------ | \--* COMMA byref
[000098] ---XG+------ | +--* ARR_BOUNDS_CHECK_Rng void
[000093] -----+------ | | +--* LCL_VAR int V03 loc2
[000097] ----G+------ | | \--* LCL_VAR int (AX) V13 tmp9
[000103] ----G+------ | \--* ADD byref
[000102] ----G+------ | +--* LCL_VAR byref (AX) V12 tmp8
[000101] -----+------ | \--* LSH long
[000099] -----+------ | +--* CAST long <- int
[000094] -----+------ | | \--* LCL_VAR int V03 loc2
[000100] -----+------ | \--* CNS_INT int 3
[000105] -----+------ \--* CNS_INT int 0
fgMorphTree BB07, STMT00013 (before)
[000112] -A---------- * ASG int
[000111] D------N---- +--* LCL_VAR int V03 loc2
[000110] ------------ \--* ADD int
[000108] ------------ +--* LCL_VAR int V03 loc2
[000109] ------------ \--* CNS_INT int 1
Morphing BB08 of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
fgMorphTree BB08, STMT00007 (before)
[000057] -A-X-------- * ASG long
[000056] D------N---- +--* LCL_VAR long V09 tmp5
[000055] #--X-------- \--* IND long
[000054] !----------- \--* LCL_VAR ref V00 this
GenTreeNode creates assertion:
[000055] #--X-------- * IND long
In BB08 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001
fgMorphTree BB08, STMT00008 (before)
[000065] -A---------- * ASG long
[000064] D------N---- +--* LCL_VAR long V10 tmp6
[000063] n----------- \--* IND long
[000062] #----------- \--* IND long
[000061] ------------ \--* ADD long
[000059] ------------ +--* LCL_VAR long V09 tmp5
[000060] ------------ \--* CNS_INT long 56
fgMorphTree BB08, STMT00019 (before)
[000121] ------------ * JTRUE void
[000083] ------------ \--* LE int
[000081] ------------ +--* IND long
[000080] ------------ | \--* ADD long
[000067] ------------ | +--* LCL_VAR long V10 tmp6
[000079] ------------ | \--* CNS_INT long 8
[000082] ------------ \--* CNS_INT long 96
Morphing BB10 of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
fgMorphTree BB10, STMT00020 (before)
[000122] ------------ * JTRUE void
[000074] ------------ \--* EQ int
[000070] n----------- +--* IND long
[000069] ------------ | \--* ADD long
[000066] ------------ | +--* LCL_VAR long V10 tmp6
[000068] ------------ | \--* CNS_INT long 96
[000073] ------------ \--* CNS_INT long 0
Morphing BB11 of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
fgMorphTree BB11, STMT00021 (before)
[000124] -A---------- * ASG long
[000123] D------N---- +--* LCL_VAR long V11 tmp7
[000075] n----------- \--* IND long
[000076] ------------ \--* ADD long
[000077] ------------ +--* LCL_VAR long V10 tmp6
[000078] ------------ \--* CNS_INT long 96
Morphing BB12 of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
fgMorphTree BB12, STMT00022 (before)
[000126] -AC-G------- * ASG long
[000125] D------N---- +--* LCL_VAR long V11 tmp7
[000072] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000058] ------------ arg0 +--* LCL_VAR long V09 tmp5
[000071] ------------ arg1 \--* CNS_INT(h) long 0x7ff9f1337fe8 token
Initializing arg info for 72.CALL:
ArgTable for 72.CALL after fgInitArgInfo:
fgArgTabEntry[arg 0 58.LCL_VAR long (By ref), 1 reg: rcx, align=1]
fgArgTabEntry[arg 1 71.CNS_INT long (By ref), 1 reg: rdx, align=1]
Morphing args for 72.CALL:
argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
Sorting the arguments:
Deferred argument ('rcx'):
[000058] -----+------ * LCL_VAR long V09 tmp5
Replaced with placeholder node:
[000141] ----------L- * ARGPLACE long
Deferred argument ('rdx'):
[000071] -----+------ * CNS_INT(h) long 0x7ff9f1337fe8 token
Replaced with placeholder node:
[000142] ----------L- * ARGPLACE long
Shuffled argument table: rcx rdx
ArgTable for 72.CALL after fgMorphArgs:
fgArgTabEntry[arg 0 58.LCL_VAR long (By ref), 1 reg: rcx, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 71.CNS_INT long (By ref), 1 reg: rdx, align=1, lateArgInx=1, processed]
fgMorphTree BB12, STMT00022 (after)
[000126] -AC-G+------ * ASG long
[000125] D----+-N---- +--* LCL_VAR long V11 tmp7
[000072] --C-G+------ \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000058] -----+------ arg0 in rcx +--* LCL_VAR long V09 tmp5
[000071] -----+------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
Morphing BB13 of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
fgMorphTree BB13, STMT00011 (before)
[000090] --C--------- * JTRUE void
[000089] --C--------- \--* LT int
[000050] ------------ +--* LCL_VAR int V03 loc2
[000132] ------------ \--* LCL_VAR int (AX) V13 tmp9
Morphing BB14 of 'System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this'
fgMorphTree BB14, STMT00014 (before)
[000114] ------------ * RETURN ref
[000113] ------------ \--* LCL_VAR ref V01 loc0
*************** Finishing PHASE Morph - Global
Trees after Morph - Global
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB05 ( cond ) i label target
BB03 [0006] 1 BB01 0.80 [???..???)-> BB05 ( cond ) i
BB04 [0007] 1 BB03 0.80 [???..???)-> BB06 (always) i
BB05 [0008] 2 BB01,BB03 0.20 [???..???) i label target hascall
BB06 [0004] 2 BB04,BB05 1 [015..019)-> BB08 (always) i label target hascall
BB07 [0001] 1 BB13 1 [019..02B) i label target bwd bwd-target
BB08 [0002] 2 BB06,BB07 1 [02B..???)-> BB12 ( cond ) i label target bwd
BB10 [0011] 1 BB08 0.80 [???..???)-> BB12 ( cond ) i
BB11 [0012] 1 BB10 0.80 [???..???)-> BB13 (always) i
BB12 [0013] 2 BB08,BB10 0.20 [???..???) i label target hascall
BB13 [0009] 2 BB11,BB12 1 [???..035)-> BB07 ( cond ) i label target bwd
BB14 [0003] 1 BB13 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB05 (cond), preds={} succs={BB03,BB05}
***** BB01
STMT00000 (IL 0x000...0x003)
[000004] -A---+------ * ASG ref
[000000] D----+-N---- +--* LCL_VAR ref V01 loc0
[000002] -----+------ \--* CNS_INT ref null
***** BB01
STMT00002 (IL 0x008...0x016)
[000015] -A-XG+------ * ASG ref
[000014] D----+-N---- +--* LCL_VAR ref V06 tmp2
[000008] ---XG+------ \--* IND ref
[000135] -----+------ \--* ADD byref
[000007] -----+------ +--* LCL_VAR ref V00 this
[000134] -----+------ \--* CNS_INT long 16 field offset Fseq[_array]
***** BB01
STMT00001 (IL 0x008... ???)
[000013] -A---+------ * ASG long
[000012] D----+-N---- +--* LCL_VAR long V05 tmp1
[000011] #----+------ \--* IND long
[000010] !----+------ \--* LCL_VAR ref V00 this
***** BB01
STMT00003 (IL ???... ???)
[000024] -A---+------ * ASG long
[000023] D----+-N---- +--* LCL_VAR long V07 tmp3
[000022] n----+------ \--* IND long
[000021] #----+------ \--* IND long
[000020] -----+------ \--* ADD long
[000018] -----+------ +--* LCL_VAR long V05 tmp1
[000019] -----+------ \--* CNS_INT long 56
***** BB01
STMT00015 (IL ???... ???)
[000115] ---X-+------ * JTRUE void
[000042] J--X-+-N---- \--* LE int
[000040] ---X-+------ +--* IND long
[000039] -----+------ | \--* ADD long
[000026] -----+------ | +--* LCL_VAR long V07 tmp3
[000038] -----+------ | \--* CNS_INT long 8
[000041] -----+------ \--* CNS_INT long 96
------------ BB03 [???..???) -> BB05 (cond), preds={BB01} succs={BB04,BB05}
***** BB03
STMT00016 (IL ???... ???)
[000116] -----+------ * JTRUE void
[000033] J----+-N---- \--* EQ int
[000029] n----+------ +--* IND long
[000028] -----+------ | \--* ADD long
[000025] -----+------ | +--* LCL_VAR long V07 tmp3
[000027] -----+------ | \--* CNS_INT long 96
[000032] -----+------ \--* CNS_INT long 0
------------ BB04 [???..???) -> BB06 (always), preds={BB03} succs={BB06}
***** BB04
STMT00017 (IL ???... ???)
[000118] -A---+------ * ASG long
[000117] D----+-N---- +--* LCL_VAR long V08 tmp4
[000034] n----+------ \--* IND long
[000035] -----+------ \--* ADD long
[000036] -----+------ +--* LCL_VAR long V07 tmp3
[000037] -----+------ \--* CNS_INT long 96
------------ BB05 [???..???), preds={BB01,BB03} succs={BB06}
***** BB05
STMT00018 (IL ???... ???)
[000120] -AC-G+------ * ASG long
[000119] D----+-N---- +--* LCL_VAR long V08 tmp4
[000031] --C-G+------ \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000017] -----+------ arg0 in rcx +--* LCL_VAR long V05 tmp1
[000030] -----+------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB06 [015..019) -> BB08 (always), preds={BB04,BB05} succs={BB08}
***** BB06
STMT00005 (IL ???... ???)
[000009] --CXG+------ * CALL void System.Span`1[__Canon][System.__Canon]..ctor
[000006] -----+------ this in rcx +--* ADDR byref
[000005] ----G+-N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9
[000045] -----+------ arg1 in rdx +--* LCL_VAR long V08 tmp4
[000016] -----+------ arg2 in r8 \--* LCL_VAR ref V06 tmp2
***** BB06
STMT00006 (IL 0x015... ???)
[000049] -A---+------ * ASG int
[000048] D----+-N---- +--* LCL_VAR int V03 loc2
[000047] -----+------ \--* CNS_INT int 0
------------ BB07 [019..02B), preds={BB13} succs={BB08}
***** BB07
STMT00012 (IL 0x019...0x022)
[000107] IA-XG+------ * ASG struct (init)
[000106] ---XG+-N---- +--* BLK struct<8>
[000104] ---XG+------ | \--* COMMA byref
[000098] ---XG+------ | +--* ARR_BOUNDS_CHECK_Rng void
[000093] -----+------ | | +--* LCL_VAR int V03 loc2
[000097] ----G+------ | | \--* LCL_VAR int (AX) V13 tmp9
[000103] ----G+------ | \--* ADD byref
[000102] ----G+------ | +--* LCL_VAR byref (AX) V12 tmp8
[000101] -----+------ | \--* LSH long
[000099] -----+------ | +--* CAST long <- int
[000094] -----+------ | | \--* LCL_VAR int V03 loc2
[000100] -----+------ | \--* CNS_INT int 3
[000105] -----+------ \--* CNS_INT int 0
***** BB07
STMT00013 (IL 0x027...0x02A)
[000112] -A---+------ * ASG int
[000111] D----+-N---- +--* LCL_VAR int V03 loc2
[000110] -----+------ \--* ADD int
[000108] -----+------ +--* LCL_VAR int V03 loc2
[000109] -----+------ \--* CNS_INT int 1
------------ BB08 [02B..???) -> BB12 (cond), preds={BB06,BB07} succs={BB10,BB12}
***** BB08
STMT00007 (IL 0x02B...0x033)
[000057] -A-X-+------ * ASG long
[000056] D----+-N---- +--* LCL_VAR long V09 tmp5
[000055] #--X-+------ \--* IND long
[000054] !----+------ \--* LCL_VAR ref V00 this
***** BB08
STMT00008 (IL ???... ???)
[000065] -A---+------ * ASG long
[000064] D----+-N---- +--* LCL_VAR long V10 tmp6
[000063] n----+------ \--* IND long
[000062] #----+------ \--* IND long
[000061] -----+------ \--* ADD long
[000059] -----+------ +--* LCL_VAR long V09 tmp5
[000060] -----+------ \--* CNS_INT long 56
***** BB08
STMT00019 (IL ???... ???)
[000121] ---X-+------ * JTRUE void
[000083] J--X-+-N---- \--* LE int
[000081] ---X-+------ +--* IND long
[000080] -----+------ | \--* ADD long
[000067] -----+------ | +--* LCL_VAR long V10 tmp6
[000079] -----+------ | \--* CNS_INT long 8
[000082] -----+------ \--* CNS_INT long 96
------------ BB10 [???..???) -> BB12 (cond), preds={BB08} succs={BB11,BB12}
***** BB10
STMT00020 (IL ???... ???)
[000122] -----+------ * JTRUE void
[000074] J----+-N---- \--* EQ int
[000070] n----+------ +--* IND long
[000069] -----+------ | \--* ADD long
[000066] -----+------ | +--* LCL_VAR long V10 tmp6
[000068] -----+------ | \--* CNS_INT long 96
[000073] -----+------ \--* CNS_INT long 0
------------ BB11 [???..???) -> BB13 (always), preds={BB10} succs={BB13}
***** BB11
STMT00021 (IL ???... ???)
[000124] -A---+------ * ASG long
[000123] D----+-N---- +--* LCL_VAR long V11 tmp7
[000075] n----+------ \--* IND long
[000076] -----+------ \--* ADD long
[000077] -----+------ +--* LCL_VAR long V10 tmp6
[000078] -----+------ \--* CNS_INT long 96
------------ BB12 [???..???), preds={BB08,BB10} succs={BB13}
***** BB12
STMT00022 (IL ???... ???)
[000126] -AC-G+------ * ASG long
[000125] D----+-N---- +--* LCL_VAR long V11 tmp7
[000072] --C-G+------ \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000058] -----+------ arg0 in rcx +--* LCL_VAR long V09 tmp5
[000071] -----+------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB13 [???..035) -> BB07 (cond), preds={BB11,BB12} succs={BB14,BB07}
***** BB13
STMT00011 (IL ???... ???)
[000090] ----G+------ * JTRUE void
[000089] J---G+-N---- \--* LT int
[000050] -----+------ +--* LCL_VAR int V03 loc2
[000132] ----G+------ \--* LCL_VAR int (AX) V13 tmp9
------------ BB14 [035..037) (return), preds={BB13} succs={}
***** BB14
STMT00014 (IL 0x035...0x036)
[000114] -----+------ * RETURN ref
[000113] -----+------ \--* LCL_VAR ref V01 loc0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE GS Cookie
No GS security needed
*************** Finishing PHASE GS Cookie
*************** Starting PHASE Mark GC poll blocks
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB05 ( cond ) i label target
BB03 [0006] 1 BB01 0.80 [???..???)-> BB05 ( cond ) i
BB04 [0007] 1 BB03 0.80 [???..???)-> BB06 (always) i
BB05 [0008] 2 BB01,BB03 0.20 [???..???) i label target hascall
BB06 [0004] 2 BB04,BB05 1 [015..019)-> BB08 (always) i label target hascall
BB07 [0001] 1 BB13 1 [019..02B) i label target bwd bwd-target
BB08 [0002] 2 BB06,BB07 1 [02B..???)-> BB12 ( cond ) i label target bwd
BB10 [0011] 1 BB08 0.80 [???..???)-> BB12 ( cond ) i
BB11 [0012] 1 BB10 0.80 [???..???)-> BB13 (always) i
BB12 [0013] 2 BB08,BB10 0.20 [???..???) i label target hascall
BB13 [0009] 2 BB11,BB12 1 [???..035)-> BB07 ( cond ) i label target bwd
BB14 [0003] 1 BB13 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
Renumber BB03 to BB02
Renumber BB04 to BB03
Renumber BB05 to BB04
Renumber BB06 to BB05
Renumber BB07 to BB06
Renumber BB08 to BB07
Renumber BB10 to BB08
Renumber BB11 to BB09
Renumber BB12 to BB10
Renumber BB13 to BB11
Renumber BB14 to BB12
*************** After renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.80 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.80 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.20 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 1 [019..02B) i label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 1 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 0.80 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 0.80 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.20 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 1 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
New BlockSet epoch 3, # of blocks (including unused BB00): 13, bitset array size: 1 (short)
*************** Finishing PHASE Mark GC poll blocks
*************** Starting PHASE Compute edge weights (1, false)
*************** In fgComputeBlockAndEdgeWeights()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.80 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.80 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.20 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 1 [019..02B) i label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 1 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 0.80 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 0.80 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.20 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 1 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights
*************** Finishing PHASE Compute edge weights (1, false)
*************** Starting PHASE Create EH funclets
*************** In fgCreateFunclets()
After fgCreateFunclets()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.80 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.80 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.20 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 1 [019..02B) i label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 1 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 0.80 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 0.80 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.20 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 1 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Create EH funclets
*************** Starting PHASE Optimize layout
*************** In optOptimizeLayout()
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.80 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.80 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.20 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 1 [019..02B) i label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 1 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 0.80 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 0.80 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.20 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 1 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgExpandRarelyRunBlocks()
*************** In fgReorderBlocks()
Initial BasicBlocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.80 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.80 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.20 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 1 [019..02B) i label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 1 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 0.80 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 0.80 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.20 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 1 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.80 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.80 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.20 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 1 [019..02B) i label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 1 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 0.80 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 0.80 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.20 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 1 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize layout
*************** Starting PHASE Compute blocks reachability
*************** In fgComputeReachability
*************** In fgDebugCheckBBlist
Renumbering the basic blocks for fgComputeReachability pass #1
*************** Before renumbering the basic blocks
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.80 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.80 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.20 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 1 [019..02B) i label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 1 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 0.80 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 0.80 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.20 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 1 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
Enter blocks: BB01
After computing reachability sets:
------------------------------------------------
BBnum Reachable by
------------------------------------------------
BB01 : BB01
BB02 : BB01 BB02
BB03 : BB01 BB02 BB03
BB04 : BB01 BB02 BB04
BB05 : BB01 BB02 BB03 BB04 BB05
BB06 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11
BB07 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11
BB08 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11
BB09 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11
BB10 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11
BB11 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11
BB12 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12
After computing reachability:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.80 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.80 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.20 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 1 [019..02B) i Loop label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 1 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 0.80 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 0.80 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.20 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 1 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgComputeDoms
*************** In fgDebugCheckBBlist
Dominator computation start blocks (those blocks with no incoming edges):
BB01
------------------------------------------------
BBnum Dominated by
------------------------------------------------
BB01: BB01
BB02: BB02 BB01
BB03: BB03 BB02 BB01
BB04: BB04 BB01
BB05: BB05 BB01
BB07: BB07 BB05 BB01
BB08: BB08 BB07 BB05 BB01
BB09: BB09 BB08 BB07 BB05 BB01
BB10: BB10 BB07 BB05 BB01
BB11: BB11 BB07 BB05 BB01
BB12: BB12 BB11 BB07 BB05 BB01
BB06: BB06 BB11 BB07 BB05 BB01
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB05 BB04 BB02
BB02 : BB03
BB05 : BB07
BB07 : BB11 BB10 BB08
BB08 : BB09
BB11 : BB12 BB06
After numbering the dominator tree:
BB01: pre=01, post=12
BB02: pre=11, post=11
BB03: pre=12, post=10
BB04: pre=10, post=09
BB05: pre=02, post=08
BB06: pre=06, post=02
BB07: pre=03, post=07
BB08: pre=08, post=06
BB09: pre=09, post=05
BB10: pre=07, post=04
BB11: pre=04, post=03
BB12: pre=05, post=01
*************** Finishing PHASE Compute blocks reachability
*************** Starting PHASE Optimize loops
*************** In optOptimizeLoops()
After optSetBlockWeights:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 0.50 [019..02B) i Loop label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 1 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 0.40 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 0.40 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.10 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 1 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In optFindNaturalLoops()
Recorded loop L00, from BB06 to BB11 (Head=BB05, Entry=BB07, ExitCnt=1 at BB11) [over V03 (ADD 1 ) from 0LTV13 ]
Final natural loop table:
L00, from BB06 to BB11 (Head=BB05, Entry=BB07, ExitCnt=1 at BB11)
Marking a loop from BB06 to BB11
BB06(wt=2 )
BB07(wt=8 )
BB08(wt=1.60)
BB09(wt=1.60)
BB10(wt=0.40)
BB11(wt=8 )
Found a total of 1 loops.
After loop weight marking:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Optimize loops
*************** Starting PHASE Clone loops
*************** In optCloneLoops()
Blocks/Trees at start of phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
***** BB01
STMT00000 (IL 0x000...0x003)
[000004] -A---+------ * ASG ref
[000000] D----+-N---- +--* LCL_VAR ref V01 loc0
[000002] -----+------ \--* CNS_INT ref null
***** BB01
STMT00002 (IL 0x008...0x016)
[000015] -A-XG+------ * ASG ref
[000014] D----+-N---- +--* LCL_VAR ref V06 tmp2
[000008] ---XG+------ \--* IND ref
[000135] -----+------ \--* ADD byref
[000007] -----+------ +--* LCL_VAR ref V00 this
[000134] -----+------ \--* CNS_INT long 16 field offset Fseq[_array]
***** BB01
STMT00001 (IL 0x008... ???)
[000013] -A---+------ * ASG long
[000012] D----+-N---- +--* LCL_VAR long V05 tmp1
[000011] #----+------ \--* IND long
[000010] !----+------ \--* LCL_VAR ref V00 this
***** BB01
STMT00003 (IL ???... ???)
[000024] -A---+------ * ASG long
[000023] D----+-N---- +--* LCL_VAR long V07 tmp3
[000022] n----+------ \--* IND long
[000021] #----+------ \--* IND long
[000020] -----+------ \--* ADD long
[000018] -----+------ +--* LCL_VAR long V05 tmp1
[000019] -----+------ \--* CNS_INT long 56
***** BB01
STMT00015 (IL ???... ???)
[000115] ---X-+------ * JTRUE void
[000042] J--X-+-N---- \--* LE int
[000040] ---X-+------ +--* IND long
[000039] -----+------ | \--* ADD long
[000026] -----+------ | +--* LCL_VAR long V07 tmp3
[000038] -----+------ | \--* CNS_INT long 8
[000041] -----+------ \--* CNS_INT long 96
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00016 (IL ???... ???)
[000116] -----+------ * JTRUE void
[000033] J----+-N---- \--* EQ int
[000029] n----+------ +--* IND long
[000028] -----+------ | \--* ADD long
[000025] -----+------ | +--* LCL_VAR long V07 tmp3
[000027] -----+------ | \--* CNS_INT long 96
[000032] -----+------ \--* CNS_INT long 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00017 (IL ???... ???)
[000118] -A---+------ * ASG long
[000117] D----+-N---- +--* LCL_VAR long V08 tmp4
[000034] n----+------ \--* IND long
[000035] -----+------ \--* ADD long
[000036] -----+------ +--* LCL_VAR long V07 tmp3
[000037] -----+------ \--* CNS_INT long 96
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
***** BB04
STMT00018 (IL ???... ???)
[000120] -AC-G+------ * ASG long
[000119] D----+-N---- +--* LCL_VAR long V08 tmp4
[000031] --C-G+------ \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000017] -----+------ arg0 in rcx +--* LCL_VAR long V05 tmp1
[000030] -----+------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
***** BB05
STMT00005 (IL ???... ???)
[000009] --CXG+------ * CALL void System.Span`1[__Canon][System.__Canon]..ctor
[000006] -----+------ this in rcx +--* ADDR byref
[000005] ----G+-N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9
[000045] -----+------ arg1 in rdx +--* LCL_VAR long V08 tmp4
[000016] -----+------ arg2 in r8 \--* LCL_VAR ref V06 tmp2
***** BB05
STMT00006 (IL 0x015... ???)
[000049] -A---+------ * ASG int
[000048] D----+-N---- +--* LCL_VAR int V03 loc2
[000047] -----+------ \--* CNS_INT int 0
------------ BB06 [019..02B), preds={BB11} succs={BB07}
***** BB06
STMT00012 (IL 0x019...0x022)
[000107] IA-XG+------ * ASG struct (init)
[000106] ---XG+-N---- +--* BLK struct<8>
[000104] ---XG+------ | \--* COMMA byref
[000098] ---XG+------ | +--* ARR_BOUNDS_CHECK_Rng void
[000093] -----+------ | | +--* LCL_VAR int V03 loc2
[000097] ----G+------ | | \--* LCL_VAR int (AX) V13 tmp9
[000103] ----G+------ | \--* ADD byref
[000102] ----G+------ | +--* LCL_VAR byref (AX) V12 tmp8
[000101] -----+------ | \--* LSH long
[000099] -----+------ | +--* CAST long <- int
[000094] -----+------ | | \--* LCL_VAR int V03 loc2
[000100] -----+------ | \--* CNS_INT int 3
[000105] -----+------ \--* CNS_INT int 0
***** BB06
STMT00013 (IL 0x027...0x02A)
[000112] -A---+------ * ASG int
[000111] D----+-N---- +--* LCL_VAR int V03 loc2
[000110] -----+------ \--* ADD int
[000108] -----+------ +--* LCL_VAR int V03 loc2
[000109] -----+------ \--* CNS_INT int 1
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
***** BB07
STMT00007 (IL 0x02B...0x033)
[000057] -A-X-+------ * ASG long
[000056] D----+-N---- +--* LCL_VAR long V09 tmp5
[000055] #--X-+------ \--* IND long
[000054] !----+------ \--* LCL_VAR ref V00 this
***** BB07
STMT00008 (IL ???... ???)
[000065] -A---+------ * ASG long
[000064] D----+-N---- +--* LCL_VAR long V10 tmp6
[000063] n----+------ \--* IND long
[000062] #----+------ \--* IND long
[000061] -----+------ \--* ADD long
[000059] -----+------ +--* LCL_VAR long V09 tmp5
[000060] -----+------ \--* CNS_INT long 56
***** BB07
STMT00019 (IL ???... ???)
[000121] ---X-+------ * JTRUE void
[000083] J--X-+-N---- \--* LE int
[000081] ---X-+------ +--* IND long
[000080] -----+------ | \--* ADD long
[000067] -----+------ | +--* LCL_VAR long V10 tmp6
[000079] -----+------ | \--* CNS_INT long 8
[000082] -----+------ \--* CNS_INT long 96
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
***** BB08
STMT00020 (IL ???... ???)
[000122] -----+------ * JTRUE void
[000074] J----+-N---- \--* EQ int
[000070] n----+------ +--* IND long
[000069] -----+------ | \--* ADD long
[000066] -----+------ | +--* LCL_VAR long V10 tmp6
[000068] -----+------ | \--* CNS_INT long 96
[000073] -----+------ \--* CNS_INT long 0
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
***** BB09
STMT00021 (IL ???... ???)
[000124] -A---+------ * ASG long
[000123] D----+-N---- +--* LCL_VAR long V11 tmp7
[000075] n----+------ \--* IND long
[000076] -----+------ \--* ADD long
[000077] -----+------ +--* LCL_VAR long V10 tmp6
[000078] -----+------ \--* CNS_INT long 96
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
***** BB10
STMT00022 (IL ???... ???)
[000126] -AC-G+------ * ASG long
[000125] D----+-N---- +--* LCL_VAR long V11 tmp7
[000072] --C-G+------ \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000058] -----+------ arg0 in rcx +--* LCL_VAR long V09 tmp5
[000071] -----+------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
***** BB11
STMT00011 (IL ???... ???)
[000090] ----G+------ * JTRUE void
[000089] J---G+-N---- \--* LT int
[000050] -----+------ +--* LCL_VAR int V03 loc2
[000132] ----G+------ \--* LCL_VAR int (AX) V13 tmp9
------------ BB12 [035..037) (return), preds={BB11} succs={}
***** BB12
STMT00014 (IL 0x035...0x036)
[000114] -----+------ * RETURN ref
[000113] -----+------ \--* LCL_VAR ref V01 loc0
-------------------------------------------------------------------------------------------------------------------
Considering loop 0 to clone for optimizations.
> Loop inversion NOT present, loop test [000089] may not protect entry from head.
------------------------------------------------------------
After loop cloning:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
***** BB01
STMT00000 (IL 0x000...0x003)
[000004] -A---+------ * ASG ref
[000000] D----+-N---- +--* LCL_VAR ref V01 loc0
[000002] -----+------ \--* CNS_INT ref null
***** BB01
STMT00002 (IL 0x008...0x016)
[000015] -A-XG+------ * ASG ref
[000014] D----+-N---- +--* LCL_VAR ref V06 tmp2
[000008] ---XG+------ \--* IND ref
[000135] -----+------ \--* ADD byref
[000007] -----+------ +--* LCL_VAR ref V00 this
[000134] -----+------ \--* CNS_INT long 16 field offset Fseq[_array]
***** BB01
STMT00001 (IL 0x008... ???)
[000013] -A---+------ * ASG long
[000012] D----+-N---- +--* LCL_VAR long V05 tmp1
[000011] #----+------ \--* IND long
[000010] !----+------ \--* LCL_VAR ref V00 this
***** BB01
STMT00003 (IL ???... ???)
[000024] -A---+------ * ASG long
[000023] D----+-N---- +--* LCL_VAR long V07 tmp3
[000022] n----+------ \--* IND long
[000021] #----+------ \--* IND long
[000020] -----+------ \--* ADD long
[000018] -----+------ +--* LCL_VAR long V05 tmp1
[000019] -----+------ \--* CNS_INT long 56
***** BB01
STMT00015 (IL ???... ???)
[000115] ---X-+------ * JTRUE void
[000042] J--X-+-N---- \--* LE int
[000040] ---X-+------ +--* IND long
[000039] -----+------ | \--* ADD long
[000026] -----+------ | +--* LCL_VAR long V07 tmp3
[000038] -----+------ | \--* CNS_INT long 8
[000041] -----+------ \--* CNS_INT long 96
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00016 (IL ???... ???)
[000116] -----+------ * JTRUE void
[000033] J----+-N---- \--* EQ int
[000029] n----+------ +--* IND long
[000028] -----+------ | \--* ADD long
[000025] -----+------ | +--* LCL_VAR long V07 tmp3
[000027] -----+------ | \--* CNS_INT long 96
[000032] -----+------ \--* CNS_INT long 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00017 (IL ???... ???)
[000118] -A---+------ * ASG long
[000117] D----+-N---- +--* LCL_VAR long V08 tmp4
[000034] n----+------ \--* IND long
[000035] -----+------ \--* ADD long
[000036] -----+------ +--* LCL_VAR long V07 tmp3
[000037] -----+------ \--* CNS_INT long 96
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
***** BB04
STMT00018 (IL ???... ???)
[000120] -AC-G+------ * ASG long
[000119] D----+-N---- +--* LCL_VAR long V08 tmp4
[000031] --C-G+------ \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000017] -----+------ arg0 in rcx +--* LCL_VAR long V05 tmp1
[000030] -----+------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
***** BB05
STMT00005 (IL ???... ???)
[000009] --CXG+------ * CALL void System.Span`1[__Canon][System.__Canon]..ctor
[000006] -----+------ this in rcx +--* ADDR byref
[000005] ----G+-N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9
[000045] -----+------ arg1 in rdx +--* LCL_VAR long V08 tmp4
[000016] -----+------ arg2 in r8 \--* LCL_VAR ref V06 tmp2
***** BB05
STMT00006 (IL 0x015... ???)
[000049] -A---+------ * ASG int
[000048] D----+-N---- +--* LCL_VAR int V03 loc2
[000047] -----+------ \--* CNS_INT int 0
------------ BB06 [019..02B), preds={BB11} succs={BB07}
***** BB06
STMT00012 (IL 0x019...0x022)
[000107] IA-XG+------ * ASG struct (init)
[000106] ---XG+-N---- +--* BLK struct<8>
[000104] ---XG+------ | \--* COMMA byref
[000098] ---XG+------ | +--* ARR_BOUNDS_CHECK_Rng void
[000093] -----+------ | | +--* LCL_VAR int V03 loc2
[000097] ----G+------ | | \--* LCL_VAR int (AX) V13 tmp9
[000103] ----G+------ | \--* ADD byref
[000102] ----G+------ | +--* LCL_VAR byref (AX) V12 tmp8
[000101] -----+------ | \--* LSH long
[000099] -----+------ | +--* CAST long <- int
[000094] -----+------ | | \--* LCL_VAR int V03 loc2
[000100] -----+------ | \--* CNS_INT int 3
[000105] -----+------ \--* CNS_INT int 0
***** BB06
STMT00013 (IL 0x027...0x02A)
[000112] -A---+------ * ASG int
[000111] D----+-N---- +--* LCL_VAR int V03 loc2
[000110] -----+------ \--* ADD int
[000108] -----+------ +--* LCL_VAR int V03 loc2
[000109] -----+------ \--* CNS_INT int 1
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
***** BB07
STMT00007 (IL 0x02B...0x033)
[000057] -A-X-+------ * ASG long
[000056] D----+-N---- +--* LCL_VAR long V09 tmp5
[000055] #--X-+------ \--* IND long
[000054] !----+------ \--* LCL_VAR ref V00 this
***** BB07
STMT00008 (IL ???... ???)
[000065] -A---+------ * ASG long
[000064] D----+-N---- +--* LCL_VAR long V10 tmp6
[000063] n----+------ \--* IND long
[000062] #----+------ \--* IND long
[000061] -----+------ \--* ADD long
[000059] -----+------ +--* LCL_VAR long V09 tmp5
[000060] -----+------ \--* CNS_INT long 56
***** BB07
STMT00019 (IL ???... ???)
[000121] ---X-+------ * JTRUE void
[000083] J--X-+-N---- \--* LE int
[000081] ---X-+------ +--* IND long
[000080] -----+------ | \--* ADD long
[000067] -----+------ | +--* LCL_VAR long V10 tmp6
[000079] -----+------ | \--* CNS_INT long 8
[000082] -----+------ \--* CNS_INT long 96
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
***** BB08
STMT00020 (IL ???... ???)
[000122] -----+------ * JTRUE void
[000074] J----+-N---- \--* EQ int
[000070] n----+------ +--* IND long
[000069] -----+------ | \--* ADD long
[000066] -----+------ | +--* LCL_VAR long V10 tmp6
[000068] -----+------ | \--* CNS_INT long 96
[000073] -----+------ \--* CNS_INT long 0
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
***** BB09
STMT00021 (IL ???... ???)
[000124] -A---+------ * ASG long
[000123] D----+-N---- +--* LCL_VAR long V11 tmp7
[000075] n----+------ \--* IND long
[000076] -----+------ \--* ADD long
[000077] -----+------ +--* LCL_VAR long V10 tmp6
[000078] -----+------ \--* CNS_INT long 96
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
***** BB10
STMT00022 (IL ???... ???)
[000126] -AC-G+------ * ASG long
[000125] D----+-N---- +--* LCL_VAR long V11 tmp7
[000072] --C-G+------ \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000058] -----+------ arg0 in rcx +--* LCL_VAR long V09 tmp5
[000071] -----+------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
***** BB11
STMT00011 (IL ???... ???)
[000090] ----G+------ * JTRUE void
[000089] J---G+-N---- \--* LT int
[000050] -----+------ +--* LCL_VAR int V03 loc2
[000132] ----G+------ \--* LCL_VAR int (AX) V13 tmp9
------------ BB12 [035..037) (return), preds={BB11} succs={}
***** BB12
STMT00014 (IL 0x035...0x036)
[000114] -----+------ * RETURN ref
[000113] -----+------ \--* LCL_VAR ref V01 loc0
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Clone loops
*************** Starting PHASE Unroll loops
*************** In optUnrollLoops()
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Unroll loops
*************** Starting PHASE Mark local vars
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
*** marking local variables in block BB01 (weight=1 )
STMT00000 (IL 0x000...0x003)
[000004] -A---+------ * ASG ref
[000000] D----+-N---- +--* LCL_VAR ref V01 loc0
[000002] -----+------ \--* CNS_INT ref null
New refCnts for V01: refCnt = 1, refCntWtd = 1
STMT00002 (IL 0x008...0x016)
[000015] -A-XG+------ * ASG ref
[000014] D----+-N---- +--* LCL_VAR ref V06 tmp2
[000008] ---XG+------ \--* IND ref
[000135] -----+------ \--* ADD byref
[000007] -----+------ +--* LCL_VAR ref V00 this
[000134] -----+------ \--* CNS_INT long 16 field offset Fseq[_array]
New refCnts for V06: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 1, refCntWtd = 1
STMT00001 (IL 0x008... ???)
[000013] -A---+------ * ASG long
[000012] D----+-N---- +--* LCL_VAR long V05 tmp1
[000011] #----+------ \--* IND long
[000010] !----+------ \--* LCL_VAR ref V00 this
New refCnts for V05: refCnt = 1, refCntWtd = 2
-- generic context in use at [000010]
New refCnts for V00: refCnt = 2, refCntWtd = 2
STMT00003 (IL ???... ???)
[000024] -A---+------ * ASG long
[000023] D----+-N---- +--* LCL_VAR long V07 tmp3
[000022] n----+------ \--* IND long
[000021] #----+------ \--* IND long
[000020] -----+------ \--* ADD long
[000018] -----+------ +--* LCL_VAR long V05 tmp1
[000019] -----+------ \--* CNS_INT long 56
New refCnts for V07: refCnt = 1, refCntWtd = 2
New refCnts for V05: refCnt = 2, refCntWtd = 4
STMT00015 (IL ???... ???)
[000115] ---X-+------ * JTRUE void
[000042] J--X-+-N---- \--* LE int
[000040] ---X-+------ +--* IND long
[000039] -----+------ | \--* ADD long
[000026] -----+------ | +--* LCL_VAR long V07 tmp3
[000038] -----+------ | \--* CNS_INT long 8
[000041] -----+------ \--* CNS_INT long 96
New refCnts for V07: refCnt = 2, refCntWtd = 4
*** marking local variables in block BB02 (weight=0.40)
STMT00016 (IL ???... ???)
[000116] -----+------ * JTRUE void
[000033] J----+-N---- \--* EQ int
[000029] n----+------ +--* IND long
[000028] -----+------ | \--* ADD long
[000025] -----+------ | +--* LCL_VAR long V07 tmp3
[000027] -----+------ | \--* CNS_INT long 96
[000032] -----+------ \--* CNS_INT long 0
New refCnts for V07: refCnt = 3, refCntWtd = 4.80
*** marking local variables in block BB03 (weight=0.40)
STMT00017 (IL ???... ???)
[000118] -A---+------ * ASG long
[000117] D----+-N---- +--* LCL_VAR long V08 tmp4
[000034] n----+------ \--* IND long
[000035] -----+------ \--* ADD long
[000036] -----+------ +--* LCL_VAR long V07 tmp3
[000037] -----+------ \--* CNS_INT long 96
New refCnts for V08: refCnt = 1, refCntWtd = 0.80
New refCnts for V07: refCnt = 4, refCntWtd = 5.60
*** marking local variables in block BB04 (weight=0.10)
STMT00018 (IL ???... ???)
[000120] -AC-G+------ * ASG long
[000119] D----+-N---- +--* LCL_VAR long V08 tmp4
[000031] --C-G+------ \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000017] -----+------ arg0 in rcx +--* LCL_VAR long V05 tmp1
[000030] -----+------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
New refCnts for V08: refCnt = 2, refCntWtd = 1
New refCnts for V05: refCnt = 3, refCntWtd = 4.20
*** marking local variables in block BB05 (weight=1 )
STMT00005 (IL ???... ???)
[000009] --CXG+------ * CALL void System.Span`1[__Canon][System.__Canon]..ctor
[000006] -----+------ this in rcx +--* ADDR byref
[000005] ----G+-N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9
[000045] -----+------ arg1 in rdx +--* LCL_VAR long V08 tmp4
[000016] -----+------ arg2 in r8 \--* LCL_VAR ref V06 tmp2
New refCnts for V12: refCnt = 1, refCntWtd = 1
New refCnts for V13: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V08: refCnt = 3, refCntWtd = 3
New refCnts for V06: refCnt = 2, refCntWtd = 4
STMT00006 (IL 0x015... ???)
[000049] -A---+------ * ASG int
[000048] D----+-N---- +--* LCL_VAR int V03 loc2
[000047] -----+------ \--* CNS_INT int 0
New refCnts for V03: refCnt = 1, refCntWtd = 1
*** marking local variables in block BB06 (weight=2 )
STMT00012 (IL 0x019...0x022)
[000107] IA-XG+------ * ASG struct (init)
[000106] ---XG+-N---- +--* BLK struct<8>
[000104] ---XG+------ | \--* COMMA byref
[000098] ---XG+------ | +--* ARR_BOUNDS_CHECK_Rng void
[000093] -----+------ | | +--* LCL_VAR int V03 loc2
[000097] ----G+------ | | \--* LCL_VAR int (AX) V13 tmp9
[000103] ----G+------ | \--* ADD byref
[000102] ----G+------ | +--* LCL_VAR byref (AX) V12 tmp8
[000101] -----+------ | \--* LSH long
[000099] -----+------ | +--* CAST long <- int
[000094] -----+------ | | \--* LCL_VAR int V03 loc2
[000100] -----+------ | \--* CNS_INT int 3
[000105] -----+------ \--* CNS_INT int 0
New refCnts for V03: refCnt = 2, refCntWtd = 3
New refCnts for V02: refCnt = 2, refCntWtd = 3
New refCnts for V13: refCnt = 2, refCntWtd = 3
New refCnts for V02: refCnt = 3, refCntWtd = 5
New refCnts for V12: refCnt = 2, refCntWtd = 3
New refCnts for V03: refCnt = 3, refCntWtd = 5
STMT00013 (IL 0x027...0x02A)
[000112] -A---+------ * ASG int
[000111] D----+-N---- +--* LCL_VAR int V03 loc2
[000110] -----+------ \--* ADD int
[000108] -----+------ +--* LCL_VAR int V03 loc2
[000109] -----+------ \--* CNS_INT int 1
New refCnts for V03: refCnt = 4, refCntWtd = 7
New refCnts for V03: refCnt = 5, refCntWtd = 9
*** marking local variables in block BB07 (weight=8 )
STMT00007 (IL 0x02B...0x033)
[000057] -A-X-+------ * ASG long
[000056] D----+-N---- +--* LCL_VAR long V09 tmp5
[000055] #--X-+------ \--* IND long
[000054] !----+------ \--* LCL_VAR ref V00 this
New refCnts for V09: refCnt = 1, refCntWtd = 16
New refCnts for V00: refCnt = 3, refCntWtd = 10
STMT00008 (IL ???... ???)
[000065] -A---+------ * ASG long
[000064] D----+-N---- +--* LCL_VAR long V10 tmp6
[000063] n----+------ \--* IND long
[000062] #----+------ \--* IND long
[000061] -----+------ \--* ADD long
[000059] -----+------ +--* LCL_VAR long V09 tmp5
[000060] -----+------ \--* CNS_INT long 56
New refCnts for V10: refCnt = 1, refCntWtd = 16
New refCnts for V09: refCnt = 2, refCntWtd = 32
STMT00019 (IL ???... ???)
[000121] ---X-+------ * JTRUE void
[000083] J--X-+-N---- \--* LE int
[000081] ---X-+------ +--* IND long
[000080] -----+------ | \--* ADD long
[000067] -----+------ | +--* LCL_VAR long V10 tmp6
[000079] -----+------ | \--* CNS_INT long 8
[000082] -----+------ \--* CNS_INT long 96
New refCnts for V10: refCnt = 2, refCntWtd = 32
*** marking local variables in block BB08 (weight=1.60)
STMT00020 (IL ???... ???)
[000122] -----+------ * JTRUE void
[000074] J----+-N---- \--* EQ int
[000070] n----+------ +--* IND long
[000069] -----+------ | \--* ADD long
[000066] -----+------ | +--* LCL_VAR long V10 tmp6
[000068] -----+------ | \--* CNS_INT long 96
[000073] -----+------ \--* CNS_INT long 0
New refCnts for V10: refCnt = 3, refCntWtd = 35.20
*** marking local variables in block BB09 (weight=1.60)
STMT00021 (IL ???... ???)
[000124] -A---+------ * ASG long
[000123] D----+-N---- +--* LCL_VAR long V11 tmp7
[000075] n----+------ \--* IND long
[000076] -----+------ \--* ADD long
[000077] -----+------ +--* LCL_VAR long V10 tmp6
[000078] -----+------ \--* CNS_INT long 96
New refCnts for V11: refCnt = 1, refCntWtd = 3.20
New refCnts for V10: refCnt = 4, refCntWtd = 38.40
*** marking local variables in block BB10 (weight=0.40)
STMT00022 (IL ???... ???)
[000126] -AC-G+------ * ASG long
[000125] D----+-N---- +--* LCL_VAR long V11 tmp7
[000072] --C-G+------ \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
[000058] -----+------ arg0 in rcx +--* LCL_VAR long V09 tmp5
[000071] -----+------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
New refCnts for V11: refCnt = 2, refCntWtd = 4
New refCnts for V09: refCnt = 3, refCntWtd = 32.80
*** marking local variables in block BB11 (weight=8 )
STMT00011 (IL ???... ???)
[000090] ----G+------ * JTRUE void
[000089] J---G+-N---- \--* LT int
[000050] -----+------ +--* LCL_VAR int V03 loc2
[000132] ----G+------ \--* LCL_VAR int (AX) V13 tmp9
New refCnts for V03: refCnt = 6, refCntWtd = 17
New refCnts for V02: refCnt = 4, refCntWtd = 13
New refCnts for V13: refCnt = 3, refCntWtd = 11
*** marking local variables in block BB12 (weight=1 )
STMT00014 (IL 0x035...0x036)
[000114] -----+------ * RETURN ref
[000113] -----+------ \--* LCL_VAR ref V01 loc0
New refCnts for V01: refCnt = 2, refCntWtd = 2
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 4, refCntWtd = 11
New refCnts for V00: refCnt = 5, refCntWtd = 12
Reporting this as generic context: referenced
*************** In optAddCopies()
*************** Finishing PHASE Mark local vars
*************** Starting PHASE Optimize bools
*************** In optOptimizeBools()
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Optimize bools
*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()
*************** Finishing PHASE Find oper order
*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
fgMarkLoopHead: Checking loop head block BB06: no guaranteed callsite exits, marking method as fully interruptible
The biggest BB has 13 tree nodes
*************** Finishing PHASE Set block order
Trees before Build SSA representation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
***** BB01
STMT00000 (IL 0x000...0x003)
N003 ( 5, 4) [000004] -A------R--- * ASG ref
N002 ( 3, 2) [000000] D------N---- +--* LCL_VAR ref V01 loc0
N001 ( 1, 1) [000002] ------------ \--* CNS_INT ref null
***** BB01
STMT00002 (IL 0x008...0x016)
N006 ( 4, 4) [000015] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000014] D------N---- +--* LCL_VAR ref V06 tmp2
N004 ( 4, 4) [000008] ---XG------- \--* IND ref
N003 ( 2, 2) [000135] -------N---- \--* ADD byref
N001 ( 1, 1) [000007] ------------ +--* LCL_VAR ref V00 this
N002 ( 1, 1) [000134] ------------ \--* CNS_INT long 16 field offset Fseq[_array]
***** BB01
STMT00001 (IL 0x008... ???)
N004 ( 3, 3) [000013] -A---O--R--- * ASG long
N003 ( 1, 1) [000012] D------N---- +--* LCL_VAR long V05 tmp1
N002 ( 3, 2) [000011] #----O------ \--* IND long
N001 ( 1, 1) [000010] !----------- \--* LCL_VAR ref V00 this
***** BB01
STMT00003 (IL ???... ???)
N007 ( 7, 6) [000024] -A------R--- * ASG long
N006 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3
N005 ( 7, 6) [000022] n----------- \--* IND long
N004 ( 4, 4) [000021] #----------- \--* IND long
N003 ( 2, 2) [000020] -------N---- \--* ADD long
N001 ( 1, 1) [000018] ------------ +--* LCL_VAR long V05 tmp1
N002 ( 1, 1) [000019] ------------ \--* CNS_INT long 56
***** BB01
STMT00015 (IL ???... ???)
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
N006 ( 6, 6) [000042] J--X---N---- \--* LE int
N004 ( 4, 4) [000040] ---X-------- +--* IND long
N003 ( 2, 2) [000039] -------N---- | \--* ADD long
N001 ( 1, 1) [000026] ------------ | +--* LCL_VAR long V07 tmp3
N002 ( 1, 1) [000038] ------------ | \--* CNS_INT long 8
N005 ( 1, 1) [000041] ------------ \--* CNS_INT long 96
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00016 (IL ???... ???)
N007 ( 8, 8) [000116] ------------ * JTRUE void
N006 ( 6, 6) [000033] J------N---- \--* EQ int
N004 ( 4, 4) [000029] n----------- +--* IND long
N003 ( 2, 2) [000028] -------N---- | \--* ADD long
N001 ( 1, 1) [000025] ------------ | +--* LCL_VAR long V07 tmp3
N002 ( 1, 1) [000027] ------------ | \--* CNS_INT long 96
N005 ( 1, 1) [000032] ------------ \--* CNS_INT long 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00017 (IL ???... ???)
N006 ( 4, 4) [000118] -A------R--- * ASG long
N005 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4
N004 ( 4, 4) [000034] n----------- \--* IND long
N003 ( 2, 2) [000035] -------N---- \--* ADD long
N001 ( 1, 1) [000036] ------------ +--* LCL_VAR long V07 tmp3
N002 ( 1, 1) [000037] ------------ \--* CNS_INT long 96
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
***** BB04
STMT00018 (IL ???... ???)
N007 ( 17, 18) [000120] -AC-G---R--- * ASG long
N006 ( 1, 1) [000119] D------N---- +--* LCL_VAR long V08 tmp4
N005 ( 17, 18) [000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000017] ------------ arg0 in rcx +--* LCL_VAR long V05 tmp1
N004 ( 2, 10) [000030] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
***** BB05
STMT00005 (IL ???... ???)
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor
N005 ( 3, 3) [000006] ------------ this in rcx +--* ADDR byref
N004 ( 3, 2) [000005] ----G--N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9
N006 ( 1, 1) [000045] ------------ arg1 in rdx +--* LCL_VAR long V08 tmp4
N007 ( 1, 1) [000016] ------------ arg2 in r8 \--* LCL_VAR ref V06 tmp2
***** BB05
STMT00006 (IL 0x015... ???)
N003 ( 1, 3) [000049] -A------R--- * ASG int
N002 ( 1, 1) [000048] D------N---- +--* LCL_VAR int V03 loc2
N001 ( 1, 1) [000047] ------------ \--* CNS_INT int 0
------------ BB06 [019..02B), preds={BB11} succs={BB07}
***** BB06
STMT00012 (IL 0x019...0x022)
N013 ( 21, 22) [000107] IA-XG------- * ASG struct (init)
N011 ( 19, 20) [000106] ---XG--N---- +--* BLK struct<8>
N010 ( 16, 18) [000104] ---XG------- | \--* COMMA byref
N003 ( 8, 10) [000098] ---XG------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000093] ------------ | | +--* LCL_VAR int V03 loc2
N002 ( 3, 2) [000097] ----G------- | | \--* LCL_VAR int (AX) V13 tmp9
N009 ( 8, 8) [000103] ----G------- | \--* ADD byref
N004 ( 3, 2) [000102] ----G------- | +--* LCL_VAR byref (AX) V12 tmp8
N008 ( 4, 5) [000101] ------------ | \--* LSH long
N006 ( 2, 3) [000099] ------------ | +--* CAST long <- int
N005 ( 1, 1) [000094] ------------ | | \--* LCL_VAR int V03 loc2
N007 ( 1, 1) [000100] ------------ | \--* CNS_INT int 3
N012 ( 1, 1) [000105] ------------ \--* CNS_INT int 0
***** BB06
STMT00013 (IL 0x027...0x02A)
N005 ( 3, 3) [000112] -A------R--- * ASG int
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2
N003 ( 3, 3) [000110] ------------ \--* ADD int
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
***** BB07
STMT00007 (IL 0x02B...0x033)
N004 ( 3, 3) [000057] -A-X----R--- * ASG long
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5
N002 ( 3, 2) [000055] #--X-------- \--* IND long
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this
***** BB07
STMT00008 (IL ???... ???)
N007 ( 7, 6) [000065] -A------R--- * ASG long
N006 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6
N005 ( 7, 6) [000063] n----------- \--* IND long
N004 ( 4, 4) [000062] #----------- \--* IND long
N003 ( 2, 2) [000061] -------N---- \--* ADD long
N001 ( 1, 1) [000059] ------------ +--* LCL_VAR long V09 tmp5
N002 ( 1, 1) [000060] ------------ \--* CNS_INT long 56
***** BB07
STMT00019 (IL ???... ???)
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
N006 ( 6, 6) [000083] J--X---N---- \--* LE int
N004 ( 4, 4) [000081] ---X-------- +--* IND long
N003 ( 2, 2) [000080] -------N---- | \--* ADD long
N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR long V10 tmp6
N002 ( 1, 1) [000079] ------------ | \--* CNS_INT long 8
N005 ( 1, 1) [000082] ------------ \--* CNS_INT long 96
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
***** BB08
STMT00020 (IL ???... ???)
N007 ( 8, 8) [000122] ------------ * JTRUE void
N006 ( 6, 6) [000074] J------N---- \--* EQ int
N004 ( 4, 4) [000070] n----------- +--* IND long
N003 ( 2, 2) [000069] -------N---- | \--* ADD long
N001 ( 1, 1) [000066] ------------ | +--* LCL_VAR long V10 tmp6
N002 ( 1, 1) [000068] ------------ | \--* CNS_INT long 96
N005 ( 1, 1) [000073] ------------ \--* CNS_INT long 0
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
***** BB09
STMT00021 (IL ???... ???)
N006 ( 4, 4) [000124] -A------R--- * ASG long
N005 ( 1, 1) [000123] D------N---- +--* LCL_VAR long V11 tmp7
N004 ( 4, 4) [000075] n----------- \--* IND long
N003 ( 2, 2) [000076] -------N---- \--* ADD long
N001 ( 1, 1) [000077] ------------ +--* LCL_VAR long V10 tmp6
N002 ( 1, 1) [000078] ------------ \--* CNS_INT long 96
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
***** BB10
STMT00022 (IL ???... ???)
N007 ( 17, 18) [000126] -AC-G---R--- * ASG long
N006 ( 1, 1) [000125] D------N---- +--* LCL_VAR long V11 tmp7
N005 ( 17, 18) [000072] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000058] ------------ arg0 in rcx +--* LCL_VAR long V09 tmp5
N004 ( 2, 10) [000071] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
***** BB11
STMT00011 (IL ???... ???)
N004 ( 7, 6) [000090] ----G------- * JTRUE void
N003 ( 5, 4) [000089] J---G--N---- \--* LT int
N001 ( 1, 1) [000050] ------------ +--* LCL_VAR int V03 loc2
N002 ( 3, 2) [000132] ----G------- \--* LCL_VAR int (AX) V13 tmp9
------------ BB12 [035..037) (return), preds={BB11} succs={}
***** BB12
STMT00014 (IL 0x035...0x036)
N002 ( 4, 3) [000114] ------------ * RETURN ref
N001 ( 3, 2) [000113] ------------ \--* LCL_VAR ref V01 loc0
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Build SSA representation
*************** In SsaBuilder::Build()
[SsaBuilder] Max block count is 13.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
[SsaBuilder] Topologically sorted the graph.
[SsaBuilder::ComputeImmediateDom]
Inside fgBuildDomTree
After computing the Dominance Tree:
BB01 : BB05 BB04 BB02
BB02 : BB03
BB05 : BB07
BB07 : BB11 BB10 BB08
BB08 : BB09
BB11 : BB12 BB06
*************** In fgLocalVarLiveness()
In fgLocalVarLivenessInit
Tracked variable (10 out of 14) table:
V10 tmp6 [ long]: refCnt = 4, refCntWtd = 38.40
V09 tmp5 [ long]: refCnt = 3, refCntWtd = 32.80
V03 loc2 [ int]: refCnt = 6, refCntWtd = 17
V00 this [ ref]: refCnt = 5, refCntWtd = 12
V07 tmp3 [ long]: refCnt = 4, refCntWtd = 5.60
V05 tmp1 [ long]: refCnt = 3, refCntWtd = 4.20
V06 tmp2 [ ref]: refCnt = 2, refCntWtd = 4
V11 tmp7 [ long]: refCnt = 2, refCntWtd = 4
V08 tmp4 [ long]: refCnt = 3, refCntWtd = 3
V01 loc0 [ ref]: refCnt = 2, refCntWtd = 2
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 } + ByrefExposed + GcHeap
DEF(4)={ V07 V05 V06 V01}
BB02 USE(1)={V07} + ByrefExposed + GcHeap
DEF(0)={ }
BB03 USE(1)={V07 } + ByrefExposed + GcHeap
DEF(1)={ V08}
BB04 USE(1)={V05 }
DEF(1)={ V08}
BB05 USE(2)={ V06 V08} + ByrefExposed + GcHeap
DEF(1)={V03 } + ByrefExposed* + GcHeap*
BB06 USE(1)={V03} + ByrefExposed
DEF(1)={V03} + ByrefExposed + GcHeap
BB07 USE(1)={ V00} + ByrefExposed + GcHeap
DEF(2)={V10 V09 }
BB08 USE(1)={V10} + ByrefExposed + GcHeap
DEF(0)={ }
BB09 USE(1)={V10 } + ByrefExposed + GcHeap
DEF(1)={ V11}
BB10 USE(1)={V09 }
DEF(1)={ V11}
BB11 USE(1)={V03} + ByrefExposed
DEF(0)={ }
BB12 USE(1)={V01}
DEF(0)={ }
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
Reporting this as generic context: referenced
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00 } + ByrefExposed + GcHeap
OUT(5)={V00 V07 V05 V06 V01} + ByrefExposed + GcHeap
BB02 IN (5)={V00 V07 V05 V06 V01} + ByrefExposed + GcHeap
OUT(5)={V00 V07 V05 V06 V01} + ByrefExposed + GcHeap
BB03 IN (4)={V00 V07 V06 V01} + ByrefExposed + GcHeap
OUT(4)={V00 V06 V08 V01} + ByrefExposed + GcHeap
BB04 IN (4)={V00 V05 V06 V01} + ByrefExposed + GcHeap
OUT(4)={V00 V06 V08 V01} + ByrefExposed + GcHeap
BB05 IN (4)={ V00 V06 V08 V01} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V01} + ByrefExposed + GcHeap
BB06 IN (3)={V03 V00 V01} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V01} + ByrefExposed + GcHeap
BB07 IN (3)={ V03 V00 V01} + ByrefExposed + GcHeap
OUT(5)={V10 V09 V03 V00 V01} + ByrefExposed + GcHeap
BB08 IN (5)={V10 V09 V03 V00 V01} + ByrefExposed + GcHeap
OUT(5)={V10 V09 V03 V00 V01} + ByrefExposed + GcHeap
BB09 IN (4)={V10 V03 V00 V01} + ByrefExposed + GcHeap
OUT(3)={ V03 V00 V01} + ByrefExposed + GcHeap
BB10 IN (4)={V09 V03 V00 V01} + ByrefExposed + GcHeap
OUT(3)={ V03 V00 V01} + ByrefExposed + GcHeap
BB11 IN (3)={V03 V00 V01} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V01} + ByrefExposed + GcHeap
BB12 IN (2)={V00 V01}
OUT(1)={V00 }
top level assign
removing stmt with no side effects
Removing statement STMT00021 (IL ???... ???)
N006 ( 4, 4) [000124] -A------R--- * ASG long
N005 ( 1, 1) [000123] D------N---- +--* LCL_VAR long V11 tmp7
N004 ( 4, 4) [000075] n----------- \--* IND long
N003 ( 2, 2) [000076] -------N---- \--* ADD long
N001 ( 1, 1) [000077] ------------ +--* LCL_VAR long V10 tmp6
N002 ( 1, 1) [000078] ------------ \--* CNS_INT long 96
in BB09 as useless:
BB09 becomes empty
BB10 - Dead assignment has side effects...
N007 ( 17, 18) [000126] -AC-G---R--- * ASG long
N006 ( 1, 1) [000125] D------N---- +--* LCL_VAR long V11 tmp7
N005 ( 17, 18) [000072] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000058] ------------ arg0 in rcx +--* LCL_VAR long V09 tmp5
N004 ( 2, 10) [000071] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
top level assign
removing stmt with no side effects
Removing statement STMT00022 (IL ???... ???)
N007 ( 17, 18) [000126] -AC-G---R--- * ASG long
N006 ( 1, 1) [000125] D------N---- +--* LCL_VAR long V11 tmp7
N005 ( 17, 18) [000072] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000058] ------------ arg0 in rcx +--* LCL_VAR long V09 tmp5
N004 ( 2, 10) [000071] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
in BB10 as useless:
BB10 becomes empty
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 } + ByrefExposed + GcHeap
DEF(4)={ V07 V05 V06 V01}
BB02 USE(1)={V07} + ByrefExposed + GcHeap
DEF(0)={ }
BB03 USE(1)={V07 } + ByrefExposed + GcHeap
DEF(1)={ V08}
BB04 USE(1)={V05 }
DEF(1)={ V08}
BB05 USE(2)={ V06 V08} + ByrefExposed + GcHeap
DEF(1)={V03 } + ByrefExposed* + GcHeap*
BB06 USE(1)={V03} + ByrefExposed
DEF(1)={V03} + ByrefExposed + GcHeap
BB07 USE(1)={ V00} + ByrefExposed + GcHeap
DEF(2)={V10 V09 }
BB08 USE(1)={V10} + ByrefExposed + GcHeap
DEF(0)={ }
BB09 USE(0)={}
DEF(0)={}
BB10 USE(0)={}
DEF(0)={}
BB11 USE(1)={V03} + ByrefExposed
DEF(0)={ }
BB12 USE(1)={V01}
DEF(0)={ }
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
Reporting this as generic context: referenced
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00 } + ByrefExposed + GcHeap
OUT(5)={V00 V07 V05 V06 V01} + ByrefExposed + GcHeap
BB02 IN (5)={V00 V07 V05 V06 V01} + ByrefExposed + GcHeap
OUT(5)={V00 V07 V05 V06 V01} + ByrefExposed + GcHeap
BB03 IN (4)={V00 V07 V06 V01} + ByrefExposed + GcHeap
OUT(4)={V00 V06 V08 V01} + ByrefExposed + GcHeap
BB04 IN (4)={V00 V05 V06 V01} + ByrefExposed + GcHeap
OUT(4)={V00 V06 V08 V01} + ByrefExposed + GcHeap
BB05 IN (4)={ V00 V06 V08 V01} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V01} + ByrefExposed + GcHeap
BB06 IN (3)={V03 V00 V01} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V01} + ByrefExposed + GcHeap
BB07 IN (3)={ V03 V00 V01} + ByrefExposed + GcHeap
OUT(4)={V10 V03 V00 V01} + ByrefExposed + GcHeap
BB08 IN (4)={V10 V03 V00 V01} + ByrefExposed + GcHeap
OUT(3)={ V03 V00 V01} + ByrefExposed + GcHeap
BB09 IN (3)={V03 V00 V01} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V01} + ByrefExposed + GcHeap
BB10 IN (3)={V03 V00 V01} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V01} + ByrefExposed + GcHeap
BB11 IN (3)={V03 V00 V01} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V01} + ByrefExposed + GcHeap
BB12 IN (2)={V00 V01}
OUT(1)={V00 }
*************** In optRemoveRedundantZeroInits()
*************** In SsaBuilder::InsertPhiFunctions()
Inserting phi functions:
Added PHI definition for V03 at start of BB07.
Inserting phi definition for ByrefExposed at start of BB07.
Added PHI definition for V08 at start of BB05.
*************** In SsaBuilder::RenameVariables()
After fgSsaBuild:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
***** BB01
STMT00000 (IL 0x000...0x003)
N003 ( 5, 4) [000004] -A------R--- * ASG ref
N002 ( 3, 2) [000000] D------N---- +--* LCL_VAR ref V01 loc0 d:2
N001 ( 1, 1) [000002] ------------ \--* CNS_INT ref null
***** BB01
STMT00002 (IL 0x008...0x016)
N006 ( 4, 4) [000015] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000014] D------N---- +--* LCL_VAR ref V06 tmp2 d:2
N004 ( 4, 4) [000008] ---XG------- \--* IND ref
N003 ( 2, 2) [000135] -------N---- \--* ADD byref
N001 ( 1, 1) [000007] ------------ +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000134] ------------ \--* CNS_INT long 16 field offset Fseq[_array]
***** BB01
STMT00001 (IL 0x008... ???)
N004 ( 3, 3) [000013] -A---O--R--- * ASG long
N003 ( 1, 1) [000012] D------N---- +--* LCL_VAR long V05 tmp1 d:2
N002 ( 3, 2) [000011] #----O------ \--* IND long
N001 ( 1, 1) [000010] !----------- \--* LCL_VAR ref V00 this u:1
***** BB01
STMT00003 (IL ???... ???)
N007 ( 7, 6) [000024] -A------R--- * ASG long
N006 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3 d:2
N005 ( 7, 6) [000022] n----------- \--* IND long
N004 ( 4, 4) [000021] #----------- \--* IND long
N003 ( 2, 2) [000020] -------N---- \--* ADD long
N001 ( 1, 1) [000018] ------------ +--* LCL_VAR long V05 tmp1 u:2
N002 ( 1, 1) [000019] ------------ \--* CNS_INT long 56
***** BB01
STMT00015 (IL ???... ???)
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
N006 ( 6, 6) [000042] J--X---N---- \--* LE int
N004 ( 4, 4) [000040] ---X-------- +--* IND long
N003 ( 2, 2) [000039] -------N---- | \--* ADD long
N001 ( 1, 1) [000026] ------------ | +--* LCL_VAR long V07 tmp3 u:2
N002 ( 1, 1) [000038] ------------ | \--* CNS_INT long 8
N005 ( 1, 1) [000041] ------------ \--* CNS_INT long 96
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00016 (IL ???... ???)
N007 ( 8, 8) [000116] ------------ * JTRUE void
N006 ( 6, 6) [000033] J------N---- \--* EQ int
N004 ( 4, 4) [000029] n----------- +--* IND long
N003 ( 2, 2) [000028] -------N---- | \--* ADD long
N001 ( 1, 1) [000025] ------------ | +--* LCL_VAR long V07 tmp3 u:2
N002 ( 1, 1) [000027] ------------ | \--* CNS_INT long 96
N005 ( 1, 1) [000032] ------------ \--* CNS_INT long 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00017 (IL ???... ???)
N006 ( 4, 4) [000118] -A------R--- * ASG long
N005 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4 d:4
N004 ( 4, 4) [000034] n----------- \--* IND long
N003 ( 2, 2) [000035] -------N---- \--* ADD long
N001 ( 1, 1) [000036] ------------ +--* LCL_VAR long V07 tmp3 u:2 (last use)
N002 ( 1, 1) [000037] ------------ \--* CNS_INT long 96
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
***** BB04
STMT00018 (IL ???... ???)
N007 ( 17, 18) [000120] -AC-G---R--- * ASG long
N006 ( 1, 1) [000119] D------N---- +--* LCL_VAR long V08 tmp4 d:3
N005 ( 17, 18) [000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000017] ------------ arg0 in rcx +--* LCL_VAR long V05 tmp1 u:2 (last use)
N004 ( 2, 10) [000030] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
***** BB05
STMT00025 (IL ???... ???)
N005 ( 0, 0) [000148] -A------R--- * ASG long
N004 ( 0, 0) [000146] D------N---- +--* LCL_VAR long V08 tmp4 d:2
N003 ( 0, 0) [000147] ------------ \--* PHI long
N001 ( 0, 0) [000152] ------------ pred BB03 +--* PHI_ARG long V08 tmp4 u:4
N002 ( 0, 0) [000151] ------------ pred BB04 \--* PHI_ARG long V08 tmp4 u:3
***** BB05
STMT00005 (IL ???... ???)
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor
N005 ( 3, 3) [000006] ------------ this in rcx +--* ADDR byref
N004 ( 3, 2) [000005] ----G--N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9
N006 ( 1, 1) [000045] ------------ arg1 in rdx +--* LCL_VAR long V08 tmp4 u:2 (last use)
N007 ( 1, 1) [000016] ------------ arg2 in r8 \--* LCL_VAR ref V06 tmp2 u:2 (last use)
***** BB05
STMT00006 (IL 0x015... ???)
N003 ( 1, 3) [000049] -A------R--- * ASG int
N002 ( 1, 1) [000048] D------N---- +--* LCL_VAR int V03 loc2 d:2
N001 ( 1, 1) [000047] ------------ \--* CNS_INT int 0
------------ BB06 [019..02B), preds={BB11} succs={BB07}
***** BB06
STMT00012 (IL 0x019...0x022)
N013 ( 21, 22) [000107] IA-XG------- * ASG struct (init)
N011 ( 19, 20) [000106] D--XG--N---- +--* BLK struct<8>
N010 ( 16, 18) [000104] ---XG------- | \--* COMMA byref
N003 ( 8, 10) [000098] ---XG------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000093] ------------ | | +--* LCL_VAR int V03 loc2 u:3
N002 ( 3, 2) [000097] ----G------- | | \--* LCL_VAR int (AX) V13 tmp9
N009 ( 8, 8) [000103] ----G------- | \--* ADD byref
N004 ( 3, 2) [000102] ----G------- | +--* LCL_VAR byref (AX) V12 tmp8
N008 ( 4, 5) [000101] ------------ | \--* LSH long
N006 ( 2, 3) [000099] ------------ | +--* CAST long <- int
N005 ( 1, 1) [000094] ------------ | | \--* LCL_VAR int V03 loc2 u:3
N007 ( 1, 1) [000100] ------------ | \--* CNS_INT int 3
N012 ( 1, 1) [000105] ------------ \--* CNS_INT int 0
***** BB06
STMT00013 (IL 0x027...0x02A)
N005 ( 3, 3) [000112] -A------R--- * ASG int
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4
N003 ( 3, 3) [000110] ------------ \--* ADD int
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use)
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
***** BB07
STMT00024 (IL ???... ???)
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2
***** BB07
STMT00007 (IL 0x02B...0x033)
N004 ( 3, 3) [000057] -A-X----R--- * ASG long
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2
N002 ( 3, 2) [000055] #--X-------- \--* IND long
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1
***** BB07
STMT00008 (IL ???... ???)
N007 ( 7, 6) [000065] -A------R--- * ASG long
N006 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6 d:2
N005 ( 7, 6) [000063] n----------- \--* IND long
N004 ( 4, 4) [000062] #----------- \--* IND long
N003 ( 2, 2) [000061] -------N---- \--* ADD long
N001 ( 1, 1) [000059] ------------ +--* LCL_VAR long V09 tmp5 u:2 (last use)
N002 ( 1, 1) [000060] ------------ \--* CNS_INT long 56
***** BB07
STMT00019 (IL ???... ???)
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
N006 ( 6, 6) [000083] J--X---N---- \--* LE int
N004 ( 4, 4) [000081] ---X-------- +--* IND long
N003 ( 2, 2) [000080] -------N---- | \--* ADD long
N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR long V10 tmp6 u:2
N002 ( 1, 1) [000079] ------------ | \--* CNS_INT long 8
N005 ( 1, 1) [000082] ------------ \--* CNS_INT long 96
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
***** BB08
STMT00020 (IL ???... ???)
N007 ( 8, 8) [000122] ------------ * JTRUE void
N006 ( 6, 6) [000074] J------N---- \--* EQ int
N004 ( 4, 4) [000070] n----------- +--* IND long
N003 ( 2, 2) [000069] -------N---- | \--* ADD long
N001 ( 1, 1) [000066] ------------ | +--* LCL_VAR long V10 tmp6 u:2 (last use)
N002 ( 1, 1) [000068] ------------ | \--* CNS_INT long 96
N005 ( 1, 1) [000073] ------------ \--* CNS_INT long 0
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
***** BB11
STMT00011 (IL ???... ???)
N004 ( 7, 6) [000090] ----G------- * JTRUE void
N003 ( 5, 4) [000089] J---G--N---- \--* LT int
N001 ( 1, 1) [000050] ------------ +--* LCL_VAR int V03 loc2 u:3
N002 ( 3, 2) [000132] ----G------- \--* LCL_VAR int (AX) V13 tmp9
------------ BB12 [035..037) (return), preds={BB11} succs={}
***** BB12
STMT00014 (IL 0x035...0x036)
N002 ( 4, 3) [000114] ------------ * RETURN ref
N001 ( 3, 2) [000113] ------------ \--* LCL_VAR ref V01 loc0 u:2 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Build SSA representation
Trees after Build SSA representation
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
***** BB01
STMT00000 (IL 0x000...0x003)
N003 ( 5, 4) [000004] -A------R--- * ASG ref
N002 ( 3, 2) [000000] D------N---- +--* LCL_VAR ref V01 loc0 d:2
N001 ( 1, 1) [000002] ------------ \--* CNS_INT ref null
***** BB01
STMT00002 (IL 0x008...0x016)
N006 ( 4, 4) [000015] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000014] D------N---- +--* LCL_VAR ref V06 tmp2 d:2
N004 ( 4, 4) [000008] ---XG------- \--* IND ref
N003 ( 2, 2) [000135] -------N---- \--* ADD byref
N001 ( 1, 1) [000007] ------------ +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000134] ------------ \--* CNS_INT long 16 field offset Fseq[_array]
***** BB01
STMT00001 (IL 0x008... ???)
N004 ( 3, 3) [000013] -A---O--R--- * ASG long
N003 ( 1, 1) [000012] D------N---- +--* LCL_VAR long V05 tmp1 d:2
N002 ( 3, 2) [000011] #----O------ \--* IND long
N001 ( 1, 1) [000010] !----------- \--* LCL_VAR ref V00 this u:1
***** BB01
STMT00003 (IL ???... ???)
N007 ( 7, 6) [000024] -A------R--- * ASG long
N006 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3 d:2
N005 ( 7, 6) [000022] n----------- \--* IND long
N004 ( 4, 4) [000021] #----------- \--* IND long
N003 ( 2, 2) [000020] -------N---- \--* ADD long
N001 ( 1, 1) [000018] ------------ +--* LCL_VAR long V05 tmp1 u:2
N002 ( 1, 1) [000019] ------------ \--* CNS_INT long 56
***** BB01
STMT00015 (IL ???... ???)
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
N006 ( 6, 6) [000042] J--X---N---- \--* LE int
N004 ( 4, 4) [000040] ---X-------- +--* IND long
N003 ( 2, 2) [000039] -------N---- | \--* ADD long
N001 ( 1, 1) [000026] ------------ | +--* LCL_VAR long V07 tmp3 u:2
N002 ( 1, 1) [000038] ------------ | \--* CNS_INT long 8
N005 ( 1, 1) [000041] ------------ \--* CNS_INT long 96
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00016 (IL ???... ???)
N007 ( 8, 8) [000116] ------------ * JTRUE void
N006 ( 6, 6) [000033] J------N---- \--* EQ int
N004 ( 4, 4) [000029] n----------- +--* IND long
N003 ( 2, 2) [000028] -------N---- | \--* ADD long
N001 ( 1, 1) [000025] ------------ | +--* LCL_VAR long V07 tmp3 u:2
N002 ( 1, 1) [000027] ------------ | \--* CNS_INT long 96
N005 ( 1, 1) [000032] ------------ \--* CNS_INT long 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00017 (IL ???... ???)
N006 ( 4, 4) [000118] -A------R--- * ASG long
N005 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4 d:4
N004 ( 4, 4) [000034] n----------- \--* IND long
N003 ( 2, 2) [000035] -------N---- \--* ADD long
N001 ( 1, 1) [000036] ------------ +--* LCL_VAR long V07 tmp3 u:2 (last use)
N002 ( 1, 1) [000037] ------------ \--* CNS_INT long 96
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
***** BB04
STMT00018 (IL ???... ???)
N007 ( 17, 18) [000120] -AC-G---R--- * ASG long
N006 ( 1, 1) [000119] D------N---- +--* LCL_VAR long V08 tmp4 d:3
N005 ( 17, 18) [000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000017] ------------ arg0 in rcx +--* LCL_VAR long V05 tmp1 u:2 (last use)
N004 ( 2, 10) [000030] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
***** BB05
STMT00025 (IL ???... ???)
N005 ( 0, 0) [000148] -A------R--- * ASG long
N004 ( 0, 0) [000146] D------N---- +--* LCL_VAR long V08 tmp4 d:2
N003 ( 0, 0) [000147] ------------ \--* PHI long
N001 ( 0, 0) [000152] ------------ pred BB03 +--* PHI_ARG long V08 tmp4 u:4
N002 ( 0, 0) [000151] ------------ pred BB04 \--* PHI_ARG long V08 tmp4 u:3
***** BB05
STMT00005 (IL ???... ???)
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor
N005 ( 3, 3) [000006] ------------ this in rcx +--* ADDR byref
N004 ( 3, 2) [000005] ----G--N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9
N006 ( 1, 1) [000045] ------------ arg1 in rdx +--* LCL_VAR long V08 tmp4 u:2 (last use)
N007 ( 1, 1) [000016] ------------ arg2 in r8 \--* LCL_VAR ref V06 tmp2 u:2 (last use)
***** BB05
STMT00006 (IL 0x015... ???)
N003 ( 1, 3) [000049] -A------R--- * ASG int
N002 ( 1, 1) [000048] D------N---- +--* LCL_VAR int V03 loc2 d:2
N001 ( 1, 1) [000047] ------------ \--* CNS_INT int 0
------------ BB06 [019..02B), preds={BB11} succs={BB07}
***** BB06
STMT00012 (IL 0x019...0x022)
N013 ( 21, 22) [000107] IA-XG------- * ASG struct (init)
N011 ( 19, 20) [000106] D--XG--N---- +--* BLK struct<8>
N010 ( 16, 18) [000104] ---XG------- | \--* COMMA byref
N003 ( 8, 10) [000098] ---XG------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000093] ------------ | | +--* LCL_VAR int V03 loc2 u:3
N002 ( 3, 2) [000097] ----G------- | | \--* LCL_VAR int (AX) V13 tmp9
N009 ( 8, 8) [000103] ----G------- | \--* ADD byref
N004 ( 3, 2) [000102] ----G------- | +--* LCL_VAR byref (AX) V12 tmp8
N008 ( 4, 5) [000101] ------------ | \--* LSH long
N006 ( 2, 3) [000099] ------------ | +--* CAST long <- int
N005 ( 1, 1) [000094] ------------ | | \--* LCL_VAR int V03 loc2 u:3
N007 ( 1, 1) [000100] ------------ | \--* CNS_INT int 3
N012 ( 1, 1) [000105] ------------ \--* CNS_INT int 0
***** BB06
STMT00013 (IL 0x027...0x02A)
N005 ( 3, 3) [000112] -A------R--- * ASG int
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4
N003 ( 3, 3) [000110] ------------ \--* ADD int
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use)
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
***** BB07
STMT00024 (IL ???... ???)
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2
***** BB07
STMT00007 (IL 0x02B...0x033)
N004 ( 3, 3) [000057] -A-X----R--- * ASG long
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2
N002 ( 3, 2) [000055] #--X-------- \--* IND long
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1
***** BB07
STMT00008 (IL ???... ???)
N007 ( 7, 6) [000065] -A------R--- * ASG long
N006 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6 d:2
N005 ( 7, 6) [000063] n----------- \--* IND long
N004 ( 4, 4) [000062] #----------- \--* IND long
N003 ( 2, 2) [000061] -------N---- \--* ADD long
N001 ( 1, 1) [000059] ------------ +--* LCL_VAR long V09 tmp5 u:2 (last use)
N002 ( 1, 1) [000060] ------------ \--* CNS_INT long 56
***** BB07
STMT00019 (IL ???... ???)
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
N006 ( 6, 6) [000083] J--X---N---- \--* LE int
N004 ( 4, 4) [000081] ---X-------- +--* IND long
N003 ( 2, 2) [000080] -------N---- | \--* ADD long
N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR long V10 tmp6 u:2
N002 ( 1, 1) [000079] ------------ | \--* CNS_INT long 8
N005 ( 1, 1) [000082] ------------ \--* CNS_INT long 96
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
***** BB08
STMT00020 (IL ???... ???)
N007 ( 8, 8) [000122] ------------ * JTRUE void
N006 ( 6, 6) [000074] J------N---- \--* EQ int
N004 ( 4, 4) [000070] n----------- +--* IND long
N003 ( 2, 2) [000069] -------N---- | \--* ADD long
N001 ( 1, 1) [000066] ------------ | +--* LCL_VAR long V10 tmp6 u:2 (last use)
N002 ( 1, 1) [000068] ------------ | \--* CNS_INT long 96
N005 ( 1, 1) [000073] ------------ \--* CNS_INT long 0
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
***** BB11
STMT00011 (IL ???... ???)
N004 ( 7, 6) [000090] ----G------- * JTRUE void
N003 ( 5, 4) [000089] J---G--N---- \--* LT int
N001 ( 1, 1) [000050] ------------ +--* LCL_VAR int V03 loc2 u:3
N002 ( 3, 2) [000132] ----G------- \--* LCL_VAR int (AX) V13 tmp9
------------ BB12 [035..037) (return), preds={BB11} succs={}
***** BB12
STMT00014 (IL 0x035...0x036)
N002 ( 4, 3) [000114] ------------ * RETURN ref
N001 ( 3, 2) [000113] ------------ \--* LCL_VAR ref V01 loc0 u:2 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Early Value Propagation
*************** In optEarlyProp()
After optEarlyProp:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
***** BB01
STMT00000 (IL 0x000...0x003)
N003 ( 5, 4) [000004] -A------R--- * ASG ref
N002 ( 3, 2) [000000] D------N---- +--* LCL_VAR ref V01 loc0 d:2
N001 ( 1, 1) [000002] ------------ \--* CNS_INT ref null
***** BB01
STMT00002 (IL 0x008...0x016)
N006 ( 4, 4) [000015] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000014] D------N---- +--* LCL_VAR ref V06 tmp2 d:2
N004 ( 4, 4) [000008] ---XG------- \--* IND ref
N003 ( 2, 2) [000135] -------N---- \--* ADD byref
N001 ( 1, 1) [000007] ------------ +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000134] ------------ \--* CNS_INT long 16 field offset Fseq[_array]
***** BB01
STMT00001 (IL 0x008... ???)
N004 ( 3, 3) [000013] -A---O--R--- * ASG long
N003 ( 1, 1) [000012] D------N---- +--* LCL_VAR long V05 tmp1 d:2
N002 ( 3, 2) [000011] #----O------ \--* IND long
N001 ( 1, 1) [000010] !----------- \--* LCL_VAR ref V00 this u:1
***** BB01
STMT00003 (IL ???... ???)
N007 ( 7, 6) [000024] -A------R--- * ASG long
N006 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3 d:2
N005 ( 7, 6) [000022] n----------- \--* IND long
N004 ( 4, 4) [000021] #----------- \--* IND long
N003 ( 2, 2) [000020] -------N---- \--* ADD long
N001 ( 1, 1) [000018] ------------ +--* LCL_VAR long V05 tmp1 u:2
N002 ( 1, 1) [000019] ------------ \--* CNS_INT long 56
***** BB01
STMT00015 (IL ???... ???)
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
N006 ( 6, 6) [000042] J--X---N---- \--* LE int
N004 ( 4, 4) [000040] ---X-------- +--* IND long
N003 ( 2, 2) [000039] -------N---- | \--* ADD long
N001 ( 1, 1) [000026] ------------ | +--* LCL_VAR long V07 tmp3 u:2
N002 ( 1, 1) [000038] ------------ | \--* CNS_INT long 8
N005 ( 1, 1) [000041] ------------ \--* CNS_INT long 96
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00016 (IL ???... ???)
N007 ( 8, 8) [000116] ------------ * JTRUE void
N006 ( 6, 6) [000033] J------N---- \--* EQ int
N004 ( 4, 4) [000029] n----------- +--* IND long
N003 ( 2, 2) [000028] -------N---- | \--* ADD long
N001 ( 1, 1) [000025] ------------ | +--* LCL_VAR long V07 tmp3 u:2
N002 ( 1, 1) [000027] ------------ | \--* CNS_INT long 96
N005 ( 1, 1) [000032] ------------ \--* CNS_INT long 0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00017 (IL ???... ???)
N006 ( 4, 4) [000118] -A------R--- * ASG long
N005 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4 d:4
N004 ( 4, 4) [000034] n----------- \--* IND long
N003 ( 2, 2) [000035] -------N---- \--* ADD long
N001 ( 1, 1) [000036] ------------ +--* LCL_VAR long V07 tmp3 u:2 (last use)
N002 ( 1, 1) [000037] ------------ \--* CNS_INT long 96
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
***** BB04
STMT00018 (IL ???... ???)
N007 ( 17, 18) [000120] -AC-G---R--- * ASG long
N006 ( 1, 1) [000119] D------N---- +--* LCL_VAR long V08 tmp4 d:3
N005 ( 17, 18) [000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000017] ------------ arg0 in rcx +--* LCL_VAR long V05 tmp1 u:2 (last use)
N004 ( 2, 10) [000030] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
***** BB05
STMT00025 (IL ???... ???)
N005 ( 0, 0) [000148] -A------R--- * ASG long
N004 ( 0, 0) [000146] D------N---- +--* LCL_VAR long V08 tmp4 d:2
N003 ( 0, 0) [000147] ------------ \--* PHI long
N001 ( 0, 0) [000152] ------------ pred BB03 +--* PHI_ARG long V08 tmp4 u:4
N002 ( 0, 0) [000151] ------------ pred BB04 \--* PHI_ARG long V08 tmp4 u:3
***** BB05
STMT00005 (IL ???... ???)
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor
N005 ( 3, 3) [000006] ------------ this in rcx +--* ADDR byref
N004 ( 3, 2) [000005] ----G--N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9
N006 ( 1, 1) [000045] ------------ arg1 in rdx +--* LCL_VAR long V08 tmp4 u:2 (last use)
N007 ( 1, 1) [000016] ------------ arg2 in r8 \--* LCL_VAR ref V06 tmp2 u:2 (last use)
***** BB05
STMT00006 (IL 0x015... ???)
N003 ( 1, 3) [000049] -A------R--- * ASG int
N002 ( 1, 1) [000048] D------N---- +--* LCL_VAR int V03 loc2 d:2
N001 ( 1, 1) [000047] ------------ \--* CNS_INT int 0
------------ BB06 [019..02B), preds={BB11} succs={BB07}
***** BB06
STMT00012 (IL 0x019...0x022)
N013 ( 21, 22) [000107] IA-XG------- * ASG struct (init)
N011 ( 19, 20) [000106] D--XG--N---- +--* BLK struct<8>
N010 ( 16, 18) [000104] ---XG------- | \--* COMMA byref
N003 ( 8, 10) [000098] ---XG------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000093] ------------ | | +--* LCL_VAR int V03 loc2 u:3
N002 ( 3, 2) [000097] ----G------- | | \--* LCL_VAR int (AX) V13 tmp9
N009 ( 8, 8) [000103] ----G------- | \--* ADD byref
N004 ( 3, 2) [000102] ----G------- | +--* LCL_VAR byref (AX) V12 tmp8
N008 ( 4, 5) [000101] ------------ | \--* LSH long
N006 ( 2, 3) [000099] ------------ | +--* CAST long <- int
N005 ( 1, 1) [000094] ------------ | | \--* LCL_VAR int V03 loc2 u:3
N007 ( 1, 1) [000100] ------------ | \--* CNS_INT int 3
N012 ( 1, 1) [000105] ------------ \--* CNS_INT int 0
***** BB06
STMT00013 (IL 0x027...0x02A)
N005 ( 3, 3) [000112] -A------R--- * ASG int
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4
N003 ( 3, 3) [000110] ------------ \--* ADD int
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use)
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
***** BB07
STMT00024 (IL ???... ???)
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2
***** BB07
STMT00007 (IL 0x02B...0x033)
N004 ( 3, 3) [000057] -A-X----R--- * ASG long
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2
N002 ( 3, 2) [000055] #--X-------- \--* IND long
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1
***** BB07
STMT00008 (IL ???... ???)
N007 ( 7, 6) [000065] -A------R--- * ASG long
N006 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6 d:2
N005 ( 7, 6) [000063] n----------- \--* IND long
N004 ( 4, 4) [000062] #----------- \--* IND long
N003 ( 2, 2) [000061] -------N---- \--* ADD long
N001 ( 1, 1) [000059] ------------ +--* LCL_VAR long V09 tmp5 u:2 (last use)
N002 ( 1, 1) [000060] ------------ \--* CNS_INT long 56
***** BB07
STMT00019 (IL ???... ???)
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
N006 ( 6, 6) [000083] J--X---N---- \--* LE int
N004 ( 4, 4) [000081] ---X-------- +--* IND long
N003 ( 2, 2) [000080] -------N---- | \--* ADD long
N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR long V10 tmp6 u:2
N002 ( 1, 1) [000079] ------------ | \--* CNS_INT long 8
N005 ( 1, 1) [000082] ------------ \--* CNS_INT long 96
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
***** BB08
STMT00020 (IL ???... ???)
N007 ( 8, 8) [000122] ------------ * JTRUE void
N006 ( 6, 6) [000074] J------N---- \--* EQ int
N004 ( 4, 4) [000070] n----------- +--* IND long
N003 ( 2, 2) [000069] -------N---- | \--* ADD long
N001 ( 1, 1) [000066] ------------ | +--* LCL_VAR long V10 tmp6 u:2 (last use)
N002 ( 1, 1) [000068] ------------ | \--* CNS_INT long 96
N005 ( 1, 1) [000073] ------------ \--* CNS_INT long 0
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
***** BB11
STMT00011 (IL ???... ???)
N004 ( 7, 6) [000090] ----G------- * JTRUE void
N003 ( 5, 4) [000089] J---G--N---- \--* LT int
N001 ( 1, 1) [000050] ------------ +--* LCL_VAR int V03 loc2 u:3
N002 ( 3, 2) [000132] ----G------- \--* LCL_VAR int (AX) V13 tmp9
------------ BB12 [035..037) (return), preds={BB11} succs={}
***** BB12
STMT00014 (IL 0x035...0x036)
N002 ( 4, 3) [000114] ------------ * RETURN ref
N001 ( 3, 2) [000113] ------------ \--* LCL_VAR ref V01 loc0 u:2 (last use)
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Early Value Propagation
*************** Starting PHASE Do value numbering
*************** In fgValueNumber()
optComputeLoopSideEffects botNext is BB12, lnum is 0
optComputeLoopSideEffectsOfBlock BB06, mostNestedLoop 0
optComputeLoopSideEffectsOfBlock BB07, mostNestedLoop 0
optComputeLoopSideEffectsOfBlock BB08, mostNestedLoop 0
optComputeLoopSideEffectsOfBlock BB09, mostNestedLoop 0
optComputeLoopSideEffectsOfBlock BB10, mostNestedLoop 0
optComputeLoopSideEffectsOfBlock BB11, mostNestedLoop 0
Memory Initial Value in BB01 is: $81
The SSA definition for ByrefExposed (#1) at start of BB01 is $81 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB01 is $81 {InitVal($41)}
***** BB01, STMT00000(before)
N003 ( 5, 4) [000004] -A------R--- * ASG ref
N002 ( 3, 2) [000000] D------N---- +--* LCL_VAR ref V01 loc0 d:2
N001 ( 1, 1) [000002] ------------ \--* CNS_INT ref null
N001 [000002] CNS_INT null => $VN.Null
N002 [000000] LCL_VAR V01 loc0 d:2 => $VN.Null
N003 [000004] ASG => $VN.Null
***** BB01, STMT00000(after)
N003 ( 5, 4) [000004] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000000] D------N---- +--* LCL_VAR ref V01 loc0 d:2 $VN.Null
N001 ( 1, 1) [000002] ------------ \--* CNS_INT ref null $VN.Null
---------
***** BB01, STMT00002(before)
N006 ( 4, 4) [000015] -A-XG---R--- * ASG ref
N005 ( 1, 1) [000014] D------N---- +--* LCL_VAR ref V06 tmp2 d:2
N004 ( 4, 4) [000008] ---XG------- \--* IND ref
N003 ( 2, 2) [000135] -------N---- \--* ADD byref
N001 ( 1, 1) [000007] ------------ +--* LCL_VAR ref V00 this u:1
N002 ( 1, 1) [000134] ------------ \--* CNS_INT long 16 field offset Fseq[_array]
N001 [000007] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
N002 [000134] CNS_INT 16 field offset Fseq[_array] => $c1 {LngCns: 16}
N003 [000135] ADD => $140 {ADD($80, $c1)}
VNApplySelectors:
VNForHandle(_array) is $180, fieldType is ref
VNForMapSelect($81, $180):ref returns $1c0 {$81[$180]}
VNForMapSelect($1c0, $80):ref returns $1c1 {$1c0[$80]}
N004 [000008] IND => <l:$1c4 {norm=$1c1 {$1c0[$80]}, exc=$1c2 {NullPtrExc($80)}}, c:$1c3 {norm=$101 {101}, exc=$1c2 {NullPtrExc($80)}}>
N005 [000014] LCL_VAR V06 tmp2 d:2 => <l:$1c1 {$1c0[$80]}, c:$101 {101}>
N006 [000015] ASG => <l:$1c4 {norm=$1c1 {$1c0[$80]}, exc=$1c2 {NullPtrExc($80)}}, c:$1c3 {norm=$101 {101}, exc=$1c2 {NullPtrExc($80)}}>
***** BB01, STMT00002(after)
N006 ( 4, 4) [000015] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000014] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 <l:$1c1, c:$101>
N004 ( 4, 4) [000008] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000135] -------N---- \--* ADD byref $140
N001 ( 1, 1) [000007] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000134] ------------ \--* CNS_INT long 16 field offset Fseq[_array] $c1
---------
***** BB01, STMT00001(before)
N004 ( 3, 3) [000013] -A---O--R--- * ASG long
N003 ( 1, 1) [000012] D------N---- +--* LCL_VAR long V05 tmp1 d:2
N002 ( 3, 2) [000011] #----O------ \--* IND long
N001 ( 1, 1) [000010] !----------- \--* LCL_VAR ref V00 this u:1
N001 [000010] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
VNForMapSelect($2, $80):ref returns $1c5 {$VN.ReadOnlyHeap[$80]}
VNForMapSelect($2, $80):ref returns $1c5 {$VN.ReadOnlyHeap[$80]}
N002 [000011] IND => $1c5 {$VN.ReadOnlyHeap[$80]}
N003 [000012] LCL_VAR V05 tmp1 d:2 => $1c5 {$VN.ReadOnlyHeap[$80]}
N004 [000013] ASG => $1c5 {$VN.ReadOnlyHeap[$80]}
***** BB01, STMT00001(after)
N004 ( 3, 3) [000013] -A---O--R--- * ASG long $1c5
N003 ( 1, 1) [000012] D------N---- +--* LCL_VAR long V05 tmp1 d:2 $1c5
N002 ( 3, 2) [000011] #----O------ \--* IND long $1c5
N001 ( 1, 1) [000010] !----------- \--* LCL_VAR ref V00 this u:1 $80
---------
***** BB01, STMT00003(before)
N007 ( 7, 6) [000024] -A------R--- * ASG long
N006 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3 d:2
N005 ( 7, 6) [000022] n----------- \--* IND long
N004 ( 4, 4) [000021] #----------- \--* IND long
N003 ( 2, 2) [000020] -------N---- \--* ADD long
N001 ( 1, 1) [000018] ------------ +--* LCL_VAR long V05 tmp1 u:2
N002 ( 1, 1) [000019] ------------ \--* CNS_INT long 56
N001 [000018] LCL_VAR V05 tmp1 u:2 => $1c5 {$VN.ReadOnlyHeap[$80]}
N002 [000019] CNS_INT 56 => $c2 {LngCns: 56}
N003 [000020] ADD => $240 {ADD($c2, $1c5)}
VNForMapSelect($2, $240):ref returns $1c6 {$VN.ReadOnlyHeap[$240]}
VNForMapSelect($2, $240):ref returns $1c6 {$VN.ReadOnlyHeap[$240]}
N004 [000021] IND => $1c6 {$VN.ReadOnlyHeap[$240]}
N005 [000022] IND => <l:$280 {ByrefExposedLoad($42, $1c6, $81)}, c:$201 {201}>
N006 [000023] LCL_VAR V07 tmp3 d:2 => <l:$280 {ByrefExposedLoad($42, $1c6, $81)}, c:$201 {201}>
N007 [000024] ASG => <l:$280 {ByrefExposedLoad($42, $1c6, $81)}, c:$201 {201}>
***** BB01, STMT00003(after)
N007 ( 7, 6) [000024] -A------R--- * ASG long <l:$280, c:$201>
N006 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3 d:2 <l:$280, c:$201>
N005 ( 7, 6) [000022] n----------- \--* IND long <l:$280, c:$201>
N004 ( 4, 4) [000021] #----------- \--* IND long $1c6
N003 ( 2, 2) [000020] -------N---- \--* ADD long $240
N001 ( 1, 1) [000018] ------------ +--* LCL_VAR long V05 tmp1 u:2 $1c5
N002 ( 1, 1) [000019] ------------ \--* CNS_INT long 56 $c2
---------
***** BB01, STMT00015(before)
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
N006 ( 6, 6) [000042] J--X---N---- \--* LE int
N004 ( 4, 4) [000040] ---X-------- +--* IND long
N003 ( 2, 2) [000039] -------N---- | \--* ADD long
N001 ( 1, 1) [000026] ------------ | +--* LCL_VAR long V07 tmp3 u:2
N002 ( 1, 1) [000038] ------------ | \--* CNS_INT long 8
N005 ( 1, 1) [000041] ------------ \--* CNS_INT long 96
N001 [000026] LCL_VAR V07 tmp3 u:2 => <l:$280 {ByrefExposedLoad($42, $1c6, $81)}, c:$201 {201}>
N002 [000038] CNS_INT 8 => $c3 {LngCns: 8}
N003 [000039] ADD => <l:$242 {ADD($c3, $280)}, c:$241 {ADD($c3, $201)}>
N004 [000040] IND => <l:$244 {norm=$281 {ByrefExposedLoad($42, $242, $81)}, exc=$1c8 {NullPtrExc($242)}}, c:$243 {norm=$203 {203}, exc=$1c7 {NullPtrExc($241)}}>
N005 [000041] CNS_INT 96 => $c4 {LngCns: 96}
N006 [000042] LE => <l:$2c3 {norm=$2c1 {LE($281, $c4)}, exc=$1c8 {NullPtrExc($242)}}, c:$2c2 {norm=$2c0 {LE($203, $c4)}, exc=$1c7 {NullPtrExc($241)}}>
***** BB01, STMT00015(after)
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
N006 ( 6, 6) [000042] J--X---N---- \--* LE int <l:$2c3, c:$2c2>
N004 ( 4, 4) [000040] ---X-------- +--* IND long <l:$244, c:$243>
N003 ( 2, 2) [000039] -------N---- | \--* ADD long <l:$242, c:$241>
N001 ( 1, 1) [000026] ------------ | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000038] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000041] ------------ \--* CNS_INT long 96 $c4
finish(BB01).
Succ(BB02).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB04).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
The SSA definition for ByrefExposed (#1) at start of BB02 is $81 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB02 is $81 {InitVal($41)}
***** BB02, STMT00016(before)
N007 ( 8, 8) [000116] ------------ * JTRUE void
N006 ( 6, 6) [000033] J------N---- \--* EQ int
N004 ( 4, 4) [000029] n----------- +--* IND long
N003 ( 2, 2) [000028] -------N---- | \--* ADD long
N001 ( 1, 1) [000025] ------------ | +--* LCL_VAR long V07 tmp3 u:2
N002 ( 1, 1) [000027] ------------ | \--* CNS_INT long 96
N005 ( 1, 1) [000032] ------------ \--* CNS_INT long 0
N001 [000025] LCL_VAR V07 tmp3 u:2 => <l:$280 {ByrefExposedLoad($42, $1c6, $81)}, c:$201 {201}>
N002 [000027] CNS_INT 96 => $c4 {LngCns: 96}
N003 [000028] ADD => <l:$246 {ADD($c4, $280)}, c:$245 {ADD($c4, $201)}>
N004 [000029] IND => <l:$282 {ByrefExposedLoad($42, $246, $81)}, c:$204 {204}>
N005 [000032] CNS_INT 0 => $c0 {LngCns: 0}
N006 [000033] EQ => <l:$2c5 {EQ($282, $c0)}, c:$2c4 {EQ($204, $c0)}>
***** BB02, STMT00016(after)
N007 ( 8, 8) [000116] ------------ * JTRUE void
N006 ( 6, 6) [000033] J------N---- \--* EQ int <l:$2c5, c:$2c4>
N004 ( 4, 4) [000029] n----------- +--* IND long <l:$282, c:$204>
N003 ( 2, 2) [000028] -------N---- | \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000025] ------------ | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000027] ------------ | \--* CNS_INT long 96 $c4
N005 ( 1, 1) [000032] ------------ \--* CNS_INT long 0 $c0
finish(BB02).
Succ(BB03).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB04).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#1) at start of BB04 is $81 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB04 is $81 {InitVal($41)}
***** BB04, STMT00018(before)
N007 ( 17, 18) [000120] -AC-G---R--- * ASG long
N006 ( 1, 1) [000119] D------N---- +--* LCL_VAR long V08 tmp4 d:3
N005 ( 17, 18) [000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS
N003 ( 1, 1) [000017] ------------ arg0 in rcx +--* LCL_VAR long V05 tmp1 u:2 (last use)
N004 ( 2, 10) [000030] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token
N001 [000136] ARGPLACE => $205 {205}
N002 [000137] ARGPLACE => $206 {206}
N003 [000017] LCL_VAR V05 tmp1 u:2 (last use) => $1c5 {$VN.ReadOnlyHeap[$80]}
N004 [000030] CNS_INT(h) 0x7ff9f1337fe8 token => $181 {Hnd const: 0x00007FF9F1337FE8}
VN of ARGPLACE tree [000136] updated to $1c5 {$VN.ReadOnlyHeap[$80]}
VN of ARGPLACE tree [000137] updated to $181 {Hnd const: 0x00007FF9F1337FE8}
N005 [000031] CALL help => $247 {RuntimeHandleClass($1c5, $181)}
N006 [000119] LCL_VAR V08 tmp4 d:3 => $247 {RuntimeHandleClass($1c5, $181)}
N007 [000120] ASG => $247 {RuntimeHandleClass($1c5, $181)}
***** BB04, STMT00018(after)
N007 ( 17, 18) [000120] -AC-G---R--- * ASG long $247
N006 ( 1, 1) [000119] D------N---- +--* LCL_VAR long V08 tmp4 d:3 $247
N005 ( 17, 18) [000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
N003 ( 1, 1) [000017] ------------ arg0 in rcx +--* LCL_VAR long V05 tmp1 u:2 (last use) $1c5
N004 ( 2, 10) [000030] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token $181
finish(BB04).
Succ(BB05).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
The SSA definition for ByrefExposed (#1) at start of BB03 is $81 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB03 is $81 {InitVal($41)}
***** BB03, STMT00017(before)
N006 ( 4, 4) [000118] -A------R--- * ASG long
N005 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4 d:4
N004 ( 4, 4) [000034] n----------- \--* IND long
N003 ( 2, 2) [000035] -------N---- \--* ADD long
N001 ( 1, 1) [000036] ------------ +--* LCL_VAR long V07 tmp3 u:2 (last use)
N002 ( 1, 1) [000037] ------------ \--* CNS_INT long 96
N001 [000036] LCL_VAR V07 tmp3 u:2 (last use) => <l:$280 {ByrefExposedLoad($42, $1c6, $81)}, c:$201 {201}>
N002 [000037] CNS_INT 96 => $c4 {LngCns: 96}
N003 [000035] ADD => <l:$246 {ADD($c4, $280)}, c:$245 {ADD($c4, $201)}>
N004 [000034] IND => <l:$282 {ByrefExposedLoad($42, $246, $81)}, c:$208 {208}>
N005 [000117] LCL_VAR V08 tmp4 d:4 => <l:$282 {ByrefExposedLoad($42, $246, $81)}, c:$208 {208}>
N006 [000118] ASG => <l:$282 {ByrefExposedLoad($42, $246, $81)}, c:$208 {208}>
***** BB03, STMT00017(after)
N006 ( 4, 4) [000118] -A------R--- * ASG long <l:$282, c:$208>
N005 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4 d:4 <l:$282, c:$208>
N004 ( 4, 4) [000034] n----------- \--* IND long <l:$282, c:$208>
N003 ( 2, 2) [000035] -------N---- \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000036] ------------ +--* LCL_VAR long V07 tmp3 u:2 (last use) <l:$280, c:$201>
N002 ( 1, 1) [000037] ------------ \--* CNS_INT long 96 $c4
finish(BB03).
Succ(BB05).
Not yet completed.
All preds complete, adding to allDone.
SSA PHI definition: set VN of local 8/2 to $283 {PhiDef($8, $2, $248)} .
The SSA definition for ByrefExposed (#1) at start of BB05 is $81 {InitVal($41)}
The SSA definition for GcHeap (#1) at start of BB05 is $81 {InitVal($41)}
***** BB05, STMT00005(before)
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor
N005 ( 3, 3) [000006] ------------ this in rcx +--* ADDR byref
N004 ( 3, 2) [000005] ----G--N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9
N006 ( 1, 1) [000045] ------------ arg1 in rdx +--* LCL_VAR long V08 tmp4 u:2 (last use)
N007 ( 1, 1) [000016] ------------ arg2 in r8 \--* LCL_VAR ref V06 tmp2 u:2 (last use)
N001 [000138] ARGPLACE => $300 {300}
N002 [000139] ARGPLACE => $20a {20a}
N003 [000140] ARGPLACE => $103 {103}
N004 [000005] LCL_VAR V02 loc1
byref V02._pointer (offs=0x00) -> V12 tmp8
int V02._length (offs=0x08) -> V13 tmp9 => $340 {340}
N005 [000006] ADDR => $301 {301}
N006 [000045] LCL_VAR V08 tmp4 u:2 (last use) => $283 {PhiDef($8, $2, $248)}
N007 [000016] LCL_VAR V06 tmp2 u:2 (last use) => <l:$1c1 {$1c0[$80]}, c:$101 {101}>
VN of ARGPLACE tree [000139] updated to $301 {301}
VN of ARGPLACE tree [000140] updated to $283 {PhiDef($8, $2, $248)}
fgCurMemoryVN[GcHeap] assigned for CALL at [000009] to VN: $104.
N008 [000009] CALL => $VN.Void
***** BB05, STMT00005(after)
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
N005 ( 3, 3) [000006] ------------ this in rcx +--* ADDR byref $301
N004 ( 3, 2) [000005] ----G--N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9 $340
N006 ( 1, 1) [000045] ------------ arg1 in rdx +--* LCL_VAR long V08 tmp4 u:2 (last use) $283
N007 ( 1, 1) [000016] ------------ arg2 in r8 \--* LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
---------
***** BB05, STMT00006(before)
N003 ( 1, 3) [000049] -A------R--- * ASG int
N002 ( 1, 1) [000048] D------N---- +--* LCL_VAR int V03 loc2 d:2
N001 ( 1, 1) [000047] ------------ \--* CNS_INT int 0
N001 [000047] CNS_INT 0 => $40 {IntCns 0}
N002 [000048] LCL_VAR V03 loc2 d:2 => $40 {IntCns 0}
N003 [000049] ASG => $40 {IntCns 0}
***** BB05, STMT00006(after)
N003 ( 1, 3) [000049] -A------R--- * ASG int $40
N002 ( 1, 1) [000048] D------N---- +--* LCL_VAR int V03 loc2 d:2 $40
N001 ( 1, 1) [000047] ------------ \--* CNS_INT int 0 $40
finish(BB05).
Succ(BB07).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
SSA PHI definition: set VN of local 3/3 to $3c0 {PhiDef($3, $3, $2c6)} .
Computing GcHeap state for block BB07, entry block for loops 0 to 0:
Loop 0 has memory havoc effect; heap state is new unique $400.
The SSA definition for GcHeap (#3) at start of BB07 is $400 {400}
***** BB07, STMT00007(before)
N004 ( 3, 3) [000057] -A-X----R--- * ASG long
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2
N002 ( 3, 2) [000055] #--X-------- \--* IND long
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1
N001 [000054] LCL_VAR V00 this u:1 => $80 {InitVal($40)}
VNForMapSelect($2, $80):ref returns $1c5 {$VN.ReadOnlyHeap[$80]}
VNForMapSelect($2, $80):ref returns $1c5 {$VN.ReadOnlyHeap[$80]}
N002 [000055] IND => $1c9 {norm=$1c5 {$VN.ReadOnlyHeap[$80]}, exc=$1c2 {NullPtrExc($80)}}
N003 [000056] LCL_VAR V09 tmp5 d:2 => $1c5 {$VN.ReadOnlyHeap[$80]}
N004 [000057] ASG => $1c9 {norm=$1c5 {$VN.ReadOnlyHeap[$80]}, exc=$1c2 {NullPtrExc($80)}}
***** BB07, STMT00007(after)
N004 ( 3, 3) [000057] -A-X----R--- * ASG long $1c9
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2 $1c5
N002 ( 3, 2) [000055] #--X-------- \--* IND long $1c9
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1 $80
---------
***** BB07, STMT00008(before)
N007 ( 7, 6) [000065] -A------R--- * ASG long
N006 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6 d:2
N005 ( 7, 6) [000063] n----------- \--* IND long
N004 ( 4, 4) [000062] #----------- \--* IND long
N003 ( 2, 2) [000061] -------N---- \--* ADD long
N001 ( 1, 1) [000059] ------------ +--* LCL_VAR long V09 tmp5 u:2 (last use)
N002 ( 1, 1) [000060] ------------ \--* CNS_INT long 56
N001 [000059] LCL_VAR V09 tmp5 u:2 (last use) => $1c5 {$VN.ReadOnlyHeap[$80]}
N002 [000060] CNS_INT 56 => $c2 {LngCns: 56}
N003 [000061] ADD => $240 {ADD($c2, $1c5)}
VNForMapSelect($2, $240):ref returns $1c6 {$VN.ReadOnlyHeap[$240]}
VNForMapSelect($2, $240):ref returns $1c6 {$VN.ReadOnlyHeap[$240]}
N004 [000062] IND => $1c6 {$VN.ReadOnlyHeap[$240]}
N005 [000063] IND => <l:$284 {ByrefExposedLoad($42, $1c6, $400)}, c:$441 {441}>
N006 [000064] LCL_VAR V10 tmp6 d:2 => <l:$284 {ByrefExposedLoad($42, $1c6, $400)}, c:$441 {441}>
N007 [000065] ASG => <l:$284 {ByrefExposedLoad($42, $1c6, $400)}, c:$441 {441}>
***** BB07, STMT00008(after)
N007 ( 7, 6) [000065] -A------R--- * ASG long <l:$284, c:$441>
N006 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6 d:2 <l:$284, c:$441>
N005 ( 7, 6) [000063] n----------- \--* IND long <l:$284, c:$441>
N004 ( 4, 4) [000062] #----------- \--* IND long $1c6
N003 ( 2, 2) [000061] -------N---- \--* ADD long $240
N001 ( 1, 1) [000059] ------------ +--* LCL_VAR long V09 tmp5 u:2 (last use) $1c5
N002 ( 1, 1) [000060] ------------ \--* CNS_INT long 56 $c2
---------
***** BB07, STMT00019(before)
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
N006 ( 6, 6) [000083] J--X---N---- \--* LE int
N004 ( 4, 4) [000081] ---X-------- +--* IND long
N003 ( 2, 2) [000080] -------N---- | \--* ADD long
N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR long V10 tmp6 u:2
N002 ( 1, 1) [000079] ------------ | \--* CNS_INT long 8
N005 ( 1, 1) [000082] ------------ \--* CNS_INT long 96
N001 [000067] LCL_VAR V10 tmp6 u:2 => <l:$284 {ByrefExposedLoad($42, $1c6, $400)}, c:$441 {441}>
N002 [000079] CNS_INT 8 => $c3 {LngCns: 8}
N003 [000080] ADD => <l:$24a {ADD($c3, $284)}, c:$249 {ADD($c3, $441)}>
N004 [000081] IND => <l:$24c {norm=$285 {ByrefExposedLoad($42, $24a, $400)}, exc=$1cb {NullPtrExc($24a)}}, c:$24b {norm=$443 {443}, exc=$1ca {NullPtrExc($249)}}>
N005 [000082] CNS_INT 96 => $c4 {LngCns: 96}
N006 [000083] LE => <l:$2ca {norm=$2c8 {LE($285, $c4)}, exc=$1cb {NullPtrExc($24a)}}, c:$2c9 {norm=$2c7 {LE($443, $c4)}, exc=$1ca {NullPtrExc($249)}}>
***** BB07, STMT00019(after)
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
N006 ( 6, 6) [000083] J--X---N---- \--* LE int <l:$2ca, c:$2c9>
N004 ( 4, 4) [000081] ---X-------- +--* IND long <l:$24c, c:$24b>
N003 ( 2, 2) [000080] -------N---- | \--* ADD long <l:$24a, c:$249>
N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR long V10 tmp6 u:2 <l:$284, c:$441>
N002 ( 1, 1) [000079] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000082] ------------ \--* CNS_INT long 96 $c4
finish(BB07).
Succ(BB08).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB10).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
The SSA definition for ByrefExposed (#3) at start of BB08 is $400 {400}
The SSA definition for GcHeap (#3) at start of BB08 is $400 {400}
***** BB08, STMT00020(before)
N007 ( 8, 8) [000122] ------------ * JTRUE void
N006 ( 6, 6) [000074] J------N---- \--* EQ int
N004 ( 4, 4) [000070] n----------- +--* IND long
N003 ( 2, 2) [000069] -------N---- | \--* ADD long
N001 ( 1, 1) [000066] ------------ | +--* LCL_VAR long V10 tmp6 u:2 (last use)
N002 ( 1, 1) [000068] ------------ | \--* CNS_INT long 96
N005 ( 1, 1) [000073] ------------ \--* CNS_INT long 0
N001 [000066] LCL_VAR V10 tmp6 u:2 (last use) => <l:$284 {ByrefExposedLoad($42, $1c6, $400)}, c:$441 {441}>
N002 [000068] CNS_INT 96 => $c4 {LngCns: 96}
N003 [000069] ADD => <l:$24e {ADD($c4, $284)}, c:$24d {ADD($c4, $441)}>
N004 [000070] IND => <l:$286 {ByrefExposedLoad($42, $24e, $400)}, c:$444 {444}>
N005 [000073] CNS_INT 0 => $c0 {LngCns: 0}
N006 [000074] EQ => <l:$2cc {EQ($286, $c0)}, c:$2cb {EQ($444, $c0)}>
***** BB08, STMT00020(after)
N007 ( 8, 8) [000122] ------------ * JTRUE void
N006 ( 6, 6) [000074] J------N---- \--* EQ int <l:$2cc, c:$2cb>
N004 ( 4, 4) [000070] n----------- +--* IND long <l:$286, c:$444>
N003 ( 2, 2) [000069] -------N---- | \--* ADD long <l:$24e, c:$24d>
N001 ( 1, 1) [000066] ------------ | +--* LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
N002 ( 1, 1) [000068] ------------ | \--* CNS_INT long 96 $c4
N005 ( 1, 1) [000073] ------------ \--* CNS_INT long 0 $c0
finish(BB08).
Succ(BB09).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB10).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#3) at start of BB10 is $400 {400}
The SSA definition for GcHeap (#3) at start of BB10 is $400 {400}
finish(BB10).
Succ(BB11).
Not yet completed.
Not all preds complete Adding to notallDone, if necessary...
Was necessary.
The SSA definition for ByrefExposed (#3) at start of BB09 is $400 {400}
The SSA definition for GcHeap (#3) at start of BB09 is $400 {400}
finish(BB09).
Succ(BB11).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#3) at start of BB11 is $400 {400}
The SSA definition for GcHeap (#3) at start of BB11 is $400 {400}
***** BB11, STMT00011(before)
N004 ( 7, 6) [000090] ----G------- * JTRUE void
N003 ( 5, 4) [000089] J---G--N---- \--* LT int
N001 ( 1, 1) [000050] ------------ +--* LCL_VAR int V03 loc2 u:3
N002 ( 3, 2) [000132] ----G------- \--* LCL_VAR int (AX) V13 tmp9
N001 [000050] LCL_VAR V03 loc2 u:3 => $3c0 {PhiDef($3, $3, $2c6)}
N002 [000132] LCL_VAR V13 tmp9 => $3c1 {ByrefExposedLoad($47, $142, $400)}
N003 [000089] LT => $2cd {LT($3c0, $3c1)}
***** BB11, STMT00011(after)
N004 ( 7, 6) [000090] ----G------- * JTRUE void
N003 ( 5, 4) [000089] J---G--N---- \--* LT int $2cd
N001 ( 1, 1) [000050] ------------ +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000132] ----G------- \--* LCL_VAR int (AX) V13 tmp9 $3c1
finish(BB11).
Succ(BB12).
Not yet completed.
All preds complete, adding to allDone.
Succ(BB06).
Not yet completed.
All preds complete, adding to allDone.
The SSA definition for ByrefExposed (#3) at start of BB06 is $400 {400}
The SSA definition for GcHeap (#3) at start of BB06 is $400 {400}
***** BB06, STMT00012(before)
N013 ( 21, 22) [000107] IA-XG------- * ASG struct (init)
N011 ( 19, 20) [000106] D--XG--N---- +--* BLK struct<8>
N010 ( 16, 18) [000104] ---XG------- | \--* COMMA byref
N003 ( 8, 10) [000098] ---XG------- | +--* ARR_BOUNDS_CHECK_Rng void
N001 ( 1, 1) [000093] ------------ | | +--* LCL_VAR int V03 loc2 u:3
N002 ( 3, 2) [000097] ----G------- | | \--* LCL_VAR int (AX) V13 tmp9
N009 ( 8, 8) [000103] ----G------- | \--* ADD byref
N004 ( 3, 2) [000102] ----G------- | +--* LCL_VAR byref (AX) V12 tmp8
N008 ( 4, 5) [000101] ------------ | \--* LSH long
N006 ( 2, 3) [000099] ------------ | +--* CAST long <- int
N005 ( 1, 1) [000094] ------------ | | \--* LCL_VAR int V03 loc2 u:3
N007 ( 1, 1) [000100] ------------ | \--* CNS_INT int 3
N012 ( 1, 1) [000105] ------------ \--* CNS_INT int 0
N001 [000093] LCL_VAR V03 loc2 u:3 => $3c0 {PhiDef($3, $3, $2c6)}
N002 [000097] LCL_VAR V13 tmp9 => $3c1 {ByrefExposedLoad($47, $142, $400)}
N003 [000098] ARR_BOUNDS_CHECK_Rng => $1ce {norm=$3 {3}, exc=$1cd {IndexOutOfRangeExc($3c0, $3c1)}}
N004 [000102] LCL_VAR V12 tmp8 => $480 {ByrefExposedLoad($49, $143, $400)}
N005 [000094] LCL_VAR V03 loc2 u:3 => $3c0 {PhiDef($3, $3, $2c6)}
VNForCastOper(long) is $4a
N006 [000099] CAST => $24f {Cast($3c0, $4a)}
N007 [000100] CNS_INT 3 => $44 {IntCns 3}
N008 [000101] LSH => $250 {LSH($24f, $44)}
N009 [000103] ADD => $144 {ADD($250, $480)}
N010 [000104] COMMA => $145 {norm=$144 {ADD($250, $480)}, exc=$1cd {IndexOutOfRangeExc($3c0, $3c1)}}
N011 [000106] BLK => $1d1 {norm=$3 {3}, exc=$1d0( {NullPtrExc($144)}, {IndexOutOfRangeExc($3c0, $3c1)})}
N012 [000105] CNS_INT 0 => $40 {IntCns 0}
fgCurMemoryVN[GcHeap] assigned for INITBLK - non local at [000107] to VN: $401.
N013 [000107] ASG => $VN.Void
***** BB06, STMT00012(after)
N013 ( 21, 22) [000107] IA-XG------- * ASG struct (init) $VN.Void
N011 ( 19, 20) [000106] D--XG--N---- +--* BLK struct<8> $1d1
N010 ( 16, 18) [000104] ---XG------- | \--* COMMA byref $145
N003 ( 8, 10) [000098] ---XG------- | +--* ARR_BOUNDS_CHECK_Rng void $1ce
N001 ( 1, 1) [000093] ------------ | | +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000097] ----G------- | | \--* LCL_VAR int (AX) V13 tmp9 $3c1
N009 ( 8, 8) [000103] ----G------- | \--* ADD byref $144
N004 ( 3, 2) [000102] ----G------- | +--* LCL_VAR byref (AX) V12 tmp8 $480
N008 ( 4, 5) [000101] ------------ | \--* LSH long $250
N006 ( 2, 3) [000099] ------------ | +--* CAST long <- int $24f
N005 ( 1, 1) [000094] ------------ | | \--* LCL_VAR int V03 loc2 u:3 $3c0
N007 ( 1, 1) [000100] ------------ | \--* CNS_INT int 3 $44
N012 ( 1, 1) [000105] ------------ \--* CNS_INT int 0 $40
---------
***** BB06, STMT00013(before)
N005 ( 3, 3) [000112] -A------R--- * ASG int
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4
N003 ( 3, 3) [000110] ------------ \--* ADD int
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use)
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1
N001 [000108] LCL_VAR V03 loc2 u:3 (last use) => $3c0 {PhiDef($3, $3, $2c6)}
N002 [000109] CNS_INT 1 => $4b {IntCns 1}
N003 [000110] ADD => $2ce {ADD($4b, $3c0)}
N004 [000111] LCL_VAR V03 loc2 d:4 => $2ce {ADD($4b, $3c0)}
N005 [000112] ASG => $2ce {ADD($4b, $3c0)}
***** BB06, STMT00013(after)
N005 ( 3, 3) [000112] -A------R--- * ASG int $2ce
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4 $2ce
N003 ( 3, 3) [000110] ------------ \--* ADD int $2ce
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1 $4b
finish(BB06).
Succ(BB07).
The SSA definition for ByrefExposed (#3) at start of BB12 is $400 {400}
The SSA definition for GcHeap (#3) at start of BB12 is $400 {400}
***** BB12, STMT00014(before)
N002 ( 4, 3) [000114] ------------ * RETURN ref
N001 ( 3, 2) [000113] ------------ \--* LCL_VAR ref V01 loc0 u:2 (last use)
N001 [000113] LCL_VAR V01 loc0 u:2 (last use) => $VN.Null
N002 [000114] RETURN => $105 {105}
***** BB12, STMT00014(after)
N002 ( 4, 3) [000114] ------------ * RETURN ref $105
N001 ( 3, 2) [000113] ------------ \--* LCL_VAR ref V01 loc0 u:2 (last use) $VN.Null
finish(BB12).
*************** Finishing PHASE Do value numbering
*************** Starting PHASE Hoist loop code
*************** In optHoistLoopCode()
Blocks/Trees before phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
***** BB01
STMT00000 (IL 0x000...0x003)
N003 ( 5, 4) [000004] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000000] D------N---- +--* LCL_VAR ref V01 loc0 d:2 $VN.Null
N001 ( 1, 1) [000002] ------------ \--* CNS_INT ref null $VN.Null
***** BB01
STMT00002 (IL 0x008...0x016)
N006 ( 4, 4) [000015] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000014] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 <l:$1c1, c:$101>
N004 ( 4, 4) [000008] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000135] -------N---- \--* ADD byref $140
N001 ( 1, 1) [000007] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000134] ------------ \--* CNS_INT long 16 field offset Fseq[_array] $c1
***** BB01
STMT00001 (IL 0x008... ???)
N004 ( 3, 3) [000013] -A---O--R--- * ASG long $1c5
N003 ( 1, 1) [000012] D------N---- +--* LCL_VAR long V05 tmp1 d:2 $1c5
N002 ( 3, 2) [000011] #----O------ \--* IND long $1c5
N001 ( 1, 1) [000010] !----------- \--* LCL_VAR ref V00 this u:1 $80
***** BB01
STMT00003 (IL ???... ???)
N007 ( 7, 6) [000024] -A------R--- * ASG long <l:$280, c:$201>
N006 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3 d:2 <l:$280, c:$201>
N005 ( 7, 6) [000022] n----------- \--* IND long <l:$280, c:$201>
N004 ( 4, 4) [000021] #----------- \--* IND long $1c6
N003 ( 2, 2) [000020] -------N---- \--* ADD long $240
N001 ( 1, 1) [000018] ------------ +--* LCL_VAR long V05 tmp1 u:2 $1c5
N002 ( 1, 1) [000019] ------------ \--* CNS_INT long 56 $c2
***** BB01
STMT00015 (IL ???... ???)
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
N006 ( 6, 6) [000042] J--X---N---- \--* LE int <l:$2c3, c:$2c2>
N004 ( 4, 4) [000040] ---X-------- +--* IND long <l:$244, c:$243>
N003 ( 2, 2) [000039] -------N---- | \--* ADD long <l:$242, c:$241>
N001 ( 1, 1) [000026] ------------ | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000038] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000041] ------------ \--* CNS_INT long 96 $c4
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00016 (IL ???... ???)
N007 ( 8, 8) [000116] ------------ * JTRUE void
N006 ( 6, 6) [000033] J------N---- \--* EQ int <l:$2c5, c:$2c4>
N004 ( 4, 4) [000029] n----------- +--* IND long <l:$282, c:$204>
N003 ( 2, 2) [000028] -------N---- | \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000025] ------------ | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000027] ------------ | \--* CNS_INT long 96 $c4
N005 ( 1, 1) [000032] ------------ \--* CNS_INT long 0 $c0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00017 (IL ???... ???)
N006 ( 4, 4) [000118] -A------R--- * ASG long <l:$282, c:$208>
N005 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4 d:4 <l:$282, c:$208>
N004 ( 4, 4) [000034] n----------- \--* IND long <l:$282, c:$208>
N003 ( 2, 2) [000035] -------N---- \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000036] ------------ +--* LCL_VAR long V07 tmp3 u:2 (last use) <l:$280, c:$201>
N002 ( 1, 1) [000037] ------------ \--* CNS_INT long 96 $c4
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
***** BB04
STMT00018 (IL ???... ???)
N007 ( 17, 18) [000120] -AC-G---R--- * ASG long $247
N006 ( 1, 1) [000119] D------N---- +--* LCL_VAR long V08 tmp4 d:3 $247
N005 ( 17, 18) [000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
N003 ( 1, 1) [000017] ------------ arg0 in rcx +--* LCL_VAR long V05 tmp1 u:2 (last use) $1c5
N004 ( 2, 10) [000030] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token $181
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
***** BB05
STMT00025 (IL ???... ???)
N005 ( 0, 0) [000148] -A------R--- * ASG long
N004 ( 0, 0) [000146] D------N---- +--* LCL_VAR long V08 tmp4 d:2
N003 ( 0, 0) [000147] ------------ \--* PHI long
N001 ( 0, 0) [000152] ------------ pred BB03 +--* PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ pred BB04 \--* PHI_ARG long V08 tmp4 u:3 $247
***** BB05
STMT00005 (IL ???... ???)
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
N005 ( 3, 3) [000006] ------------ this in rcx +--* ADDR byref $301
N004 ( 3, 2) [000005] ----G--N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9 $340
N006 ( 1, 1) [000045] ------------ arg1 in rdx +--* LCL_VAR long V08 tmp4 u:2 (last use) $283
N007 ( 1, 1) [000016] ------------ arg2 in r8 \--* LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
***** BB05
STMT00006 (IL 0x015... ???)
N003 ( 1, 3) [000049] -A------R--- * ASG int $40
N002 ( 1, 1) [000048] D------N---- +--* LCL_VAR int V03 loc2 d:2 $40
N001 ( 1, 1) [000047] ------------ \--* CNS_INT int 0 $40
------------ BB06 [019..02B), preds={BB11} succs={BB07}
***** BB06
STMT00012 (IL 0x019...0x022)
N013 ( 21, 22) [000107] IA-XG------- * ASG struct (init) $VN.Void
N011 ( 19, 20) [000106] D--XG--N---- +--* BLK struct<8> $1d1
N010 ( 16, 18) [000104] ---XG------- | \--* COMMA byref $145
N003 ( 8, 10) [000098] ---XG------- | +--* ARR_BOUNDS_CHECK_Rng void $1ce
N001 ( 1, 1) [000093] ------------ | | +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000097] ----G------- | | \--* LCL_VAR int (AX) V13 tmp9 $3c1
N009 ( 8, 8) [000103] ----G------- | \--* ADD byref $144
N004 ( 3, 2) [000102] ----G------- | +--* LCL_VAR byref (AX) V12 tmp8 $480
N008 ( 4, 5) [000101] ------------ | \--* LSH long $250
N006 ( 2, 3) [000099] ------------ | +--* CAST long <- int $24f
N005 ( 1, 1) [000094] ------------ | | \--* LCL_VAR int V03 loc2 u:3 $3c0
N007 ( 1, 1) [000100] ------------ | \--* CNS_INT int 3 $44
N012 ( 1, 1) [000105] ------------ \--* CNS_INT int 0 $40
***** BB06
STMT00013 (IL 0x027...0x02A)
N005 ( 3, 3) [000112] -A------R--- * ASG int $2ce
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4 $2ce
N003 ( 3, 3) [000110] ------------ \--* ADD int $2ce
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1 $4b
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
***** BB07
STMT00024 (IL ???... ???)
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
***** BB07
STMT00007 (IL 0x02B...0x033)
N004 ( 3, 3) [000057] -A-X----R--- * ASG long $1c9
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2 $1c5
N002 ( 3, 2) [000055] #--X-------- \--* IND long $1c9
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1 $80
***** BB07
STMT00008 (IL ???... ???)
N007 ( 7, 6) [000065] -A------R--- * ASG long <l:$284, c:$441>
N006 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6 d:2 <l:$284, c:$441>
N005 ( 7, 6) [000063] n----------- \--* IND long <l:$284, c:$441>
N004 ( 4, 4) [000062] #----------- \--* IND long $1c6
N003 ( 2, 2) [000061] -------N---- \--* ADD long $240
N001 ( 1, 1) [000059] ------------ +--* LCL_VAR long V09 tmp5 u:2 (last use) $1c5
N002 ( 1, 1) [000060] ------------ \--* CNS_INT long 56 $c2
***** BB07
STMT00019 (IL ???... ???)
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
N006 ( 6, 6) [000083] J--X---N---- \--* LE int <l:$2ca, c:$2c9>
N004 ( 4, 4) [000081] ---X-------- +--* IND long <l:$24c, c:$24b>
N003 ( 2, 2) [000080] -------N---- | \--* ADD long <l:$24a, c:$249>
N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR long V10 tmp6 u:2 <l:$284, c:$441>
N002 ( 1, 1) [000079] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000082] ------------ \--* CNS_INT long 96 $c4
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
***** BB08
STMT00020 (IL ???... ???)
N007 ( 8, 8) [000122] ------------ * JTRUE void
N006 ( 6, 6) [000074] J------N---- \--* EQ int <l:$2cc, c:$2cb>
N004 ( 4, 4) [000070] n----------- +--* IND long <l:$286, c:$444>
N003 ( 2, 2) [000069] -------N---- | \--* ADD long <l:$24e, c:$24d>
N001 ( 1, 1) [000066] ------------ | +--* LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
N002 ( 1, 1) [000068] ------------ | \--* CNS_INT long 96 $c4
N005 ( 1, 1) [000073] ------------ \--* CNS_INT long 0 $c0
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
***** BB11
STMT00011 (IL ???... ???)
N004 ( 7, 6) [000090] ----G------- * JTRUE void
N003 ( 5, 4) [000089] J---G--N---- \--* LT int $2cd
N001 ( 1, 1) [000050] ------------ +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000132] ----G------- \--* LCL_VAR int (AX) V13 tmp9 $3c1
------------ BB12 [035..037) (return), preds={BB11} succs={}
***** BB12
STMT00014 (IL 0x035...0x036)
N002 ( 4, 3) [000114] ------------ * RETURN ref $105
N001 ( 3, 2) [000113] ------------ \--* LCL_VAR ref V01 loc0 u:2 (last use) $VN.Null
-------------------------------------------------------------------------------------------------------------------
*************** Finishing PHASE Hoist loop code
*************** Starting PHASE VN based copy prop
*************** In optVnCopyProp()
Copy Assertion for BB01
curSsaName stack: { }
Live vars: {V00} => {V00 V01}
Live vars: {V00 V01} => {V00 V01 V06}
Live vars: {V00 V01 V06} => {V00 V01 V05 V06}
Live vars: {V00 V01 V05 V06} => {V00 V01 V05 V06 V07}
Copy Assertion for BB05
curSsaName stack: { 0-[000007]:V00 1-[000000]:V01 5-[000012]:V05 6-[000014]:V06 7-[000023]:V07 }
Live vars: {V00 V01 V06 V08} => {V00 V01 V06}
Live vars: {V00 V01 V06} => {V00 V01}
Live vars: {V00 V01} => {V00 V01 V03}
Copy Assertion for BB07
curSsaName stack: { 0-[000007]:V00 1-[000000]:V01 3-[000048]:V03 5-[000012]:V05 6-[000014]:V06 7-[000023]:V07 8-[000146]:V08 }
Live vars: {V00 V01 V03} => {V00 V01 V03 V09}
Live vars: {V00 V01 V03 V09} => {V00 V01 V03}
Live vars: {V00 V01 V03} => {V00 V01 V03 V10}
Copy Assertion for BB11
curSsaName stack: { 0-[000007]:V00 1-[000000]:V01 3-[000143]:V03 5-[000012]:V05 6-[000014]:V06 7-[000023]:V07 8-[000146]:V08 9-[000056]:V09 10-[000064]:V10 }
Copy Assertion for BB12
curSsaName stack: { 0-[000007]:V00 1-[000000]:V01 3-[000143]:V03 5-[000012]:V05 6-[000014]:V06 7-[000023]:V07 8-[000146]:V08 9-[000056]:V09 10-[000064]:V10 }
Live vars: {V00 V01} => {V00}
Copy Assertion for BB06
curSsaName stack: { 0-[000007]:V00 1-[000000]:V01 3-[000143]:V03 5-[000012]:V05 6-[000014]:V06 7-[000023]:V07 8-[000146]:V08 9-[000056]:V09 10-[000064]:V10 }
Live vars: {V00 V01 V03} => {V00 V01}
Live vars: {V00 V01} => {V00 V01 V03}
Copy Assertion for BB10
curSsaName stack: { 0-[000007]:V00 1-[000000]:V01 3-[000143]:V03 5-[000012]:V05 6-[000014]:V06 7-[000023]:V07 8-[000146]:V08 9-[000056]:V09 10-[000064]:V10 }
Copy Assertion for BB08
curSsaName stack: { 0-[000007]:V00 1-[000000]:V01 3-[000143]:V03 5-[000012]:V05 6-[000014]:V06 7-[000023]:V07 8-[000146]:V08 9-[000056]:V09 10-[000064]:V10 }
Live vars: {V00 V01 V03 V10} => {V00 V01 V03}
Copy Assertion for BB09
curSsaName stack: { 0-[000007]:V00 1-[000000]:V01 3-[000143]:V03 5-[000012]:V05 6-[000014]:V06 7-[000023]:V07 8-[000146]:V08 9-[000056]:V09 10-[000064]:V10 }
Copy Assertion for BB04
curSsaName stack: { 0-[000007]:V00 1-[000000]:V01 5-[000012]:V05 6-[000014]:V06 7-[000023]:V07 }
Live vars: {V00 V01 V05 V06} => {V00 V01 V06}
Live vars: {V00 V01 V06} => {V00 V01 V06 V08}
Copy Assertion for BB02
curSsaName stack: { 0-[000007]:V00 1-[000000]:V01 5-[000012]:V05 6-[000014]:V06 7-[000023]:V07 }
Copy Assertion for BB03
curSsaName stack: { 0-[000007]:V00 1-[000000]:V01 5-[000012]:V05 6-[000014]:V06 7-[000023]:V07 }
Live vars: {V00 V01 V06 V07} => {V00 V01 V06}
Live vars: {V00 V01 V06} => {V00 V01 V06 V08}
*************** Finishing PHASE VN based copy prop
*************** Starting PHASE Optimize Valnum CSEs
*************** In optOptimizeCSEs()
Blocks/Trees at start of optOptimizeCSE phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
***** BB01
STMT00000 (IL 0x000...0x003)
N003 ( 5, 4) [000004] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000000] D------N---- +--* LCL_VAR ref V01 loc0 d:2 $VN.Null
N001 ( 1, 1) [000002] ------------ \--* CNS_INT ref null $VN.Null
***** BB01
STMT00002 (IL 0x008...0x016)
N006 ( 4, 4) [000015] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000014] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 <l:$1c1, c:$101>
N004 ( 4, 4) [000008] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000135] -------N---- \--* ADD byref $140
N001 ( 1, 1) [000007] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000134] ------------ \--* CNS_INT long 16 field offset Fseq[_array] $c1
***** BB01
STMT00001 (IL 0x008... ???)
N004 ( 3, 3) [000013] -A---O--R--- * ASG long $1c5
N003 ( 1, 1) [000012] D------N---- +--* LCL_VAR long V05 tmp1 d:2 $1c5
N002 ( 3, 2) [000011] #----O------ \--* IND long $1c5
N001 ( 1, 1) [000010] !----------- \--* LCL_VAR ref V00 this u:1 $80
***** BB01
STMT00003 (IL ???... ???)
N007 ( 7, 6) [000024] -A------R--- * ASG long <l:$280, c:$201>
N006 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3 d:2 <l:$280, c:$201>
N005 ( 7, 6) [000022] n----------- \--* IND long <l:$280, c:$201>
N004 ( 4, 4) [000021] #----------- \--* IND long $1c6
N003 ( 2, 2) [000020] -------N---- \--* ADD long $240
N001 ( 1, 1) [000018] ------------ +--* LCL_VAR long V05 tmp1 u:2 $1c5
N002 ( 1, 1) [000019] ------------ \--* CNS_INT long 56 $c2
***** BB01
STMT00015 (IL ???... ???)
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
N006 ( 6, 6) [000042] J--X---N---- \--* LE int <l:$2c3, c:$2c2>
N004 ( 4, 4) [000040] ---X-------- +--* IND long <l:$244, c:$243>
N003 ( 2, 2) [000039] -------N---- | \--* ADD long <l:$242, c:$241>
N001 ( 1, 1) [000026] ------------ | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000038] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000041] ------------ \--* CNS_INT long 96 $c4
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00016 (IL ???... ???)
N007 ( 8, 8) [000116] ------------ * JTRUE void
N006 ( 6, 6) [000033] J------N---- \--* EQ int <l:$2c5, c:$2c4>
N004 ( 4, 4) [000029] n----------- +--* IND long <l:$282, c:$204>
N003 ( 2, 2) [000028] -------N---- | \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000025] ------------ | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000027] ------------ | \--* CNS_INT long 96 $c4
N005 ( 1, 1) [000032] ------------ \--* CNS_INT long 0 $c0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00017 (IL ???... ???)
N006 ( 4, 4) [000118] -A------R--- * ASG long <l:$282, c:$208>
N005 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4 d:4 <l:$282, c:$208>
N004 ( 4, 4) [000034] n----------- \--* IND long <l:$282, c:$208>
N003 ( 2, 2) [000035] -------N---- \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000036] ------------ +--* LCL_VAR long V07 tmp3 u:2 (last use) <l:$280, c:$201>
N002 ( 1, 1) [000037] ------------ \--* CNS_INT long 96 $c4
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
***** BB04
STMT00018 (IL ???... ???)
N007 ( 17, 18) [000120] -AC-G---R--- * ASG long $247
N006 ( 1, 1) [000119] D------N---- +--* LCL_VAR long V08 tmp4 d:3 $247
N005 ( 17, 18) [000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
N003 ( 1, 1) [000017] ------------ arg0 in rcx +--* LCL_VAR long V05 tmp1 u:2 (last use) $1c5
N004 ( 2, 10) [000030] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token $181
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
***** BB05
STMT00025 (IL ???... ???)
N005 ( 0, 0) [000148] -A------R--- * ASG long
N004 ( 0, 0) [000146] D------N---- +--* LCL_VAR long V08 tmp4 d:2
N003 ( 0, 0) [000147] ------------ \--* PHI long
N001 ( 0, 0) [000152] ------------ pred BB03 +--* PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ pred BB04 \--* PHI_ARG long V08 tmp4 u:3 $247
***** BB05
STMT00005 (IL ???... ???)
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
N005 ( 3, 3) [000006] ------------ this in rcx +--* ADDR byref $301
N004 ( 3, 2) [000005] ----G--N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9 $340
N006 ( 1, 1) [000045] ------------ arg1 in rdx +--* LCL_VAR long V08 tmp4 u:2 (last use) $283
N007 ( 1, 1) [000016] ------------ arg2 in r8 \--* LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
***** BB05
STMT00006 (IL 0x015... ???)
N003 ( 1, 3) [000049] -A------R--- * ASG int $40
N002 ( 1, 1) [000048] D------N---- +--* LCL_VAR int V03 loc2 d:2 $40
N001 ( 1, 1) [000047] ------------ \--* CNS_INT int 0 $40
------------ BB06 [019..02B), preds={BB11} succs={BB07}
***** BB06
STMT00012 (IL 0x019...0x022)
N013 ( 21, 22) [000107] IA-XG------- * ASG struct (init) $VN.Void
N011 ( 19, 20) [000106] D--XG--N---- +--* BLK struct<8> $1d1
N010 ( 16, 18) [000104] ---XG------- | \--* COMMA byref $145
N003 ( 8, 10) [000098] ---XG------- | +--* ARR_BOUNDS_CHECK_Rng void $1ce
N001 ( 1, 1) [000093] ------------ | | +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000097] ----G------- | | \--* LCL_VAR int (AX) V13 tmp9 $3c1
N009 ( 8, 8) [000103] ----G------- | \--* ADD byref $144
N004 ( 3, 2) [000102] ----G------- | +--* LCL_VAR byref (AX) V12 tmp8 $480
N008 ( 4, 5) [000101] ------------ | \--* LSH long $250
N006 ( 2, 3) [000099] ------------ | +--* CAST long <- int $24f
N005 ( 1, 1) [000094] ------------ | | \--* LCL_VAR int V03 loc2 u:3 $3c0
N007 ( 1, 1) [000100] ------------ | \--* CNS_INT int 3 $44
N012 ( 1, 1) [000105] ------------ \--* CNS_INT int 0 $40
***** BB06
STMT00013 (IL 0x027...0x02A)
N005 ( 3, 3) [000112] -A------R--- * ASG int $2ce
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4 $2ce
N003 ( 3, 3) [000110] ------------ \--* ADD int $2ce
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1 $4b
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
***** BB07
STMT00024 (IL ???... ???)
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
***** BB07
STMT00007 (IL 0x02B...0x033)
N004 ( 3, 3) [000057] -A-X----R--- * ASG long $1c9
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2 $1c5
N002 ( 3, 2) [000055] #--X-------- \--* IND long $1c9
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1 $80
***** BB07
STMT00008 (IL ???... ???)
N007 ( 7, 6) [000065] -A------R--- * ASG long <l:$284, c:$441>
N006 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6 d:2 <l:$284, c:$441>
N005 ( 7, 6) [000063] n----------- \--* IND long <l:$284, c:$441>
N004 ( 4, 4) [000062] #----------- \--* IND long $1c6
N003 ( 2, 2) [000061] -------N---- \--* ADD long $240
N001 ( 1, 1) [000059] ------------ +--* LCL_VAR long V09 tmp5 u:2 (last use) $1c5
N002 ( 1, 1) [000060] ------------ \--* CNS_INT long 56 $c2
***** BB07
STMT00019 (IL ???... ???)
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
N006 ( 6, 6) [000083] J--X---N---- \--* LE int <l:$2ca, c:$2c9>
N004 ( 4, 4) [000081] ---X-------- +--* IND long <l:$24c, c:$24b>
N003 ( 2, 2) [000080] -------N---- | \--* ADD long <l:$24a, c:$249>
N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR long V10 tmp6 u:2 <l:$284, c:$441>
N002 ( 1, 1) [000079] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000082] ------------ \--* CNS_INT long 96 $c4
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
***** BB08
STMT00020 (IL ???... ???)
N007 ( 8, 8) [000122] ------------ * JTRUE void
N006 ( 6, 6) [000074] J------N---- \--* EQ int <l:$2cc, c:$2cb>
N004 ( 4, 4) [000070] n----------- +--* IND long <l:$286, c:$444>
N003 ( 2, 2) [000069] -------N---- | \--* ADD long <l:$24e, c:$24d>
N001 ( 1, 1) [000066] ------------ | +--* LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
N002 ( 1, 1) [000068] ------------ | \--* CNS_INT long 96 $c4
N005 ( 1, 1) [000073] ------------ \--* CNS_INT long 0 $c0
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
***** BB11
STMT00011 (IL ???... ???)
N004 ( 7, 6) [000090] ----G------- * JTRUE void
N003 ( 5, 4) [000089] J---G--N---- \--* LT int $2cd
N001 ( 1, 1) [000050] ------------ +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000132] ----G------- \--* LCL_VAR int (AX) V13 tmp9 $3c1
------------ BB12 [035..037) (return), preds={BB11} succs={}
***** BB12
STMT00014 (IL 0x035...0x036)
N002 ( 4, 3) [000114] ------------ * RETURN ref $105
N001 ( 3, 2) [000113] ------------ \--* LCL_VAR ref V01 loc0 u:2 (last use) $VN.Null
-------------------------------------------------------------------------------------------------------------------
*************** In optOptimizeValnumCSEs()
CSE candidate #01, key=$282 in BB03, [cost= 4, size= 4]:
N004 ( 4, 4) CSE #01 (use)[000034] n----------- * IND long <l:$282, c:$208>
N003 ( 2, 2) [000035] -------N---- \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000036] ------------ +--* LCL_VAR long V07 tmp3 u:2 (last use) <l:$280, c:$201>
N002 ( 1, 1) [000037] ------------ \--* CNS_INT long 96 $c4
CSE candidate #02, key=$1c5 in BB07, [cost= 3, size= 2]:
N002 ( 3, 2) CSE #02 (use)[000055] #--X-------- * IND long $1c9
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1 $80
CSE candidate #03, key=$1c6 in BB07, [cost= 4, size= 4]:
N004 ( 4, 4) CSE #03 (use)[000062] #----------- * IND long $1c6
N003 ( 2, 2) [000061] -------N---- \--* ADD long $240
N001 ( 1, 1) [000059] ------------ +--* LCL_VAR long V09 tmp5 u:2 (last use) $1c5
N002 ( 1, 1) [000060] ------------ \--* CNS_INT long 56 $c2
Blocks that generate CSE def/uses
BB01 cseGen = 000000000000003C
BB02 cseGen = 0000000000000003
BB03 cseGen = 0000000000000003
BB07 cseGen = 000000000000003C
Performing DataFlow for ValnumCSE's
StartMerge BB01
:: cseOut = 000000000000007F
EndMerge BB01
:: cseIn = 0000000000000000
:: cseGen = 000000000000003C
=> cseOut = 000000000000003C
!= preMerge = 000000000000007F, => true
StartMerge BB02
:: cseOut = 000000000000007F
Merge BB02 and BB01
:: cseIn = 000000000000007F
:: cseOut = 000000000000007F
=> cseIn = 000000000000003C
EndMerge BB02
:: cseIn = 000000000000003C
:: cseGen = 0000000000000003
=> cseOut = 000000000000003F
!= preMerge = 000000000000007F, => true
StartMerge BB04
:: cseOut = 000000000000007F
Merge BB04 and BB01
:: cseIn = 000000000000007F
:: cseOut = 000000000000007F
=> cseIn = 000000000000003C
Merge BB04 and BB02
:: cseIn = 000000000000003C
:: cseOut = 000000000000007F
=> cseIn = 000000000000003C
EndMerge BB04
:: cseIn = 000000000000003C
-- cseKill = 0000000000000015
:: cseGen = 0000000000000000
=> cseOut = 0000000000000014
!= preMerge = 000000000000007F, => true
StartMerge BB03
:: cseOut = 000000000000007F
Merge BB03 and BB02
:: cseIn = 000000000000007F
:: cseOut = 000000000000007F
=> cseIn = 000000000000003F
EndMerge BB03
:: cseIn = 000000000000003F
:: cseGen = 0000000000000003
=> cseOut = 000000000000003F
!= preMerge = 000000000000007F, => true
StartMerge BB04
:: cseOut = 0000000000000014
Merge BB04 and BB01
:: cseIn = 000000000000003C
:: cseOut = 0000000000000014
=> cseIn = 000000000000003C
Merge BB04 and BB02
:: cseIn = 000000000000003C
:: cseOut = 0000000000000014
=> cseIn = 000000000000003C
EndMerge BB04
:: cseIn = 000000000000003C
-- cseKill = 0000000000000015
:: cseGen = 0000000000000000
=> cseOut = 0000000000000014
!= preMerge = 0000000000000014, => false
StartMerge BB05
:: cseOut = 000000000000007F
Merge BB05 and BB03
:: cseIn = 000000000000007F
:: cseOut = 000000000000007F
=> cseIn = 000000000000003F
Merge BB05 and BB04
:: cseIn = 000000000000003F
:: cseOut = 000000000000007F
=> cseIn = 0000000000000014
EndMerge BB05
:: cseIn = 0000000000000014
-- cseKill = 0000000000000015
:: cseGen = 0000000000000000
=> cseOut = 0000000000000014
!= preMerge = 000000000000007F, => true
StartMerge BB05
:: cseOut = 0000000000000014
Merge BB05 and BB03
:: cseIn = 0000000000000014
:: cseOut = 0000000000000014
=> cseIn = 0000000000000014
Merge BB05 and BB04
:: cseIn = 0000000000000014
:: cseOut = 0000000000000014
=> cseIn = 0000000000000014
EndMerge BB05
:: cseIn = 0000000000000014
-- cseKill = 0000000000000015
:: cseGen = 0000000000000000
=> cseOut = 0000000000000014
!= preMerge = 0000000000000014, => false
StartMerge BB07
:: cseOut = 000000000000007F
Merge BB07 and BB05
:: cseIn = 000000000000007F
:: cseOut = 000000000000007F
=> cseIn = 0000000000000014
Merge BB07 and BB06
:: cseIn = 0000000000000014
:: cseOut = 000000000000007F
=> cseIn = 0000000000000014
EndMerge BB07
:: cseIn = 0000000000000014
:: cseGen = 000000000000003C
=> cseOut = 000000000000003C
!= preMerge = 000000000000007F, => true
StartMerge BB08
:: cseOut = 000000000000007F
Merge BB08 and BB07
:: cseIn = 000000000000007F
:: cseOut = 000000000000007F
=> cseIn = 000000000000003C
EndMerge BB08
:: cseIn = 000000000000003C
:: cseGen = 0000000000000000
=> cseOut = 000000000000003C
!= preMerge = 000000000000007F, => true
StartMerge BB10
:: cseOut = 000000000000007F
Merge BB10 and BB07
:: cseIn = 000000000000007F
:: cseOut = 000000000000007F
=> cseIn = 000000000000003C
Merge BB10 and BB08
:: cseIn = 000000000000003C
:: cseOut = 000000000000007F
=> cseIn = 000000000000003C
EndMerge BB10
:: cseIn = 000000000000003C
-- cseKill = 0000000000000015
:: cseGen = 0000000000000000
=> cseOut = 0000000000000014
!= preMerge = 000000000000007F, => true
StartMerge BB09
:: cseOut = 000000000000007F
Merge BB09 and BB08
:: cseIn = 000000000000007F
:: cseOut = 000000000000007F
=> cseIn = 000000000000003C
EndMerge BB09
:: cseIn = 000000000000003C
:: cseGen = 0000000000000000
=> cseOut = 000000000000003C
!= preMerge = 000000000000007F, => true
StartMerge BB10
:: cseOut = 0000000000000014
Merge BB10 and BB07
:: cseIn = 000000000000003C
:: cseOut = 0000000000000014
=> cseIn = 000000000000003C
Merge BB10 and BB08
:: cseIn = 000000000000003C
:: cseOut = 0000000000000014
=> cseIn = 000000000000003C
EndMerge BB10
:: cseIn = 000000000000003C
-- cseKill = 0000000000000015
:: cseGen = 0000000000000000
=> cseOut = 0000000000000014
!= preMerge = 0000000000000014, => false
StartMerge BB11
:: cseOut = 000000000000007F
Merge BB11 and BB09
:: cseIn = 000000000000007F
:: cseOut = 000000000000007F
=> cseIn = 000000000000003C
Merge BB11 and BB10
:: cseIn = 000000000000003C
:: cseOut = 000000000000007F
=> cseIn = 0000000000000014
EndMerge BB11
:: cseIn = 0000000000000014
:: cseGen = 0000000000000000
=> cseOut = 0000000000000014
!= preMerge = 000000000000007F, => true
StartMerge BB11
:: cseOut = 0000000000000014
Merge BB11 and BB09
:: cseIn = 0000000000000014
:: cseOut = 0000000000000014
=> cseIn = 0000000000000014
Merge BB11 and BB10
:: cseIn = 0000000000000014
:: cseOut = 0000000000000014
=> cseIn = 0000000000000014
EndMerge BB11
:: cseIn = 0000000000000014
:: cseGen = 0000000000000000
=> cseOut = 0000000000000014
!= preMerge = 0000000000000014, => false
StartMerge BB12
:: cseOut = 000000000000007F
Merge BB12 and BB11
:: cseIn = 000000000000007F
:: cseOut = 000000000000007F
=> cseIn = 0000000000000014
EndMerge BB12
:: cseIn = 0000000000000014
:: cseGen = 0000000000000000
=> cseOut = 0000000000000014
!= preMerge = 000000000000007F, => true
StartMerge BB06
:: cseOut = 000000000000007F
Merge BB06 and BB11
:: cseIn = 000000000000007F
:: cseOut = 000000000000007F
=> cseIn = 0000000000000014
EndMerge BB06
:: cseIn = 0000000000000014
:: cseGen = 0000000000000000
=> cseOut = 0000000000000014
!= preMerge = 000000000000007F, => true
StartMerge BB07
:: cseOut = 000000000000003C
Merge BB07 and BB05
:: cseIn = 0000000000000014
:: cseOut = 000000000000003C
=> cseIn = 0000000000000014
Merge BB07 and BB06
:: cseIn = 0000000000000014
:: cseOut = 000000000000003C
=> cseIn = 0000000000000014
EndMerge BB07
:: cseIn = 0000000000000014
:: cseGen = 000000000000003C
=> cseOut = 000000000000003C
!= preMerge = 000000000000003C, => false
After performing DataFlow for ValnumCSE's
BB01 cseIn = 0000000000000000, cseGen = 000000000000003C, cseOut = 000000000000003C
BB02 cseIn = 000000000000003C, cseGen = 0000000000000003, cseOut = 000000000000003F
BB03 cseIn = 000000000000003F, cseGen = 0000000000000003, cseOut = 000000000000003F
BB04 cseIn = 000000000000003C, cseGen = 0000000000000000, cseOut = 0000000000000014
BB05 cseIn = 0000000000000014, cseGen = 0000000000000000, cseOut = 0000000000000014
BB06 cseIn = 0000000000000014, cseGen = 0000000000000000, cseOut = 0000000000000014
BB07 cseIn = 0000000000000014, cseGen = 000000000000003C, cseOut = 000000000000003C
BB08 cseIn = 000000000000003C, cseGen = 0000000000000000, cseOut = 000000000000003C
BB09 cseIn = 000000000000003C, cseGen = 0000000000000000, cseOut = 000000000000003C
BB10 cseIn = 000000000000003C, cseGen = 0000000000000000, cseOut = 0000000000000014
BB11 cseIn = 0000000000000014, cseGen = 0000000000000000, cseOut = 0000000000000014
BB12 cseIn = 0000000000000014, cseGen = 0000000000000000, cseOut = 0000000000000014
Labeling the CSEs with Use/Def information
BB01 [000011] Def of CSE #02 [weight=1 ]
BB01 [000021] Def of CSE #03 [weight=1 ]
BB02 [000029] Def of CSE #01 [weight=0.40]
BB03 [000034] Use of CSE #01 [weight=0.40]
BB07 [000055] Use of CSE #02 [weight=8 ] *** Now Live Across Call ***
NO_CSE - This use has an exception set item that isn't contained in the defs!
BB07 [000062] Use of CSE #03 [weight=8 ] *** Now Live Across Call ***
************ Trees at start of optValnumCSE_Heuristic()
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
***** BB01
STMT00000 (IL 0x000...0x003)
N003 ( 5, 4) [000004] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000000] D------N---- +--* LCL_VAR ref V01 loc0 d:2 $VN.Null
N001 ( 1, 1) [000002] ------------ \--* CNS_INT ref null $VN.Null
***** BB01
STMT00002 (IL 0x008...0x016)
N006 ( 4, 4) [000015] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000014] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 <l:$1c1, c:$101>
N004 ( 4, 4) [000008] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000135] -------N---- \--* ADD byref $140
N001 ( 1, 1) [000007] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000134] ------------ \--* CNS_INT long 16 field offset Fseq[_array] $c1
***** BB01
STMT00001 (IL 0x008... ???)
N004 ( 3, 3) [000013] -A---O--R--- * ASG long $1c5
N003 ( 1, 1) [000012] D------N---- +--* LCL_VAR long V05 tmp1 d:2 $1c5
N002 ( 3, 2) CSE #02 (def)[000011] #----O------ \--* IND long $1c5
N001 ( 1, 1) [000010] !----------- \--* LCL_VAR ref V00 this u:1 $80
***** BB01
STMT00003 (IL ???... ???)
N007 ( 7, 6) [000024] -A------R--- * ASG long <l:$280, c:$201>
N006 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3 d:2 <l:$280, c:$201>
N005 ( 7, 6) [000022] n----------- \--* IND long <l:$280, c:$201>
N004 ( 4, 4) CSE #03 (def)[000021] #----------- \--* IND long $1c6
N003 ( 2, 2) [000020] -------N---- \--* ADD long $240
N001 ( 1, 1) [000018] ------------ +--* LCL_VAR long V05 tmp1 u:2 $1c5
N002 ( 1, 1) [000019] ------------ \--* CNS_INT long 56 $c2
***** BB01
STMT00015 (IL ???... ???)
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
N006 ( 6, 6) [000042] J--X---N---- \--* LE int <l:$2c3, c:$2c2>
N004 ( 4, 4) [000040] ---X-------- +--* IND long <l:$244, c:$243>
N003 ( 2, 2) [000039] -------N---- | \--* ADD long <l:$242, c:$241>
N001 ( 1, 1) [000026] ------------ | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000038] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000041] ------------ \--* CNS_INT long 96 $c4
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00016 (IL ???... ???)
N007 ( 8, 8) [000116] ------------ * JTRUE void
N006 ( 6, 6) [000033] J------N---- \--* EQ int <l:$2c5, c:$2c4>
N004 ( 4, 4) CSE #01 (def)[000029] n----------- +--* IND long <l:$282, c:$204>
N003 ( 2, 2) [000028] -------N---- | \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000025] ------------ | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000027] ------------ | \--* CNS_INT long 96 $c4
N005 ( 1, 1) [000032] ------------ \--* CNS_INT long 0 $c0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00017 (IL ???... ???)
N006 ( 4, 4) [000118] -A------R--- * ASG long <l:$282, c:$208>
N005 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4 d:4 <l:$282, c:$208>
N004 ( 4, 4) CSE #01 (use)[000034] n----------- \--* IND long <l:$282, c:$208>
N003 ( 2, 2) [000035] -------N---- \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000036] ------------ +--* LCL_VAR long V07 tmp3 u:2 (last use) <l:$280, c:$201>
N002 ( 1, 1) [000037] ------------ \--* CNS_INT long 96 $c4
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
***** BB04
STMT00018 (IL ???... ???)
N007 ( 17, 18) [000120] -AC-G---R--- * ASG long $247
N006 ( 1, 1) [000119] D------N---- +--* LCL_VAR long V08 tmp4 d:3 $247
N005 ( 17, 18) [000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
N003 ( 1, 1) [000017] ------------ arg0 in rcx +--* LCL_VAR long V05 tmp1 u:2 (last use) $1c5
N004 ( 2, 10) [000030] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token $181
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
***** BB05
STMT00025 (IL ???... ???)
N005 ( 0, 0) [000148] -A------R--- * ASG long
N004 ( 0, 0) [000146] D------N---- +--* LCL_VAR long V08 tmp4 d:2
N003 ( 0, 0) [000147] ------------ \--* PHI long
N001 ( 0, 0) [000152] ------------ pred BB03 +--* PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ pred BB04 \--* PHI_ARG long V08 tmp4 u:3 $247
***** BB05
STMT00005 (IL ???... ???)
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
N005 ( 3, 3) [000006] ------------ this in rcx +--* ADDR byref $301
N004 ( 3, 2) [000005] ----G--N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9 $340
N006 ( 1, 1) [000045] ------------ arg1 in rdx +--* LCL_VAR long V08 tmp4 u:2 (last use) $283
N007 ( 1, 1) [000016] ------------ arg2 in r8 \--* LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
***** BB05
STMT00006 (IL 0x015... ???)
N003 ( 1, 3) [000049] -A------R--- * ASG int $40
N002 ( 1, 1) [000048] D------N---- +--* LCL_VAR int V03 loc2 d:2 $40
N001 ( 1, 1) [000047] ------------ \--* CNS_INT int 0 $40
------------ BB06 [019..02B), preds={BB11} succs={BB07}
***** BB06
STMT00012 (IL 0x019...0x022)
N013 ( 21, 22) [000107] IA-XG------- * ASG struct (init) $VN.Void
N011 ( 19, 20) [000106] D--XG--N---- +--* BLK struct<8> $1d1
N010 ( 16, 18) [000104] ---XG------- | \--* COMMA byref $145
N003 ( 8, 10) [000098] ---XG------- | +--* ARR_BOUNDS_CHECK_Rng void $1ce
N001 ( 1, 1) [000093] ------------ | | +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000097] ----G------- | | \--* LCL_VAR int (AX) V13 tmp9 $3c1
N009 ( 8, 8) [000103] ----G------- | \--* ADD byref $144
N004 ( 3, 2) [000102] ----G------- | +--* LCL_VAR byref (AX) V12 tmp8 $480
N008 ( 4, 5) [000101] ------------ | \--* LSH long $250
N006 ( 2, 3) [000099] ------------ | +--* CAST long <- int $24f
N005 ( 1, 1) [000094] ------------ | | \--* LCL_VAR int V03 loc2 u:3 $3c0
N007 ( 1, 1) [000100] ------------ | \--* CNS_INT int 3 $44
N012 ( 1, 1) [000105] ------------ \--* CNS_INT int 0 $40
***** BB06
STMT00013 (IL 0x027...0x02A)
N005 ( 3, 3) [000112] -A------R--- * ASG int $2ce
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4 $2ce
N003 ( 3, 3) [000110] ------------ \--* ADD int $2ce
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1 $4b
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
***** BB07
STMT00024 (IL ???... ???)
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
***** BB07
STMT00007 (IL 0x02B...0x033)
N004 ( 3, 3) [000057] -A-X----R--- * ASG long $1c9
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2 $1c5
N002 ( 3, 2) [000055] #--X-------- \--* IND long $1c9
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1 $80
***** BB07
STMT00008 (IL ???... ???)
N007 ( 7, 6) [000065] -A------R--- * ASG long <l:$284, c:$441>
N006 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6 d:2 <l:$284, c:$441>
N005 ( 7, 6) [000063] n----------- \--* IND long <l:$284, c:$441>
N004 ( 4, 4) CSE #03 (use)[000062] #----------- \--* IND long $1c6
N003 ( 2, 2) [000061] -------N---- \--* ADD long $240
N001 ( 1, 1) [000059] ------------ +--* LCL_VAR long V09 tmp5 u:2 (last use) $1c5
N002 ( 1, 1) [000060] ------------ \--* CNS_INT long 56 $c2
***** BB07
STMT00019 (IL ???... ???)
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
N006 ( 6, 6) [000083] J--X---N---- \--* LE int <l:$2ca, c:$2c9>
N004 ( 4, 4) [000081] ---X-------- +--* IND long <l:$24c, c:$24b>
N003 ( 2, 2) [000080] -------N---- | \--* ADD long <l:$24a, c:$249>
N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR long V10 tmp6 u:2 <l:$284, c:$441>
N002 ( 1, 1) [000079] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000082] ------------ \--* CNS_INT long 96 $c4
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
***** BB08
STMT00020 (IL ???... ???)
N007 ( 8, 8) [000122] ------------ * JTRUE void
N006 ( 6, 6) [000074] J------N---- \--* EQ int <l:$2cc, c:$2cb>
N004 ( 4, 4) [000070] n----------- +--* IND long <l:$286, c:$444>
N003 ( 2, 2) [000069] -------N---- | \--* ADD long <l:$24e, c:$24d>
N001 ( 1, 1) [000066] ------------ | +--* LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
N002 ( 1, 1) [000068] ------------ | \--* CNS_INT long 96 $c4
N005 ( 1, 1) [000073] ------------ \--* CNS_INT long 0 $c0
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
***** BB11
STMT00011 (IL ???... ???)
N004 ( 7, 6) [000090] ----G------- * JTRUE void
N003 ( 5, 4) [000089] J---G--N---- \--* LT int $2cd
N001 ( 1, 1) [000050] ------------ +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000132] ----G------- \--* LCL_VAR int (AX) V13 tmp9 $3c1
------------ BB12 [035..037) (return), preds={BB11} succs={}
***** BB12
STMT00014 (IL 0x035...0x036)
N002 ( 4, 3) [000114] ------------ * RETURN ref $105
N001 ( 3, 2) [000113] ------------ \--* LCL_VAR ref V01 loc0 u:2 (last use) $VN.Null
-------------------------------------------------------------------------------------------------------------------
Aggressive CSE Promotion cutoff is 200
Moderate CSE Promotion cutoff is 100
enregCount is 10
Framesize estimate is 0x001C
We have a small frame
Sorted CSE candidates:
CSE #03, {$1c6, $4 } useCnt=1: [def=100, use=800, cost= 4, call]
:: N004 ( 4, 4) CSE #03 (def)[000021] #----------- * IND long $1c6
CSE #01, {$282, $4 } useCnt=1: [def= 40, use= 40, cost= 4 ]
:: N004 ( 4, 4) CSE #01 (def)[000029] n----------- * IND long <l:$282, c:$204>
CSE #02, {$1c5, $4 } useCnt=0: [def=100, use= 0, cost= 3, call]
:: N002 ( 3, 2) CSE #02 (def)[000011] #----O------ * IND long $1c5
Considering CSE #03 {$1c6, $4 } [def=100, use=800, cost= 4, call]
CSE Expression :
N004 ( 4, 4) CSE #03 (def)[000021] #----------- * IND long $1c6
N003 ( 2, 2) [000020] -------N---- \--* ADD long $240
N001 ( 1, 1) [000018] ------------ +--* LCL_VAR long V05 tmp1 u:2 $1c5
N002 ( 1, 1) [000019] ------------ \--* CNS_INT long 56 $c2
Aggressive CSE Promotion (1000 >= 200)
cseRefCnt=1000, aggressiveRefCnt=200, moderateRefCnt=100
defCnt=100, useCnt=800, cost=4, size=4, LiveAcrossCall
def_cost=1, use_cost=1, extra_no_cost=6, extra_yes_cost=100
CSE cost savings check (3206 >= 1000) passes
Promoting CSE:
lvaGrabTemp returning 14 (V14 rat0) (a long lifetime temp) called for CSE - aggressive.
CSE #03 is single-def, so associated CSE temp V14 will be in SSA
New refCnts for V14: refCnt = 2, refCntWtd = 2
New refCnts for V14: refCnt = 3, refCntWtd = 10
CSE #03 def at [000021] replaced in BB01 with def of V14
optValnumCSE morphed tree:
N011 ( 8, 7) [000024] -A------R--- * ASG long <l:$280, c:$201>
N010 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3 d:2 <l:$280, c:$201>
N009 ( 8, 7) [000022] nA---------- \--* IND long <l:$280, c:$201>
N008 ( 5, 5) [000156] -A---------- \--* COMMA long $1c6
N006 ( 4, 4) [000154] -A------R--- +--* ASG long $VN.Void
N005 ( 1, 1) [000153] D------N---- | +--* LCL_VAR long V14 cse0 d:1 $1c6
N004 ( 4, 4) [000021] #----------- | \--* IND long $1c6
N003 ( 2, 2) [000020] -------N---- | \--* ADD long $240
N001 ( 1, 1) [000018] ------------ | +--* LCL_VAR long V05 tmp1 u:2 $1c5
N002 ( 1, 1) [000019] ------------ | \--* CNS_INT long 56 $c2
N007 ( 1, 1) [000155] ------------ \--* LCL_VAR long V14 cse0 u:1 $1c6
Working on the replacement of the CSE #03 use at [000062] in BB07
optValnumCSE morphed tree:
N004 ( 3, 3) [000065] -A------R--- * ASG long <l:$284, c:$441>
N003 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6 d:2 <l:$284, c:$441>
N002 ( 3, 2) [000063] n----------- \--* IND long <l:$284, c:$441>
N001 ( 1, 1) [000157] ------------ \--* LCL_VAR long V14 cse0 u:1 $1c6
Considering CSE #01 {$282, $4 } [def= 40, use= 40, cost= 4 ]
CSE Expression :
N004 ( 4, 4) CSE #01 (def)[000029] n----------- * IND long <l:$282, c:$204>
N003 ( 2, 2) [000028] -------N---- \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000025] ------------ +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000027] ------------ \--* CNS_INT long 96 $c4
Conservative CSE Promotion (not enregisterable) (120 < 150)
cseRefCnt=120, aggressiveRefCnt=300, moderateRefCnt=150
defCnt=40, useCnt=40, cost=4, size=4
def_cost=2, use_cost=2, extra_no_cost=4, extra_yes_cost=0
CSE cost savings check (164 >= 160) passes
Promoting CSE:
lvaGrabTemp returning 15 (V15 rat0) (a long lifetime temp) called for CSE - conservative.
CSE #01 is single-def, so associated CSE temp V15 will be in SSA
New refCnts for V15: refCnt = 2, refCntWtd = 0.80
New refCnts for V15: refCnt = 3, refCntWtd = 1.20
CSE #01 def at [000029] replaced in BB02 with def of V15
optValnumCSE morphed tree:
N011 ( 15, 13) [000116] -A---------- * JTRUE void
N010 ( 13, 11) [000033] JA-----N---- \--* EQ int <l:$2c5, c:$2c4>
N008 ( 11, 9) [000161] -A---------- +--* COMMA long <l:$282, c:$204>
N006 ( 8, 7) [000159] -A------R--- | +--* ASG long $VN.Void
N005 ( 3, 2) [000158] D------N---- | | +--* LCL_VAR long V15 cse1 d:1 <l:$282, c:$204>
N004 ( 4, 4) [000029] n----------- | | \--* IND long <l:$282, c:$204>
N003 ( 2, 2) [000028] -------N---- | | \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000025] ------------ | | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000027] ------------ | | \--* CNS_INT long 96 $c4
N007 ( 3, 2) [000160] ------------ | \--* LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
N009 ( 1, 1) [000032] ------------ \--* CNS_INT long 0 $c0
Working on the replacement of the CSE #01 use at [000034] in BB03
optValnumCSE morphed tree:
N003 ( 3, 3) [000118] -A------R--- * ASG long <l:$282, c:$208>
N002 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4 d:4 <l:$282, c:$208>
N001 ( 3, 2) [000162] ------------ \--* LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
Skipped CSE #02 because use count is 0
*************** Finishing PHASE Optimize Valnum CSEs
*************** Starting PHASE Assertion prop
*************** In optAssertionPropMain()
Blocks/Trees at start of phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
***** BB01
STMT00000 (IL 0x000...0x003)
N003 ( 5, 4) [000004] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000000] D------N---- +--* LCL_VAR ref V01 loc0 d:2 $VN.Null
N001 ( 1, 1) [000002] ------------ \--* CNS_INT ref null $VN.Null
***** BB01
STMT00002 (IL 0x008...0x016)
N006 ( 4, 4) [000015] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000014] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 <l:$1c1, c:$101>
N004 ( 4, 4) [000008] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000135] -------N---- \--* ADD byref $140
N001 ( 1, 1) [000007] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000134] ------------ \--* CNS_INT long 16 field offset Fseq[_array] $c1
***** BB01
STMT00001 (IL 0x008... ???)
N004 ( 3, 3) [000013] -A---O--R--- * ASG long $1c5
N003 ( 1, 1) [000012] D------N---- +--* LCL_VAR long V05 tmp1 d:2 $1c5
N002 ( 3, 2) [000011] #----O------ \--* IND long $1c5
N001 ( 1, 1) [000010] !----------- \--* LCL_VAR ref V00 this u:1 $80
***** BB01
STMT00003 (IL ???... ???)
N011 ( 8, 7) [000024] -A------R--- * ASG long <l:$280, c:$201>
N010 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3 d:2 <l:$280, c:$201>
N009 ( 8, 7) [000022] nA---------- \--* IND long <l:$280, c:$201>
N008 ( 5, 5) [000156] -A---------- \--* COMMA long $1c6
N006 ( 4, 4) [000154] -A------R--- +--* ASG long $VN.Void
N005 ( 1, 1) [000153] D------N---- | +--* LCL_VAR long V14 cse0 d:1 $1c6
N004 ( 4, 4) [000021] #----------- | \--* IND long $1c6
N003 ( 2, 2) [000020] -------N---- | \--* ADD long $240
N001 ( 1, 1) [000018] ------------ | +--* LCL_VAR long V05 tmp1 u:2 $1c5
N002 ( 1, 1) [000019] ------------ | \--* CNS_INT long 56 $c2
N007 ( 1, 1) [000155] ------------ \--* LCL_VAR long V14 cse0 u:1 $1c6
***** BB01
STMT00015 (IL ???... ???)
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
N006 ( 6, 6) [000042] J--X---N---- \--* LE int <l:$2c3, c:$2c2>
N004 ( 4, 4) [000040] ---X-------- +--* IND long <l:$244, c:$243>
N003 ( 2, 2) [000039] -------N---- | \--* ADD long <l:$242, c:$241>
N001 ( 1, 1) [000026] ------------ | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000038] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000041] ------------ \--* CNS_INT long 96 $c4
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00016 (IL ???... ???)
N011 ( 15, 13) [000116] -A---------- * JTRUE void
N010 ( 13, 11) [000033] JA-----N---- \--* EQ int <l:$2c5, c:$2c4>
N008 ( 11, 9) [000161] -A---------- +--* COMMA long <l:$282, c:$204>
N006 ( 8, 7) [000159] -A------R--- | +--* ASG long $VN.Void
N005 ( 3, 2) [000158] D------N---- | | +--* LCL_VAR long V15 cse1 d:1 <l:$282, c:$204>
N004 ( 4, 4) [000029] n----------- | | \--* IND long <l:$282, c:$204>
N003 ( 2, 2) [000028] -------N---- | | \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000025] ------------ | | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000027] ------------ | | \--* CNS_INT long 96 $c4
N007 ( 3, 2) [000160] ------------ | \--* LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
N009 ( 1, 1) [000032] ------------ \--* CNS_INT long 0 $c0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00017 (IL ???... ???)
N003 ( 3, 3) [000118] -A------R--- * ASG long <l:$282, c:$208>
N002 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4 d:4 <l:$282, c:$208>
N001 ( 3, 2) [000162] ------------ \--* LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
***** BB04
STMT00018 (IL ???... ???)
N007 ( 17, 18) [000120] -AC-G---R--- * ASG long $247
N006 ( 1, 1) [000119] D------N---- +--* LCL_VAR long V08 tmp4 d:3 $247
N005 ( 17, 18) [000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
N003 ( 1, 1) [000017] ------------ arg0 in rcx +--* LCL_VAR long V05 tmp1 u:2 (last use) $1c5
N004 ( 2, 10) [000030] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token $181
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
***** BB05
STMT00025 (IL ???... ???)
N005 ( 0, 0) [000148] -A------R--- * ASG long
N004 ( 0, 0) [000146] D------N---- +--* LCL_VAR long V08 tmp4 d:2
N003 ( 0, 0) [000147] ------------ \--* PHI long
N001 ( 0, 0) [000152] ------------ pred BB03 +--* PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ pred BB04 \--* PHI_ARG long V08 tmp4 u:3 $247
***** BB05
STMT00005 (IL ???... ???)
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
N005 ( 3, 3) [000006] ------------ this in rcx +--* ADDR byref $301
N004 ( 3, 2) [000005] ----G--N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9 $340
N006 ( 1, 1) [000045] ------------ arg1 in rdx +--* LCL_VAR long V08 tmp4 u:2 (last use) $283
N007 ( 1, 1) [000016] ------------ arg2 in r8 \--* LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
***** BB05
STMT00006 (IL 0x015... ???)
N003 ( 1, 3) [000049] -A------R--- * ASG int $40
N002 ( 1, 1) [000048] D------N---- +--* LCL_VAR int V03 loc2 d:2 $40
N001 ( 1, 1) [000047] ------------ \--* CNS_INT int 0 $40
------------ BB06 [019..02B), preds={BB11} succs={BB07}
***** BB06
STMT00012 (IL 0x019...0x022)
N013 ( 21, 22) [000107] IA-XG------- * ASG struct (init) $VN.Void
N011 ( 19, 20) [000106] D--XG--N---- +--* BLK struct<8> $1d1
N010 ( 16, 18) [000104] ---XG------- | \--* COMMA byref $145
N003 ( 8, 10) [000098] ---XG------- | +--* ARR_BOUNDS_CHECK_Rng void $1ce
N001 ( 1, 1) [000093] ------------ | | +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000097] ----G------- | | \--* LCL_VAR int (AX) V13 tmp9 $3c1
N009 ( 8, 8) [000103] ----G------- | \--* ADD byref $144
N004 ( 3, 2) [000102] ----G------- | +--* LCL_VAR byref (AX) V12 tmp8 $480
N008 ( 4, 5) [000101] ------------ | \--* LSH long $250
N006 ( 2, 3) [000099] ------------ | +--* CAST long <- int $24f
N005 ( 1, 1) [000094] ------------ | | \--* LCL_VAR int V03 loc2 u:3 $3c0
N007 ( 1, 1) [000100] ------------ | \--* CNS_INT int 3 $44
N012 ( 1, 1) [000105] ------------ \--* CNS_INT int 0 $40
***** BB06
STMT00013 (IL 0x027...0x02A)
N005 ( 3, 3) [000112] -A------R--- * ASG int $2ce
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4 $2ce
N003 ( 3, 3) [000110] ------------ \--* ADD int $2ce
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1 $4b
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
***** BB07
STMT00024 (IL ???... ???)
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
***** BB07
STMT00007 (IL 0x02B...0x033)
N004 ( 3, 3) [000057] -A-X----R--- * ASG long $1c9
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2 $1c5
N002 ( 3, 2) [000055] #--X-------- \--* IND long $1c9
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1 $80
***** BB07
STMT00008 (IL ???... ???)
N004 ( 3, 3) [000065] -A------R--- * ASG long <l:$284, c:$441>
N003 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6 d:2 <l:$284, c:$441>
N002 ( 3, 2) [000063] n----------- \--* IND long <l:$284, c:$441>
N001 ( 1, 1) [000157] ------------ \--* LCL_VAR long V14 cse0 u:1 $1c6
***** BB07
STMT00019 (IL ???... ???)
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
N006 ( 6, 6) [000083] J--X---N---- \--* LE int <l:$2ca, c:$2c9>
N004 ( 4, 4) [000081] ---X-------- +--* IND long <l:$24c, c:$24b>
N003 ( 2, 2) [000080] -------N---- | \--* ADD long <l:$24a, c:$249>
N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR long V10 tmp6 u:2 <l:$284, c:$441>
N002 ( 1, 1) [000079] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000082] ------------ \--* CNS_INT long 96 $c4
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
***** BB08
STMT00020 (IL ???... ???)
N007 ( 8, 8) [000122] ------------ * JTRUE void
N006 ( 6, 6) [000074] J------N---- \--* EQ int <l:$2cc, c:$2cb>
N004 ( 4, 4) [000070] n----------- +--* IND long <l:$286, c:$444>
N003 ( 2, 2) [000069] -------N---- | \--* ADD long <l:$24e, c:$24d>
N001 ( 1, 1) [000066] ------------ | +--* LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
N002 ( 1, 1) [000068] ------------ | \--* CNS_INT long 96 $c4
N005 ( 1, 1) [000073] ------------ \--* CNS_INT long 0 $c0
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
***** BB11
STMT00011 (IL ???... ???)
N004 ( 7, 6) [000090] ----G------- * JTRUE void
N003 ( 5, 4) [000089] J---G--N---- \--* LT int $2cd
N001 ( 1, 1) [000050] ------------ +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000132] ----G------- \--* LCL_VAR int (AX) V13 tmp9 $3c1
------------ BB12 [035..037) (return), preds={BB11} succs={}
***** BB12
STMT00014 (IL 0x035...0x036)
N002 ( 4, 3) [000114] ------------ * RETURN ref $105
N001 ( 3, 2) [000113] ------------ \--* LCL_VAR ref V01 loc0 u:2 (last use) $VN.Null
-------------------------------------------------------------------------------------------------------------------
GenTreeNode creates assertion:
N004 ( 4, 4) [000008] ---XG------- * IND ref <l:$1c4, c:$1c3>
In BB01 New Global Constant Assertion: (128, 0) ($80,$0) V00.01 != null index=#01, mask=0000000000000001
GenTreeNode creates assertion:
N003 ( 8, 10) [000098] ---XG------- * ARR_BOUNDS_CHECK_Rng void $1ce
In BB06 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {PhiDef($3, $3, $2c6)};len: {ByrefExposedLoad($47, $142, $400)}] in range index=#02, mask=0000000000000002
GenTreeNode creates assertion:
N004 ( 7, 6) [000090] ----G------- * JTRUE void
In BB11 New Global Constant Assertion: (717, 64) ($2cd,$40) Loop_Bnd { {PhiDef($3, $3, $2c6)} LT {ByrefExposedLoad($47, $142, $400)}} is not {IntCns 0} index=#03, mask=0000000000000004
GenTreeNode creates assertion:
N004 ( 7, 6) [000090] ----G------- * JTRUE void
In BB11 New Global Constant Assertion: (717, 64) ($2cd,$40) Loop_Bnd { {PhiDef($3, $3, $2c6)} LT {ByrefExposedLoad($47, $142, $400)}} is {IntCns 0} index=#04, mask=0000000000000008
After constant propagation on [000113]:
STMT00014 (IL 0x035...0x036)
N002 ( 4, 3) [000114] ------------ * RETURN ref $105
[000163] ------------ \--* CNS_INT ref null $VN.Null
optVNAssertionPropCurStmt morphed tree:
N002 ( 2, 2) [000114] ------------ * RETURN ref $105
N001 ( 1, 1) [000163] ------------ \--* CNS_INT ref null $VN.Null
BB01 valueGen = 0000000000000001 => BB04 valueGen = 0000000000000001,
BB02 valueGen = 0000000000000000 => BB04 valueGen = 0000000000000000,
BB03 valueGen = 0000000000000000
BB04 valueGen = 0000000000000000
BB05 valueGen = 0000000000000000
BB06 valueGen = 0000000000000002
BB07 valueGen = 0000000000000001 => BB10 valueGen = 0000000000000001,
BB08 valueGen = 0000000000000000 => BB10 valueGen = 0000000000000000,
BB09 valueGen = 0000000000000000
BB10 valueGen = 0000000000000000
BB11 valueGen = 0000000000000008 => BB06 valueGen = 0000000000000004,
BB12 valueGen = 0000000000000000
AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000
AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000
AssertionPropCallback::Changed : BB01 before out -> 000000000000000F; after out -> 0000000000000001;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000001;
AssertionPropCallback::StartMerge: BB02 in -> 000000000000000F
AssertionPropCallback::Merge : BB02 in -> 000000000000000F, predBlock BB01 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB02 in -> 0000000000000001
AssertionPropCallback::Changed : BB02 before out -> 000000000000000F; after out -> 0000000000000001;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000001;
AssertionPropCallback::StartMerge: BB04 in -> 000000000000000F
AssertionPropCallback::Merge : BB04 in -> 000000000000000F, predBlock BB01 out -> 0000000000000001
AssertionPropCallback::Merge : BB04 in -> 0000000000000001, predBlock BB02 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB04 in -> 0000000000000001
AssertionPropCallback::Changed : BB04 before out -> 000000000000000F; after out -> 0000000000000001;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000001;
AssertionPropCallback::StartMerge: BB03 in -> 000000000000000F
AssertionPropCallback::Merge : BB03 in -> 000000000000000F, predBlock BB02 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB03 in -> 0000000000000001
AssertionPropCallback::Changed : BB03 before out -> 000000000000000F; after out -> 0000000000000001;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000001;
AssertionPropCallback::StartMerge: BB04 in -> 0000000000000001
AssertionPropCallback::Merge : BB04 in -> 0000000000000001, predBlock BB01 out -> 0000000000000001
AssertionPropCallback::Merge : BB04 in -> 0000000000000001, predBlock BB02 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB04 in -> 0000000000000001
AssertionPropCallback::Unchanged : BB04 out -> 0000000000000001; jumpDest out -> 0000000000000001
AssertionPropCallback::StartMerge: BB05 in -> 000000000000000F
AssertionPropCallback::Merge : BB05 in -> 000000000000000F, predBlock BB03 out -> 0000000000000001
AssertionPropCallback::Merge : BB05 in -> 0000000000000001, predBlock BB04 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB05 in -> 0000000000000001
AssertionPropCallback::Changed : BB05 before out -> 000000000000000F; after out -> 0000000000000001;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000001;
AssertionPropCallback::StartMerge: BB05 in -> 0000000000000001
AssertionPropCallback::Merge : BB05 in -> 0000000000000001, predBlock BB03 out -> 0000000000000001
AssertionPropCallback::Merge : BB05 in -> 0000000000000001, predBlock BB04 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB05 in -> 0000000000000001
AssertionPropCallback::Unchanged : BB05 out -> 0000000000000001; jumpDest out -> 0000000000000001
AssertionPropCallback::StartMerge: BB07 in -> 000000000000000F
AssertionPropCallback::Merge : BB07 in -> 000000000000000F, predBlock BB05 out -> 0000000000000001
AssertionPropCallback::Merge : BB07 in -> 0000000000000001, predBlock BB06 out -> 000000000000000F
AssertionPropCallback::EndMerge : BB07 in -> 0000000000000001
AssertionPropCallback::Changed : BB07 before out -> 000000000000000F; after out -> 0000000000000001;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000001;
AssertionPropCallback::StartMerge: BB08 in -> 000000000000000F
AssertionPropCallback::Merge : BB08 in -> 000000000000000F, predBlock BB07 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB08 in -> 0000000000000001
AssertionPropCallback::Changed : BB08 before out -> 000000000000000F; after out -> 0000000000000001;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000001;
AssertionPropCallback::StartMerge: BB10 in -> 000000000000000F
AssertionPropCallback::Merge : BB10 in -> 000000000000000F, predBlock BB07 out -> 0000000000000001
AssertionPropCallback::Merge : BB10 in -> 0000000000000001, predBlock BB08 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB10 in -> 0000000000000001
AssertionPropCallback::Changed : BB10 before out -> 000000000000000F; after out -> 0000000000000001;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000001;
AssertionPropCallback::StartMerge: BB09 in -> 000000000000000F
AssertionPropCallback::Merge : BB09 in -> 000000000000000F, predBlock BB08 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB09 in -> 0000000000000001
AssertionPropCallback::Changed : BB09 before out -> 000000000000000F; after out -> 0000000000000001;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000001;
AssertionPropCallback::StartMerge: BB10 in -> 0000000000000001
AssertionPropCallback::Merge : BB10 in -> 0000000000000001, predBlock BB07 out -> 0000000000000001
AssertionPropCallback::Merge : BB10 in -> 0000000000000001, predBlock BB08 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB10 in -> 0000000000000001
AssertionPropCallback::Unchanged : BB10 out -> 0000000000000001; jumpDest out -> 0000000000000001
AssertionPropCallback::StartMerge: BB11 in -> 000000000000000F
AssertionPropCallback::Merge : BB11 in -> 000000000000000F, predBlock BB09 out -> 0000000000000001
AssertionPropCallback::Merge : BB11 in -> 0000000000000001, predBlock BB10 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB11 in -> 0000000000000001
AssertionPropCallback::Changed : BB11 before out -> 000000000000000F; after out -> 0000000000000009;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000005;
AssertionPropCallback::StartMerge: BB11 in -> 0000000000000001
AssertionPropCallback::Merge : BB11 in -> 0000000000000001, predBlock BB09 out -> 0000000000000001
AssertionPropCallback::Merge : BB11 in -> 0000000000000001, predBlock BB10 out -> 0000000000000001
AssertionPropCallback::EndMerge : BB11 in -> 0000000000000001
AssertionPropCallback::Unchanged : BB11 out -> 0000000000000009; jumpDest out -> 0000000000000005
AssertionPropCallback::StartMerge: BB12 in -> 000000000000000F
AssertionPropCallback::Merge : BB12 in -> 000000000000000F, predBlock BB11 out -> 0000000000000009
AssertionPropCallback::EndMerge : BB12 in -> 0000000000000009
AssertionPropCallback::Changed : BB12 before out -> 000000000000000F; after out -> 0000000000000009;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000009;
AssertionPropCallback::StartMerge: BB06 in -> 000000000000000F
AssertionPropCallback::Merge : BB06 in -> 000000000000000F, predBlock BB11 out -> 0000000000000009
AssertionPropCallback::EndMerge : BB06 in -> 0000000000000005
AssertionPropCallback::Changed : BB06 before out -> 000000000000000F; after out -> 0000000000000007;
jumpDest before out -> 000000000000000F; jumpDest after out -> 0000000000000005;
AssertionPropCallback::StartMerge: BB07 in -> 0000000000000001
AssertionPropCallback::Merge : BB07 in -> 0000000000000001, predBlock BB05 out -> 0000000000000001
AssertionPropCallback::Merge : BB07 in -> 0000000000000001, predBlock BB06 out -> 0000000000000007
AssertionPropCallback::EndMerge : BB07 in -> 0000000000000001
AssertionPropCallback::Unchanged : BB07 out -> 0000000000000001; jumpDest out -> 0000000000000001
BB01 valueIn = 0000000000000000 valueOut = 0000000000000001 => BB04 valueOut= 0000000000000001
BB02 valueIn = 0000000000000001 valueOut = 0000000000000001 => BB04 valueOut= 0000000000000001
BB03 valueIn = 0000000000000001 valueOut = 0000000000000001
BB04 valueIn = 0000000000000001 valueOut = 0000000000000001
BB05 valueIn = 0000000000000001 valueOut = 0000000000000001
BB06 valueIn = 0000000000000005 valueOut = 0000000000000007
BB07 valueIn = 0000000000000001 valueOut = 0000000000000001 => BB10 valueOut= 0000000000000001
BB08 valueIn = 0000000000000001 valueOut = 0000000000000001 => BB10 valueOut= 0000000000000001
BB09 valueIn = 0000000000000001 valueOut = 0000000000000001
BB10 valueIn = 0000000000000001 valueOut = 0000000000000001
BB11 valueIn = 0000000000000001 valueOut = 0000000000000009 => BB06 valueOut= 0000000000000005
BB12 valueIn = 0000000000000009 valueOut = 0000000000000009
Propagating 0000000000000000 assertions for BB01, stmt STMT00000, tree [000002], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00000, tree [000000], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00000, tree [000004], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000007], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000134], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000135], tree -> 0
Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000008], tree -> 1
Propagating 0000000000000001 assertions for BB01, stmt STMT00002, tree [000014], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00002, tree [000015], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000010], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000011], tree -> 1
Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000012], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000013], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000018], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000019], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000020], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000021], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000153], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000154], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000155], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000156], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000022], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000023], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000024], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00015, tree [000026], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00015, tree [000038], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00015, tree [000039], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00015, tree [000040], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00015, tree [000041], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00015, tree [000042], tree -> 0
Propagating 0000000000000001 assertions for BB01, stmt STMT00015, tree [000115], tree -> 0
Propagating 0000000000000001 assertions for BB02, stmt STMT00016, tree [000025], tree -> 0
Propagating 0000000000000001 assertions for BB02, stmt STMT00016, tree [000027], tree -> 0
Propagating 0000000000000001 assertions for BB02, stmt STMT00016, tree [000028], tree -> 0
Propagating 0000000000000001 assertions for BB02, stmt STMT00016, tree [000029], tree -> 0
Propagating 0000000000000001 assertions for BB02, stmt STMT00016, tree [000158], tree -> 0
Propagating 0000000000000001 assertions for BB02, stmt STMT00016, tree [000159], tree -> 0
Propagating 0000000000000001 assertions for BB02, stmt STMT00016, tree [000160], tree -> 0
Propagating 0000000000000001 assertions for BB02, stmt STMT00016, tree [000161], tree -> 0
Propagating 0000000000000001 assertions for BB02, stmt STMT00016, tree [000032], tree -> 0
Propagating 0000000000000001 assertions for BB02, stmt STMT00016, tree [000033], tree -> 0
Propagating 0000000000000001 assertions for BB02, stmt STMT00016, tree [000116], tree -> 0
Propagating 0000000000000001 assertions for BB03, stmt STMT00017, tree [000162], tree -> 0
Propagating 0000000000000001 assertions for BB03, stmt STMT00017, tree [000117], tree -> 0
Propagating 0000000000000001 assertions for BB03, stmt STMT00017, tree [000118], tree -> 0
Propagating 0000000000000001 assertions for BB04, stmt STMT00018, tree [000136], tree -> 0
Propagating 0000000000000001 assertions for BB04, stmt STMT00018, tree [000137], tree -> 0
Propagating 0000000000000001 assertions for BB04, stmt STMT00018, tree [000017], tree -> 0
Propagating 0000000000000001 assertions for BB04, stmt STMT00018, tree [000030], tree -> 0
Propagating 0000000000000001 assertions for BB04, stmt STMT00018, tree [000031], tree -> 0
Propagating 0000000000000001 assertions for BB04, stmt STMT00018, tree [000119], tree -> 0
Propagating 0000000000000001 assertions for BB04, stmt STMT00018, tree [000120], tree -> 0
Propagating 0000000000000001 assertions for BB05, stmt STMT00005, tree [000138], tree -> 0
Propagating 0000000000000001 assertions for BB05, stmt STMT00005, tree [000139], tree -> 0
Propagating 0000000000000001 assertions for BB05, stmt STMT00005, tree [000140], tree -> 0
Propagating 0000000000000001 assertions for BB05, stmt STMT00005, tree [000005], tree -> 0
Propagating 0000000000000001 assertions for BB05, stmt STMT00005, tree [000006], tree -> 0
Propagating 0000000000000001 assertions for BB05, stmt STMT00005, tree [000045], tree -> 0
Propagating 0000000000000001 assertions for BB05, stmt STMT00005, tree [000016], tree -> 0
Propagating 0000000000000001 assertions for BB05, stmt STMT00005, tree [000009], tree -> 0
Propagating 0000000000000001 assertions for BB05, stmt STMT00006, tree [000047], tree -> 0
Propagating 0000000000000001 assertions for BB05, stmt STMT00006, tree [000048], tree -> 0
Propagating 0000000000000001 assertions for BB05, stmt STMT00006, tree [000049], tree -> 0
Propagating 0000000000000005 assertions for BB06, stmt STMT00012, tree [000093], tree -> 0
Propagating 0000000000000005 assertions for BB06, stmt STMT00012, tree [000097], tree -> 0
Propagating 0000000000000005 assertions for BB06, stmt STMT00012, tree [000098], tree -> 2
Propagating 0000000000000007 assertions for BB06, stmt STMT00012, tree [000102], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00012, tree [000094], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00012, tree [000099], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00012, tree [000100], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00012, tree [000101], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00012, tree [000103], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00012, tree [000104], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00012, tree [000106], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00012, tree [000105], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00012, tree [000107], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00013, tree [000108], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00013, tree [000109], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00013, tree [000110], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00013, tree [000111], tree -> 0
Propagating 0000000000000007 assertions for BB06, stmt STMT00013, tree [000112], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00007, tree [000054], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00007, tree [000055], tree -> 1
Non-null prop for index #01 in BB07:
N002 ( 3, 2) [000055] #--X-------- * IND long $1c9
Propagating 0000000000000001 assertions for BB07, stmt STMT00007, tree [000056], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00007, tree [000057], tree -> 0
Re-morphing this stmt:
STMT00007 (IL 0x02B...0x033)
N004 ( 3, 3) [000057] -A-X----R--- * ASG long $1c9
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2 $1c5
N002 ( 3, 2) [000055] #----O------ \--* IND long $1c9
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1 $80
optAssertionPropMain morphed tree:
N004 ( 3, 3) [000057] -A---O--R--- * ASG long $1c9
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2 $1c5
N002 ( 3, 2) [000055] #----O------ \--* IND long $1c9
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1 $80
Propagating 0000000000000001 assertions for BB07, stmt STMT00008, tree [000157], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00008, tree [000063], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00008, tree [000064], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00008, tree [000065], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00019, tree [000067], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00019, tree [000079], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00019, tree [000080], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00019, tree [000081], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00019, tree [000082], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00019, tree [000083], tree -> 0
Propagating 0000000000000001 assertions for BB07, stmt STMT00019, tree [000121], tree -> 0
Propagating 0000000000000001 assertions for BB08, stmt STMT00020, tree [000066], tree -> 0
Propagating 0000000000000001 assertions for BB08, stmt STMT00020, tree [000068], tree -> 0
Propagating 0000000000000001 assertions for BB08, stmt STMT00020, tree [000069], tree -> 0
Propagating 0000000000000001 assertions for BB08, stmt STMT00020, tree [000070], tree -> 0
Propagating 0000000000000001 assertions for BB08, stmt STMT00020, tree [000073], tree -> 0
Propagating 0000000000000001 assertions for BB08, stmt STMT00020, tree [000074], tree -> 0
Propagating 0000000000000001 assertions for BB08, stmt STMT00020, tree [000122], tree -> 0
Propagating 0000000000000001 assertions for BB11, stmt STMT00011, tree [000050], tree -> 0
Propagating 0000000000000001 assertions for BB11, stmt STMT00011, tree [000132], tree -> 0
Propagating 0000000000000001 assertions for BB11, stmt STMT00011, tree [000089], tree -> 0
Propagating 0000000000000001 assertions for BB11, stmt STMT00011, tree [000090], tree -> 3
Propagating 0000000000000009 assertions for BB12, stmt STMT00014, tree [000163], tree -> 0
Propagating 0000000000000009 assertions for BB12, stmt STMT00014, tree [000114], tree -> 0
*************** In fgDebugCheckBBlist
*************** Finishing PHASE Assertion prop
*************** Starting PHASE Optimize index checks
*************** In OptimizeRangeChecks()
Blocks/trees before phase
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
***** BB01
STMT00000 (IL 0x000...0x003)
N003 ( 5, 4) [000004] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000000] D------N---- +--* LCL_VAR ref V01 loc0 d:2 $VN.Null
N001 ( 1, 1) [000002] ------------ \--* CNS_INT ref null $VN.Null
***** BB01
STMT00002 (IL 0x008...0x016)
N006 ( 4, 4) [000015] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000014] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 <l:$1c1, c:$101>
N004 ( 4, 4) [000008] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000135] -------N---- \--* ADD byref $140
N001 ( 1, 1) [000007] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000134] ------------ \--* CNS_INT long 16 field offset Fseq[_array] $c1
***** BB01
STMT00001 (IL 0x008... ???)
N004 ( 3, 3) [000013] -A---O--R--- * ASG long $1c5
N003 ( 1, 1) [000012] D------N---- +--* LCL_VAR long V05 tmp1 d:2 $1c5
N002 ( 3, 2) [000011] #----O------ \--* IND long $1c5
N001 ( 1, 1) [000010] !----------- \--* LCL_VAR ref V00 this u:1 $80
***** BB01
STMT00003 (IL ???... ???)
N011 ( 8, 7) [000024] -A------R--- * ASG long <l:$280, c:$201>
N010 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3 d:2 <l:$280, c:$201>
N009 ( 8, 7) [000022] nA---------- \--* IND long <l:$280, c:$201>
N008 ( 5, 5) [000156] -A---------- \--* COMMA long $1c6
N006 ( 4, 4) [000154] -A------R--- +--* ASG long $VN.Void
N005 ( 1, 1) [000153] D------N---- | +--* LCL_VAR long V14 cse0 d:1 $1c6
N004 ( 4, 4) [000021] #----------- | \--* IND long $1c6
N003 ( 2, 2) [000020] -------N---- | \--* ADD long $240
N001 ( 1, 1) [000018] ------------ | +--* LCL_VAR long V05 tmp1 u:2 $1c5
N002 ( 1, 1) [000019] ------------ | \--* CNS_INT long 56 $c2
N007 ( 1, 1) [000155] ------------ \--* LCL_VAR long V14 cse0 u:1 $1c6
***** BB01
STMT00015 (IL ???... ???)
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
N006 ( 6, 6) [000042] J--X---N---- \--* LE int <l:$2c3, c:$2c2>
N004 ( 4, 4) [000040] ---X-------- +--* IND long <l:$244, c:$243>
N003 ( 2, 2) [000039] -------N---- | \--* ADD long <l:$242, c:$241>
N001 ( 1, 1) [000026] ------------ | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000038] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000041] ------------ \--* CNS_INT long 96 $c4
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00016 (IL ???... ???)
N011 ( 15, 13) [000116] -A---------- * JTRUE void
N010 ( 13, 11) [000033] JA-----N---- \--* EQ int <l:$2c5, c:$2c4>
N008 ( 11, 9) [000161] -A---------- +--* COMMA long <l:$282, c:$204>
N006 ( 8, 7) [000159] -A------R--- | +--* ASG long $VN.Void
N005 ( 3, 2) [000158] D------N---- | | +--* LCL_VAR long V15 cse1 d:1 <l:$282, c:$204>
N004 ( 4, 4) [000029] n----------- | | \--* IND long <l:$282, c:$204>
N003 ( 2, 2) [000028] -------N---- | | \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000025] ------------ | | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000027] ------------ | | \--* CNS_INT long 96 $c4
N007 ( 3, 2) [000160] ------------ | \--* LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
N009 ( 1, 1) [000032] ------------ \--* CNS_INT long 0 $c0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00017 (IL ???... ???)
N003 ( 3, 3) [000118] -A------R--- * ASG long <l:$282, c:$208>
N002 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4 d:4 <l:$282, c:$208>
N001 ( 3, 2) [000162] ------------ \--* LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
***** BB04
STMT00018 (IL ???... ???)
N007 ( 17, 18) [000120] -AC-G---R--- * ASG long $247
N006 ( 1, 1) [000119] D------N---- +--* LCL_VAR long V08 tmp4 d:3 $247
N005 ( 17, 18) [000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
N003 ( 1, 1) [000017] ------------ arg0 in rcx +--* LCL_VAR long V05 tmp1 u:2 (last use) $1c5
N004 ( 2, 10) [000030] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token $181
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
***** BB05
STMT00025 (IL ???... ???)
N005 ( 0, 0) [000148] -A------R--- * ASG long
N004 ( 0, 0) [000146] D------N---- +--* LCL_VAR long V08 tmp4 d:2
N003 ( 0, 0) [000147] ------------ \--* PHI long
N001 ( 0, 0) [000152] ------------ pred BB03 +--* PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ pred BB04 \--* PHI_ARG long V08 tmp4 u:3 $247
***** BB05
STMT00005 (IL ???... ???)
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
N005 ( 3, 3) [000006] ------------ this in rcx +--* ADDR byref $301
N004 ( 3, 2) [000005] ----G--N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9 $340
N006 ( 1, 1) [000045] ------------ arg1 in rdx +--* LCL_VAR long V08 tmp4 u:2 (last use) $283
N007 ( 1, 1) [000016] ------------ arg2 in r8 \--* LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
***** BB05
STMT00006 (IL 0x015... ???)
N003 ( 1, 3) [000049] -A------R--- * ASG int $40
N002 ( 1, 1) [000048] D------N---- +--* LCL_VAR int V03 loc2 d:2 $40
N001 ( 1, 1) [000047] ------------ \--* CNS_INT int 0 $40
------------ BB06 [019..02B), preds={BB11} succs={BB07}
***** BB06
STMT00012 (IL 0x019...0x022)
N013 ( 21, 22) [000107] IA-XG------- * ASG struct (init) $VN.Void
N011 ( 19, 20) [000106] D--XG--N---- +--* BLK struct<8> $1d1
N010 ( 16, 18) [000104] ---XG------- | \--* COMMA byref $145
N003 ( 8, 10) [000098] ---XG------- | +--* ARR_BOUNDS_CHECK_Rng void $1ce
N001 ( 1, 1) [000093] ------------ | | +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000097] ----G------- | | \--* LCL_VAR int (AX) V13 tmp9 $3c1
N009 ( 8, 8) [000103] ----G------- | \--* ADD byref $144
N004 ( 3, 2) [000102] ----G------- | +--* LCL_VAR byref (AX) V12 tmp8 $480
N008 ( 4, 5) [000101] ------------ | \--* LSH long $250
N006 ( 2, 3) [000099] ------------ | +--* CAST long <- int $24f
N005 ( 1, 1) [000094] ------------ | | \--* LCL_VAR int V03 loc2 u:3 $3c0
N007 ( 1, 1) [000100] ------------ | \--* CNS_INT int 3 $44
N012 ( 1, 1) [000105] ------------ \--* CNS_INT int 0 $40
***** BB06
STMT00013 (IL 0x027...0x02A)
N005 ( 3, 3) [000112] -A------R--- * ASG int $2ce
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4 $2ce
N003 ( 3, 3) [000110] ------------ \--* ADD int $2ce
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1 $4b
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
***** BB07
STMT00024 (IL ???... ???)
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
***** BB07
STMT00007 (IL 0x02B...0x033)
N004 ( 3, 3) [000057] -A---O--R--- * ASG long $1c9
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2 $1c5
N002 ( 3, 2) [000055] #----O------ \--* IND long $1c9
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1 $80
***** BB07
STMT00008 (IL ???... ???)
N004 ( 3, 3) [000065] -A------R--- * ASG long <l:$284, c:$441>
N003 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6 d:2 <l:$284, c:$441>
N002 ( 3, 2) [000063] n----------- \--* IND long <l:$284, c:$441>
N001 ( 1, 1) [000157] ------------ \--* LCL_VAR long V14 cse0 u:1 $1c6
***** BB07
STMT00019 (IL ???... ???)
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
N006 ( 6, 6) [000083] J--X---N---- \--* LE int <l:$2ca, c:$2c9>
N004 ( 4, 4) [000081] ---X-------- +--* IND long <l:$24c, c:$24b>
N003 ( 2, 2) [000080] -------N---- | \--* ADD long <l:$24a, c:$249>
N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR long V10 tmp6 u:2 <l:$284, c:$441>
N002 ( 1, 1) [000079] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000082] ------------ \--* CNS_INT long 96 $c4
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
***** BB08
STMT00020 (IL ???... ???)
N007 ( 8, 8) [000122] ------------ * JTRUE void
N006 ( 6, 6) [000074] J------N---- \--* EQ int <l:$2cc, c:$2cb>
N004 ( 4, 4) [000070] n----------- +--* IND long <l:$286, c:$444>
N003 ( 2, 2) [000069] -------N---- | \--* ADD long <l:$24e, c:$24d>
N001 ( 1, 1) [000066] ------------ | +--* LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
N002 ( 1, 1) [000068] ------------ | \--* CNS_INT long 96 $c4
N005 ( 1, 1) [000073] ------------ \--* CNS_INT long 0 $c0
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
***** BB11
STMT00011 (IL ???... ???)
N004 ( 7, 6) [000090] ----G------- * JTRUE void
N003 ( 5, 4) [000089] J---G--N---- \--* LT int $2cd
N001 ( 1, 1) [000050] ------------ +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000132] ----G------- \--* LCL_VAR int (AX) V13 tmp9 $3c1
------------ BB12 [035..037) (return), preds={BB11} succs={}
***** BB12
STMT00014 (IL 0x035...0x036)
N002 ( 2, 2) [000114] ------------ * RETURN ref $105
N001 ( 1, 1) [000163] ------------ \--* CNS_INT ref null $VN.Null
-------------------------------------------------------------------------------------------------------------------
ArrSize for lengthVN:3C1 = 0
[RangeCheck::GetRange] BB06N001 ( 1, 1) [000093] ------------ * LCL_VAR int V03 loc2 u:3 $3c0
{
----------------------------------------------------
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
----------------------------------------------------
[RangeCheck::GetRange] BB07N003 ( 0, 0) [000144] ------------ * PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
{
[RangeCheck::GetRange] BB07N001 ( 0, 0) [000150] ------------ * PHI_ARG int V03 loc2 u:4
{
----------------------------------------------------
N005 ( 3, 3) [000112] -A------R--- * ASG int $2ce
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4 $2ce
N003 ( 3, 3) [000110] ------------ \--* ADD int $2ce
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1 $4b
----------------------------------------------------
[RangeCheck::GetRange] BB06N003 ( 3, 3) [000110] ------------ * ADD int $2ce
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1 $4b
{
[RangeCheck::GetRange] BB06N001 ( 1, 1) [000108] ------------ * LCL_VAR int V03 loc2 u:3 (last use) $3c0
{
----------------------------------------------------
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
----------------------------------------------------
[RangeCheck::GetRange] BB07N003 ( 0, 0) [000144] ------------ * PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
{
PhiArg [000150] is already being computed
Merging assertions from pred edges of BB07 for op [000150] $ffffffff
Merge assertions from pred BB06 edge: 0000000000000007
Merging ranges <Undef, Undef> <Dependent, Dependent>:<Dependent, Dependent>
[RangeCheck::GetRange] BB07N002 ( 0, 0) [000149] ------------ * PHI_ARG int V03 loc2 u:2 $40
{
Computed Range [000149] => <0, 0>
}
Merging assertions from pred edges of BB07 for op [000149] $40
Merge assertions from pred BB05 JTrue edge: 0000000000000001
Merging ranges <Dependent, Dependent> <0, 0>:<Dependent, Dependent>
Computed Range [000144] => <Dependent, Dependent>
}
Merge assertions from BB06:0000000000000005 for assignment about [000143]
Constant Assertion: (717, 64) ($2cd,$40) Loop_Bnd { {PhiDef($3, $3, $2c6)} LT {ByrefExposedLoad($47, $142, $400)}} is not {IntCns 0} index=#03, mask=0000000000000004
The range after edge merging:<Dependent, $3c1 + -1>
done merging
Merging assertions from pred edges of BB06 for op [000108] $3c0
Constant Assertion: (717, 64) ($2cd,$40) Loop_Bnd { {PhiDef($3, $3, $2c6)} LT {ByrefExposedLoad($47, $142, $400)}} is not {IntCns 0} index=#03, mask=0000000000000004
Bound limit -1 doesn't tighten current bound -1
Computed Range [000108] => <Dependent, $3c1 + -1>
}
Merging assertions from pred edges of BB06 for op [000108] $3c0
Constant Assertion: (717, 64) ($2cd,$40) Loop_Bnd { {PhiDef($3, $3, $2c6)} LT {ByrefExposedLoad($47, $142, $400)}} is not {IntCns 0} index=#03, mask=0000000000000004
Bound limit -1 doesn't tighten current bound -1
[RangeCheck::GetRange] BB06N002 ( 1, 1) [000109] ------------ * CNS_INT int 1 $4b
{
Computed Range [000109] => <1, 1>
}
Merging assertions from pred edges of BB06 for op [000109] $4b
BinOp add ranges <Dependent, $3c1 + -1> <1, 1> = <Dependent, $3c1 + 0>
Computed Range [000110] => <Dependent, $3c1 + 0>
}
Merge assertions from BB07:0000000000000001 for assignment about [000111]
done merging
Merging assertions from pred edges of BB07 for op [000150] $ffffffff
Merge assertions from pred BB06 edge: 0000000000000007
Computed Range [000150] => <Dependent, $3c1 + 0>
}
Merging assertions from pred edges of BB07 for op [000150] $ffffffff
Merge assertions from pred BB06 edge: 0000000000000007
Merging ranges <Undef, Undef> <Dependent, $3c1 + 0>:<Dependent, $3c1 + 0>
[RangeCheck::GetRange] BB07N002 ( 0, 0) [000149] ------------ * PHI_ARG int V03 loc2 u:2 $40
{
Cached Range [000149] => <0, 0>
}
Merging assertions from pred edges of BB07 for op [000149] $40
Merge assertions from pred BB05 JTrue edge: 0000000000000001
Merging ranges <Dependent, $3c1 + 0> <0, 0>:<Dependent, $3c1 + 0>
Computed Range [000144] => <Dependent, $3c1 + 0>
}
Merge assertions from BB06:0000000000000005 for assignment about [000143]
Constant Assertion: (717, 64) ($2cd,$40) Loop_Bnd { {PhiDef($3, $3, $2c6)} LT {ByrefExposedLoad($47, $142, $400)}} is not {IntCns 0} index=#03, mask=0000000000000004
The range after edge merging:<Dependent, $3c1 + -1>
done merging
Merging assertions from pred edges of BB06 for op [000093] $3c0
Constant Assertion: (717, 64) ($2cd,$40) Loop_Bnd { {PhiDef($3, $3, $2c6)} LT {ByrefExposedLoad($47, $142, $400)}} is not {IntCns 0} index=#03, mask=0000000000000004
Bound limit -1 doesn't tighten current bound -1
Computed Range [000093] => <Dependent, $3c1 + -1>
}
Does overflow [000093]?
Does overflow [000144]?
Does overflow [000150]?
Does overflow [000110]?
Does overflow [000108]?
Does overflow [000144]?
Does overflow [000149]?
[000149] does not overflow
[000144] does not overflow
[000108] does not overflow
Does overflow [000109]?
[000109] does not overflow
Checking bin op overflow <Dependent, $3c1 + -1> <1, 1>
[000110] does not overflow
[000150] does not overflow
[000144] does not overflow
[000093] does not overflow
Range value <Dependent, $3c1 + -1>
[RangeCheck::Widen] BB06,
[000093]
[RangeCheck::IsMonotonicallyIncreasing] [000093]
[RangeCheck::IsMonotonicallyIncreasing] [000144]
[RangeCheck::IsMonotonicallyIncreasing] [000150]
[RangeCheck::IsMonotonicallyIncreasing] [000110]
[RangeCheck::IsBinOpMonotonicallyIncreasing] [000108], [000109]
[RangeCheck::IsMonotonicallyIncreasing] [000108]
[RangeCheck::IsMonotonicallyIncreasing] [000144]
[RangeCheck::IsMonotonicallyIncreasing] [000149]
[000093] is monotonically increasing.
[RangeCheck::GetRange] BB06N001 ( 1, 1) [000093] ------------ * LCL_VAR int V03 loc2 u:3 $3c0
{
----------------------------------------------------
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
----------------------------------------------------
[RangeCheck::GetRange] BB07N003 ( 0, 0) [000144] ------------ * PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
{
[RangeCheck::GetRange] BB07N001 ( 0, 0) [000150] ------------ * PHI_ARG int V03 loc2 u:4
{
----------------------------------------------------
N005 ( 3, 3) [000112] -A------R--- * ASG int $2ce
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4 $2ce
N003 ( 3, 3) [000110] ------------ \--* ADD int $2ce
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1 $4b
----------------------------------------------------
[RangeCheck::GetRange] BB06N003 ( 3, 3) [000110] ------------ * ADD int $2ce
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1 $4b
{
[RangeCheck::GetRange] BB06N001 ( 1, 1) [000108] ------------ * LCL_VAR int V03 loc2 u:3 (last use) $3c0
{
----------------------------------------------------
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
----------------------------------------------------
[RangeCheck::GetRange] BB07N003 ( 0, 0) [000144] ------------ * PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
{
PhiArg [000150] is already being computed
Merging assertions from pred edges of BB07 for op [000150] $ffffffff
Merge assertions from pred BB06 edge: 0000000000000007
Merging ranges <Undef, Undef> <Dependent, Dependent>:<Dependent, Dependent>
[RangeCheck::GetRange] BB07N002 ( 0, 0) [000149] ------------ * PHI_ARG int V03 loc2 u:2 $40
{
Computed Range [000149] => <0, 0>
}
Merging assertions from pred edges of BB07 for op [000149] $40
Merge assertions from pred BB05 JTrue edge: 0000000000000001
Merging ranges <Dependent, Dependent> <0, 0>:<0, Dependent>
Computed Range [000144] => <0, Dependent>
}
Merge assertions from BB06:0000000000000005 for assignment about [000143]
Constant Assertion: (717, 64) ($2cd,$40) Loop_Bnd { {PhiDef($3, $3, $2c6)} LT {ByrefExposedLoad($47, $142, $400)}} is not {IntCns 0} index=#03, mask=0000000000000004
The range after edge merging:<0, $3c1 + -1>
done merging
Merging assertions from pred edges of BB06 for op [000108] $3c0
Constant Assertion: (717, 64) ($2cd,$40) Loop_Bnd { {PhiDef($3, $3, $2c6)} LT {ByrefExposedLoad($47, $142, $400)}} is not {IntCns 0} index=#03, mask=0000000000000004
Bound limit -1 doesn't tighten current bound -1
Computed Range [000108] => <0, $3c1 + -1>
}
Merging assertions from pred edges of BB06 for op [000108] $3c0
Constant Assertion: (717, 64) ($2cd,$40) Loop_Bnd { {PhiDef($3, $3, $2c6)} LT {ByrefExposedLoad($47, $142, $400)}} is not {IntCns 0} index=#03, mask=0000000000000004
Bound limit -1 doesn't tighten current bound -1
[RangeCheck::GetRange] BB06N002 ( 1, 1) [000109] ------------ * CNS_INT int 1 $4b
{
Computed Range [000109] => <1, 1>
}
Merging assertions from pred edges of BB06 for op [000109] $4b
BinOp add ranges <0, $3c1 + -1> <1, 1> = <1, $3c1 + 0>
Computed Range [000110] => <1, $3c1 + 0>
}
Merge assertions from BB07:0000000000000001 for assignment about [000111]
done merging
Merging assertions from pred edges of BB07 for op [000150] $ffffffff
Merge assertions from pred BB06 edge: 0000000000000007
Computed Range [000150] => <1, $3c1 + 0>
}
Merging assertions from pred edges of BB07 for op [000150] $ffffffff
Merge assertions from pred BB06 edge: 0000000000000007
Merging ranges <Undef, Undef> <1, $3c1 + 0>:<1, $3c1 + 0>
[RangeCheck::GetRange] BB07N002 ( 0, 0) [000149] ------------ * PHI_ARG int V03 loc2 u:2 $40
{
Cached Range [000149] => <0, 0>
}
Merging assertions from pred edges of BB07 for op [000149] $40
Merge assertions from pred BB05 JTrue edge: 0000000000000001
Merging ranges <1, $3c1 + 0> <0, 0>:<0, $3c1 + 0>
Computed Range [000144] => <0, $3c1 + 0>
}
Merge assertions from BB06:0000000000000005 for assignment about [000143]
Constant Assertion: (717, 64) ($2cd,$40) Loop_Bnd { {PhiDef($3, $3, $2c6)} LT {ByrefExposedLoad($47, $142, $400)}} is not {IntCns 0} index=#03, mask=0000000000000004
The range after edge merging:<0, $3c1 + -1>
done merging
Merging assertions from pred edges of BB06 for op [000093] $3c0
Constant Assertion: (717, 64) ($2cd,$40) Loop_Bnd { {PhiDef($3, $3, $2c6)} LT {ByrefExposedLoad($47, $142, $400)}} is not {IntCns 0} index=#03, mask=0000000000000004
Bound limit -1 doesn't tighten current bound -1
Computed Range [000093] => <0, $3c1 + -1>
}
<0, $3c1 + -1> BetweenBounds <0, [000097]>
$3c1 upper bound is: {ByrefExposedLoad($47, $142, $400)}
Array size is: 0
[RangeCheck::OptimizeRangeCheck] Between bounds
Before optRemoveRangeCheck:
N010 ( 16, 18) [000104] ---XG------- * COMMA byref $145
N003 ( 8, 10) [000098] ---XG------- +--* ARR_BOUNDS_CHECK_Rng void $1ce
N001 ( 1, 1) [000093] ------------ | +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000097] ----G------- | \--* LCL_VAR int (AX) V13 tmp9 $3c1
N009 ( 8, 8) [000103] ----G------- \--* ADD byref $144
N004 ( 3, 2) [000102] ----G------- +--* LCL_VAR byref (AX) V12 tmp8 $480
N008 ( 4, 5) [000101] ------------ \--* LSH long $250
N006 ( 2, 3) [000099] ------------ +--* CAST long <- int $24f
N005 ( 1, 1) [000094] ------------ | \--* LCL_VAR int V03 loc2 u:3 $3c0
N007 ( 1, 1) [000100] ------------ \--* CNS_INT int 3 $44
After optRemoveRangeCheck:
N008 ( 8, 8) [000104] ----G--N---- * COMMA byref $145
N001 ( 0, 0) [000164] ------------ +--* NOP void
N007 ( 8, 8) [000103] ----G------- \--* ADD byref $144
N002 ( 3, 2) [000102] ----G------- +--* LCL_VAR byref (AX) V12 tmp8 $480
N006 ( 4, 5) [000101] ------------ \--* LSH long $250
N004 ( 2, 3) [000099] ------------ +--* CAST long <- int $24f
N003 ( 1, 1) [000094] ------------ | \--* LCL_VAR int V03 loc2 u:3 $3c0
N005 ( 1, 1) [000100] ------------ \--* CNS_INT int 3 $44
*************** Finishing PHASE Optimize index checks
*************** Starting PHASE Insert GC Polls
*************** Finishing PHASE Insert GC Polls [no changes]
*************** Starting PHASE Determine first cold block
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** Finishing PHASE Determine first cold block
Trees before Rationalize IR
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd
BB12 [0003] 1 BB11 1 [035..037) (return) i
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
***** BB01
STMT00000 (IL 0x000...0x003)
N003 ( 5, 4) [000004] -A------R--- * ASG ref $VN.Null
N002 ( 3, 2) [000000] D------N---- +--* LCL_VAR ref V01 loc0 d:2 $VN.Null
N001 ( 1, 1) [000002] ------------ \--* CNS_INT ref null $VN.Null
***** BB01
STMT00002 (IL 0x008...0x016)
N006 ( 4, 4) [000015] -A-XG---R--- * ASG ref <l:$1c4, c:$1c3>
N005 ( 1, 1) [000014] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 <l:$1c1, c:$101>
N004 ( 4, 4) [000008] ---XG------- \--* IND ref <l:$1c4, c:$1c3>
N003 ( 2, 2) [000135] -------N---- \--* ADD byref $140
N001 ( 1, 1) [000007] ------------ +--* LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000134] ------------ \--* CNS_INT long 16 field offset Fseq[_array] $c1
***** BB01
STMT00001 (IL 0x008... ???)
N004 ( 3, 3) [000013] -A---O--R--- * ASG long $1c5
N003 ( 1, 1) [000012] D------N---- +--* LCL_VAR long V05 tmp1 d:2 $1c5
N002 ( 3, 2) [000011] #----O------ \--* IND long $1c5
N001 ( 1, 1) [000010] !----------- \--* LCL_VAR ref V00 this u:1 $80
***** BB01
STMT00003 (IL ???... ???)
N011 ( 8, 7) [000024] -A------R--- * ASG long <l:$280, c:$201>
N010 ( 1, 1) [000023] D------N---- +--* LCL_VAR long V07 tmp3 d:2 <l:$280, c:$201>
N009 ( 8, 7) [000022] nA---------- \--* IND long <l:$280, c:$201>
N008 ( 5, 5) [000156] -A---------- \--* COMMA long $1c6
N006 ( 4, 4) [000154] -A------R--- +--* ASG long $VN.Void
N005 ( 1, 1) [000153] D------N---- | +--* LCL_VAR long V14 cse0 d:1 $1c6
N004 ( 4, 4) [000021] #----------- | \--* IND long $1c6
N003 ( 2, 2) [000020] -------N---- | \--* ADD long $240
N001 ( 1, 1) [000018] ------------ | +--* LCL_VAR long V05 tmp1 u:2 $1c5
N002 ( 1, 1) [000019] ------------ | \--* CNS_INT long 56 $c2
N007 ( 1, 1) [000155] ------------ \--* LCL_VAR long V14 cse0 u:1 $1c6
***** BB01
STMT00015 (IL ???... ???)
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
N006 ( 6, 6) [000042] J--X---N---- \--* LE int <l:$2c3, c:$2c2>
N004 ( 4, 4) [000040] ---X-------- +--* IND long <l:$244, c:$243>
N003 ( 2, 2) [000039] -------N---- | \--* ADD long <l:$242, c:$241>
N001 ( 1, 1) [000026] ------------ | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000038] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000041] ------------ \--* CNS_INT long 96 $c4
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
***** BB02
STMT00016 (IL ???... ???)
N011 ( 15, 13) [000116] -A---------- * JTRUE void
N010 ( 13, 11) [000033] JA-----N---- \--* EQ int <l:$2c5, c:$2c4>
N008 ( 11, 9) [000161] -A---------- +--* COMMA long <l:$282, c:$204>
N006 ( 8, 7) [000159] -A------R--- | +--* ASG long $VN.Void
N005 ( 3, 2) [000158] D------N---- | | +--* LCL_VAR long V15 cse1 d:1 <l:$282, c:$204>
N004 ( 4, 4) [000029] n----------- | | \--* IND long <l:$282, c:$204>
N003 ( 2, 2) [000028] -------N---- | | \--* ADD long <l:$246, c:$245>
N001 ( 1, 1) [000025] ------------ | | +--* LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000027] ------------ | | \--* CNS_INT long 96 $c4
N007 ( 3, 2) [000160] ------------ | \--* LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
N009 ( 1, 1) [000032] ------------ \--* CNS_INT long 0 $c0
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
***** BB03
STMT00017 (IL ???... ???)
N003 ( 3, 3) [000118] -A------R--- * ASG long <l:$282, c:$208>
N002 ( 1, 1) [000117] D------N---- +--* LCL_VAR long V08 tmp4 d:4 <l:$282, c:$208>
N001 ( 3, 2) [000162] ------------ \--* LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
***** BB04
STMT00018 (IL ???... ???)
N007 ( 17, 18) [000120] -AC-G---R--- * ASG long $247
N006 ( 1, 1) [000119] D------N---- +--* LCL_VAR long V08 tmp4 d:3 $247
N005 ( 17, 18) [000031] --C-G------- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
N003 ( 1, 1) [000017] ------------ arg0 in rcx +--* LCL_VAR long V05 tmp1 u:2 (last use) $1c5
N004 ( 2, 10) [000030] ------------ arg1 in rdx \--* CNS_INT(h) long 0x7ff9f1337fe8 token $181
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
***** BB05
STMT00025 (IL ???... ???)
N005 ( 0, 0) [000148] -A------R--- * ASG long
N004 ( 0, 0) [000146] D------N---- +--* LCL_VAR long V08 tmp4 d:2
N003 ( 0, 0) [000147] ------------ \--* PHI long
N001 ( 0, 0) [000152] ------------ pred BB03 +--* PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ pred BB04 \--* PHI_ARG long V08 tmp4 u:3 $247
***** BB05
STMT00005 (IL ???... ???)
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
N005 ( 3, 3) [000006] ------------ this in rcx +--* ADDR byref $301
N004 ( 3, 2) [000005] ----G--N---- | \--* LCL_VAR struct<System.Span`1[__Canon], 16>(AX)(P) V02 loc1
| \--* byref V02._pointer (offs=0x00) -> V12 tmp8
| \--* int V02._length (offs=0x08) -> V13 tmp9 $340
N006 ( 1, 1) [000045] ------------ arg1 in rdx +--* LCL_VAR long V08 tmp4 u:2 (last use) $283
N007 ( 1, 1) [000016] ------------ arg2 in r8 \--* LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
***** BB05
STMT00006 (IL 0x015... ???)
N003 ( 1, 3) [000049] -A------R--- * ASG int $40
N002 ( 1, 1) [000048] D------N---- +--* LCL_VAR int V03 loc2 d:2 $40
N001 ( 1, 1) [000047] ------------ \--* CNS_INT int 0 $40
------------ BB06 [019..02B), preds={BB11} succs={BB07}
***** BB06
STMT00012 (IL 0x019...0x022)
N011 ( 13, 12) [000107] IA-XG------- * ASG struct (init) $VN.Void
N009 ( 11, 10) [000106] D--XG--N---- +--* BLK struct<8> $1d1
N008 ( 8, 8) [000104] ----G--N---- | \--* COMMA byref $145
N001 ( 0, 0) [000164] ------------ | +--* NOP void
N007 ( 8, 8) [000103] ----G------- | \--* ADD byref $144
N002 ( 3, 2) [000102] ----G------- | +--* LCL_VAR byref (AX) V12 tmp8 $480
N006 ( 4, 5) [000101] ------------ | \--* LSH long $250
N004 ( 2, 3) [000099] ------------ | +--* CAST long <- int $24f
N003 ( 1, 1) [000094] ------------ | | \--* LCL_VAR int V03 loc2 u:3 $3c0
N005 ( 1, 1) [000100] ------------ | \--* CNS_INT int 3 $44
N010 ( 1, 1) [000105] ------------ \--* CNS_INT int 0 $40
***** BB06
STMT00013 (IL 0x027...0x02A)
N005 ( 3, 3) [000112] -A------R--- * ASG int $2ce
N004 ( 1, 1) [000111] D------N---- +--* LCL_VAR int V03 loc2 d:4 $2ce
N003 ( 3, 3) [000110] ------------ \--* ADD int $2ce
N001 ( 1, 1) [000108] ------------ +--* LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ \--* CNS_INT int 1 $4b
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
***** BB07
STMT00024 (IL ???... ???)
N005 ( 0, 0) [000145] -A------R--- * ASG int
N004 ( 0, 0) [000143] D------N---- +--* LCL_VAR int V03 loc2 d:3
N003 ( 0, 0) [000144] ------------ \--* PHI int
N001 ( 0, 0) [000150] ------------ pred BB06 +--* PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ pred BB05 \--* PHI_ARG int V03 loc2 u:2 $40
***** BB07
STMT00007 (IL 0x02B...0x033)
N004 ( 3, 3) [000057] -A---O--R--- * ASG long $1c9
N003 ( 1, 1) [000056] D------N---- +--* LCL_VAR long V09 tmp5 d:2 $1c5
N002 ( 3, 2) [000055] #----O------ \--* IND long $1c9
N001 ( 1, 1) [000054] !----------- \--* LCL_VAR ref V00 this u:1 $80
***** BB07
STMT00008 (IL ???... ???)
N004 ( 3, 3) [000065] -A------R--- * ASG long <l:$284, c:$441>
N003 ( 1, 1) [000064] D------N---- +--* LCL_VAR long V10 tmp6 d:2 <l:$284, c:$441>
N002 ( 3, 2) [000063] n----------- \--* IND long <l:$284, c:$441>
N001 ( 1, 1) [000157] ------------ \--* LCL_VAR long V14 cse0 u:1 $1c6
***** BB07
STMT00019 (IL ???... ???)
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
N006 ( 6, 6) [000083] J--X---N---- \--* LE int <l:$2ca, c:$2c9>
N004 ( 4, 4) [000081] ---X-------- +--* IND long <l:$24c, c:$24b>
N003 ( 2, 2) [000080] -------N---- | \--* ADD long <l:$24a, c:$249>
N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR long V10 tmp6 u:2 <l:$284, c:$441>
N002 ( 1, 1) [000079] ------------ | \--* CNS_INT long 8 $c3
N005 ( 1, 1) [000082] ------------ \--* CNS_INT long 96 $c4
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
***** BB08
STMT00020 (IL ???... ???)
N007 ( 8, 8) [000122] ------------ * JTRUE void
N006 ( 6, 6) [000074] J------N---- \--* EQ int <l:$2cc, c:$2cb>
N004 ( 4, 4) [000070] n----------- +--* IND long <l:$286, c:$444>
N003 ( 2, 2) [000069] -------N---- | \--* ADD long <l:$24e, c:$24d>
N001 ( 1, 1) [000066] ------------ | +--* LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
N002 ( 1, 1) [000068] ------------ | \--* CNS_INT long 96 $c4
N005 ( 1, 1) [000073] ------------ \--* CNS_INT long 0 $c0
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
***** BB11
STMT00011 (IL ???... ???)
N004 ( 7, 6) [000090] ----G------- * JTRUE void
N003 ( 5, 4) [000089] J---G--N---- \--* LT int $2cd
N001 ( 1, 1) [000050] ------------ +--* LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000132] ----G------- \--* LCL_VAR int (AX) V13 tmp9 $3c1
------------ BB12 [035..037) (return), preds={BB11} succs={}
***** BB12
STMT00014 (IL 0x035...0x036)
N002 ( 2, 2) [000114] ------------ * RETURN ref $105
N001 ( 1, 1) [000163] ------------ \--* CNS_INT ref null $VN.Null
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Rationalize IR
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 5, 4) [000004] DA---------- * STORE_LCL_VAR ref V01 loc0 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N006 ( 4, 4) [000015] DA-XG------- * STORE_LCL_VAR ref V06 tmp2 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 3, 3) [000013] DA---O------ * STORE_LCL_VAR long V05 tmp1 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N006 ( 4, 4) [000154] DA---------- * STORE_LCL_VAR long V14 cse0 d:1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N011 ( 8, 7) [000024] DA---------- * STORE_LCL_VAR long V07 tmp3 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N006 ( 8, 7) [000159] DA---------- * STORE_LCL_VAR long V15 cse1 d:1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR long V08 tmp4 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N007 ( 17, 18) [000120] DAC-G------- * STORE_LCL_VAR long V08 tmp4 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 0, 0) [000148] DA---------- * STORE_LCL_VAR long V08 tmp4 d:2
Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR:
N004 ( 3, 2) [000005] -------N---- t5 = LCL_VAR_ADDR byref V02 loc1
* byref V02._pointer (offs=0x00) -> V12 tmp8
* int V02._length (offs=0x08) -> V13 tmp9
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 1, 3) [000049] DA---------- * STORE_LCL_VAR int V03 loc2 d:2
Rewriting GT_ASG(BLK(X), Y) to STORE_BLK(X,Y):
N002 ( 3, 2) [000102] ------------ t102 = LCL_VAR byref (AX) V12 tmp8 $480
N003 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V03 loc2 u:3 $3c0
/--* t94 int
N004 ( 2, 3) [000099] ------------ t99 = * CAST long <- int $24f
N005 ( 1, 1) [000100] ------------ t100 = CNS_INT int 3 $44
/--* t99 long
+--* t100 int
N006 ( 4, 5) [000101] ------------ t101 = * LSH long $250
/--* t102 byref
+--* t101 long
N007 ( 8, 8) [000103] ----G------- t103 = * ADD byref $144
N010 ( 1, 1) [000105] ------------ t105 = CNS_INT int 0 $40
/--* t103 byref
+--* t105 int
N009 ( 11, 10) [000106] -A-XG------- * STORE_BLK struct<8> (init) $1d1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 3, 3) [000112] DA---------- * STORE_LCL_VAR int V03 loc2 d:4
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 0, 0) [000145] DA---------- * STORE_LCL_VAR int V03 loc2 d:3
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 3, 3) [000057] DA---O------ * STORE_LCL_VAR long V09 tmp5 d:2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR long V10 tmp6 d:2
*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target LIR
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i LIR
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i LIR
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall LIR
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall LIR
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target LIR
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd LIR
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i LIR
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i LIR
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall LIR
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd LIR
BB12 [0003] 1 BB11 1 [035..037) (return) i LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
[000165] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000002] ------------ t2 = CNS_INT ref null $VN.Null
/--* t2 ref
N003 ( 5, 4) [000004] DA---------- * STORE_LCL_VAR ref V01 loc0 d:2
[000166] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000134] ------------ t134 = CNS_INT long 16 field offset Fseq[_array] $c1
/--* t7 ref
+--* t134 long
N003 ( 2, 2) [000135] -------N---- t135 = * ADD byref $140
/--* t135 byref
N004 ( 4, 4) [000008] ---XG------- t8 = * IND ref <l:$1c4, c:$1c3>
/--* t8 ref
N006 ( 4, 4) [000015] DA-XG------- * STORE_LCL_VAR ref V06 tmp2 d:2
[000167] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000010] !----------- t10 = LCL_VAR ref V00 this u:1 $80
/--* t10 ref
N002 ( 3, 2) [000011] #----O------ t11 = * IND long $1c5
/--* t11 long
N004 ( 3, 3) [000013] DA---O------ * STORE_LCL_VAR long V05 tmp1 d:2
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR long V05 tmp1 u:2 $1c5
N002 ( 1, 1) [000019] ------------ t19 = CNS_INT long 56 $c2
/--* t18 long
+--* t19 long
N003 ( 2, 2) [000020] -------N---- t20 = * ADD long $240
/--* t20 long
N004 ( 4, 4) [000021] #----------- t21 = * IND long $1c6
/--* t21 long
N006 ( 4, 4) [000154] DA---------- * STORE_LCL_VAR long V14 cse0 d:1
N007 ( 1, 1) [000155] ------------ t155 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t155 long
N009 ( 8, 7) [000022] n----------- t22 = * IND long <l:$280, c:$201>
/--* t22 long
N011 ( 8, 7) [000024] DA---------- * STORE_LCL_VAR long V07 tmp3 d:2
N001 ( 1, 1) [000026] ------------ t26 = LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000038] ------------ t38 = CNS_INT long 8 $c3
/--* t26 long
+--* t38 long
N003 ( 2, 2) [000039] -------N---- t39 = * ADD long <l:$242, c:$241>
/--* t39 long
N004 ( 4, 4) [000040] ---X-------- t40 = * IND long <l:$244, c:$243>
N005 ( 1, 1) [000041] ------------ t41 = CNS_INT long 96 $c4
/--* t40 long
+--* t41 long
N006 ( 6, 6) [000042] J--X---N---- t42 = * LE int <l:$2c3, c:$2c2>
/--* t42 int
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000027] ------------ t27 = CNS_INT long 96 $c4
/--* t25 long
+--* t27 long
N003 ( 2, 2) [000028] -------N---- t28 = * ADD long <l:$246, c:$245>
/--* t28 long
N004 ( 4, 4) [000029] n----------- t29 = * IND long <l:$282, c:$204>
/--* t29 long
N006 ( 8, 7) [000159] DA---------- * STORE_LCL_VAR long V15 cse1 d:1
N007 ( 3, 2) [000160] ------------ t160 = LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
N009 ( 1, 1) [000032] ------------ t32 = CNS_INT long 0 $c0
/--* t160 long
+--* t32 long
N010 ( 13, 11) [000033] J------N---- t33 = * EQ int <l:$2c5, c:$2c4>
/--* t33 int
N011 ( 15, 13) [000116] ------------ * JTRUE void
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
N001 ( 3, 2) [000162] ------------ t162 = LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
/--* t162 long
N003 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR long V08 tmp4 d:4
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR long V05 tmp1 u:2 (last use) $1c5
N004 ( 2, 10) [000030] ------------ t30 = CNS_INT(h) long 0x7ff9f1337fe8 token $181
/--* t17 long arg0 in rcx
+--* t30 long arg1 in rdx
N005 ( 17, 18) [000031] --C-G------- t31 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
/--* t31 long
N007 ( 17, 18) [000120] DA--G------- * STORE_LCL_VAR long V08 tmp4 d:3
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ t151 = PHI_ARG long V08 tmp4 u:3 $247
/--* t152 long
+--* t151 long
N003 ( 0, 0) [000147] ------------ t147 = * PHI long
/--* t147 long
N005 ( 0, 0) [000148] DA---------- * STORE_LCL_VAR long V08 tmp4 d:2
N004 ( 3, 2) [000005] -------N---- t5 = LCL_VAR_ADDR byref V02 loc1
* byref V02._pointer (offs=0x00) -> V12 tmp8
* int V02._length (offs=0x08) -> V13 tmp9
N006 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V08 tmp4 u:2 (last use) $283
N007 ( 1, 1) [000016] ------------ t16 = LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
/--* t5 byref this in rcx
+--* t45 long arg1 in rdx
+--* t16 ref arg2 in r8
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
[000168] ------------ IL_OFFSET void IL offset: 0x15
N001 ( 1, 1) [000047] ------------ t47 = CNS_INT int 0 $40
/--* t47 int
N003 ( 1, 3) [000049] DA---------- * STORE_LCL_VAR int V03 loc2 d:2
------------ BB06 [019..02B), preds={BB11} succs={BB07}
[000169] ------------ IL_OFFSET void IL offset: 0x19
N002 ( 3, 2) [000102] ------------ t102 = LCL_VAR byref (AX) V12 tmp8 $480
N003 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V03 loc2 u:3 $3c0
/--* t94 int
N004 ( 2, 3) [000099] ------------ t99 = * CAST long <- int $24f
N005 ( 1, 1) [000100] ------------ t100 = CNS_INT int 3 $44
/--* t99 long
+--* t100 int
N006 ( 4, 5) [000101] ------------ t101 = * LSH long $250
/--* t102 byref
+--* t101 long
N007 ( 8, 8) [000103] ----G------- t103 = * ADD byref $144
N010 ( 1, 1) [000105] ------------ t105 = CNS_INT int 0 $40
/--* t103 byref
+--* t105 int
N009 ( 11, 10) [000106] -A-XG------- * STORE_BLK struct<8> (init) $1d1
[000170] ------------ IL_OFFSET void IL offset: 0x27
N001 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ t109 = CNS_INT int 1 $4b
/--* t108 int
+--* t109 int
N003 ( 3, 3) [000110] ------------ t110 = * ADD int $2ce
/--* t110 int
N005 ( 3, 3) [000112] DA---------- * STORE_LCL_VAR int V03 loc2 d:4
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ t149 = PHI_ARG int V03 loc2 u:2 $40
/--* t150 int
+--* t149 int
N003 ( 0, 0) [000144] ------------ t144 = * PHI int
/--* t144 int
N005 ( 0, 0) [000145] DA---------- * STORE_LCL_VAR int V03 loc2 d:3
[000171] ------------ IL_OFFSET void IL offset: 0x2b
N001 ( 1, 1) [000054] !----------- t54 = LCL_VAR ref V00 this u:1 $80
/--* t54 ref
N002 ( 3, 2) [000055] #----O------ t55 = * IND long $1c9
/--* t55 long
N004 ( 3, 3) [000057] DA---O------ * STORE_LCL_VAR long V09 tmp5 d:2
N001 ( 1, 1) [000157] ------------ t157 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t157 long
N002 ( 3, 2) [000063] n----------- t63 = * IND long <l:$284, c:$441>
/--* t63 long
N004 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR long V10 tmp6 d:2
N001 ( 1, 1) [000067] ------------ t67 = LCL_VAR long V10 tmp6 u:2 <l:$284, c:$441>
N002 ( 1, 1) [000079] ------------ t79 = CNS_INT long 8 $c3
/--* t67 long
+--* t79 long
N003 ( 2, 2) [000080] -------N---- t80 = * ADD long <l:$24a, c:$249>
/--* t80 long
N004 ( 4, 4) [000081] ---X-------- t81 = * IND long <l:$24c, c:$24b>
N005 ( 1, 1) [000082] ------------ t82 = CNS_INT long 96 $c4
/--* t81 long
+--* t82 long
N006 ( 6, 6) [000083] J--X---N---- t83 = * LE int <l:$2ca, c:$2c9>
/--* t83 int
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
N001 ( 1, 1) [000066] ------------ t66 = LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
N002 ( 1, 1) [000068] ------------ t68 = CNS_INT long 96 $c4
/--* t66 long
+--* t68 long
N003 ( 2, 2) [000069] -------N---- t69 = * ADD long <l:$24e, c:$24d>
/--* t69 long
N004 ( 4, 4) [000070] n----------- t70 = * IND long <l:$286, c:$444>
N005 ( 1, 1) [000073] ------------ t73 = CNS_INT long 0 $c0
/--* t70 long
+--* t73 long
N006 ( 6, 6) [000074] J------N---- t74 = * EQ int <l:$2cc, c:$2cb>
/--* t74 int
N007 ( 8, 8) [000122] ------------ * JTRUE void
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
N001 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000132] ------------ t132 = LCL_VAR int (AX) V13 tmp9 $3c1
/--* t50 int
+--* t132 int
N003 ( 5, 4) [000089] J---G--N---- t89 = * LT int $2cd
/--* t89 int
N004 ( 7, 6) [000090] ----G------- * JTRUE void
------------ BB12 [035..037) (return), preds={BB11} succs={}
[000172] ------------ IL_OFFSET void IL offset: 0x35
N001 ( 1, 1) [000163] ------------ t163 = CNS_INT ref null $VN.Null
/--* t163 ref
N002 ( 2, 2) [000114] ------------ * RETURN ref $105
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** Starting PHASE Do 'simple' lowering
Bumping outgoingArgSpaceSize to 32 for call [000031]
outgoingArgSpaceSize 32 sufficient for call [000009], which needs 32
*************** Finishing PHASE Do 'simple' lowering
*************** In fgDebugCheckBBlist
Trees before Lowering nodeinfo
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target LIR
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i LIR
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i LIR
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall LIR
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall LIR
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target LIR
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd LIR
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i LIR
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i LIR
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall LIR
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd LIR
BB12 [0003] 1 BB11 1 [035..037) (return) i LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
[000165] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000002] ------------ t2 = CNS_INT ref null $VN.Null
/--* t2 ref
N003 ( 5, 4) [000004] DA---------- * STORE_LCL_VAR ref V01 loc0 d:2
[000166] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V00 this u:1 $80
N002 ( 1, 1) [000134] ------------ t134 = CNS_INT long 16 field offset Fseq[_array] $c1
/--* t7 ref
+--* t134 long
N003 ( 2, 2) [000135] -------N---- t135 = * ADD byref $140
/--* t135 byref
N004 ( 4, 4) [000008] ---XG------- t8 = * IND ref <l:$1c4, c:$1c3>
/--* t8 ref
N006 ( 4, 4) [000015] DA-XG------- * STORE_LCL_VAR ref V06 tmp2 d:2
[000167] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000010] !----------- t10 = LCL_VAR ref V00 this u:1 $80
/--* t10 ref
N002 ( 3, 2) [000011] #----O------ t11 = * IND long $1c5
/--* t11 long
N004 ( 3, 3) [000013] DA---O------ * STORE_LCL_VAR long V05 tmp1 d:2
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR long V05 tmp1 u:2 $1c5
N002 ( 1, 1) [000019] ------------ t19 = CNS_INT long 56 $c2
/--* t18 long
+--* t19 long
N003 ( 2, 2) [000020] -------N---- t20 = * ADD long $240
/--* t20 long
N004 ( 4, 4) [000021] #----------- t21 = * IND long $1c6
/--* t21 long
N006 ( 4, 4) [000154] DA---------- * STORE_LCL_VAR long V14 cse0 d:1
N007 ( 1, 1) [000155] ------------ t155 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t155 long
N009 ( 8, 7) [000022] n----------- t22 = * IND long <l:$280, c:$201>
/--* t22 long
N011 ( 8, 7) [000024] DA---------- * STORE_LCL_VAR long V07 tmp3 d:2
N001 ( 1, 1) [000026] ------------ t26 = LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000038] ------------ t38 = CNS_INT long 8 $c3
/--* t26 long
+--* t38 long
N003 ( 2, 2) [000039] -------N---- t39 = * ADD long <l:$242, c:$241>
/--* t39 long
N004 ( 4, 4) [000040] ---X-------- t40 = * IND long <l:$244, c:$243>
N005 ( 1, 1) [000041] ------------ t41 = CNS_INT long 96 $c4
/--* t40 long
+--* t41 long
N006 ( 6, 6) [000042] J--X---N---- t42 = * LE int <l:$2c3, c:$2c2>
/--* t42 int
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
N002 ( 1, 1) [000027] ------------ t27 = CNS_INT long 96 $c4
/--* t25 long
+--* t27 long
N003 ( 2, 2) [000028] -------N---- t28 = * ADD long <l:$246, c:$245>
/--* t28 long
N004 ( 4, 4) [000029] n----------- t29 = * IND long <l:$282, c:$204>
/--* t29 long
N006 ( 8, 7) [000159] DA---------- * STORE_LCL_VAR long V15 cse1 d:1
N007 ( 3, 2) [000160] ------------ t160 = LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
N009 ( 1, 1) [000032] ------------ t32 = CNS_INT long 0 $c0
/--* t160 long
+--* t32 long
N010 ( 13, 11) [000033] J------N---- t33 = * EQ int <l:$2c5, c:$2c4>
/--* t33 int
N011 ( 15, 13) [000116] ------------ * JTRUE void
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
N001 ( 3, 2) [000162] ------------ t162 = LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
/--* t162 long
N003 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR long V08 tmp4 d:4
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR long V05 tmp1 u:2 (last use) $1c5
N004 ( 2, 10) [000030] ------------ t30 = CNS_INT(h) long 0x7ff9f1337fe8 token $181
/--* t17 long arg0 in rcx
+--* t30 long arg1 in rdx
N005 ( 17, 18) [000031] --C-G------- t31 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
/--* t31 long
N007 ( 17, 18) [000120] DA--G------- * STORE_LCL_VAR long V08 tmp4 d:3
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ t151 = PHI_ARG long V08 tmp4 u:3 $247
/--* t152 long
+--* t151 long
N003 ( 0, 0) [000147] ------------ t147 = * PHI long
/--* t147 long
N005 ( 0, 0) [000148] DA---------- * STORE_LCL_VAR long V08 tmp4 d:2
N004 ( 3, 2) [000005] -------N---- t5 = LCL_VAR_ADDR byref V02 loc1
* byref V02._pointer (offs=0x00) -> V12 tmp8
* int V02._length (offs=0x08) -> V13 tmp9
N006 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V08 tmp4 u:2 (last use) $283
N007 ( 1, 1) [000016] ------------ t16 = LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
/--* t5 byref this in rcx
+--* t45 long arg1 in rdx
+--* t16 ref arg2 in r8
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
[000168] ------------ IL_OFFSET void IL offset: 0x15
N001 ( 1, 1) [000047] ------------ t47 = CNS_INT int 0 $40
/--* t47 int
N003 ( 1, 3) [000049] DA---------- * STORE_LCL_VAR int V03 loc2 d:2
------------ BB06 [019..02B), preds={BB11} succs={BB07}
[000169] ------------ IL_OFFSET void IL offset: 0x19
N002 ( 3, 2) [000102] ------------ t102 = LCL_VAR byref (AX) V12 tmp8 $480
N003 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V03 loc2 u:3 $3c0
/--* t94 int
N004 ( 2, 3) [000099] ------------ t99 = * CAST long <- int $24f
N005 ( 1, 1) [000100] ------------ t100 = CNS_INT int 3 $44
/--* t99 long
+--* t100 int
N006 ( 4, 5) [000101] ------------ t101 = * LSH long $250
/--* t102 byref
+--* t101 long
N007 ( 8, 8) [000103] ----G------- t103 = * ADD byref $144
N010 ( 1, 1) [000105] ------------ t105 = CNS_INT int 0 $40
/--* t103 byref
+--* t105 int
N009 ( 11, 10) [000106] -A-XG------- * STORE_BLK struct<8> (init) $1d1
[000170] ------------ IL_OFFSET void IL offset: 0x27
N001 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] ------------ t109 = CNS_INT int 1 $4b
/--* t108 int
+--* t109 int
N003 ( 3, 3) [000110] ------------ t110 = * ADD int $2ce
/--* t110 int
N005 ( 3, 3) [000112] DA---------- * STORE_LCL_VAR int V03 loc2 d:4
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ t149 = PHI_ARG int V03 loc2 u:2 $40
/--* t150 int
+--* t149 int
N003 ( 0, 0) [000144] ------------ t144 = * PHI int
/--* t144 int
N005 ( 0, 0) [000145] DA---------- * STORE_LCL_VAR int V03 loc2 d:3
[000171] ------------ IL_OFFSET void IL offset: 0x2b
N001 ( 1, 1) [000054] !----------- t54 = LCL_VAR ref V00 this u:1 $80
/--* t54 ref
N002 ( 3, 2) [000055] #----O------ t55 = * IND long $1c9
/--* t55 long
N004 ( 3, 3) [000057] DA---O------ * STORE_LCL_VAR long V09 tmp5 d:2
N001 ( 1, 1) [000157] ------------ t157 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t157 long
N002 ( 3, 2) [000063] n----------- t63 = * IND long <l:$284, c:$441>
/--* t63 long
N004 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR long V10 tmp6 d:2
N001 ( 1, 1) [000067] ------------ t67 = LCL_VAR long V10 tmp6 u:2 <l:$284, c:$441>
N002 ( 1, 1) [000079] ------------ t79 = CNS_INT long 8 $c3
/--* t67 long
+--* t79 long
N003 ( 2, 2) [000080] -------N---- t80 = * ADD long <l:$24a, c:$249>
/--* t80 long
N004 ( 4, 4) [000081] ---X-------- t81 = * IND long <l:$24c, c:$24b>
N005 ( 1, 1) [000082] ------------ t82 = CNS_INT long 96 $c4
/--* t81 long
+--* t82 long
N006 ( 6, 6) [000083] J--X---N---- t83 = * LE int <l:$2ca, c:$2c9>
/--* t83 int
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
N001 ( 1, 1) [000066] ------------ t66 = LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
N002 ( 1, 1) [000068] ------------ t68 = CNS_INT long 96 $c4
/--* t66 long
+--* t68 long
N003 ( 2, 2) [000069] -------N---- t69 = * ADD long <l:$24e, c:$24d>
/--* t69 long
N004 ( 4, 4) [000070] n----------- t70 = * IND long <l:$286, c:$444>
N005 ( 1, 1) [000073] ------------ t73 = CNS_INT long 0 $c0
/--* t70 long
+--* t73 long
N006 ( 6, 6) [000074] J------N---- t74 = * EQ int <l:$2cc, c:$2cb>
/--* t74 int
N007 ( 8, 8) [000122] ------------ * JTRUE void
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
N001 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000132] ------------ t132 = LCL_VAR int (AX) V13 tmp9 $3c1
/--* t50 int
+--* t132 int
N003 ( 5, 4) [000089] J---G--N---- t89 = * LT int $2cd
/--* t89 int
N004 ( 7, 6) [000090] ----G------- * JTRUE void
------------ BB12 [035..037) (return), preds={BB11} succs={}
[000172] ------------ IL_OFFSET void IL offset: 0x35
N001 ( 1, 1) [000163] ------------ t163 = CNS_INT ref null $VN.Null
/--* t163 ref
N002 ( 2, 2) [000114] ------------ * RETURN ref $105
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Lowering nodeinfo
lowering store lcl var/field (before):
N001 ( 1, 1) [000002] ------------ t2 = CNS_INT ref null $VN.Null
/--* t2 ref
N003 ( 5, 4) [000004] DA---------- * STORE_LCL_VAR ref V01 loc0 d:2
lowering store lcl var/field (after):
N001 ( 1, 1) [000002] ------------ t2 = CNS_INT ref null $VN.Null
/--* t2 ref
N003 ( 5, 4) [000004] DA---------- * STORE_LCL_VAR ref V01 loc0 d:2
Addressing mode:
Base
N001 ( 1, 1) [000007] ------------ * LCL_VAR ref V00 this u:1 $80
+ 16
Removing unused node:
N002 ( 1, 1) [000134] -c---------- * CNS_INT long 16 field offset Fseq[_array] $c1
New addressing mode node:
N003 ( 2, 2) [000135] ------------ * LEA(b+16) byref
lowering store lcl var/field (before):
N001 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V00 this u:1 $80
/--* t7 ref
N003 ( 2, 2) [000135] -c---------- t135 = * LEA(b+16) byref
/--* t135 byref
N004 ( 4, 4) [000008] ---XG------- t8 = * IND ref <l:$1c4, c:$1c3>
/--* t8 ref
N006 ( 4, 4) [000015] DA-XG------- * STORE_LCL_VAR ref V06 tmp2 d:2
lowering store lcl var/field (after):
N001 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V00 this u:1 $80
/--* t7 ref
N003 ( 2, 2) [000135] -c---------- t135 = * LEA(b+16) byref
/--* t135 byref
N004 ( 4, 4) [000008] ---XG------- t8 = * IND ref <l:$1c4, c:$1c3>
/--* t8 ref
N006 ( 4, 4) [000015] DA-XG------- * STORE_LCL_VAR ref V06 tmp2 d:2
lowering store lcl var/field (before):
N001 ( 1, 1) [000010] !----------- t10 = LCL_VAR ref V00 this u:1 $80
/--* t10 ref
N002 ( 3, 2) [000011] #----O------ t11 = * IND long $1c5
/--* t11 long
N004 ( 3, 3) [000013] DA---O------ * STORE_LCL_VAR long V05 tmp1 d:2
lowering store lcl var/field (after):
N001 ( 1, 1) [000010] !----------- t10 = LCL_VAR ref V00 this u:1 $80
/--* t10 ref
N002 ( 3, 2) [000011] #----O------ t11 = * IND long $1c5
/--* t11 long
N004 ( 3, 3) [000013] DA---O------ * STORE_LCL_VAR long V05 tmp1 d:2
Addressing mode:
Base
N001 ( 1, 1) [000018] ------------ * LCL_VAR long V05 tmp1 u:2 $1c5
+ 56
Removing unused node:
N002 ( 1, 1) [000019] -c---------- * CNS_INT long 56 $c2
New addressing mode node:
N003 ( 2, 2) [000020] ------------ * LEA(b+56) long
lowering store lcl var/field (before):
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR long V05 tmp1 u:2 $1c5
/--* t18 long
N003 ( 2, 2) [000020] -c---------- t20 = * LEA(b+56) long
/--* t20 long
N004 ( 4, 4) [000021] #----------- t21 = * IND long $1c6
/--* t21 long
N006 ( 4, 4) [000154] DA---------- * STORE_LCL_VAR long V14 cse0 d:1
lowering store lcl var/field (after):
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR long V05 tmp1 u:2 $1c5
/--* t18 long
N003 ( 2, 2) [000020] -c---------- t20 = * LEA(b+56) long
/--* t20 long
N004 ( 4, 4) [000021] #----------- t21 = * IND long $1c6
/--* t21 long
N006 ( 4, 4) [000154] DA---------- * STORE_LCL_VAR long V14 cse0 d:1
lowering store lcl var/field (before):
N007 ( 1, 1) [000155] ------------ t155 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t155 long
N009 ( 8, 7) [000022] n----------- t22 = * IND long <l:$280, c:$201>
/--* t22 long
N011 ( 8, 7) [000024] DA---------- * STORE_LCL_VAR long V07 tmp3 d:2
lowering store lcl var/field (after):
N007 ( 1, 1) [000155] ------------ t155 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t155 long
N009 ( 8, 7) [000022] n----------- t22 = * IND long <l:$280, c:$201>
/--* t22 long
N011 ( 8, 7) [000024] DA---------- * STORE_LCL_VAR long V07 tmp3 d:2
Addressing mode:
Base
N001 ( 1, 1) [000026] ------------ * LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
+ 8
Removing unused node:
N002 ( 1, 1) [000038] -c---------- * CNS_INT long 8 $c3
New addressing mode node:
N003 ( 2, 2) [000039] ------------ * LEA(b+8) long
Addressing mode:
Base
N001 ( 1, 1) [000025] ------------ * LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
+ 96
Removing unused node:
N002 ( 1, 1) [000027] -c---------- * CNS_INT long 96 $c4
New addressing mode node:
N003 ( 2, 2) [000028] ------------ * LEA(b+96) long
lowering store lcl var/field (before):
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
/--* t25 long
N003 ( 2, 2) [000028] -c---------- t28 = * LEA(b+96) long
/--* t28 long
N004 ( 4, 4) [000029] n----------- t29 = * IND long <l:$282, c:$204>
/--* t29 long
N006 ( 8, 7) [000159] DA---------- * STORE_LCL_VAR long V15 cse1 d:1
lowering store lcl var/field (after):
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
/--* t25 long
N003 ( 2, 2) [000028] -c---------- t28 = * LEA(b+96) long
/--* t28 long
N004 ( 4, 4) [000029] n----------- t29 = * IND long <l:$282, c:$204>
/--* t29 long
N006 ( 8, 7) [000159] DA---------- * STORE_LCL_VAR long V15 cse1 d:1
lowering store lcl var/field (before):
N001 ( 3, 2) [000162] ------------ t162 = LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
/--* t162 long
N003 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR long V08 tmp4 d:4
lowering store lcl var/field (after):
N001 ( 3, 2) [000162] ------------ t162 = LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
/--* t162 long
N003 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR long V08 tmp4 d:4
lowering call (before):
N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR long V05 tmp1 u:2 (last use) $1c5
N004 ( 2, 10) [000030] ------------ t30 = CNS_INT(h) long 0x7ff9f1337fe8 token $181
/--* t17 long arg0 in rcx
+--* t30 long arg1 in rdx
N005 ( 17, 18) [000031] --C-G------- t31 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000136] ----------L- * ARGPLACE long $1c5
lowering arg : N002 ( 0, 0) [000137] ----------L- * ARGPLACE long $181
late:
======
lowering arg : N003 ( 1, 1) [000017] ------------ * LCL_VAR long V05 tmp1 u:2 (last use) $1c5
new node is : [000173] ------------ * PUTARG_REG long REG rcx
lowering arg : N004 ( 2, 10) [000030] ------------ * CNS_INT(h) long 0x7ff9f1337fe8 token $181
new node is : [000174] ------------ * PUTARG_REG long REG rdx
lowering call (after):
N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR long V05 tmp1 u:2 (last use) $1c5
/--* t17 long
[000173] ------------ t173 = * PUTARG_REG long REG rcx
N004 ( 2, 10) [000030] ------------ t30 = CNS_INT(h) long 0x7ff9f1337fe8 token $181
/--* t30 long
[000174] ------------ t174 = * PUTARG_REG long REG rdx
/--* t173 long arg0 in rcx
+--* t174 long arg1 in rdx
N005 ( 17, 18) [000031] --C-G------- t31 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
lowering store lcl var/field (before):
N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR long V05 tmp1 u:2 (last use) $1c5
/--* t17 long
[000173] ------------ t173 = * PUTARG_REG long REG rcx
N004 ( 2, 10) [000030] ------------ t30 = CNS_INT(h) long 0x7ff9f1337fe8 token $181
/--* t30 long
[000174] ------------ t174 = * PUTARG_REG long REG rdx
/--* t173 long arg0 in rcx
+--* t174 long arg1 in rdx
N005 ( 17, 18) [000031] --C-G------- t31 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
/--* t31 long
N007 ( 17, 18) [000120] DA--G------- * STORE_LCL_VAR long V08 tmp4 d:3
lowering store lcl var/field (after):
N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR long V05 tmp1 u:2 (last use) $1c5
/--* t17 long
[000173] ------------ t173 = * PUTARG_REG long REG rcx
N004 ( 2, 10) [000030] ------------ t30 = CNS_INT(h) long 0x7ff9f1337fe8 token $181
/--* t30 long
[000174] ------------ t174 = * PUTARG_REG long REG rdx
/--* t173 long arg0 in rcx
+--* t174 long arg1 in rdx
N005 ( 17, 18) [000031] --C-G------- t31 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
/--* t31 long
N007 ( 17, 18) [000120] DA--G------- * STORE_LCL_VAR long V08 tmp4 d:3
lowering store lcl var/field (before):
N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ t151 = PHI_ARG long V08 tmp4 u:3 $247
/--* t152 long
+--* t151 long
N003 ( 0, 0) [000147] ------------ t147 = * PHI long
/--* t147 long
N005 ( 0, 0) [000148] DA---------- * STORE_LCL_VAR long V08 tmp4 d:2
lowering store lcl var/field (after):
N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ t151 = PHI_ARG long V08 tmp4 u:3 $247
/--* t152 long
+--* t151 long
N003 ( 0, 0) [000147] ------------ t147 = * PHI long
/--* t147 long
N005 ( 0, 0) [000148] DA---------- * STORE_LCL_VAR long V08 tmp4 d:2
lowering call (before):
N004 ( 3, 2) [000005] -------N---- t5 = LCL_VAR_ADDR byref V02 loc1
* byref V02._pointer (offs=0x00) -> V12 tmp8
* int V02._length (offs=0x08) -> V13 tmp9
N006 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V08 tmp4 u:2 (last use) $283
N007 ( 1, 1) [000016] ------------ t16 = LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
/--* t5 byref this in rcx
+--* t45 long arg1 in rdx
+--* t16 ref arg2 in r8
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
objp:
======
lowering arg : N001 ( 0, 0) [000138] ----------L- * ARGPLACE byref $300
args:
======
lowering arg : N002 ( 0, 0) [000139] ----------L- * ARGPLACE long $301
lowering arg : N003 ( 0, 0) [000140] ----------L- * ARGPLACE ref $283
late:
======
lowering arg : N004 ( 3, 2) [000005] -------N---- * LCL_VAR_ADDR byref V02 loc1
* byref V02._pointer (offs=0x00) -> V12 tmp8
* int V02._length (offs=0x08) -> V13 tmp9
new node is : [000175] ------------ * PUTARG_REG byref REG rcx
lowering arg : N006 ( 1, 1) [000045] ------------ * LCL_VAR long V08 tmp4 u:2 (last use) $283
new node is : [000176] ------------ * PUTARG_REG long REG rdx
lowering arg : N007 ( 1, 1) [000016] ------------ * LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
new node is : [000177] ------------ * PUTARG_REG ref REG r8
lowering call (after):
N004 ( 3, 2) [000005] -------N---- t5 = LCL_VAR_ADDR byref V02 loc1
* byref V02._pointer (offs=0x00) -> V12 tmp8
* int V02._length (offs=0x08) -> V13 tmp9
/--* t5 byref
[000175] ------------ t175 = * PUTARG_REG byref REG rcx
N006 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V08 tmp4 u:2 (last use) $283
/--* t45 long
[000176] ------------ t176 = * PUTARG_REG long REG rdx
N007 ( 1, 1) [000016] ------------ t16 = LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
/--* t16 ref
[000177] ------------ t177 = * PUTARG_REG ref REG r8
/--* t175 byref this in rcx
+--* t176 long arg1 in rdx
+--* t177 ref arg2 in r8
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
lowering store lcl var/field (before):
N001 ( 1, 1) [000047] ------------ t47 = CNS_INT int 0 $40
/--* t47 int
N003 ( 1, 3) [000049] DA---------- * STORE_LCL_VAR int V03 loc2 d:2
lowering store lcl var/field (after):
N001 ( 1, 1) [000047] ------------ t47 = CNS_INT int 0 $40
/--* t47 int
N003 ( 1, 3) [000049] DA---------- * STORE_LCL_VAR int V03 loc2 d:2
Addressing mode:
Base
N002 ( 3, 2) [000102] -c---------- * LCL_VAR byref (AX) V12 tmp8 $480
+ Index * 8 + 0
N004 ( 2, 3) [000099] ------------ * CAST long <- int $24f
Removing unused node:
N006 ( 4, 5) [000101] ------------ * LSH long $250
Removing unused node:
N005 ( 1, 1) [000100] -c---------- * CNS_INT int 3 $44
New addressing mode node:
N007 ( 8, 8) [000103] ------------ * LEA(b+(i*8)+0) byref
lowering store lcl var/field (before):
N001 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] -c---------- t109 = CNS_INT int 1 $4b
/--* t108 int
+--* t109 int
N003 ( 3, 3) [000110] ------------ t110 = * ADD int $2ce
/--* t110 int
N005 ( 3, 3) [000112] DA---------- * STORE_LCL_VAR int V03 loc2 d:4
lowering store lcl var/field (after):
N001 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] -c---------- t109 = CNS_INT int 1 $4b
/--* t108 int
+--* t109 int
N003 ( 3, 3) [000110] ------------ t110 = * ADD int $2ce
/--* t110 int
N005 ( 3, 3) [000112] DA---------- * STORE_LCL_VAR int V03 loc2 d:4
lowering store lcl var/field (before):
N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ t149 = PHI_ARG int V03 loc2 u:2 $40
/--* t150 int
+--* t149 int
N003 ( 0, 0) [000144] ------------ t144 = * PHI int
/--* t144 int
N005 ( 0, 0) [000145] DA---------- * STORE_LCL_VAR int V03 loc2 d:3
lowering store lcl var/field (after):
N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ t149 = PHI_ARG int V03 loc2 u:2 $40
/--* t150 int
+--* t149 int
N003 ( 0, 0) [000144] ------------ t144 = * PHI int
/--* t144 int
N005 ( 0, 0) [000145] DA---------- * STORE_LCL_VAR int V03 loc2 d:3
lowering store lcl var/field (before):
N001 ( 1, 1) [000054] !----------- t54 = LCL_VAR ref V00 this u:1 $80
/--* t54 ref
N002 ( 3, 2) [000055] #----O------ t55 = * IND long $1c9
/--* t55 long
N004 ( 3, 3) [000057] DA---O------ * STORE_LCL_VAR long V09 tmp5 d:2
lowering store lcl var/field (after):
N001 ( 1, 1) [000054] !----------- t54 = LCL_VAR ref V00 this u:1 $80
/--* t54 ref
N002 ( 3, 2) [000055] #----O------ t55 = * IND long $1c9
/--* t55 long
N004 ( 3, 3) [000057] DA---O------ * STORE_LCL_VAR long V09 tmp5 d:2
lowering store lcl var/field (before):
N001 ( 1, 1) [000157] ------------ t157 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t157 long
N002 ( 3, 2) [000063] n----------- t63 = * IND long <l:$284, c:$441>
/--* t63 long
N004 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR long V10 tmp6 d:2
lowering store lcl var/field (after):
N001 ( 1, 1) [000157] ------------ t157 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t157 long
N002 ( 3, 2) [000063] n----------- t63 = * IND long <l:$284, c:$441>
/--* t63 long
N004 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR long V10 tmp6 d:2
Addressing mode:
Base
N001 ( 1, 1) [000067] ------------ * LCL_VAR long V10 tmp6 u:2 <l:$284, c:$441>
+ 8
Removing unused node:
N002 ( 1, 1) [000079] -c---------- * CNS_INT long 8 $c3
New addressing mode node:
N003 ( 2, 2) [000080] ------------ * LEA(b+8) long
Addressing mode:
Base
N001 ( 1, 1) [000066] ------------ * LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
+ 96
Removing unused node:
N002 ( 1, 1) [000068] -c---------- * CNS_INT long 96 $c4
New addressing mode node:
N003 ( 2, 2) [000069] ------------ * LEA(b+96) long
lowering GT_RETURN
N002 ( 2, 2) [000114] ------------ * RETURN ref $105
============Lower has completed modifying nodes.
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target LIR
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i LIR
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i LIR
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall LIR
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall LIR
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target LIR
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd LIR
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i LIR
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i LIR
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall LIR
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd LIR
BB12 [0003] 1 BB11 1 [035..037) (return) i LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
[000165] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000002] ------------ t2 = CNS_INT ref null $VN.Null
/--* t2 ref
N003 ( 5, 4) [000004] DA---------- * STORE_LCL_VAR ref V01 loc0 d:2
[000166] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V00 this u:1 $80
/--* t7 ref
N003 ( 2, 2) [000135] -c---------- t135 = * LEA(b+16) byref
/--* t135 byref
N004 ( 4, 4) [000008] ---XG------- t8 = * IND ref <l:$1c4, c:$1c3>
/--* t8 ref
N006 ( 4, 4) [000015] DA-XG------- * STORE_LCL_VAR ref V06 tmp2 d:2
[000167] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000010] !----------- t10 = LCL_VAR ref V00 this u:1 $80
/--* t10 ref
N002 ( 3, 2) [000011] #----O------ t11 = * IND long $1c5
/--* t11 long
N004 ( 3, 3) [000013] DA---O------ * STORE_LCL_VAR long V05 tmp1 d:2
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR long V05 tmp1 u:2 $1c5
/--* t18 long
N003 ( 2, 2) [000020] -c---------- t20 = * LEA(b+56) long
/--* t20 long
N004 ( 4, 4) [000021] #----------- t21 = * IND long $1c6
/--* t21 long
N006 ( 4, 4) [000154] DA---------- * STORE_LCL_VAR long V14 cse0 d:1
N007 ( 1, 1) [000155] ------------ t155 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t155 long
N009 ( 8, 7) [000022] n----------- t22 = * IND long <l:$280, c:$201>
/--* t22 long
N011 ( 8, 7) [000024] DA---------- * STORE_LCL_VAR long V07 tmp3 d:2
N001 ( 1, 1) [000026] ------------ t26 = LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
/--* t26 long
N003 ( 2, 2) [000039] -c---------- t39 = * LEA(b+8) long
/--* t39 long
N004 ( 4, 4) [000040] -c-X-------- t40 = * IND long <l:$244, c:$243>
N005 ( 1, 1) [000041] -c---------- t41 = CNS_INT long 96 $c4
/--* t40 long
+--* t41 long
N006 ( 6, 6) [000042] J--X---N---- * LE void <l:$2c3, c:$2c2>
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
/--* t25 long
N003 ( 2, 2) [000028] -c---------- t28 = * LEA(b+96) long
/--* t28 long
N004 ( 4, 4) [000029] n----------- t29 = * IND long <l:$282, c:$204>
/--* t29 long
N006 ( 8, 7) [000159] DA---------- * STORE_LCL_VAR long V15 cse1 d:1
N007 ( 3, 2) [000160] ------------ t160 = LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
N009 ( 1, 1) [000032] -c---------- t32 = CNS_INT long 0 $c0
/--* t160 long
+--* t32 long
N010 ( 13, 11) [000033] J------N---- * EQ void <l:$2c5, c:$2c4>
N011 ( 15, 13) [000116] ------------ * JTRUE void
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
N001 ( 3, 2) [000162] ------------ t162 = LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
/--* t162 long
N003 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR long V08 tmp4 d:4
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR long V05 tmp1 u:2 (last use) $1c5
/--* t17 long
[000173] ------------ t173 = * PUTARG_REG long REG rcx
N004 ( 2, 10) [000030] ------------ t30 = CNS_INT(h) long 0x7ff9f1337fe8 token $181
/--* t30 long
[000174] ------------ t174 = * PUTARG_REG long REG rdx
/--* t173 long arg0 in rcx
+--* t174 long arg1 in rdx
N005 ( 17, 18) [000031] --C-G------- t31 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
/--* t31 long
N007 ( 17, 18) [000120] DA--G------- * STORE_LCL_VAR long V08 tmp4 d:3
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ t151 = PHI_ARG long V08 tmp4 u:3 $247
/--* t152 long
+--* t151 long
N003 ( 0, 0) [000147] ------------ t147 = * PHI long
/--* t147 long
N005 ( 0, 0) [000148] DA---------- * STORE_LCL_VAR long V08 tmp4 d:2
N004 ( 3, 2) [000005] -------N---- t5 = LCL_VAR_ADDR byref V02 loc1
* byref V02._pointer (offs=0x00) -> V12 tmp8
* int V02._length (offs=0x08) -> V13 tmp9
/--* t5 byref
[000175] ------------ t175 = * PUTARG_REG byref REG rcx
N006 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V08 tmp4 u:2 (last use) $283
/--* t45 long
[000176] ------------ t176 = * PUTARG_REG long REG rdx
N007 ( 1, 1) [000016] ------------ t16 = LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
/--* t16 ref
[000177] ------------ t177 = * PUTARG_REG ref REG r8
/--* t175 byref this in rcx
+--* t176 long arg1 in rdx
+--* t177 ref arg2 in r8
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
[000168] ------------ IL_OFFSET void IL offset: 0x15
N001 ( 1, 1) [000047] ------------ t47 = CNS_INT int 0 $40
/--* t47 int
N003 ( 1, 3) [000049] DA---------- * STORE_LCL_VAR int V03 loc2 d:2
------------ BB06 [019..02B), preds={BB11} succs={BB07}
[000169] ------------ IL_OFFSET void IL offset: 0x19
N002 ( 3, 2) [000102] ------------ t102 = LCL_VAR byref (AX) V12 tmp8 $480
N003 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V03 loc2 u:3 $3c0
/--* t94 int
N004 ( 2, 3) [000099] ------------ t99 = * CAST long <- int $24f
/--* t102 byref
+--* t99 long
N007 ( 8, 8) [000103] -c---------- t103 = * LEA(b+(i*8)+0) byref
N010 ( 1, 1) [000105] ------------ t105 = CNS_INT int 0 $40
/--* t103 byref
+--* t105 int
N009 ( 11, 10) [000106] -A-XG------- * STORE_BLK struct<8> (init) (Unroll) $1d1
[000170] ------------ IL_OFFSET void IL offset: 0x27
N001 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] -c---------- t109 = CNS_INT int 1 $4b
/--* t108 int
+--* t109 int
N003 ( 3, 3) [000110] ------------ t110 = * ADD int $2ce
/--* t110 int
N005 ( 3, 3) [000112] DA---------- * STORE_LCL_VAR int V03 loc2 d:4
------------ BB07 [02B..???) -> BB10 (cond), preds={BB05,BB06} succs={BB08,BB10}
N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ t149 = PHI_ARG int V03 loc2 u:2 $40
/--* t150 int
+--* t149 int
N003 ( 0, 0) [000144] ------------ t144 = * PHI int
/--* t144 int
N005 ( 0, 0) [000145] DA---------- * STORE_LCL_VAR int V03 loc2 d:3
[000171] ------------ IL_OFFSET void IL offset: 0x2b
N001 ( 1, 1) [000054] !----------- t54 = LCL_VAR ref V00 this u:1 $80
/--* t54 ref
N002 ( 3, 2) [000055] #----O------ t55 = * IND long $1c9
/--* t55 long
N004 ( 3, 3) [000057] DA---O------ * STORE_LCL_VAR long V09 tmp5 d:2
N001 ( 1, 1) [000157] ------------ t157 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t157 long
N002 ( 3, 2) [000063] n----------- t63 = * IND long <l:$284, c:$441>
/--* t63 long
N004 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR long V10 tmp6 d:2
N001 ( 1, 1) [000067] ------------ t67 = LCL_VAR long V10 tmp6 u:2 <l:$284, c:$441>
/--* t67 long
N003 ( 2, 2) [000080] -c---------- t80 = * LEA(b+8) long
/--* t80 long
N004 ( 4, 4) [000081] -c-X-------- t81 = * IND long <l:$24c, c:$24b>
N005 ( 1, 1) [000082] -c---------- t82 = CNS_INT long 96 $c4
/--* t81 long
+--* t82 long
N006 ( 6, 6) [000083] J--X---N---- * LE void <l:$2ca, c:$2c9>
N007 ( 8, 8) [000121] ---X-------- * JTRUE void
------------ BB08 [???..???) -> BB10 (cond), preds={BB07} succs={BB09,BB10}
N001 ( 1, 1) [000066] ------------ t66 = LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
/--* t66 long
N003 ( 2, 2) [000069] -c---------- t69 = * LEA(b+96) long
/--* t69 long
N004 ( 4, 4) [000070] nc---------- t70 = * IND long <l:$286, c:$444>
N005 ( 1, 1) [000073] -c---------- t73 = CNS_INT long 0 $c0
/--* t70 long
+--* t73 long
N006 ( 6, 6) [000074] J------N---- * EQ void <l:$2cc, c:$2cb>
N007 ( 8, 8) [000122] ------------ * JTRUE void
------------ BB09 [???..???) -> BB11 (always), preds={BB08} succs={BB11}
------------ BB10 [???..???), preds={BB07,BB08} succs={BB11}
------------ BB11 [???..035) -> BB06 (cond), preds={BB09,BB10} succs={BB12,BB06}
N001 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000132] -c---------- t132 = LCL_VAR int (AX) V13 tmp9 $3c1
/--* t50 int
+--* t132 int
N003 ( 5, 4) [000089] J---G--N---- * LT void $2cd
N004 ( 7, 6) [000090] ----G------- * JTRUE void
------------ BB12 [035..037) (return), preds={BB11} succs={}
[000172] ------------ IL_OFFSET void IL offset: 0x35
N001 ( 1, 1) [000163] ------------ t163 = CNS_INT ref null $VN.Null
/--* t163 ref
N002 ( 2, 2) [000114] ------------ * RETURN ref $105
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V01: refCnt = 1, refCntWtd = 1
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V06: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V05: refCnt = 1, refCntWtd = 2
New refCnts for V05: refCnt = 2, refCntWtd = 4
New refCnts for V14: refCnt = 1, refCntWtd = 1
New refCnts for V14: refCnt = 2, refCntWtd = 2
New refCnts for V07: refCnt = 1, refCntWtd = 2
New refCnts for V07: refCnt = 2, refCntWtd = 4
New refCnts for V07: refCnt = 3, refCntWtd = 4.80
New refCnts for V15: refCnt = 1, refCntWtd = 0.40
New refCnts for V15: refCnt = 2, refCntWtd = 0.80
New refCnts for V15: refCnt = 3, refCntWtd = 1.20
New refCnts for V08: refCnt = 1, refCntWtd = 0.80
New refCnts for V05: refCnt = 3, refCntWtd = 4.20
New refCnts for V08: refCnt = 2, refCntWtd = 1
New refCnts for V12: refCnt = 1, refCntWtd = 1
New refCnts for V13: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V08: refCnt = 3, refCntWtd = 3
New refCnts for V06: refCnt = 2, refCntWtd = 4
New refCnts for V03: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 2, refCntWtd = 3
New refCnts for V12: refCnt = 2, refCntWtd = 3
New refCnts for V03: refCnt = 2, refCntWtd = 3
New refCnts for V03: refCnt = 3, refCntWtd = 5
New refCnts for V03: refCnt = 4, refCntWtd = 7
New refCnts for V00: refCnt = 3, refCntWtd = 10
New refCnts for V09: refCnt = 1, refCntWtd = 16
New refCnts for V14: refCnt = 3, refCntWtd = 10
New refCnts for V10: refCnt = 1, refCntWtd = 16
New refCnts for V10: refCnt = 2, refCntWtd = 32
New refCnts for V10: refCnt = 3, refCntWtd = 35.20
New refCnts for V03: refCnt = 5, refCntWtd = 15
New refCnts for V02: refCnt = 3, refCntWtd = 11
New refCnts for V13: refCnt = 2, refCntWtd = 9
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 4, refCntWtd = 11
New refCnts for V00: refCnt = 5, refCntWtd = 12
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 ref ld-addr-op class-hnd
; V02 loc1 struct <System.Span`1[__Canon], 16> do-not-enreg[XS] addr-exposed ld-addr-op
; V03 loc2 int
; V04 OutArgs lclBlk <32> "OutgoingArgSpace"
; V05 tmp1 long "impRuntimeLookup slot"
; V06 tmp2 ref class-hnd "impAppendStmt"
; V07 tmp3 long "impRuntimeLookup indirectOffset"
; V08 tmp4 long "spilling Runtime Lookup tree"
; V09 tmp5 long "impRuntimeLookup slot"
; V10 tmp6 long "impRuntimeLookup indirectOffset"
; V11 tmp7 long "spilling Runtime Lookup tree"
; V12 tmp8 byref do-not-enreg[X] addr-exposed V02._pointer(offs=0x00) P-DEP "field V02._pointer (fldOffset=0x0)"
; V13 tmp9 int do-not-enreg[X] addr-exposed V02._length(offs=0x08) P-DEP "field V02._length (fldOffset=0x8)"
; V14 cse0 long "CSE - aggressive"
; V15 cse1 long "CSE - conservative"
In fgLocalVarLivenessInit
Tracked variable (11 out of 16) table:
V10 tmp6 [ long]: refCnt = 3, refCntWtd = 35.20
V09 tmp5 [ long]: refCnt = 1, refCntWtd = 16
V03 loc2 [ int]: refCnt = 5, refCntWtd = 15
V00 this [ ref]: refCnt = 5, refCntWtd = 12
V14 cse0 [ long]: refCnt = 3, refCntWtd = 10
V07 tmp3 [ long]: refCnt = 3, refCntWtd = 4.80
V05 tmp1 [ long]: refCnt = 3, refCntWtd = 4.20
V06 tmp2 [ ref]: refCnt = 2, refCntWtd = 4
V08 tmp4 [ long]: refCnt = 3, refCntWtd = 3
V15 cse1 [ long]: refCnt = 3, refCntWtd = 1.20
V01 loc0 [ ref]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 } + ByrefExposed + GcHeap
DEF(5)={ V14 V07 V05 V06 V01}
BB02 USE(1)={V07 } + ByrefExposed + GcHeap
DEF(1)={ V15}
BB03 USE(1)={ V15}
DEF(1)={V08 }
BB04 USE(1)={V05 }
DEF(1)={ V08}
BB05 USE(2)={ V06 V08} + ByrefExposed + GcHeap
DEF(1)={V03 } + ByrefExposed* + GcHeap*
BB06 USE(1)={V03} + ByrefExposed
DEF(1)={V03} + ByrefExposed + GcHeap
BB07 USE(2)={ V00 V14} + ByrefExposed + GcHeap
DEF(2)={V10 V09 }
BB08 USE(1)={V10} + ByrefExposed + GcHeap
DEF(0)={ }
BB09 USE(0)={}
DEF(0)={}
BB10 USE(0)={}
DEF(0)={}
BB11 USE(1)={V03} + ByrefExposed
DEF(0)={ }
BB12 USE(0)={}
DEF(0)={}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
Reporting this as generic context: referenced
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00 } + ByrefExposed + GcHeap
OUT(5)={V00 V14 V07 V05 V06} + ByrefExposed + GcHeap
BB02 IN (5)={V00 V14 V07 V05 V06 } + ByrefExposed + GcHeap
OUT(5)={V00 V14 V05 V06 V15} + ByrefExposed + GcHeap
BB03 IN (4)={V00 V14 V06 V15} + ByrefExposed + GcHeap
OUT(4)={V00 V14 V06 V08 } + ByrefExposed + GcHeap
BB04 IN (4)={V00 V14 V05 V06 } + ByrefExposed + GcHeap
OUT(4)={V00 V14 V06 V08} + ByrefExposed + GcHeap
BB05 IN (4)={ V00 V14 V06 V08} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14 } + ByrefExposed + GcHeap
BB06 IN (3)={V03 V00 V14} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14} + ByrefExposed + GcHeap
BB07 IN (3)={ V03 V00 V14} + ByrefExposed + GcHeap
OUT(4)={V10 V03 V00 V14} + ByrefExposed + GcHeap
BB08 IN (4)={V10 V03 V00 V14} + ByrefExposed + GcHeap
OUT(3)={ V03 V00 V14} + ByrefExposed + GcHeap
BB09 IN (3)={V03 V00 V14} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14} + ByrefExposed + GcHeap
BB10 IN (3)={V03 V00 V14} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14} + ByrefExposed + GcHeap
BB11 IN (3)={V03 V00 V14} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14} + ByrefExposed + GcHeap
BB12 IN (1)={V00}
OUT(1)={V00}
Removing dead store:
N003 ( 5, 4) [000004] DA---------- * STORE_LCL_VAR ref V01 loc0 d:2 (last use)
Removing dead node:
N001 ( 1, 1) [000002] ------------ * CNS_INT ref null $VN.Null
Removing dead store:
N004 ( 3, 3) [000057] DA---O------ * STORE_LCL_VAR long V09 tmp5 d:2 (last use)
Removing dead node:
N002 ( 3, 2) [000055] #----O------ * IND long $1c9
Removing dead LclVar use:
N001 ( 1, 1) [000054] !----------- * LCL_VAR ref V00 this u:1 $80
*************** In fgUpdateFlowGraph()
Before updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target LIR
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i LIR
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i LIR
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall LIR
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall LIR
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target LIR
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd LIR
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB10 ( cond ) i LIR
BB09 [0012] 1 BB08 1.60 0 [???..???)-> BB11 (always) i LIR
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall LIR
BB11 [0009] 2 BB09,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd LIR
BB12 [0003] 1 BB11 1 [035..037) (return) i LIR
-----------------------------------------------------------------------------------------------------------------------------------------
Reversing a conditional jump around an unconditional jump (BB08 -> BB10 -> BB11)
After reversing the jump:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target LIR
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i LIR
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i LIR
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall LIR
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall LIR
BB06 [0001] 1 BB11 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target LIR
BB07 [0002] 2 BB05,BB06 8 0 [02B..???)-> BB10 ( cond ) i label target bwd LIR
BB08 [0011] 1 BB07 1.60 0 [???..???)-> BB11 ( cond ) i LIR
BB10 [0013] 2 BB07,BB08 0.40 0 [???..???) i label target hascall LIR
BB11 [0009] 2 BB08,BB10 8 0 [???..035)-> BB06 ( cond ) i label target bwd LIR
BB12 [0003] 1 BB11 1 [035..037) (return) i LIR
-----------------------------------------------------------------------------------------------------------------------------------------
Compacting blocks BB10 and BB11:
Second block has multiple incoming edges
*************** In fgDebugCheckBBlist
Removing conditional jump to next block (BB08 -> BB10)
Compacting blocks BB08 and BB10:
Second block has multiple incoming edges
*************** In fgDebugCheckBBlist
Removing conditional jump to next block (BB07 -> BB08)
After updating the flow graph:
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target LIR
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i LIR
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i LIR
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall LIR
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall LIR
BB06 [0001] 1 BB08 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target LIR
BB07 [0002] 2 BB05,BB06 8 0 [02B..???) i label target bwd LIR
BB08 [0011] 1 BB07 8 0 [???..035)-> BB06 ( cond ) i target bwd LIR
BB12 [0003] 1 BB08 1 [035..037) (return) i LIR
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
had to run another liveness pass:
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 this ref this class-hnd
; V01 loc0 ref ld-addr-op class-hnd
; V02 loc1 struct <System.Span`1[__Canon], 16> do-not-enreg[XS] addr-exposed ld-addr-op
; V03 loc2 int
; V04 OutArgs lclBlk <32> "OutgoingArgSpace"
; V05 tmp1 long "impRuntimeLookup slot"
; V06 tmp2 ref class-hnd "impAppendStmt"
; V07 tmp3 long "impRuntimeLookup indirectOffset"
; V08 tmp4 long "spilling Runtime Lookup tree"
; V09 tmp5 long "impRuntimeLookup slot"
; V10 tmp6 long "impRuntimeLookup indirectOffset"
; V11 tmp7 long "spilling Runtime Lookup tree"
; V12 tmp8 byref do-not-enreg[X] addr-exposed V02._pointer(offs=0x00) P-DEP "field V02._pointer (fldOffset=0x0)"
; V13 tmp9 int do-not-enreg[X] addr-exposed V02._length(offs=0x08) P-DEP "field V02._length (fldOffset=0x8)"
; V14 cse0 long "CSE - aggressive"
; V15 cse1 long "CSE - conservative"
In fgLocalVarLivenessInit
Tracked variable (11 out of 16) table:
V10 tmp6 [ long]: refCnt = 3, refCntWtd = 35.20
V09 tmp5 [ long]: refCnt = 1, refCntWtd = 16
V03 loc2 [ int]: refCnt = 5, refCntWtd = 15
V00 this [ ref]: refCnt = 5, refCntWtd = 12
V14 cse0 [ long]: refCnt = 3, refCntWtd = 10
V07 tmp3 [ long]: refCnt = 3, refCntWtd = 4.80
V05 tmp1 [ long]: refCnt = 3, refCntWtd = 4.20
V06 tmp2 [ ref]: refCnt = 2, refCntWtd = 4
V08 tmp4 [ long]: refCnt = 3, refCntWtd = 3
V15 cse1 [ long]: refCnt = 3, refCntWtd = 1.20
V01 loc0 [ ref]: refCnt = 1, refCntWtd = 1
*************** In fgPerBlockLocalVarLiveness()
BB01 USE(1)={V00 } + ByrefExposed + GcHeap
DEF(4)={ V14 V07 V05 V06}
BB02 USE(1)={V07 } + ByrefExposed + GcHeap
DEF(1)={ V15}
BB03 USE(1)={ V15}
DEF(1)={V08 }
BB04 USE(1)={V05 }
DEF(1)={ V08}
BB05 USE(2)={ V06 V08} + ByrefExposed + GcHeap
DEF(1)={V03 } + ByrefExposed* + GcHeap*
BB06 USE(1)={V03} + ByrefExposed
DEF(1)={V03} + ByrefExposed + GcHeap
BB07 USE(1)={ V14} + ByrefExposed + GcHeap
DEF(1)={V10 }
BB08 USE(1)={V03} + ByrefExposed
DEF(0)={ }
BB12 USE(0)={}
DEF(0)={}
** Memory liveness computed, GcHeap states and ByrefExposed states match
*************** In fgInterBlockLocalVarLiveness()
Reporting this as generic context: referenced
BB liveness after fgLiveVarAnalysis():
BB01 IN (1)={V00 } + ByrefExposed + GcHeap
OUT(5)={V00 V14 V07 V05 V06} + ByrefExposed + GcHeap
BB02 IN (5)={V00 V14 V07 V05 V06 } + ByrefExposed + GcHeap
OUT(5)={V00 V14 V05 V06 V15} + ByrefExposed + GcHeap
BB03 IN (4)={V00 V14 V06 V15} + ByrefExposed + GcHeap
OUT(4)={V00 V14 V06 V08 } + ByrefExposed + GcHeap
BB04 IN (4)={V00 V14 V05 V06 } + ByrefExposed + GcHeap
OUT(4)={V00 V14 V06 V08} + ByrefExposed + GcHeap
BB05 IN (4)={ V00 V14 V06 V08} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14 } + ByrefExposed + GcHeap
BB06 IN (3)={V03 V00 V14} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14} + ByrefExposed + GcHeap
BB07 IN (3)={V03 V00 V14} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14} + ByrefExposed + GcHeap
BB08 IN (3)={V03 V00 V14} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14} + ByrefExposed + GcHeap
BB12 IN (1)={V00}
OUT(1)={V00}
Removing dead node:
N006 ( 6, 6) [000083] J--X---N---- * LE void <l:$2ca, c:$2c9>
Removing dead node:
N005 ( 1, 1) [000082] ------------ * CNS_INT long 96 $c4
*** lvaComputeRefCounts ***
*** lvaComputeRefCounts -- explicit counts ***
New refCnts for V00: refCnt = 1, refCntWtd = 1
New refCnts for V06: refCnt = 1, refCntWtd = 2
New refCnts for V00: refCnt = 2, refCntWtd = 2
New refCnts for V05: refCnt = 1, refCntWtd = 2
New refCnts for V05: refCnt = 2, refCntWtd = 4
New refCnts for V14: refCnt = 1, refCntWtd = 1
New refCnts for V14: refCnt = 2, refCntWtd = 2
New refCnts for V07: refCnt = 1, refCntWtd = 2
New refCnts for V07: refCnt = 2, refCntWtd = 4
New refCnts for V07: refCnt = 3, refCntWtd = 4.80
New refCnts for V15: refCnt = 1, refCntWtd = 0.40
New refCnts for V15: refCnt = 2, refCntWtd = 0.80
New refCnts for V15: refCnt = 3, refCntWtd = 1.20
New refCnts for V08: refCnt = 1, refCntWtd = 0.80
New refCnts for V05: refCnt = 3, refCntWtd = 4.20
New refCnts for V08: refCnt = 2, refCntWtd = 1
New refCnts for V12: refCnt = 1, refCntWtd = 1
New refCnts for V13: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 1, refCntWtd = 1
New refCnts for V08: refCnt = 3, refCntWtd = 3
New refCnts for V06: refCnt = 2, refCntWtd = 4
New refCnts for V03: refCnt = 1, refCntWtd = 1
New refCnts for V02: refCnt = 2, refCntWtd = 3
New refCnts for V12: refCnt = 2, refCntWtd = 3
New refCnts for V03: refCnt = 2, refCntWtd = 3
New refCnts for V03: refCnt = 3, refCntWtd = 5
New refCnts for V03: refCnt = 4, refCntWtd = 7
New refCnts for V14: refCnt = 3, refCntWtd = 10
New refCnts for V10: refCnt = 1, refCntWtd = 16
New refCnts for V10: refCnt = 2, refCntWtd = 32
New refCnts for V03: refCnt = 5, refCntWtd = 15
New refCnts for V02: refCnt = 3, refCntWtd = 11
New refCnts for V13: refCnt = 2, refCntWtd = 9
*** lvaComputeRefCounts -- implicit counts ***
New refCnts for V00: refCnt = 3, refCntWtd = 3
New refCnts for V00: refCnt = 4, refCntWtd = 4
*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target LIR
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i LIR
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i LIR
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall LIR
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall LIR
BB06 [0001] 1 BB08 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target LIR
BB07 [0002] 2 BB05,BB06 8 0 [02B..???) i label target bwd LIR
BB08 [0011] 1 BB07 8 0 [???..035)-> BB06 ( cond ) i target bwd LIR
BB12 [0003] 1 BB08 1 [035..037) (return) i LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
[000165] ------------ IL_OFFSET void IL offset: 0x0
[000166] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V00 this u:1 $80
/--* t7 ref
N003 ( 2, 2) [000135] -c---------- t135 = * LEA(b+16) byref
/--* t135 byref
N004 ( 4, 4) [000008] ---XG------- t8 = * IND ref <l:$1c4, c:$1c3>
/--* t8 ref
N006 ( 4, 4) [000015] DA-XG------- * STORE_LCL_VAR ref V06 tmp2 d:2
[000167] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000010] !----------- t10 = LCL_VAR ref V00 this u:1 $80
/--* t10 ref
N002 ( 3, 2) [000011] #----O------ t11 = * IND long $1c5
/--* t11 long
N004 ( 3, 3) [000013] DA---O------ * STORE_LCL_VAR long V05 tmp1 d:2
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR long V05 tmp1 u:2 $1c5
/--* t18 long
N003 ( 2, 2) [000020] -c---------- t20 = * LEA(b+56) long
/--* t20 long
N004 ( 4, 4) [000021] #----------- t21 = * IND long $1c6
/--* t21 long
N006 ( 4, 4) [000154] DA---------- * STORE_LCL_VAR long V14 cse0 d:1
N007 ( 1, 1) [000155] ------------ t155 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t155 long
N009 ( 8, 7) [000022] n----------- t22 = * IND long <l:$280, c:$201>
/--* t22 long
N011 ( 8, 7) [000024] DA---------- * STORE_LCL_VAR long V07 tmp3 d:2
N001 ( 1, 1) [000026] ------------ t26 = LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
/--* t26 long
N003 ( 2, 2) [000039] -c---------- t39 = * LEA(b+8) long
/--* t39 long
N004 ( 4, 4) [000040] -c-X-------- t40 = * IND long <l:$244, c:$243>
N005 ( 1, 1) [000041] -c---------- t41 = CNS_INT long 96 $c4
/--* t40 long
+--* t41 long
N006 ( 6, 6) [000042] J--X---N---- * LE void <l:$2c3, c:$2c2>
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V07 tmp3 u:2 (last use) <l:$280, c:$201>
/--* t25 long
N003 ( 2, 2) [000028] -c---------- t28 = * LEA(b+96) long
/--* t28 long
N004 ( 4, 4) [000029] n----------- t29 = * IND long <l:$282, c:$204>
/--* t29 long
N006 ( 8, 7) [000159] DA---------- * STORE_LCL_VAR long V15 cse1 d:1
N007 ( 3, 2) [000160] ------------ t160 = LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
N009 ( 1, 1) [000032] -c---------- t32 = CNS_INT long 0 $c0
/--* t160 long
+--* t32 long
N010 ( 13, 11) [000033] J------N---- * EQ void <l:$2c5, c:$2c4>
N011 ( 15, 13) [000116] ------------ * JTRUE void
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
N001 ( 3, 2) [000162] ------------ t162 = LCL_VAR long V15 cse1 u:1 (last use) <l:$282, c:$204>
/--* t162 long
N003 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR long V08 tmp4 d:4
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR long V05 tmp1 u:2 (last use) $1c5
/--* t17 long
[000173] ------------ t173 = * PUTARG_REG long REG rcx
N004 ( 2, 10) [000030] ------------ t30 = CNS_INT(h) long 0x7ff9f1337fe8 token $181
/--* t30 long
[000174] ------------ t174 = * PUTARG_REG long REG rdx
/--* t173 long arg0 in rcx
+--* t174 long arg1 in rdx
N005 ( 17, 18) [000031] --C-G------- t31 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
/--* t31 long
N007 ( 17, 18) [000120] DA--G------- * STORE_LCL_VAR long V08 tmp4 d:3
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ t151 = PHI_ARG long V08 tmp4 u:3 $247
/--* t152 long
+--* t151 long
N003 ( 0, 0) [000147] ------------ t147 = * PHI long
/--* t147 long
N005 ( 0, 0) [000148] DA---------- * STORE_LCL_VAR long V08 tmp4 d:2
N004 ( 3, 2) [000005] -------N---- t5 = LCL_VAR_ADDR byref V02 loc1
* byref V02._pointer (offs=0x00) -> V12 tmp8
* int V02._length (offs=0x08) -> V13 tmp9
/--* t5 byref
[000175] ------------ t175 = * PUTARG_REG byref REG rcx
N006 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V08 tmp4 u:2 (last use) $283
/--* t45 long
[000176] ------------ t176 = * PUTARG_REG long REG rdx
N007 ( 1, 1) [000016] ------------ t16 = LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
/--* t16 ref
[000177] ------------ t177 = * PUTARG_REG ref REG r8
/--* t175 byref this in rcx
+--* t176 long arg1 in rdx
+--* t177 ref arg2 in r8
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
[000168] ------------ IL_OFFSET void IL offset: 0x15
N001 ( 1, 1) [000047] ------------ t47 = CNS_INT int 0 $40
/--* t47 int
N003 ( 1, 3) [000049] DA---------- * STORE_LCL_VAR int V03 loc2 d:2
------------ BB06 [019..02B), preds={BB08} succs={BB07}
[000169] ------------ IL_OFFSET void IL offset: 0x19
N002 ( 3, 2) [000102] ------------ t102 = LCL_VAR byref (AX) V12 tmp8 $480
N003 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V03 loc2 u:3 $3c0
/--* t94 int
N004 ( 2, 3) [000099] ------------ t99 = * CAST long <- int $24f
/--* t102 byref
+--* t99 long
N007 ( 8, 8) [000103] -c---------- t103 = * LEA(b+(i*8)+0) byref
N010 ( 1, 1) [000105] ------------ t105 = CNS_INT int 0 $40
/--* t103 byref
+--* t105 int
N009 ( 11, 10) [000106] -A-XG------- * STORE_BLK struct<8> (init) (Unroll) $1d1
[000170] ------------ IL_OFFSET void IL offset: 0x27
N001 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] -c---------- t109 = CNS_INT int 1 $4b
/--* t108 int
+--* t109 int
N003 ( 3, 3) [000110] ------------ t110 = * ADD int $2ce
/--* t110 int
N005 ( 3, 3) [000112] DA---------- * STORE_LCL_VAR int V03 loc2 d:4
------------ BB07 [02B..???), preds={BB05,BB06} succs={BB08}
N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ t149 = PHI_ARG int V03 loc2 u:2 $40
/--* t150 int
+--* t149 int
N003 ( 0, 0) [000144] ------------ t144 = * PHI int
/--* t144 int
N005 ( 0, 0) [000145] DA---------- * STORE_LCL_VAR int V03 loc2 d:3
[000171] ------------ IL_OFFSET void IL offset: 0x2b
N001 ( 1, 1) [000157] ------------ t157 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t157 long
N002 ( 3, 2) [000063] n----------- t63 = * IND long <l:$284, c:$441>
/--* t63 long
N004 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR long V10 tmp6 d:2
N001 ( 1, 1) [000067] ------------ t67 = LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
/--* t67 long
N003 ( 2, 2) [000080] -c---------- t80 = * LEA(b+8) long
/--* t80 long
N004 ( 4, 4) [000081] ---X-------- t81 = * IND long <l:$24c, c:$24b>
------------ BB08 [???..035) -> BB06 (cond), preds={BB07} succs={BB12,BB06}
N001 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000132] -c---------- t132 = LCL_VAR int (AX) V13 tmp9 $3c1
/--* t50 int
+--* t132 int
N003 ( 5, 4) [000089] J---G--N---- * LT void $2cd
N004 ( 7, 6) [000090] ----G------- * JTRUE void
------------ BB12 [035..037) (return), preds={BB08} succs={}
[000172] ------------ IL_OFFSET void IL offset: 0x35
N001 ( 1, 1) [000163] ------------ t163 = CNS_INT ref null $VN.Null
/--* t163 ref
N002 ( 2, 2) [000114] ------------ * RETURN ref $105
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Trees before Calculate stack level slots
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target LIR
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i LIR
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i LIR
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall LIR
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall LIR
BB06 [0001] 1 BB08 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target LIR
BB07 [0002] 2 BB05,BB06 8 0 [02B..???) i label target bwd LIR
BB08 [0011] 1 BB07 8 0 [???..035)-> BB06 ( cond ) i target bwd LIR
BB12 [0003] 1 BB08 1 [035..037) (return) i LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
[000165] ------------ IL_OFFSET void IL offset: 0x0
[000166] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V00 this u:1 $80
/--* t7 ref
N003 ( 2, 2) [000135] -c---------- t135 = * LEA(b+16) byref
/--* t135 byref
N004 ( 4, 4) [000008] ---XG------- t8 = * IND ref <l:$1c4, c:$1c3>
/--* t8 ref
N006 ( 4, 4) [000015] DA-XG------- * STORE_LCL_VAR ref V06 tmp2 d:2
[000167] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000010] !----------- t10 = LCL_VAR ref V00 this u:1 $80
/--* t10 ref
N002 ( 3, 2) [000011] #----O------ t11 = * IND long $1c5
/--* t11 long
N004 ( 3, 3) [000013] DA---O------ * STORE_LCL_VAR long V05 tmp1 d:2
N001 ( 1, 1) [000018] ------------ t18 = LCL_VAR long V05 tmp1 u:2 $1c5
/--* t18 long
N003 ( 2, 2) [000020] -c---------- t20 = * LEA(b+56) long
/--* t20 long
N004 ( 4, 4) [000021] #----------- t21 = * IND long $1c6
/--* t21 long
N006 ( 4, 4) [000154] DA---------- * STORE_LCL_VAR long V14 cse0 d:1
N007 ( 1, 1) [000155] ------------ t155 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t155 long
N009 ( 8, 7) [000022] n----------- t22 = * IND long <l:$280, c:$201>
/--* t22 long
N011 ( 8, 7) [000024] DA---------- * STORE_LCL_VAR long V07 tmp3 d:2
N001 ( 1, 1) [000026] ------------ t26 = LCL_VAR long V07 tmp3 u:2 <l:$280, c:$201>
/--* t26 long
N003 ( 2, 2) [000039] -c---------- t39 = * LEA(b+8) long
/--* t39 long
N004 ( 4, 4) [000040] -c-X-------- t40 = * IND long <l:$244, c:$243>
N005 ( 1, 1) [000041] -c---------- t41 = CNS_INT long 96 $c4
/--* t40 long
+--* t41 long
N006 ( 6, 6) [000042] J--X---N---- * LE void <l:$2c3, c:$2c2>
N007 ( 8, 8) [000115] ---X-------- * JTRUE void
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V07 tmp3 u:2 (last use) <l:$280, c:$201>
/--* t25 long
N003 ( 2, 2) [000028] -c---------- t28 = * LEA(b+96) long
/--* t28 long
N004 ( 4, 4) [000029] n----------- t29 = * IND long <l:$282, c:$204>
/--* t29 long
N006 ( 8, 7) [000159] DA---------- * STORE_LCL_VAR long V15 cse1 d:1
N007 ( 3, 2) [000160] ------------ t160 = LCL_VAR long V15 cse1 u:1 <l:$282, c:$204>
N009 ( 1, 1) [000032] -c---------- t32 = CNS_INT long 0 $c0
/--* t160 long
+--* t32 long
N010 ( 13, 11) [000033] J------N---- * EQ void <l:$2c5, c:$2c4>
N011 ( 15, 13) [000116] ------------ * JTRUE void
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
N001 ( 3, 2) [000162] ------------ t162 = LCL_VAR long V15 cse1 u:1 (last use) <l:$282, c:$204>
/--* t162 long
N003 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR long V08 tmp4 d:4
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR long V05 tmp1 u:2 (last use) $1c5
/--* t17 long
[000173] ------------ t173 = * PUTARG_REG long REG rcx
N004 ( 2, 10) [000030] ------------ t30 = CNS_INT(h) long 0x7ff9f1337fe8 token $181
/--* t30 long
[000174] ------------ t174 = * PUTARG_REG long REG rdx
/--* t173 long arg0 in rcx
+--* t174 long arg1 in rdx
N005 ( 17, 18) [000031] --C-G------- t31 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $247
/--* t31 long
N007 ( 17, 18) [000120] DA--G------- * STORE_LCL_VAR long V08 tmp4 d:3
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG long V08 tmp4 u:4 <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ t151 = PHI_ARG long V08 tmp4 u:3 $247
/--* t152 long
+--* t151 long
N003 ( 0, 0) [000147] ------------ t147 = * PHI long
/--* t147 long
N005 ( 0, 0) [000148] DA---------- * STORE_LCL_VAR long V08 tmp4 d:2
N004 ( 3, 2) [000005] -------N---- t5 = LCL_VAR_ADDR byref V02 loc1
* byref V02._pointer (offs=0x00) -> V12 tmp8
* int V02._length (offs=0x08) -> V13 tmp9
/--* t5 byref
[000175] ------------ t175 = * PUTARG_REG byref REG rcx
N006 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V08 tmp4 u:2 (last use) $283
/--* t45 long
[000176] ------------ t176 = * PUTARG_REG long REG rdx
N007 ( 1, 1) [000016] ------------ t16 = LCL_VAR ref V06 tmp2 u:2 (last use) <l:$1c1, c:$101>
/--* t16 ref
[000177] ------------ t177 = * PUTARG_REG ref REG r8
/--* t175 byref this in rcx
+--* t176 long arg1 in rdx
+--* t177 ref arg2 in r8
N008 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor $VN.Void
[000168] ------------ IL_OFFSET void IL offset: 0x15
N001 ( 1, 1) [000047] ------------ t47 = CNS_INT int 0 $40
/--* t47 int
N003 ( 1, 3) [000049] DA---------- * STORE_LCL_VAR int V03 loc2 d:2
------------ BB06 [019..02B), preds={BB08} succs={BB07}
[000169] ------------ IL_OFFSET void IL offset: 0x19
N002 ( 3, 2) [000102] ------------ t102 = LCL_VAR byref (AX) V12 tmp8 $480
N003 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V03 loc2 u:3 $3c0
/--* t94 int
N004 ( 2, 3) [000099] ------------ t99 = * CAST long <- int $24f
/--* t102 byref
+--* t99 long
N007 ( 8, 8) [000103] -c---------- t103 = * LEA(b+(i*8)+0) byref
N010 ( 1, 1) [000105] ------------ t105 = CNS_INT int 0 $40
/--* t103 byref
+--* t105 int
N009 ( 11, 10) [000106] -A-XG------- * STORE_BLK struct<8> (init) (Unroll) $1d1
[000170] ------------ IL_OFFSET void IL offset: 0x27
N001 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V03 loc2 u:3 (last use) $3c0
N002 ( 1, 1) [000109] -c---------- t109 = CNS_INT int 1 $4b
/--* t108 int
+--* t109 int
N003 ( 3, 3) [000110] ------------ t110 = * ADD int $2ce
/--* t110 int
N005 ( 3, 3) [000112] DA---------- * STORE_LCL_VAR int V03 loc2 d:4
------------ BB07 [02B..???), preds={BB05,BB06} succs={BB08}
N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG int V03 loc2 u:4
N002 ( 0, 0) [000149] ------------ t149 = PHI_ARG int V03 loc2 u:2 $40
/--* t150 int
+--* t149 int
N003 ( 0, 0) [000144] ------------ t144 = * PHI int
/--* t144 int
N005 ( 0, 0) [000145] DA---------- * STORE_LCL_VAR int V03 loc2 d:3
[000171] ------------ IL_OFFSET void IL offset: 0x2b
N001 ( 1, 1) [000157] ------------ t157 = LCL_VAR long V14 cse0 u:1 $1c6
/--* t157 long
N002 ( 3, 2) [000063] n----------- t63 = * IND long <l:$284, c:$441>
/--* t63 long
N004 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR long V10 tmp6 d:2
N001 ( 1, 1) [000067] ------------ t67 = LCL_VAR long V10 tmp6 u:2 (last use) <l:$284, c:$441>
/--* t67 long
N003 ( 2, 2) [000080] -c---------- t80 = * LEA(b+8) long
/--* t80 long
N004 ( 4, 4) [000081] ---X-------- t81 = * IND long <l:$24c, c:$24b>
------------ BB08 [???..035) -> BB06 (cond), preds={BB07} succs={BB12,BB06}
N001 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V03 loc2 u:3 $3c0
N002 ( 3, 2) [000132] -c---------- t132 = LCL_VAR int (AX) V13 tmp9 $3c1
/--* t50 int
+--* t132 int
N003 ( 5, 4) [000089] J---G--N---- * LT void $2cd
N004 ( 7, 6) [000090] ----G------- * JTRUE void
------------ BB12 [035..037) (return), preds={BB08} succs={}
[000172] ------------ IL_OFFSET void IL offset: 0x35
N001 ( 1, 1) [000163] ------------ t163 = CNS_INT ref null $VN.Null
/--* t163 ref
N002 ( 2, 2) [000114] ------------ * RETURN ref $105
-------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Calculate stack level slots
*************** Finishing PHASE Calculate stack level slots [no changes]
*************** Starting PHASE Linear scan register alloc
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{V00}
{V05 V06 V07 V14}
{V00}
{V00 V05 V06 V07 V14}
BB02 use def in out
{V07}
{V15}
{V00 V05 V06 V07 V14}
{V00 V05 V06 V14 V15}
BB03 use def in out
{V15}
{V08}
{V00 V06 V14 V15}
{V00 V06 V08 V14}
BB04 use def in out
{V05}
{V08}
{V00 V05 V06 V14}
{V00 V06 V08 V14}
BB05 use def in out
{V06 V08}
{V03}
{V00 V06 V08 V14}
{V00 V03 V14}
BB06 use def in out
{V03}
{V03}
{V00 V03 V14}
{V00 V03 V14}
BB07 use def in out
{V14}
{V10}
{V00 V03 V14}
{V00 V03 V14}
BB08 use def in out
{V03}
{}
{V00 V03 V14}
{V00 V03 V14}
BB12 use def in out
{}
{}
{V00}
{V00}
Interval 0: ref RefPositions {} physReg:NA Preferences=[allInt]
Interval 0: (V00) ref RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: int RefPositions {} physReg:NA Preferences=[allInt]
Interval 1: (V03) int RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: long RefPositions {} physReg:NA Preferences=[allInt]
Interval 2: (V05) long RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: ref RefPositions {} physReg:NA Preferences=[allInt]
Interval 3: (V06) ref RefPositions {} physReg:NA Preferences=[allInt]
Interval 4: long RefPositions {} physReg:NA Preferences=[allInt]
Interval 4: (V07) long RefPositions {} physReg:NA Preferences=[allInt]
Interval 5: long RefPositions {} physReg:NA Preferences=[allInt]
Interval 5: (V08) long RefPositions {} physReg:NA Preferences=[allInt]
Interval 6: long RefPositions {} physReg:NA Preferences=[allInt]
Interval 6: (V10) long RefPositions {} physReg:NA Preferences=[allInt]
Interval 7: long RefPositions {} physReg:NA Preferences=[allInt]
Interval 7: (V14) long RefPositions {} physReg:NA Preferences=[allInt]
Interval 8: long RefPositions {} physReg:NA Preferences=[allInt]
Interval 8: (V15) long RefPositions {} physReg:NA Preferences=[allInt]
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 1, singleExit = 1
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 )
BB02( 0.40)
BB03( 0.40)
BB04( 0.10)
BB05( 1 )
BB07( 8 )
BB08( 8 )
BB06( 2 )
BB12( 1 )
BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
=====
N000. IL_OFFSET IL offset: 0x0
N000. IL_OFFSET IL offset: 0x8
N001. V00(t7)
N003. t135 = LEA(b+16); t7
N004. t8 = IND ; t135
N006. V06(t15); t8
N000. IL_OFFSET IL offset: 0x8
N001. V00(t10)
N002. t11 = IND ; t10
N004. V05(t13); t11
N001. V05(t18)
N003. t20 = LEA(b+56); t18
N004. t21 = IND ; t20
N006. V14(t154); t21
N007. V14(t155)
N009. t22 = IND ; t155
N011. V07(t24); t22
N001. V07(t26)
N003. t39 = LEA(b+8) ; t26
N004. t40 = IND ; t39
N005. CNS_INT 96
N006. LE ; t40
N007. JTRUE
BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
=====
N001. V07(t25*)
N003. t28 = LEA(b+96); t25*
N004. t29 = IND ; t28
N006. V15(t159); t29
N007. V15(t160)
N009. CNS_INT 0
N010. EQ ; t160
N011. JTRUE
BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
=====
N001. V15(t162*)
N003. V08(t118); t162*
BB04 [???..???), preds={BB01,BB02} succs={BB05}
=====
N003. V05(t17*)
N000. t173 = PUTARG_REG; t17*
N004. t30 = CNS_INT(h) 0x7ff9f1337fe8 token
N000. t174 = PUTARG_REG; t30
N005. t31 = CALL help; t173,t174
N007. V08(t120); t31
BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
=====
N004. t5 = LCL_VAR_ADDR V02 loc1
byref V02._pointer (offs=0x00) -> V12 tmp8
int V02._length (offs=0x08) -> V13 tmp9
N000. t175 = PUTARG_REG; t5
N006. V08(t45*)
N000. t176 = PUTARG_REG; t45*
N007. V06(t16*)
N000. t177 = PUTARG_REG; t16*
N008. CALL ; t175,t176,t177
N000. IL_OFFSET IL offset: 0x15
N001. t47 = CNS_INT 0
N003. V03(t49); t47
BB07 [02B..???), preds={BB05,BB06} succs={BB08}
=====
N000. IL_OFFSET IL offset: 0x2b
N001. V14(t157)
N002. t63 = IND ; t157
N004. V10(t65); t63
N001. V10(t67*)
N003. t80 = LEA(b+8) ; t67*
N004. IND ; t80
BB08 [???..035) -> BB06 (cond), preds={BB07} succs={BB12,BB06}
=====
N001. V03(t50)
N002. V13 MEM
N003. LT ; t50
N004. JTRUE
BB06 [019..02B), preds={BB08} succs={BB07}
=====
N000. IL_OFFSET IL offset: 0x19
N002. t102 = V12 MEM
N003. V03(t94)
N004. t99 = CAST ; t94
N007. t103 = LEA(b+(i*8)+0); t102,t99
N010. t105 = CNS_INT 0
N009. STORE_BLK; t103,t105
N000. IL_OFFSET IL offset: 0x27
N001. V03(t108*)
N002. CNS_INT 1
N003. t110 = ADD ; t108*
N005. V03(t112); t110
BB12 [035..037) (return), preds={BB08} succs={}
=====
N000. IL_OFFSET IL offset: 0x35
N001. t163 = CNS_INT null
N002. RETURN ; t163
buildIntervals second part ========
Int arg V00 in reg rcx
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed>
NEW BLOCK BB01
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N003 (???,???) [000165] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
DefList: { }
N005 (???,???) [000166] ------------ * IL_OFFSET void IL offset: 0x8 REG NA
DefList: { }
N007 ( 1, 1) [000007] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $80
DefList: { }
N009 ( 2, 2) [000135] -c---------- * LEA(b+16) byref REG NA
Contained
DefList: { }
N011 ( 4, 4) [000008] ---XG------- * IND ref REG NA <l:$1c4, c:$1c3>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 9: ref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #3 @12 RefTypeDef <Ivl:9> IND BB01 regmask=[allInt] minReg=1>
DefList: { N011.t8. IND }
N013 ( 4, 4) [000015] DA-XG------- * STORE_LCL_VAR ref V06 tmp2 d:2 NA REG NA
<RefPosition #4 @13 RefTypeUse <Ivl:9> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V06/L3> to <I9>
<RefPosition #5 @14 RefTypeDef <Ivl:3 V06> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N015 (???,???) [000167] ------------ * IL_OFFSET void IL offset: 0x8 REG NA
DefList: { }
N017 ( 1, 1) [000010] !----------- * LCL_VAR ref V00 this u:1 NA REG NA $80
DefList: { }
N019 ( 3, 2) [000011] #----O------ * IND long REG NA $1c5
<RefPosition #6 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 10: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #7 @20 RefTypeDef <Ivl:10> IND BB01 regmask=[allInt] minReg=1>
DefList: { N019.t11. IND }
N021 ( 3, 3) [000013] DA---O------ * STORE_LCL_VAR long V05 tmp1 d:2 NA REG NA
<RefPosition #8 @21 RefTypeUse <Ivl:10> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V05/L2> to <I10>
<RefPosition #9 @22 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N023 ( 1, 1) [000018] ------------ * LCL_VAR long V05 tmp1 u:2 NA REG NA $1c5
DefList: { }
N025 ( 2, 2) [000020] -c---------- * LEA(b+56) long REG NA
Contained
DefList: { }
N027 ( 4, 4) [000021] #----------- * IND long REG NA $1c6
<RefPosition #10 @27 RefTypeUse <Ivl:2 V05> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 11: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #11 @28 RefTypeDef <Ivl:11> IND BB01 regmask=[allInt] minReg=1>
DefList: { N027.t21. IND }
N029 ( 4, 4) [000154] DA---------- * STORE_LCL_VAR long V14 cse0 d:1 NA REG NA
<RefPosition #12 @29 RefTypeUse <Ivl:11> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V14/L7> to <I11>
<RefPosition #13 @30 RefTypeDef <Ivl:7 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N031 ( 1, 1) [000155] ------------ * LCL_VAR long V14 cse0 u:1 NA REG NA $1c6
DefList: { }
N033 ( 8, 7) [000022] n----------- * IND long REG NA <l:$280, c:$201>
<RefPosition #14 @33 RefTypeUse <Ivl:7 V14> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
Interval 12: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #15 @34 RefTypeDef <Ivl:12> IND BB01 regmask=[allInt] minReg=1>
DefList: { N033.t22. IND }
N035 ( 8, 7) [000024] DA---------- * STORE_LCL_VAR long V07 tmp3 d:2 NA REG NA
<RefPosition #16 @35 RefTypeUse <Ivl:12> BB01 regmask=[allInt] minReg=1 last>
Assigning related <V07/L4> to <I12>
<RefPosition #17 @36 RefTypeDef <Ivl:4 V07> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N037 ( 1, 1) [000026] ------------ * LCL_VAR long V07 tmp3 u:2 NA REG NA <l:$280, c:$201>
DefList: { }
N039 ( 2, 2) [000039] -c---------- * LEA(b+8) long REG NA
Contained
DefList: { }
N041 ( 4, 4) [000040] -c-X-------- * IND long REG NA <l:$244, c:$243>
Contained
DefList: { }
N043 ( 1, 1) [000041] -c---------- * CNS_INT long 96 REG NA $c4
Contained
DefList: { }
N045 ( 6, 6) [000042] J--X---N---- * LE void REG NA <l:$2c3, c:$2c2>
<RefPosition #18 @45 RefTypeUse <Ivl:4 V07> LCL_VAR BB01 regmask=[allInt] minReg=1 last>
DefList: { }
N047 ( 8, 8) [000115] ---X-------- * JTRUE void REG NA
CHECKING LAST USES for BB01, liveout={V00 V05 V06 V07 V14}
==============================
Reporting this as generic context: referenced
use: {V00}
def: {V05 V06 V07 V14}
NEW BLOCK BB02
Setting BB01 as the predecessor for determining incoming variable registers of BB02
<RefPosition #19 @49 RefTypeBB BB02 regmask=[] minReg=1>
DefList: { }
N051 ( 1, 1) [000025] ------------ * LCL_VAR long V07 tmp3 u:2 NA (last use) REG NA <l:$280, c:$201>
DefList: { }
N053 ( 2, 2) [000028] -c---------- * LEA(b+96) long REG NA
Contained
DefList: { }
N055 ( 4, 4) [000029] n----------- * IND long REG NA <l:$282, c:$204>
<RefPosition #20 @55 RefTypeUse <Ivl:4 V07> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
Interval 13: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #21 @56 RefTypeDef <Ivl:13> IND BB02 regmask=[allInt] minReg=1>
DefList: { N055.t29. IND }
N057 ( 8, 7) [000159] DA---------- * STORE_LCL_VAR long V15 cse1 d:1 NA REG NA
<RefPosition #22 @57 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
Assigning related <V15/L8> to <I13>
<RefPosition #23 @58 RefTypeDef <Ivl:8 V15> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last>
DefList: { }
N059 ( 3, 2) [000160] ------------ * LCL_VAR long V15 cse1 u:1 NA REG NA <l:$282, c:$204>
DefList: { }
N061 ( 1, 1) [000032] -c---------- * CNS_INT long 0 REG NA $c0
Contained
DefList: { }
N063 ( 13, 11) [000033] J------N---- * EQ void REG NA <l:$2c5, c:$2c4>
<RefPosition #24 @63 RefTypeUse <Ivl:8 V15> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
DefList: { }
N065 ( 15, 13) [000116] ------------ * JTRUE void REG NA
CHECKING LAST USES for BB02, liveout={V00 V05 V06 V14 V15}
==============================
Reporting this as generic context: referenced
use: {V07}
def: {V15}
NEW BLOCK BB03
Setting BB02 as the predecessor for determining incoming variable registers of BB03
<RefPosition #25 @67 RefTypeBB BB03 regmask=[] minReg=1>
DefList: { }
N069 ( 3, 2) [000162] ------------ * LCL_VAR long V15 cse1 u:1 NA (last use) REG NA <l:$282, c:$204>
DefList: { }
N071 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR long V08 tmp4 d:4 NA REG NA
<RefPosition #26 @71 RefTypeUse <Ivl:8 V15> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
Assigning related <V08/L5> to <V15/L8>
<RefPosition #27 @72 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 last>
CHECKING LAST USES for BB03, liveout={V00 V06 V08 V14}
==============================
Reporting this as generic context: referenced
use: {V15}
def: {V08}
NEW BLOCK BB04
Setting BB01 as the predecessor for determining incoming variable registers of BB04
<RefPosition #28 @73 RefTypeBB BB04 regmask=[] minReg=1>
DefList: { }
N075 ( 1, 1) [000017] ------------ * LCL_VAR long V05 tmp1 u:2 NA (last use) REG NA $1c5
DefList: { }
N077 (???,???) [000173] ------------ * PUTARG_REG long REG rcx
<RefPosition #29 @77 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #30 @77 RefTypeUse <Ivl:2 V05> LCL_VAR BB04 regmask=[rcx] minReg=1 last fixed>
Interval 14: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #31 @78 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #32 @78 RefTypeDef <Ivl:14> PUTARG_REG BB04 regmask=[rcx] minReg=1 fixed>
DefList: { N077.t173. PUTARG_REG }
N079 ( 2, 10) [000030] ------------ * CNS_INT(h) long 0x7ff9f1337fe8 token REG NA $181
Interval 15: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #33 @80 RefTypeDef <Ivl:15> CNS_INT BB04 regmask=[allInt] minReg=1>
DefList: { N077.t173. PUTARG_REG; N079.t30. CNS_INT }
N081 (???,???) [000174] ------------ * PUTARG_REG long REG rdx
<RefPosition #34 @81 RefTypeFixedReg <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #35 @81 RefTypeUse <Ivl:15> BB04 regmask=[rdx] minReg=1 last fixed>
Interval 16: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #36 @82 RefTypeFixedReg <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #37 @82 RefTypeDef <Ivl:16> PUTARG_REG BB04 regmask=[rdx] minReg=1 fixed>
DefList: { N077.t173. PUTARG_REG; N081.t174. PUTARG_REG }
N083 ( 17, 18) [000031] --C-G------- * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG NA $247
<RefPosition #38 @83 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #39 @83 RefTypeUse <Ivl:14> BB04 regmask=[rcx] minReg=1 last fixed>
<RefPosition #40 @83 RefTypeFixedReg <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #41 @83 RefTypeUse <Ivl:16> BB04 regmask=[rdx] minReg=1 last fixed>
<RefPosition #42 @84 RefTypeKill <Reg:rax> BB04 regmask=[rax] minReg=1>
<RefPosition #43 @84 RefTypeKill <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #44 @84 RefTypeKill <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #45 @84 RefTypeKill <Reg:r8 > BB04 regmask=[r8] minReg=1>
<RefPosition #46 @84 RefTypeKill <Reg:r9 > BB04 regmask=[r9] minReg=1>
<RefPosition #47 @84 RefTypeKill <Reg:r10> BB04 regmask=[r10] minReg=1>
<RefPosition #48 @84 RefTypeKill <Reg:r11> BB04 regmask=[r11] minReg=1>
Interval 17: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #49 @84 RefTypeFixedReg <Reg:rax> BB04 regmask=[rax] minReg=1>
<RefPosition #50 @84 RefTypeDef <Ivl:17> CALL BB04 regmask=[rax] minReg=1 fixed>
DefList: { N083.t31. CALL }
N085 ( 17, 18) [000120] DA--G------- * STORE_LCL_VAR long V08 tmp4 d:3 NA REG NA
<RefPosition #51 @85 RefTypeUse <Ivl:17> BB04 regmask=[allInt] minReg=1 last>
Assigning related <V08/L5> to <I17>
<RefPosition #52 @86 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last>
CHECKING LAST USES for BB04, liveout={V00 V06 V08 V14}
==============================
Reporting this as generic context: referenced
use: {V05}
def: {V08}
NEW BLOCK BB05
Setting BB03 as the predecessor for determining incoming variable registers of BB05
<RefPosition #53 @87 RefTypeBB BB05 regmask=[] minReg=1>
DefList: { }
N089 ( 3, 2) [000005] -------N---- * LCL_VAR_ADDR byref V02 loc1 NA
* byref V02._pointer (offs=0x00) -> V12 tmp8
* int V02._length (offs=0x08) -> V13 tmp9 REG NA
Interval 18: byref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #54 @90 RefTypeDef <Ivl:18> LCL_VAR_ADDR BB05 regmask=[allInt] minReg=1>
DefList: { N089.t5. LCL_VAR_ADDR }
N091 (???,???) [000175] ------------ * PUTARG_REG byref REG rcx
<RefPosition #55 @91 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #56 @91 RefTypeUse <Ivl:18> BB05 regmask=[rcx] minReg=1 last fixed>
Interval 19: byref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #57 @92 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #58 @92 RefTypeDef <Ivl:19> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
DefList: { N091.t175. PUTARG_REG }
N093 ( 1, 1) [000045] ------------ * LCL_VAR long V08 tmp4 u:2 NA (last use) REG NA $283
DefList: { N091.t175. PUTARG_REG }
N095 (???,???) [000176] ------------ * PUTARG_REG long REG rdx
<RefPosition #59 @95 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #60 @95 RefTypeUse <Ivl:5 V08> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed>
Interval 20: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #61 @96 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #62 @96 RefTypeDef <Ivl:20> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed>
DefList: { N091.t175. PUTARG_REG; N095.t176. PUTARG_REG }
N097 ( 1, 1) [000016] ------------ * LCL_VAR ref V06 tmp2 u:2 NA (last use) REG NA <l:$1c1, c:$101>
DefList: { N091.t175. PUTARG_REG; N095.t176. PUTARG_REG }
N099 (???,???) [000177] ------------ * PUTARG_REG ref REG r8
<RefPosition #63 @99 RefTypeFixedReg <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #64 @99 RefTypeUse <Ivl:3 V06> LCL_VAR BB05 regmask=[r8] minReg=1 last fixed>
Interval 21: ref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #65 @100 RefTypeFixedReg <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #66 @100 RefTypeDef <Ivl:21> PUTARG_REG BB05 regmask=[r8] minReg=1 fixed>
DefList: { N091.t175. PUTARG_REG; N095.t176. PUTARG_REG; N099.t177. PUTARG_REG }
N101 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor REG NA $VN.Void
<RefPosition #67 @101 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #68 @101 RefTypeUse <Ivl:19> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #69 @101 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #70 @101 RefTypeUse <Ivl:20> BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #71 @101 RefTypeFixedReg <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #72 @101 RefTypeUse <Ivl:21> BB05 regmask=[r8] minReg=1 last fixed>
<RefPosition #73 @102 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1>
<RefPosition #74 @102 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #75 @102 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #76 @102 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #77 @102 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1>
<RefPosition #78 @102 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1>
<RefPosition #79 @102 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1>
DefList: { }
N103 (???,???) [000168] ------------ * IL_OFFSET void IL offset: 0x15 REG NA
DefList: { }
N105 ( 1, 1) [000047] ------------ * CNS_INT int 0 REG NA $40
Interval 22: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #80 @106 RefTypeDef <Ivl:22> CNS_INT BB05 regmask=[allInt] minReg=1>
DefList: { N105.t47. CNS_INT }
N107 ( 1, 3) [000049] DA---------- * STORE_LCL_VAR int V03 loc2 d:2 NA REG NA
<RefPosition #81 @107 RefTypeUse <Ivl:22> BB05 regmask=[allInt] minReg=1 last>
Assigning related <V03/L1> to <I22>
<RefPosition #82 @108 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1 last>
CHECKING LAST USES for BB05, liveout={V00 V03 V14}
==============================
Reporting this as generic context: referenced
use: {V06 V08}
def: {V03}
NEW BLOCK BB07
Setting BB05 as the predecessor for determining incoming variable registers of BB07
<RefPosition #83 @109 RefTypeBB BB07 regmask=[] minReg=1>
DefList: { }
N111 (???,???) [000171] ------------ * IL_OFFSET void IL offset: 0x2b REG NA
DefList: { }
N113 ( 1, 1) [000157] ------------ * LCL_VAR long V14 cse0 u:1 NA REG NA $1c6
DefList: { }
N115 ( 3, 2) [000063] n----------- * IND long REG NA <l:$284, c:$441>
<RefPosition #84 @115 RefTypeUse <Ivl:7 V14> LCL_VAR BB07 regmask=[allInt] minReg=1 last>
Interval 23: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #85 @116 RefTypeDef <Ivl:23> IND BB07 regmask=[allInt] minReg=1>
DefList: { N115.t63. IND }
N117 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR long V10 tmp6 d:2 NA REG NA
<RefPosition #86 @117 RefTypeUse <Ivl:23> BB07 regmask=[allInt] minReg=1 last>
Assigning related <V10/L6> to <I23>
<RefPosition #87 @118 RefTypeDef <Ivl:6 V10> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1 last>
DefList: { }
N119 ( 1, 1) [000067] ------------ * LCL_VAR long V10 tmp6 u:2 NA (last use) REG NA <l:$284, c:$441>
DefList: { }
N121 ( 2, 2) [000080] -c---------- * LEA(b+8) long REG NA
Contained
DefList: { }
N123 ( 4, 4) [000081] ---X-------- * IND long REG NA <l:$24c, c:$24b>
<RefPosition #88 @123 RefTypeUse <Ivl:6 V10> LCL_VAR BB07 regmask=[allInt] minReg=1 last>
Interval 24: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #89 @124 RefTypeDef <Ivl:24> IND BB07 regmask=[allInt] minReg=1>
CHECKING LAST USES for BB07, liveout={V00 V03 V14}
==============================
Reporting this as generic context: referenced
use: {V14}
def: {V10}
NEW BLOCK BB08
Setting BB07 as the predecessor for determining incoming variable registers of BB08
<RefPosition #90 @125 RefTypeBB BB08 regmask=[] minReg=1>
DefList: { }
N127 ( 1, 1) [000050] ------------ * LCL_VAR int V03 loc2 u:3 NA REG NA $3c0
DefList: { }
N129 ( 3, 2) [000132] -c---------- * LCL_VAR int (AX) V13 tmp9 NA REG NA $3c1
Contained
DefList: { }
N131 ( 5, 4) [000089] J---G--N---- * LT void REG NA $2cd
<RefPosition #91 @131 RefTypeUse <Ivl:1 V03> LCL_VAR BB08 regmask=[allInt] minReg=1 last>
DefList: { }
N133 ( 7, 6) [000090] ----G------- * JTRUE void REG NA
CHECKING LAST USES for BB08, liveout={V00 V03 V14}
==============================
Reporting this as generic context: referenced
use: {V03}
def: {}
NEW BLOCK BB06
Setting BB08 as the predecessor for determining incoming variable registers of BB06
<RefPosition #92 @135 RefTypeBB BB06 regmask=[] minReg=1>
DefList: { }
N137 (???,???) [000169] ------------ * IL_OFFSET void IL offset: 0x19 REG NA
DefList: { }
N139 ( 3, 2) [000102] ------------ * LCL_VAR byref (AX) V12 tmp8 NA REG NA $480
Interval 25: byref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #93 @140 RefTypeDef <Ivl:25> LCL_VAR BB06 regmask=[allInt] minReg=1>
DefList: { N139.t102. LCL_VAR }
N141 ( 1, 1) [000094] ------------ * LCL_VAR int V03 loc2 u:3 NA REG NA $3c0
DefList: { N139.t102. LCL_VAR }
N143 ( 2, 3) [000099] ------------ * CAST long <- int REG NA $24f
<RefPosition #94 @143 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
Interval 26: long RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #95 @144 RefTypeDef <Ivl:26> CAST BB06 regmask=[allInt] minReg=1>
DefList: { N139.t102. LCL_VAR; N143.t99. CAST }
N145 ( 8, 8) [000103] -c---------- * LEA(b+(i*8)+0) byref REG NA
Contained
DefList: { N139.t102. LCL_VAR; N143.t99. CAST }
N147 ( 1, 1) [000105] ------------ * CNS_INT int 0 REG NA $40
Interval 27: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #96 @148 RefTypeDef <Ivl:27> CNS_INT BB06 regmask=[allInt] minReg=1>
DefList: { N139.t102. LCL_VAR; N143.t99. CAST; N147.t105. CNS_INT }
N149 ( 11, 10) [000106] -A-XG------- * STORE_BLK struct<8> (init) (Unroll) REG NA $1d1
<RefPosition #97 @149 RefTypeUse <Ivl:25> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #98 @149 RefTypeUse <Ivl:26> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #99 @149 RefTypeUse <Ivl:27> BB06 regmask=[allInt] minReg=1 last>
DefList: { }
N151 (???,???) [000170] ------------ * IL_OFFSET void IL offset: 0x27 REG NA
DefList: { }
N153 ( 1, 1) [000108] ------------ * LCL_VAR int V03 loc2 u:3 NA (last use) REG NA $3c0
DefList: { }
N155 ( 1, 1) [000109] -c---------- * CNS_INT int 1 REG NA $4b
Contained
DefList: { }
N157 ( 3, 3) [000110] ------------ * ADD int REG NA $2ce
<RefPosition #100 @157 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
Interval 28: int RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #101 @158 RefTypeDef <Ivl:28> ADD BB06 regmask=[allInt] minReg=1>
Assigning related <I28> to <V03/L1>
DefList: { N157.t110. ADD }
N159 ( 3, 3) [000112] DA---------- * STORE_LCL_VAR int V03 loc2 d:4 NA REG NA
<RefPosition #102 @159 RefTypeUse <Ivl:28> BB06 regmask=[allInt] minReg=1 last>
Assigning related <V03/L1> to <I28>
<RefPosition #103 @160 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last>
Exposed uses:<RefPosition #104 @161 RefTypeExpUse <Ivl:1 V03> BB06 regmask=[allInt] minReg=1>
V03<RefPosition #105 @161 RefTypeExpUse <Ivl:7 V14> BB06 regmask=[allInt] minReg=1>
V14
CHECKING LAST USES for BB06, liveout={V00 V03 V14}
==============================
Reporting this as generic context: referenced
use: {V03}
def: {V03}
NEW BLOCK BB12
Setting BB08 as the predecessor for determining incoming variable registers of BB12
<RefPosition #106 @161 RefTypeBB BB12 regmask=[] minReg=1>
DefList: { }
N163 (???,???) [000172] ------------ * IL_OFFSET void IL offset: 0x35 REG NA
DefList: { }
N165 ( 1, 1) [000163] ------------ * CNS_INT ref null REG NA $VN.Null
Interval 29: ref RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #107 @166 RefTypeDef <Ivl:29> CNS_INT BB12 regmask=[allInt] minReg=1>
DefList: { N165.t163. CNS_INT }
N167 ( 2, 2) [000114] ------------ * RETURN ref REG NA $105
<RefPosition #108 @167 RefTypeFixedReg <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #109 @167 RefTypeUse <Ivl:29> BB12 regmask=[rax] minReg=1 last fixed>
Exposed uses:<RefPosition #110 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1>
V00
CHECKING LAST USES for BB12, liveout={V00}
==============================
Reporting this as generic context: referenced
use: {}
def: {}
Reporting this as generic context: referenced
Adding exposed use of this, for lvaKeepAliveAndReportThis
<RefPosition #111 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1>
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (V00) ref RefPositions {#0@0 #2@11 #6@19 #110@169 #111@169} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15]
Interval 1: (V03) int RefPositions {#82@108 #91@131 #94@143 #100@157 #103@160 #104@161} physReg:NA Preferences=[allInt] RelatedInterval <I28>
Interval 2: (V05) long RefPositions {#9@22 #10@27 #30@77} physReg:NA Preferences=[rcx]
Interval 3: (V06) ref RefPositions {#5@14 #64@99} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15]
Interval 4: (V07) long RefPositions {#17@36 #18@45 #20@55} physReg:NA Preferences=[allInt]
Interval 5: (V08) long RefPositions {#27@72 #52@86 #60@95} physReg:NA Preferences=[rdx]
Interval 6: (V10) long RefPositions {#87@118 #88@123} physReg:NA Preferences=[allInt]
Interval 7: (V14) long RefPositions {#13@30 #14@33 #84@115 #105@161} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15]
Interval 8: (V15) long RefPositions {#23@58 #24@63 #26@71} physReg:NA Preferences=[allInt] RelatedInterval <V08/L5>
Interval 9: ref RefPositions {#3@12 #4@13} physReg:NA Preferences=[allInt] RelatedInterval <V06/L3>
Interval 10: long RefPositions {#7@20 #8@21} physReg:NA Preferences=[allInt] RelatedInterval <V05/L2>
Interval 11: long RefPositions {#11@28 #12@29} physReg:NA Preferences=[allInt] RelatedInterval <V14/L7>
Interval 12: long RefPositions {#15@34 #16@35} physReg:NA Preferences=[allInt] RelatedInterval <V07/L4>
Interval 13: long RefPositions {#21@56 #22@57} physReg:NA Preferences=[allInt] RelatedInterval <V15/L8>
Interval 14: long RefPositions {#32@78 #39@83} physReg:NA Preferences=[rcx]
Interval 15: long (constant) RefPositions {#33@80 #35@81} physReg:NA Preferences=[rdx]
Interval 16: long RefPositions {#37@82 #41@83} physReg:NA Preferences=[rdx]
Interval 17: long RefPositions {#50@84 #51@85} physReg:NA Preferences=[rax] RelatedInterval <V08/L5>
Interval 18: byref RefPositions {#54@90 #56@91} physReg:NA Preferences=[rcx]
Interval 19: byref RefPositions {#58@92 #68@101} physReg:NA Preferences=[rcx]
Interval 20: long RefPositions {#62@96 #70@101} physReg:NA Preferences=[rdx]
Interval 21: ref RefPositions {#66@100 #72@101} physReg:NA Preferences=[r8]
Interval 22: int (constant) RefPositions {#80@106 #81@107} physReg:NA Preferences=[allInt] RelatedInterval <V03/L1>
Interval 23: long RefPositions {#85@116 #86@117} physReg:NA Preferences=[allInt] RelatedInterval <V10/L6>
Interval 24: long RefPositions {#89@124} physReg:NA Preferences=[allInt]
Interval 25: byref RefPositions {#93@140 #97@149} physReg:NA Preferences=[allInt]
Interval 26: long RefPositions {#95@144 #98@149} physReg:NA Preferences=[allInt]
Interval 27: int (constant) RefPositions {#96@148 #99@149} physReg:NA Preferences=[allInt]
Interval 28: int RefPositions {#101@158 #102@159} physReg:NA Preferences=[allInt] RelatedInterval <V03/L1>
Interval 29: ref (constant) RefPositions {#107@166 #109@167} physReg:NA Preferences=[rax]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #3 @12 RefTypeDef <Ivl:9> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #4 @13 RefTypeUse <Ivl:9> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #5 @14 RefTypeDef <Ivl:3 V06> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #6 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #7 @20 RefTypeDef <Ivl:10> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #8 @21 RefTypeUse <Ivl:10> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #9 @22 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @27 RefTypeUse <Ivl:2 V05> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @28 RefTypeDef <Ivl:11> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #12 @29 RefTypeUse <Ivl:11> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #13 @30 RefTypeDef <Ivl:7 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #14 @33 RefTypeUse <Ivl:7 V14> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #15 @34 RefTypeDef <Ivl:12> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #16 @35 RefTypeUse <Ivl:12> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #17 @36 RefTypeDef <Ivl:4 V07> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #18 @45 RefTypeUse <Ivl:4 V07> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #19 @49 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #20 @55 RefTypeUse <Ivl:4 V07> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #21 @56 RefTypeDef <Ivl:13> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #22 @57 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #23 @58 RefTypeDef <Ivl:8 V15> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #24 @63 RefTypeUse <Ivl:8 V15> LCL_VAR BB02 regmask=[allInt] minReg=1 regOptional>
<RefPosition #25 @67 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #26 @71 RefTypeUse <Ivl:8 V15> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
<RefPosition #27 @72 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #28 @73 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #29 @77 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #30 @77 RefTypeUse <Ivl:2 V05> LCL_VAR BB04 regmask=[rcx] minReg=1 last fixed>
<RefPosition #31 @78 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #32 @78 RefTypeDef <Ivl:14> PUTARG_REG BB04 regmask=[rcx] minReg=1 fixed>
<RefPosition #33 @80 RefTypeDef <Ivl:15> CNS_INT BB04 regmask=[rdx] minReg=1>
<RefPosition #34 @81 RefTypeFixedReg <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #35 @81 RefTypeUse <Ivl:15> BB04 regmask=[rdx] minReg=1 last fixed>
<RefPosition #36 @82 RefTypeFixedReg <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #37 @82 RefTypeDef <Ivl:16> PUTARG_REG BB04 regmask=[rdx] minReg=1 fixed>
<RefPosition #38 @83 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #39 @83 RefTypeUse <Ivl:14> BB04 regmask=[rcx] minReg=1 last fixed>
<RefPosition #40 @83 RefTypeFixedReg <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #41 @83 RefTypeUse <Ivl:16> BB04 regmask=[rdx] minReg=1 last fixed>
<RefPosition #42 @84 RefTypeKill <Reg:rax> BB04 regmask=[rax] minReg=1 last>
<RefPosition #43 @84 RefTypeKill <Reg:rcx> BB04 regmask=[rcx] minReg=1 last>
<RefPosition #44 @84 RefTypeKill <Reg:rdx> BB04 regmask=[rdx] minReg=1 last>
<RefPosition #45 @84 RefTypeKill <Reg:r8 > BB04 regmask=[r8] minReg=1 last>
<RefPosition #46 @84 RefTypeKill <Reg:r9 > BB04 regmask=[r9] minReg=1 last>
<RefPosition #47 @84 RefTypeKill <Reg:r10> BB04 regmask=[r10] minReg=1 last>
<RefPosition #48 @84 RefTypeKill <Reg:r11> BB04 regmask=[r11] minReg=1 last>
<RefPosition #49 @84 RefTypeFixedReg <Reg:rax> BB04 regmask=[rax] minReg=1>
<RefPosition #50 @84 RefTypeDef <Ivl:17> CALL BB04 regmask=[rax] minReg=1 fixed>
<RefPosition #51 @85 RefTypeUse <Ivl:17> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #52 @86 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #53 @87 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #54 @90 RefTypeDef <Ivl:18> LCL_VAR_ADDR BB05 regmask=[rcx] minReg=1>
<RefPosition #55 @91 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #56 @91 RefTypeUse <Ivl:18> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #57 @92 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #58 @92 RefTypeDef <Ivl:19> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #59 @95 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #60 @95 RefTypeUse <Ivl:5 V08> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #61 @96 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #62 @96 RefTypeDef <Ivl:20> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed>
<RefPosition #63 @99 RefTypeFixedReg <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #64 @99 RefTypeUse <Ivl:3 V06> LCL_VAR BB05 regmask=[r8] minReg=1 last fixed>
<RefPosition #65 @100 RefTypeFixedReg <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #66 @100 RefTypeDef <Ivl:21> PUTARG_REG BB05 regmask=[r8] minReg=1 fixed>
<RefPosition #67 @101 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #68 @101 RefTypeUse <Ivl:19> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #69 @101 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #70 @101 RefTypeUse <Ivl:20> BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #71 @101 RefTypeFixedReg <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #72 @101 RefTypeUse <Ivl:21> BB05 regmask=[r8] minReg=1 last fixed>
<RefPosition #73 @102 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #74 @102 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #75 @102 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #76 @102 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #77 @102 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #78 @102 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #79 @102 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #80 @106 RefTypeDef <Ivl:22> CNS_INT BB05 regmask=[allInt] minReg=1>
<RefPosition #81 @107 RefTypeUse <Ivl:22> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #82 @108 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #83 @109 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #84 @115 RefTypeUse <Ivl:7 V14> LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #85 @116 RefTypeDef <Ivl:23> IND BB07 regmask=[allInt] minReg=1>
<RefPosition #86 @117 RefTypeUse <Ivl:23> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #87 @118 RefTypeDef <Ivl:6 V10> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #88 @123 RefTypeUse <Ivl:6 V10> LCL_VAR BB07 regmask=[allInt] minReg=1 last>
<RefPosition #89 @124 RefTypeDef <Ivl:24> IND BB07 regmask=[allInt] minReg=1 last local>
<RefPosition #90 @125 RefTypeBB BB08 regmask=[] minReg=1>
<RefPosition #91 @131 RefTypeUse <Ivl:1 V03> LCL_VAR BB08 regmask=[allInt] minReg=1>
<RefPosition #92 @135 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #93 @140 RefTypeDef <Ivl:25> LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #94 @143 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #95 @144 RefTypeDef <Ivl:26> CAST BB06 regmask=[allInt] minReg=1>
<RefPosition #96 @148 RefTypeDef <Ivl:27> CNS_INT BB06 regmask=[allInt] minReg=1>
<RefPosition #97 @149 RefTypeUse <Ivl:25> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #98 @149 RefTypeUse <Ivl:26> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #99 @149 RefTypeUse <Ivl:27> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #100 @157 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
<RefPosition #101 @158 RefTypeDef <Ivl:28> ADD BB06 regmask=[allInt] minReg=1>
<RefPosition #102 @159 RefTypeUse <Ivl:28> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #103 @160 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #104 @161 RefTypeExpUse <Ivl:1 V03> BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #105 @161 RefTypeExpUse <Ivl:7 V14> BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #106 @161 RefTypeBB BB12 regmask=[] minReg=1>
<RefPosition #107 @166 RefTypeDef <Ivl:29> CNS_INT BB12 regmask=[rax] minReg=1>
<RefPosition #108 @167 RefTypeFixedReg <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #109 @167 RefTypeUse <Ivl:29> BB12 regmask=[rax] minReg=1 last fixed>
<RefPosition #110 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1 regOptional>
<RefPosition #111 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1 regOptional>
-----------------
<RefPosition #87 @118 RefTypeDef <Ivl:6 V10> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #88 @123 RefTypeUse <Ivl:6 V10> LCL_VAR BB07 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #82 @108 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #91 @131 RefTypeUse <Ivl:1 V03> LCL_VAR BB08 regmask=[allInt] minReg=1>
<RefPosition #94 @143 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #100 @157 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
<RefPosition #103 @160 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #104 @161 RefTypeExpUse <Ivl:1 V03> BB06 regmask=[allInt] minReg=1 regOptional>
-----------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #6 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #110 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1 regOptional>
<RefPosition #111 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1 regOptional>
-----------------
<RefPosition #13 @30 RefTypeDef <Ivl:7 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #14 @33 RefTypeUse <Ivl:7 V14> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #84 @115 RefTypeUse <Ivl:7 V14> LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #105 @161 RefTypeExpUse <Ivl:7 V14> BB06 regmask=[allInt] minReg=1 regOptional>
-----------------
<RefPosition #17 @36 RefTypeDef <Ivl:4 V07> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #18 @45 RefTypeUse <Ivl:4 V07> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #20 @55 RefTypeUse <Ivl:4 V07> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
-----------------
<RefPosition #9 @22 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @27 RefTypeUse <Ivl:2 V05> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #30 @77 RefTypeUse <Ivl:2 V05> LCL_VAR BB04 regmask=[rcx] minReg=1 last fixed>
-----------------
<RefPosition #5 @14 RefTypeDef <Ivl:3 V06> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #64 @99 RefTypeUse <Ivl:3 V06> LCL_VAR BB05 regmask=[r8] minReg=1 last fixed>
-----------------
<RefPosition #27 @72 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #52 @86 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #60 @95 RefTypeUse <Ivl:5 V08> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed>
-----------------
<RefPosition #23 @58 RefTypeDef <Ivl:8 V15> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #24 @63 RefTypeUse <Ivl:8 V15> LCL_VAR BB02 regmask=[allInt] minReg=1 regOptional>
<RefPosition #26 @71 RefTypeUse <Ivl:8 V15> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: V00
BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
=====
N003. IL_OFFSET IL offset: 0x0
N005. IL_OFFSET IL offset: 0x8
N007. V00(L0)
N009. LEA(b+16)
N011. IND
Use:<V00/L0>(#2)
Def:<I9>(#3) Pref:<V06/L3>
N013. V06(L3)
Use:<I9>(#4) *
Def:<V06/L3>(#5)
N015. IL_OFFSET IL offset: 0x8
N017. V00(L0)
N019. IND
Use:<V00/L0>(#6)
Def:<I10>(#7) Pref:<V05/L2>
N021. V05(L2)
Use:<I10>(#8) *
Def:<V05/L2>(#9)
N023. V05(L2)
N025. LEA(b+56)
N027. IND
Use:<V05/L2>(#10)
Def:<I11>(#11) Pref:<V14/L7>
N029. V14(L7)
Use:<I11>(#12) *
Def:<V14/L7>(#13)
N031. V14(L7)
N033. IND
Use:<V14/L7>(#14)
Def:<I12>(#15) Pref:<V07/L4>
N035. V07(L4)
Use:<I12>(#16) *
Def:<V07/L4>(#17)
N037. V07(L4)
N039. LEA(b+8)
N041. IND
N043. CNS_INT 96
N045. LE
Use:<V07/L4>(#18)
N047. JTRUE
BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
=====
N051. V07(L4)
N053. LEA(b+96)
N055. IND
Use:<V07/L4>(#20) *
Def:<I13>(#21) Pref:<V15/L8>
N057. V15(L8)
Use:<I13>(#22) *
Def:<V15/L8>(#23) Pref:<V08/L5>
N059. V15(L8)
N061. CNS_INT 0
N063. EQ
Use:<V15/L8>(#24)
N065. JTRUE
BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
=====
N069. V15(L8)
N071. V08(L5)
Use:<V15/L8>(#26) *
Def:<V08/L5>(#27)
BB04 [???..???), preds={BB01,BB02} succs={BB05}
=====
N075. V05(L2)
N077. PUTARG_REG
Use:<V05/L2>(#30) Fixed:rcx(#29) *
Def:<I14>(#32) rcx
N079. CNS_INT(h) 0x7ff9f1337fe8 token
Def:<I15>(#33)
N081. PUTARG_REG
Use:<I15>(#35) Fixed:rdx(#34) *
Def:<I16>(#37) rdx
N083. CALL help
Use:<I14>(#39) Fixed:rcx(#38) *
Use:<I16>(#41) Fixed:rdx(#40) *
Kill: rax rcx rdx r8 r9 r10 r11
Def:<I17>(#50) rax Pref:<V08/L5>
N085. V08(L5)
Use:<I17>(#51) *
Def:<V08/L5>(#52)
BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
=====
N089. LCL_VAR_ADDR V02 loc1 NA
byref V02._pointer (offs=0x00) -> V12 tmp8
int V02._length (offs=0x08) -> V13 tmp9
Def:<I18>(#54)
N091. PUTARG_REG
Use:<I18>(#56) Fixed:rcx(#55) *
Def:<I19>(#58) rcx
N093. V08(L5)
N095. PUTARG_REG
Use:<V08/L5>(#60) Fixed:rdx(#59) *
Def:<I20>(#62) rdx
N097. V06(L3)
N099. PUTARG_REG
Use:<V06/L3>(#64) Fixed:r8(#63) *
Def:<I21>(#66) r8
N101. CALL
Use:<I19>(#68) Fixed:rcx(#67) *
Use:<I20>(#70) Fixed:rdx(#69) *
Use:<I21>(#72) Fixed:r8(#71) *
Kill: rax rcx rdx r8 r9 r10 r11
N103. IL_OFFSET IL offset: 0x15
N105. CNS_INT 0
Def:<I22>(#80) Pref:<V03/L1>
N107. V03(L1)
Use:<I22>(#81) *
Def:<V03/L1>(#82) Pref:<I28>
BB07 [02B..???), preds={BB05,BB06} succs={BB08}
=====
N111. IL_OFFSET IL offset: 0x2b
N113. V14(L7)
N115. IND
Use:<V14/L7>(#84)
Def:<I23>(#85) Pref:<V10/L6>
N117. V10(L6)
Use:<I23>(#86) *
Def:<V10/L6>(#87)
N119. V10(L6)
N121. LEA(b+8)
N123. IND
Use:<V10/L6>(#88) *
Def:<I24>(#89) LocalDefUse *
BB08 [???..035) -> BB06 (cond), preds={BB07} succs={BB12,BB06}
=====
N127. V03(L1)
N129. V13 MEM
N131. LT
Use:<V03/L1>(#91)
N133. JTRUE
BB06 [019..02B), preds={BB08} succs={BB07}
=====
N137. IL_OFFSET IL offset: 0x19
N139. V12 MEM
Def:<I25>(#93)
N141. V03(L1)
N143. CAST
Use:<V03/L1>(#94)
Def:<I26>(#95)
N145. LEA(b+(i*8)+0)
N147. CNS_INT 0
Def:<I27>(#96)
N149. STORE_BLK
Use:<I25>(#97) *
Use:<I26>(#98) *
Use:<I27>(#99) *
N151. IL_OFFSET IL offset: 0x27
N153. V03(L1)
N155. CNS_INT 1
N157. ADD
Use:<V03/L1>(#100) *
Def:<I28>(#101) Pref:<V03/L1>
N159. V03(L1)
Use:<I28>(#102) *
Def:<V03/L1>(#103) Pref:<I28>
Exposed use of V03 at #104
Exposed use of V14 at #105
BB12 [035..037) (return), preds={BB08} succs={}
=====
N163. IL_OFFSET IL offset: 0x35
N165. CNS_INT null
Def:<I29>(#107)
N167. RETURN
Use:<I29>(#109) Fixed:rax(#108) *
Linear scan intervals after buildIntervals:
Interval 0: (V00) ref RefPositions {#0@0 #2@11 #6@19 #110@169 #111@169} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15]
Interval 1: (V03) int RefPositions {#82@108 #91@131 #94@143 #100@157 #103@160 #104@161} physReg:NA Preferences=[allInt] RelatedInterval <I28>
Interval 2: (V05) long RefPositions {#9@22 #10@27 #30@77} physReg:NA Preferences=[rcx]
Interval 3: (V06) ref RefPositions {#5@14 #64@99} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15]
Interval 4: (V07) long RefPositions {#17@36 #18@45 #20@55} physReg:NA Preferences=[allInt]
Interval 5: (V08) long RefPositions {#27@72 #52@86 #60@95} physReg:NA Preferences=[rdx]
Interval 6: (V10) long RefPositions {#87@118 #88@123} physReg:NA Preferences=[allInt]
Interval 7: (V14) long RefPositions {#13@30 #14@33 #84@115 #105@161} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15]
Interval 8: (V15) long RefPositions {#23@58 #24@63 #26@71} physReg:NA Preferences=[allInt] RelatedInterval <V08/L5>
Interval 9: ref RefPositions {#3@12 #4@13} physReg:NA Preferences=[allInt] RelatedInterval <V06/L3>
Interval 10: long RefPositions {#7@20 #8@21} physReg:NA Preferences=[allInt] RelatedInterval <V05/L2>
Interval 11: long RefPositions {#11@28 #12@29} physReg:NA Preferences=[allInt] RelatedInterval <V14/L7>
Interval 12: long RefPositions {#15@34 #16@35} physReg:NA Preferences=[allInt] RelatedInterval <V07/L4>
Interval 13: long RefPositions {#21@56 #22@57} physReg:NA Preferences=[allInt] RelatedInterval <V15/L8>
Interval 14: long RefPositions {#32@78 #39@83} physReg:NA Preferences=[rcx]
Interval 15: long (constant) RefPositions {#33@80 #35@81} physReg:NA Preferences=[rdx]
Interval 16: long RefPositions {#37@82 #41@83} physReg:NA Preferences=[rdx]
Interval 17: long RefPositions {#50@84 #51@85} physReg:NA Preferences=[rax] RelatedInterval <V08/L5>
Interval 18: byref RefPositions {#54@90 #56@91} physReg:NA Preferences=[rcx]
Interval 19: byref RefPositions {#58@92 #68@101} physReg:NA Preferences=[rcx]
Interval 20: long RefPositions {#62@96 #70@101} physReg:NA Preferences=[rdx]
Interval 21: ref RefPositions {#66@100 #72@101} physReg:NA Preferences=[r8]
Interval 22: int (constant) RefPositions {#80@106 #81@107} physReg:NA Preferences=[allInt] RelatedInterval <V03/L1>
Interval 23: long RefPositions {#85@116 #86@117} physReg:NA Preferences=[allInt] RelatedInterval <V10/L6>
Interval 24: long RefPositions {#89@124} physReg:NA Preferences=[allInt]
Interval 25: byref RefPositions {#93@140 #97@149} physReg:NA Preferences=[allInt]
Interval 26: long RefPositions {#95@144 #98@149} physReg:NA Preferences=[allInt]
Interval 27: int (constant) RefPositions {#96@148 #99@149} physReg:NA Preferences=[allInt]
Interval 28: int RefPositions {#101@158 #102@159} physReg:NA Preferences=[allInt] RelatedInterval <V03/L1>
Interval 29: ref (constant) RefPositions {#107@166 #109@167} physReg:NA Preferences=[rax]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (V00) ref RefPositions {#0@0 #2@11 #6@19 #110@169 #111@169} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15]
Interval 1: (V03) int RefPositions {#82@108 #91@131 #94@143 #100@157 #103@160 #104@161} physReg:NA Preferences=[allInt] RelatedInterval <I28>
Interval 2: (V05) long RefPositions {#9@22 #10@27 #30@77} physReg:NA Preferences=[rcx]
Interval 3: (V06) ref RefPositions {#5@14 #64@99} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15]
Interval 4: (V07) long RefPositions {#17@36 #18@45 #20@55} physReg:NA Preferences=[allInt]
Interval 5: (V08) long RefPositions {#27@72 #52@86 #60@95} physReg:NA Preferences=[rdx]
Interval 6: (V10) long RefPositions {#87@118 #88@123} physReg:NA Preferences=[allInt]
Interval 7: (V14) long RefPositions {#13@30 #14@33 #84@115 #105@161} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15]
Interval 8: (V15) long RefPositions {#23@58 #24@63 #26@71} physReg:NA Preferences=[allInt] RelatedInterval <V08/L5>
Interval 9: ref RefPositions {#3@12 #4@13} physReg:NA Preferences=[allInt] RelatedInterval <V06/L3>
Interval 10: long RefPositions {#7@20 #8@21} physReg:NA Preferences=[allInt] RelatedInterval <V05/L2>
Interval 11: long RefPositions {#11@28 #12@29} physReg:NA Preferences=[allInt] RelatedInterval <V14/L7>
Interval 12: long RefPositions {#15@34 #16@35} physReg:NA Preferences=[allInt] RelatedInterval <V07/L4>
Interval 13: long RefPositions {#21@56 #22@57} physReg:NA Preferences=[allInt] RelatedInterval <V15/L8>
Interval 14: long RefPositions {#32@78 #39@83} physReg:NA Preferences=[rcx]
Interval 15: long (constant) RefPositions {#33@80 #35@81} physReg:NA Preferences=[rdx]
Interval 16: long RefPositions {#37@82 #41@83} physReg:NA Preferences=[rdx]
Interval 17: long RefPositions {#50@84 #51@85} physReg:NA Preferences=[rax] RelatedInterval <V08/L5>
Interval 18: byref RefPositions {#54@90 #56@91} physReg:NA Preferences=[rcx]
Interval 19: byref RefPositions {#58@92 #68@101} physReg:NA Preferences=[rcx]
Interval 20: long RefPositions {#62@96 #70@101} physReg:NA Preferences=[rdx]
Interval 21: ref RefPositions {#66@100 #72@101} physReg:NA Preferences=[r8]
Interval 22: int (constant) RefPositions {#80@106 #81@107} physReg:NA Preferences=[allInt] RelatedInterval <V03/L1>
Interval 23: long RefPositions {#85@116 #86@117} physReg:NA Preferences=[allInt] RelatedInterval <V10/L6>
Interval 24: long RefPositions {#89@124} physReg:NA Preferences=[allInt]
Interval 25: byref RefPositions {#93@140 #97@149} physReg:NA Preferences=[allInt]
Interval 26: long RefPositions {#95@144 #98@149} physReg:NA Preferences=[allInt]
Interval 27: int (constant) RefPositions {#96@148 #99@149} physReg:NA Preferences=[allInt]
Interval 28: int RefPositions {#101@158 #102@159} physReg:NA Preferences=[allInt] RelatedInterval <V03/L1>
Interval 29: ref (constant) RefPositions {#107@166 #109@167} physReg:NA Preferences=[rax]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #3 @12 RefTypeDef <Ivl:9> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #4 @13 RefTypeUse <Ivl:9> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #5 @14 RefTypeDef <Ivl:3 V06> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #6 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #7 @20 RefTypeDef <Ivl:10> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #8 @21 RefTypeUse <Ivl:10> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #9 @22 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @27 RefTypeUse <Ivl:2 V05> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #11 @28 RefTypeDef <Ivl:11> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #12 @29 RefTypeUse <Ivl:11> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #13 @30 RefTypeDef <Ivl:7 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #14 @33 RefTypeUse <Ivl:7 V14> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #15 @34 RefTypeDef <Ivl:12> IND BB01 regmask=[allInt] minReg=1>
<RefPosition #16 @35 RefTypeUse <Ivl:12> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #17 @36 RefTypeDef <Ivl:4 V07> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #18 @45 RefTypeUse <Ivl:4 V07> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #19 @49 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #20 @55 RefTypeUse <Ivl:4 V07> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
<RefPosition #21 @56 RefTypeDef <Ivl:13> IND BB02 regmask=[allInt] minReg=1>
<RefPosition #22 @57 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #23 @58 RefTypeDef <Ivl:8 V15> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #24 @63 RefTypeUse <Ivl:8 V15> LCL_VAR BB02 regmask=[allInt] minReg=1 regOptional>
<RefPosition #25 @67 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #26 @71 RefTypeUse <Ivl:8 V15> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
<RefPosition #27 @72 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #28 @73 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #29 @77 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #30 @77 RefTypeUse <Ivl:2 V05> LCL_VAR BB04 regmask=[rcx] minReg=1 last fixed>
<RefPosition #31 @78 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #32 @78 RefTypeDef <Ivl:14> PUTARG_REG BB04 regmask=[rcx] minReg=1 fixed>
<RefPosition #33 @80 RefTypeDef <Ivl:15> CNS_INT BB04 regmask=[rdx] minReg=1>
<RefPosition #34 @81 RefTypeFixedReg <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #35 @81 RefTypeUse <Ivl:15> BB04 regmask=[rdx] minReg=1 last fixed>
<RefPosition #36 @82 RefTypeFixedReg <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #37 @82 RefTypeDef <Ivl:16> PUTARG_REG BB04 regmask=[rdx] minReg=1 fixed>
<RefPosition #38 @83 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #39 @83 RefTypeUse <Ivl:14> BB04 regmask=[rcx] minReg=1 last fixed>
<RefPosition #40 @83 RefTypeFixedReg <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #41 @83 RefTypeUse <Ivl:16> BB04 regmask=[rdx] minReg=1 last fixed>
<RefPosition #42 @84 RefTypeKill <Reg:rax> BB04 regmask=[rax] minReg=1 last>
<RefPosition #43 @84 RefTypeKill <Reg:rcx> BB04 regmask=[rcx] minReg=1 last>
<RefPosition #44 @84 RefTypeKill <Reg:rdx> BB04 regmask=[rdx] minReg=1 last>
<RefPosition #45 @84 RefTypeKill <Reg:r8 > BB04 regmask=[r8] minReg=1 last>
<RefPosition #46 @84 RefTypeKill <Reg:r9 > BB04 regmask=[r9] minReg=1 last>
<RefPosition #47 @84 RefTypeKill <Reg:r10> BB04 regmask=[r10] minReg=1 last>
<RefPosition #48 @84 RefTypeKill <Reg:r11> BB04 regmask=[r11] minReg=1 last>
<RefPosition #49 @84 RefTypeFixedReg <Reg:rax> BB04 regmask=[rax] minReg=1>
<RefPosition #50 @84 RefTypeDef <Ivl:17> CALL BB04 regmask=[rax] minReg=1 fixed>
<RefPosition #51 @85 RefTypeUse <Ivl:17> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #52 @86 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #53 @87 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #54 @90 RefTypeDef <Ivl:18> LCL_VAR_ADDR BB05 regmask=[rcx] minReg=1>
<RefPosition #55 @91 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #56 @91 RefTypeUse <Ivl:18> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #57 @92 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #58 @92 RefTypeDef <Ivl:19> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #59 @95 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #60 @95 RefTypeUse <Ivl:5 V08> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #61 @96 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #62 @96 RefTypeDef <Ivl:20> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed>
<RefPosition #63 @99 RefTypeFixedReg <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #64 @99 RefTypeUse <Ivl:3 V06> LCL_VAR BB05 regmask=[r8] minReg=1 last fixed>
<RefPosition #65 @100 RefTypeFixedReg <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #66 @100 RefTypeDef <Ivl:21> PUTARG_REG BB05 regmask=[r8] minReg=1 fixed>
<RefPosition #67 @101 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #68 @101 RefTypeUse <Ivl:19> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #69 @101 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #70 @101 RefTypeUse <Ivl:20> BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #71 @101 RefTypeFixedReg <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #72 @101 RefTypeUse <Ivl:21> BB05 regmask=[r8] minReg=1 last fixed>
<RefPosition #73 @102 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #74 @102 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #75 @102 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #76 @102 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #77 @102 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #78 @102 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #79 @102 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #80 @106 RefTypeDef <Ivl:22> CNS_INT BB05 regmask=[allInt] minReg=1>
<RefPosition #81 @107 RefTypeUse <Ivl:22> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #82 @108 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #83 @109 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #84 @115 RefTypeUse <Ivl:7 V14> LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #85 @116 RefTypeDef <Ivl:23> IND BB07 regmask=[allInt] minReg=1>
<RefPosition #86 @117 RefTypeUse <Ivl:23> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #87 @118 RefTypeDef <Ivl:6 V10> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #88 @123 RefTypeUse <Ivl:6 V10> LCL_VAR BB07 regmask=[allInt] minReg=1 last>
<RefPosition #89 @124 RefTypeDef <Ivl:24> IND BB07 regmask=[allInt] minReg=1 last local>
<RefPosition #90 @125 RefTypeBB BB08 regmask=[] minReg=1>
<RefPosition #91 @131 RefTypeUse <Ivl:1 V03> LCL_VAR BB08 regmask=[allInt] minReg=1>
<RefPosition #92 @135 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #93 @140 RefTypeDef <Ivl:25> LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #94 @143 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #95 @144 RefTypeDef <Ivl:26> CAST BB06 regmask=[allInt] minReg=1>
<RefPosition #96 @148 RefTypeDef <Ivl:27> CNS_INT BB06 regmask=[allInt] minReg=1>
<RefPosition #97 @149 RefTypeUse <Ivl:25> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #98 @149 RefTypeUse <Ivl:26> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #99 @149 RefTypeUse <Ivl:27> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #100 @157 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
<RefPosition #101 @158 RefTypeDef <Ivl:28> ADD BB06 regmask=[allInt] minReg=1>
<RefPosition #102 @159 RefTypeUse <Ivl:28> BB06 regmask=[allInt] minReg=1 last>
<RefPosition #103 @160 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #104 @161 RefTypeExpUse <Ivl:1 V03> BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #105 @161 RefTypeExpUse <Ivl:7 V14> BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #106 @161 RefTypeBB BB12 regmask=[] minReg=1>
<RefPosition #107 @166 RefTypeDef <Ivl:29> CNS_INT BB12 regmask=[rax] minReg=1>
<RefPosition #108 @167 RefTypeFixedReg <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #109 @167 RefTypeUse <Ivl:29> BB12 regmask=[rax] minReg=1 last fixed>
<RefPosition #110 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1 regOptional>
<RefPosition #111 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1 regOptional>
VAR REFPOSITIONS BEFORE ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rcx] minReg=1 fixed regOptional>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #6 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #110 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1 regOptional>
<RefPosition #111 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1 regOptional>
--- V01
--- V02
--- V03 (Interval 1)
<RefPosition #82 @108 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #91 @131 RefTypeUse <Ivl:1 V03> LCL_VAR BB08 regmask=[allInt] minReg=1>
<RefPosition #94 @143 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #100 @157 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[allInt] minReg=1 last>
<RefPosition #103 @160 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1>
<RefPosition #104 @161 RefTypeExpUse <Ivl:1 V03> BB06 regmask=[allInt] minReg=1 regOptional>
--- V04
--- V05 (Interval 2)
<RefPosition #9 @22 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #10 @27 RefTypeUse <Ivl:2 V05> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #30 @77 RefTypeUse <Ivl:2 V05> LCL_VAR BB04 regmask=[rcx] minReg=1 last fixed>
--- V06 (Interval 3)
<RefPosition #5 @14 RefTypeDef <Ivl:3 V06> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #64 @99 RefTypeUse <Ivl:3 V06> LCL_VAR BB05 regmask=[r8] minReg=1 last fixed>
--- V07 (Interval 4)
<RefPosition #17 @36 RefTypeDef <Ivl:4 V07> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #18 @45 RefTypeUse <Ivl:4 V07> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #20 @55 RefTypeUse <Ivl:4 V07> LCL_VAR BB02 regmask=[allInt] minReg=1 last>
--- V08 (Interval 5)
<RefPosition #27 @72 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #52 @86 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #60 @95 RefTypeUse <Ivl:5 V08> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed>
--- V09
--- V10 (Interval 6)
<RefPosition #87 @118 RefTypeDef <Ivl:6 V10> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #88 @123 RefTypeUse <Ivl:6 V10> LCL_VAR BB07 regmask=[allInt] minReg=1 last>
--- V11
--- V12
--- V13
--- V14 (Interval 7)
<RefPosition #13 @30 RefTypeDef <Ivl:7 V14> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #14 @33 RefTypeUse <Ivl:7 V14> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #84 @115 RefTypeUse <Ivl:7 V14> LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #105 @161 RefTypeExpUse <Ivl:7 V14> BB06 regmask=[allInt] minReg=1 regOptional>
--- V15 (Interval 8)
<RefPosition #23 @58 RefTypeDef <Ivl:8 V15> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #24 @63 RefTypeUse <Ivl:8 V15> LCL_VAR BB02 regmask=[allInt] minReg=1 regOptional>
<RefPosition #26 @71 RefTypeUse <Ivl:8 V15> LCL_VAR BB03 regmask=[allInt] minReg=1 last>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
Columns are only printed up to the last modifed register, which may increase during allocation,
in which case additional columns will appear.
Registers which are not marked modified have ---- in their column.
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
| |V0 a| | | | | | | |
0.#0 V0 Parm Alloc rsi | | | | | |V0 a| | | |
1.#1 BB1 PredBB0 | | | | | |V0 a| | | |
11.#2 V0 Use Keep rsi | | | | | |V0 a| | | |
12.#3 I9 Def Alloc rdi | | | | | |V0 a|I9 a| | |
13.#4 I9 Use * Keep rdi | | | | | |V0 a|I9 a| | |
14.#5 V6 Def Alloc rdi | | | | | |V0 a|V6 a| | |
19.#6 V0 Use Keep rsi | | | | | |V0 a|V6 a| | |
20.#7 I10 Def Alloc rcx | |I10a| | | |V0 a|V6 a| | |
21.#8 I10 Use * Keep rcx | |I10a| | | |V0 a|V6 a| | |
22.#9 V5 Def Alloc rcx | |V5 a| | | |V0 a|V6 a| | |
27.#10 V5 Use Keep rcx | |V5 a| | | |V0 a|V6 a| | |
28.#11 I11 Def Alloc rbx | |V5 a| |I11a| |V0 a|V6 a| | |
29.#12 I11 Use * Keep rbx | |V5 a| |I11a| |V0 a|V6 a| | |
30.#13 V14 Def Alloc rbx | |V5 a| |V14a| |V0 a|V6 a| | |
33.#14 V14 Use Keep rbx | |V5 a| |V14a| |V0 a|V6 a| | |
34.#15 I12 Def Alloc rdx | |V5 a|I12a|V14a| |V0 a|V6 a| | |
35.#16 I12 Use * Keep rdx | |V5 a|I12a|V14a| |V0 a|V6 a| | |
36.#17 V7 Def Alloc rdx | |V5 a|V7 a|V14a| |V0 a|V6 a| | |
45.#18 V7 Use Keep rdx | |V5 a|V7 a|V14a| |V0 a|V6 a| | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
49.#19 BB2 PredBB1 | |V5 a|V7 a|V14a| |V0 a|V6 a| | |
55.#20 V7 Use * Keep rdx | |V5 a|V7 a|V14a| |V0 a|V6 a| | |
56.#21 I13 Def Alloc rdx | |V5 a|I13a|V14a| |V0 a|V6 a| | |
57.#22 I13 Use * Keep rdx | |V5 a|I13a|V14a| |V0 a|V6 a| | |
58.#23 V15 Def Alloc rdx | |V5 a|V15a|V14a| |V0 a|V6 a| | |
63.#24 V15 Use Keep rdx | |V5 a|V15a|V14a| |V0 a|V6 a| | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
67.#25 BB3 PredBB2 | |V5 i|V15a|V14a| |V0 a|V6 a| | |
71.#26 V15 Use * Keep rdx | |V5 i|V15a|V14a| |V0 a|V6 a| | |
72.#27 V8 Def Alloc rdx | |V5 i|V8 a|V14a| |V0 a|V6 a| | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
73.#28 BB4 PredBB1 | |V5 a|V8 i|V14a| |V0 a|V6 a| | |
77.#29 rcx Fixd Keep rcx | |V5 a|V8 i|V14a| |V0 a|V6 a| | |
77.#30 V5 Use * Keep rcx | |V5 a|V8 i|V14a| |V0 a|V6 a| | |
78.#31 rcx Fixd Keep rcx | | |V8 i|V14a| |V0 a|V6 a| | |
78.#32 I14 Def Alloc rcx | |I14a|V8 i|V14a| |V0 a|V6 a| | |
80.#33 C15 Def Alloc rdx | |I14a|C15a|V14a| |V0 a|V6 a| | |
81.#34 rdx Fixd Keep rdx | |I14a|C15a|V14a| |V0 a|V6 a| | |
81.#35 C15 Use * Keep rdx | |I14a|C15a|V14a| |V0 a|V6 a| | |
82.#36 rdx Fixd Keep rdx | |I14a| |V14a| |V0 a|V6 a| | |
82.#37 I16 Def Alloc rdx | |I14a|I16a|V14a| |V0 a|V6 a| | |
83.#38 rcx Fixd Keep rcx | |I14a|I16a|V14a| |V0 a|V6 a| | |
83.#39 I14 Use * Keep rcx | |I14a|I16a|V14a| |V0 a|V6 a| | |
83.#40 rdx Fixd Keep rdx | |I14a|I16a|V14a| |V0 a|V6 a| | |
83.#41 I16 Use * Keep rdx | |I14a|I16a|V14a| |V0 a|V6 a| | |
Restr rdx | | |V8 i|V14a| |V0 a|V6 a| | |
84.#42 rax Kill Keep rax | | |V8 i|V14a| |V0 a|V6 a| | |
84.#43 rcx Kill Keep rcx | | |V8 i|V14a| |V0 a|V6 a| | |
84.#44 rdx Kill Keep rdx | | | |V14a| |V0 a|V6 a| | |
84.#45 r8 Kill Keep r8 | | | |V14a| |V0 a|V6 a| | |
84.#46 r9 Kill Keep r9 | | | |V14a| |V0 a|V6 a| | |
84.#47 r10 Kill Keep r10 | | | |V14a| |V0 a|V6 a| | |
84.#48 r11 Kill Keep r11 | | | |V14a| |V0 a|V6 a| | |
84.#49 rax Fixd Keep rax | | | |V14a| |V0 a|V6 a| | |
84.#50 I17 Def Alloc rax |I17a| | |V14a| |V0 a|V6 a| | |
85.#51 I17 Use * Keep rax |I17a| | |V14a| |V0 a|V6 a| | |
86.#52 V8 Def Alloc rdx | | |V8 a|V14a| |V0 a|V6 a| | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
87.#53 BB5 PredBB3 | | |V8 a|V14a| |V0 a|V6 a| | |
90.#54 I18 Def Alloc rcx | |I18a|V8 a|V14a| |V0 a|V6 a| | |
91.#55 rcx Fixd Keep rcx | |I18a|V8 a|V14a| |V0 a|V6 a| | |
91.#56 I18 Use * Keep rcx | |I18a|V8 a|V14a| |V0 a|V6 a| | |
92.#57 rcx Fixd Keep rcx | | |V8 a|V14a| |V0 a|V6 a| | |
92.#58 I19 Def Alloc rcx | |I19a|V8 a|V14a| |V0 a|V6 a| | |
95.#59 rdx Fixd Keep rdx | |I19a|V8 a|V14a| |V0 a|V6 a| | |
95.#60 V8 Use * Keep rdx | |I19a|V8 a|V14a| |V0 a|V6 a| | |
96.#61 rdx Fixd Keep rdx | |I19a| |V14a| |V0 a|V6 a| | |
96.#62 I20 Def Alloc rdx | |I19a|I20a|V14a| |V0 a|V6 a| | |
99.#63 r8 Fixd Keep r8 | |I19a|I20a|V14a| |V0 a|V6 a| | |
99.#64 V6 Use * Copy r8 | |I19a|I20a|V14a| |V0 a|V6 a|V6 a| |
100.#65 r8 Fixd Keep r8 | |I19a|I20a|V14a| |V0 a| | | |
100.#66 I21 Def Alloc r8 | |I19a|I20a|V14a| |V0 a| |I21a| |
101.#67 rcx Fixd Keep rcx | |I19a|I20a|V14a| |V0 a| |I21a| |
101.#68 I19 Use * Keep rcx | |I19a|I20a|V14a| |V0 a| |I21a| |
101.#69 rdx Fixd Keep rdx | |I19a|I20a|V14a| |V0 a| |I21a| |
101.#70 I20 Use * Keep rdx | |I19a|I20a|V14a| |V0 a| |I21a| |
101.#71 r8 Fixd Keep r8 | |I19a|I20a|V14a| |V0 a| |I21a| |
101.#72 I21 Use * Keep r8 | |I19a|I20a|V14a| |V0 a| |I21a| |
102.#73 rax Kill Keep rax | | | |V14a| |V0 a| | | |
102.#74 rcx Kill Keep rcx | | | |V14a| |V0 a| | | |
102.#75 rdx Kill Keep rdx | | | |V14a| |V0 a| | | |
102.#76 r8 Kill Keep r8 | | | |V14a| |V0 a| | | |
102.#77 r9 Kill Keep r9 | | | |V14a| |V0 a| | | |
102.#78 r10 Kill Keep r10 | | | |V14a| |V0 a| | | |
102.#79 r11 Kill Keep r11 | | | |V14a| |V0 a| | | |
106.#80 C22 Def Alloc rax |C22a| | |V14a| |V0 a| | | |
107.#81 C22 Use * Keep rax |C22a| | |V14a| |V0 a| | | |
108.#82 V3 Def Alloc rax |V3 a| | |V14a| |V0 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
109.#83 BB7 PredBB5 |V3 a| | |V14a| |V0 a| | | |
115.#84 V14 Use Keep rbx |V3 a| | |V14a| |V0 a| | | |
116.#85 I23 Def Alloc rdx |V3 a| |I23a|V14a| |V0 a| | | |
117.#86 I23 Use * Keep rdx |V3 a| |I23a|V14a| |V0 a| | | |
118.#87 V10 Def Alloc rdx |V3 a| |V10a|V14a| |V0 a| | | |
123.#88 V10 Use * Keep rdx |V3 a| |V10a|V14a| |V0 a| | | |
124.#89 I24 Def * Alloc rdx |V3 a| |I24a|V14a| |V0 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
125.#90 BB8 PredBB7 |V3 a| | |V14a| |V0 a| | | |
131.#91 V3 Use Keep rax |V3 a| | |V14a| |V0 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
135.#92 BB6 PredBB8 |V3 a| | |V14a| |V0 a| | | |
140.#93 I25 Def Alloc rdx |V3 a| |I25a|V14a| |V0 a| | | |
143.#94 V3 Use Keep rax |V3 a| |I25a|V14a| |V0 a| | | |
144.#95 I26 Def Alloc rcx |V3 a|I26a|I25a|V14a| |V0 a| | | |
148.#96 C27 Def Alloc r8 |V3 a|I26a|I25a|V14a| |V0 a| |C27a| |
149.#97 I25 Use * Keep rdx |V3 a|I26a|I25a|V14a| |V0 a| |C27a| |
149.#98 I26 Use * Keep rcx |V3 a|I26a|I25a|V14a| |V0 a| |C27a| |
149.#99 C27 Use * Keep r8 |V3 a|I26a|I25a|V14a| |V0 a| |C27a| |
157.#100 V3 Use * Keep rax |V3 i| | |V14a| |V0 a| |C27i| |
158.#101 I28 Def Alloc rax |I28a| | |V14a| |V0 a| |C27i| |
159.#102 I28 Use * Keep rax |I28a| | |V14a| |V0 a| |C27i| |
Restr rax |V3 i| | |V14a| |V0 a| |C27i| |
160.#103 V3 Def Alloc rax |V3 a| | |V14a| |V0 a| |C27i| |
161.#104 V3 ExpU Keep NA |V3 a| | |V14a| |V0 a| |C27i| |
161.#105 V14 ExpU Keep NA |V3 a| | |V14a| |V0 a| |C27i| |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
161.#106 BB12 PredBB8 | | | | | |V0 a| | | |
166.#107 C29 Def Alloc rax |C29a| | | | |V0 a| | | |
167.#108 rax Fixd Keep rax |C29a| | | | |V0 a| | | |
167.#109 C29 Use * Keep rax |C29a| | | | |V0 a| | | |
169.#110 V0 ExpU Keep NA |C29i| | | | |V0 a| | | |
169.#111 V0 ExpU Keep NA |C29i| | | | |V0 a| | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rsi] minReg=1 fixed regOptional>
<RefPosition #1 @1 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rsi] minReg=1>
<RefPosition #3 @12 RefTypeDef <Ivl:9> IND BB01 regmask=[rdi] minReg=1>
<RefPosition #4 @13 RefTypeUse <Ivl:9> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #5 @14 RefTypeDef <Ivl:3 V06> STORE_LCL_VAR BB01 regmask=[rdi] minReg=1>
<RefPosition #6 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rsi] minReg=1>
<RefPosition #7 @20 RefTypeDef <Ivl:10> IND BB01 regmask=[rcx] minReg=1>
<RefPosition #8 @21 RefTypeUse <Ivl:10> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #9 @22 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #10 @27 RefTypeUse <Ivl:2 V05> LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #11 @28 RefTypeDef <Ivl:11> IND BB01 regmask=[rbx] minReg=1>
<RefPosition #12 @29 RefTypeUse <Ivl:11> BB01 regmask=[rbx] minReg=1 last>
<RefPosition #13 @30 RefTypeDef <Ivl:7 V14> STORE_LCL_VAR BB01 regmask=[rbx] minReg=1>
<RefPosition #14 @33 RefTypeUse <Ivl:7 V14> LCL_VAR BB01 regmask=[rbx] minReg=1>
<RefPosition #15 @34 RefTypeDef <Ivl:12> IND BB01 regmask=[rdx] minReg=1>
<RefPosition #16 @35 RefTypeUse <Ivl:12> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #17 @36 RefTypeDef <Ivl:4 V07> STORE_LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #18 @45 RefTypeUse <Ivl:4 V07> LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #19 @49 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #20 @55 RefTypeUse <Ivl:4 V07> LCL_VAR BB02 regmask=[rdx] minReg=1 last>
<RefPosition #21 @56 RefTypeDef <Ivl:13> IND BB02 regmask=[rdx] minReg=1>
<RefPosition #22 @57 RefTypeUse <Ivl:13> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #23 @58 RefTypeDef <Ivl:8 V15> STORE_LCL_VAR BB02 regmask=[rdx] minReg=1>
<RefPosition #24 @63 RefTypeUse <Ivl:8 V15> LCL_VAR BB02 regmask=[rdx] minReg=1 regOptional>
<RefPosition #25 @67 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #26 @71 RefTypeUse <Ivl:8 V15> LCL_VAR BB03 regmask=[rdx] minReg=1 last>
<RefPosition #27 @72 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB03 regmask=[rdx] minReg=1>
<RefPosition #28 @73 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #29 @77 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #30 @77 RefTypeUse <Ivl:2 V05> LCL_VAR BB04 regmask=[rcx] minReg=1 last fixed>
<RefPosition #31 @78 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #32 @78 RefTypeDef <Ivl:14> PUTARG_REG BB04 regmask=[rcx] minReg=1 fixed>
<RefPosition #33 @80 RefTypeDef <Ivl:15> CNS_INT BB04 regmask=[rdx] minReg=1>
<RefPosition #34 @81 RefTypeFixedReg <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #35 @81 RefTypeUse <Ivl:15> BB04 regmask=[rdx] minReg=1 last fixed>
<RefPosition #36 @82 RefTypeFixedReg <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #37 @82 RefTypeDef <Ivl:16> PUTARG_REG BB04 regmask=[rdx] minReg=1 fixed>
<RefPosition #38 @83 RefTypeFixedReg <Reg:rcx> BB04 regmask=[rcx] minReg=1>
<RefPosition #39 @83 RefTypeUse <Ivl:14> BB04 regmask=[rcx] minReg=1 last fixed>
<RefPosition #40 @83 RefTypeFixedReg <Reg:rdx> BB04 regmask=[rdx] minReg=1>
<RefPosition #41 @83 RefTypeUse <Ivl:16> BB04 regmask=[rdx] minReg=1 last fixed>
<RefPosition #42 @84 RefTypeKill <Reg:rax> BB04 regmask=[rax] minReg=1 last>
<RefPosition #43 @84 RefTypeKill <Reg:rcx> BB04 regmask=[rcx] minReg=1 last>
<RefPosition #44 @84 RefTypeKill <Reg:rdx> BB04 regmask=[rdx] minReg=1 last>
<RefPosition #45 @84 RefTypeKill <Reg:r8 > BB04 regmask=[r8] minReg=1 last>
<RefPosition #46 @84 RefTypeKill <Reg:r9 > BB04 regmask=[r9] minReg=1 last>
<RefPosition #47 @84 RefTypeKill <Reg:r10> BB04 regmask=[r10] minReg=1 last>
<RefPosition #48 @84 RefTypeKill <Reg:r11> BB04 regmask=[r11] minReg=1 last>
<RefPosition #49 @84 RefTypeFixedReg <Reg:rax> BB04 regmask=[rax] minReg=1>
<RefPosition #50 @84 RefTypeDef <Ivl:17> CALL BB04 regmask=[rax] minReg=1 fixed>
<RefPosition #51 @85 RefTypeUse <Ivl:17> BB04 regmask=[rax] minReg=1 last>
<RefPosition #52 @86 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB04 regmask=[rdx] minReg=1>
<RefPosition #53 @87 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #54 @90 RefTypeDef <Ivl:18> LCL_VAR_ADDR BB05 regmask=[rcx] minReg=1>
<RefPosition #55 @91 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #56 @91 RefTypeUse <Ivl:18> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #57 @92 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #58 @92 RefTypeDef <Ivl:19> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
<RefPosition #59 @95 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #60 @95 RefTypeUse <Ivl:5 V08> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #61 @96 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #62 @96 RefTypeDef <Ivl:20> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed>
<RefPosition #63 @99 RefTypeFixedReg <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #64 @99 RefTypeUse <Ivl:3 V06> LCL_VAR BB05 regmask=[r8] minReg=1 last copy fixed>
<RefPosition #65 @100 RefTypeFixedReg <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #66 @100 RefTypeDef <Ivl:21> PUTARG_REG BB05 regmask=[r8] minReg=1 fixed>
<RefPosition #67 @101 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
<RefPosition #68 @101 RefTypeUse <Ivl:19> BB05 regmask=[rcx] minReg=1 last fixed>
<RefPosition #69 @101 RefTypeFixedReg <Reg:rdx> BB05 regmask=[rdx] minReg=1>
<RefPosition #70 @101 RefTypeUse <Ivl:20> BB05 regmask=[rdx] minReg=1 last fixed>
<RefPosition #71 @101 RefTypeFixedReg <Reg:r8 > BB05 regmask=[r8] minReg=1>
<RefPosition #72 @101 RefTypeUse <Ivl:21> BB05 regmask=[r8] minReg=1 last fixed>
<RefPosition #73 @102 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
<RefPosition #74 @102 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #75 @102 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #76 @102 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
<RefPosition #77 @102 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
<RefPosition #78 @102 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
<RefPosition #79 @102 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
<RefPosition #80 @106 RefTypeDef <Ivl:22> CNS_INT BB05 regmask=[rax] minReg=1>
<RefPosition #81 @107 RefTypeUse <Ivl:22> BB05 regmask=[rax] minReg=1 last>
<RefPosition #82 @108 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB05 regmask=[rax] minReg=1>
<RefPosition #83 @109 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #84 @115 RefTypeUse <Ivl:7 V14> LCL_VAR BB07 regmask=[rbx] minReg=1>
<RefPosition #85 @116 RefTypeDef <Ivl:23> IND BB07 regmask=[rdx] minReg=1>
<RefPosition #86 @117 RefTypeUse <Ivl:23> BB07 regmask=[rdx] minReg=1 last>
<RefPosition #87 @118 RefTypeDef <Ivl:6 V10> STORE_LCL_VAR BB07 regmask=[rdx] minReg=1>
<RefPosition #88 @123 RefTypeUse <Ivl:6 V10> LCL_VAR BB07 regmask=[rdx] minReg=1 last>
<RefPosition #89 @124 RefTypeDef <Ivl:24> IND BB07 regmask=[rdx] minReg=1 last local>
<RefPosition #90 @125 RefTypeBB BB08 regmask=[] minReg=1>
<RefPosition #91 @131 RefTypeUse <Ivl:1 V03> LCL_VAR BB08 regmask=[rax] minReg=1>
<RefPosition #92 @135 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #93 @140 RefTypeDef <Ivl:25> LCL_VAR BB06 regmask=[rdx] minReg=1>
<RefPosition #94 @143 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[rax] minReg=1>
<RefPosition #95 @144 RefTypeDef <Ivl:26> CAST BB06 regmask=[rcx] minReg=1>
<RefPosition #96 @148 RefTypeDef <Ivl:27> CNS_INT BB06 regmask=[r8] minReg=1>
<RefPosition #97 @149 RefTypeUse <Ivl:25> BB06 regmask=[rdx] minReg=1 last>
<RefPosition #98 @149 RefTypeUse <Ivl:26> BB06 regmask=[rcx] minReg=1 last>
<RefPosition #99 @149 RefTypeUse <Ivl:27> BB06 regmask=[r8] minReg=1 last>
<RefPosition #100 @157 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[rax] minReg=1 last>
<RefPosition #101 @158 RefTypeDef <Ivl:28> ADD BB06 regmask=[rax] minReg=1>
<RefPosition #102 @159 RefTypeUse <Ivl:28> BB06 regmask=[rax] minReg=1 last>
<RefPosition #103 @160 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB06 regmask=[rax] minReg=1>
<RefPosition #104 @161 RefTypeExpUse <Ivl:1 V03> BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #105 @161 RefTypeExpUse <Ivl:7 V14> BB06 regmask=[allInt] minReg=1 regOptional>
<RefPosition #106 @161 RefTypeBB BB12 regmask=[] minReg=1>
<RefPosition #107 @166 RefTypeDef <Ivl:29> CNS_INT BB12 regmask=[rax] minReg=1>
<RefPosition #108 @167 RefTypeFixedReg <Reg:rax> BB12 regmask=[rax] minReg=1>
<RefPosition #109 @167 RefTypeUse <Ivl:29> BB12 regmask=[rax] minReg=1 last fixed>
<RefPosition #110 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1 regOptional>
<RefPosition #111 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1 regOptional>
VAR REFPOSITIONS AFTER ALLOCATION
--- V00 (Interval 0)
<RefPosition #0 @0 RefTypeParamDef <Ivl:0 V00> BB00 regmask=[rsi] minReg=1 fixed regOptional>
<RefPosition #2 @11 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rsi] minReg=1>
<RefPosition #6 @19 RefTypeUse <Ivl:0 V00> LCL_VAR BB01 regmask=[rsi] minReg=1>
<RefPosition #110 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1 regOptional>
<RefPosition #111 @169 RefTypeExpUse <Ivl:0 V00> BB12 regmask=[allInt] minReg=1 regOptional>
--- V01
--- V02
--- V03 (Interval 1)
<RefPosition #82 @108 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB05 regmask=[rax] minReg=1>
<RefPosition #91 @131 RefTypeUse <Ivl:1 V03> LCL_VAR BB08 regmask=[rax] minReg=1>
<RefPosition #94 @143 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[rax] minReg=1>
<RefPosition #100 @157 RefTypeUse <Ivl:1 V03> LCL_VAR BB06 regmask=[rax] minReg=1 last>
<RefPosition #103 @160 RefTypeDef <Ivl:1 V03> STORE_LCL_VAR BB06 regmask=[rax] minReg=1>
<RefPosition #104 @161 RefTypeExpUse <Ivl:1 V03> BB06 regmask=[allInt] minReg=1 regOptional>
--- V04
--- V05 (Interval 2)
<RefPosition #9 @22 RefTypeDef <Ivl:2 V05> STORE_LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #10 @27 RefTypeUse <Ivl:2 V05> LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #30 @77 RefTypeUse <Ivl:2 V05> LCL_VAR BB04 regmask=[rcx] minReg=1 last fixed>
--- V06 (Interval 3)
<RefPosition #5 @14 RefTypeDef <Ivl:3 V06> STORE_LCL_VAR BB01 regmask=[rdi] minReg=1>
<RefPosition #64 @99 RefTypeUse <Ivl:3 V06> LCL_VAR BB05 regmask=[r8] minReg=1 last copy fixed>
--- V07 (Interval 4)
<RefPosition #17 @36 RefTypeDef <Ivl:4 V07> STORE_LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #18 @45 RefTypeUse <Ivl:4 V07> LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #20 @55 RefTypeUse <Ivl:4 V07> LCL_VAR BB02 regmask=[rdx] minReg=1 last>
--- V08 (Interval 5)
<RefPosition #27 @72 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB03 regmask=[rdx] minReg=1>
<RefPosition #52 @86 RefTypeDef <Ivl:5 V08> STORE_LCL_VAR BB04 regmask=[rdx] minReg=1>
<RefPosition #60 @95 RefTypeUse <Ivl:5 V08> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed>
--- V09
--- V10 (Interval 6)
<RefPosition #87 @118 RefTypeDef <Ivl:6 V10> STORE_LCL_VAR BB07 regmask=[rdx] minReg=1>
<RefPosition #88 @123 RefTypeUse <Ivl:6 V10> LCL_VAR BB07 regmask=[rdx] minReg=1 last>
--- V11
--- V12
--- V13
--- V14 (Interval 7)
<RefPosition #13 @30 RefTypeDef <Ivl:7 V14> STORE_LCL_VAR BB01 regmask=[rbx] minReg=1>
<RefPosition #14 @33 RefTypeUse <Ivl:7 V14> LCL_VAR BB01 regmask=[rbx] minReg=1>
<RefPosition #84 @115 RefTypeUse <Ivl:7 V14> LCL_VAR BB07 regmask=[rbx] minReg=1>
<RefPosition #105 @161 RefTypeExpUse <Ivl:7 V14> BB06 regmask=[allInt] minReg=1 regOptional>
--- V15 (Interval 8)
<RefPosition #23 @58 RefTypeDef <Ivl:8 V15> STORE_LCL_VAR BB02 regmask=[rdx] minReg=1>
<RefPosition #24 @63 RefTypeUse <Ivl:8 V15> LCL_VAR BB02 regmask=[rdx] minReg=1 regOptional>
<RefPosition #26 @71 RefTypeUse <Ivl:8 V15> LCL_VAR BB03 regmask=[rdx] minReg=1 last>
Active intervals at end of allocation:
Active Interval 0: (V00) ref RefPositions {#0@0 #2@11 #6@19 #110@169 #111@169} physReg:rsi Preferences=[rsi]
-----------------------
RESOLVING BB BOUNDARIES
-----------------------
Resolution Candidates: {V00 V03 V05 V06 V07 V08 V14 V15}
Has Critical Edges
Prior to Resolution
BB01
use def in out
{V00}
{V05 V06 V07 V14}
{V00}
{V00 V05 V06 V07 V14}
Var=Reg beg of BB01: V00=rsi
Var=Reg end of BB01: V00=rsi V14=rbx V07=rdx V05=rcx V06=rdi
BB02
use def in out
{V07}
{V15}
{V00 V05 V06 V07 V14}
{V00 V05 V06 V14 V15}
Var=Reg beg of BB02: V00=rsi V14=rbx V07=rdx V05=rcx V06=rdi
Var=Reg end of BB02: V00=rsi V14=rbx V05=rcx V06=rdi V15=rdx
BB03
use def in out
{V15}
{V08}
{V00 V06 V14 V15}
{V00 V06 V08 V14}
Var=Reg beg of BB03: V00=rsi V14=rbx V06=rdi V15=rdx
Var=Reg end of BB03: V00=rsi V14=rbx V06=rdi V08=rdx
BB04
use def in out
{V05}
{V08}
{V00 V05 V06 V14}
{V00 V06 V08 V14}
Var=Reg beg of BB04: V00=rsi V14=rbx V05=rcx V06=rdi
Var=Reg end of BB04: V00=rsi V14=rbx V06=rdi V08=rdx
BB05
use def in out
{V06 V08}
{V03}
{V00 V06 V08 V14}
{V00 V03 V14}
Var=Reg beg of BB05: V00=rsi V14=rbx V06=rdi V08=rdx
Var=Reg end of BB05: V03=rax V00=rsi V14=rbx
BB06
use def in out
{V03}
{V03}
{V00 V03 V14}
{V00 V03 V14}
Var=Reg beg of BB06: V03=rax V00=rsi V14=rbx
Var=Reg end of BB06: V03=rax V00=rsi V14=rbx
BB07
use def in out
{V14}
{V10}
{V00 V03 V14}
{V00 V03 V14}
Var=Reg beg of BB07: V03=rax V00=rsi V14=rbx
Var=Reg end of BB07: V03=rax V00=rsi V14=rbx
BB08
use def in out
{V03}
{}
{V00 V03 V14}
{V00 V03 V14}
Var=Reg beg of BB08: V03=rax V00=rsi V14=rbx
Var=Reg end of BB08: V03=rax V00=rsi V14=rbx
BB12
use def in out
{}
{}
{V00}
{V00}
Var=Reg beg of BB12: V00=rsi
Var=Reg end of BB12: V00=rsi
RESOLVING EDGES
Set V00 argument initial register to rsi
Trees after linear scan register allocator (LSRA)
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target LIR
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i LIR
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i LIR
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall LIR
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall LIR
BB06 [0001] 1 BB08 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target LIR
BB07 [0002] 2 BB05,BB06 8 0 [02B..???) i label target bwd LIR
BB08 [0011] 1 BB07 8 0 [???..035)-> BB06 ( cond ) i target bwd LIR
BB12 [0003] 1 BB08 1 [035..037) (return) i LIR
-----------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
N003 (???,???) [000165] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N005 (???,???) [000166] ------------ IL_OFFSET void IL offset: 0x8 REG NA
N007 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V00 this u:1 rsi REG rsi $80
/--* t7 ref
N009 ( 2, 2) [000135] -c---------- t135 = * LEA(b+16) byref REG NA
/--* t135 byref
N011 ( 4, 4) [000008] ---XG------- t8 = * IND ref REG rdi <l:$1c4, c:$1c3>
/--* t8 ref
N013 ( 4, 4) [000015] DA-XG------- * STORE_LCL_VAR ref V06 tmp2 d:2 rdi REG rdi
N015 (???,???) [000167] ------------ IL_OFFSET void IL offset: 0x8 REG NA
N017 ( 1, 1) [000010] !----------- t10 = LCL_VAR ref V00 this u:1 rsi REG rsi $80
/--* t10 ref
N019 ( 3, 2) [000011] #----O------ t11 = * IND long REG rcx $1c5
/--* t11 long
N021 ( 3, 3) [000013] DA---O------ * STORE_LCL_VAR long V05 tmp1 d:2 rcx REG rcx
N023 ( 1, 1) [000018] ------------ t18 = LCL_VAR long V05 tmp1 u:2 rcx REG rcx $1c5
/--* t18 long
N025 ( 2, 2) [000020] -c---------- t20 = * LEA(b+56) long REG NA
/--* t20 long
N027 ( 4, 4) [000021] #----------- t21 = * IND long REG rbx $1c6
/--* t21 long
N029 ( 4, 4) [000154] DA---------- * STORE_LCL_VAR long V14 cse0 d:1 rbx REG rbx
N031 ( 1, 1) [000155] ------------ t155 = LCL_VAR long V14 cse0 u:1 rbx REG rbx $1c6
/--* t155 long
N033 ( 8, 7) [000022] n----------- t22 = * IND long REG rdx <l:$280, c:$201>
/--* t22 long
N035 ( 8, 7) [000024] DA---------- * STORE_LCL_VAR long V07 tmp3 d:2 rdx REG rdx
N037 ( 1, 1) [000026] ------------ t26 = LCL_VAR long V07 tmp3 u:2 rdx REG rdx <l:$280, c:$201>
/--* t26 long
N039 ( 2, 2) [000039] -c---------- t39 = * LEA(b+8) long REG NA
/--* t39 long
N041 ( 4, 4) [000040] -c-X-------- t40 = * IND long REG NA <l:$244, c:$243>
N043 ( 1, 1) [000041] -c---------- t41 = CNS_INT long 96 REG NA $c4
/--* t40 long
+--* t41 long
N045 ( 6, 6) [000042] J--X---N---- * LE void REG NA <l:$2c3, c:$2c2>
N047 ( 8, 8) [000115] ---X-------- * JTRUE void REG NA
------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
N051 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V07 tmp3 u:2 rdx (last use) REG rdx <l:$280, c:$201>
/--* t25 long
N053 ( 2, 2) [000028] -c---------- t28 = * LEA(b+96) long REG NA
/--* t28 long
N055 ( 4, 4) [000029] n----------- t29 = * IND long REG rdx <l:$282, c:$204>
/--* t29 long
N057 ( 8, 7) [000159] DA---------- * STORE_LCL_VAR long V15 cse1 d:1 rdx REG rdx
N059 ( 3, 2) [000160] ------------ t160 = LCL_VAR long V15 cse1 u:1 rdx REG rdx <l:$282, c:$204>
N061 ( 1, 1) [000032] -c---------- t32 = CNS_INT long 0 REG NA $c0
/--* t160 long
+--* t32 long
N063 ( 13, 11) [000033] J------N---- * EQ void REG NA <l:$2c5, c:$2c4>
N065 ( 15, 13) [000116] ------------ * JTRUE void REG NA
------------ BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
N069 ( 3, 2) [000162] ------------ t162 = LCL_VAR long V15 cse1 u:1 rdx (last use) REG rdx <l:$282, c:$204>
/--* t162 long
N071 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR long V08 tmp4 d:4 rdx REG rdx
------------ BB04 [???..???), preds={BB01,BB02} succs={BB05}
N075 ( 1, 1) [000017] ------------ t17 = LCL_VAR long V05 tmp1 u:2 rcx (last use) REG rcx $1c5
/--* t17 long
N077 (???,???) [000173] ------------ t173 = * PUTARG_REG long REG rcx
N079 ( 2, 10) [000030] ------------ t30 = CNS_INT(h) long 0x7ff9f1337fe8 token REG rdx $181
/--* t30 long
N081 (???,???) [000174] ------------ t174 = * PUTARG_REG long REG rdx
/--* t173 long arg0 in rcx
+--* t174 long arg1 in rdx
N083 ( 17, 18) [000031] --C-G------- t31 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG rax $247
/--* t31 long
N085 ( 17, 18) [000120] DA--G------- * STORE_LCL_VAR long V08 tmp4 d:3 rdx REG rdx
------------ BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG long V08 tmp4 u:4 rdx <l:$282, c:$208>
N002 ( 0, 0) [000151] ------------ t151 = PHI_ARG long V08 tmp4 u:3 rdx $247
/--* t152 long
+--* t151 long
N003 ( 0, 0) [000147] ------------ t147 = * PHI long
/--* t147 long
N005 ( 0, 0) [000148] DA---------- * STORE_LCL_VAR long V08 tmp4 d:2 rdx
N089 ( 3, 2) [000005] -------N---- t5 = LCL_VAR_ADDR byref V02 loc1 rcx
* byref V02._pointer (offs=0x00) -> V12 tmp8
* int V02._length (offs=0x08) -> V13 tmp9 REG rcx
/--* t5 byref
N091 (???,???) [000175] ------------ t175 = * PUTARG_REG byref REG rcx
N093 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V08 tmp4 u:2 rdx (last use) REG rdx $283
/--* t45 long
N095 (???,???) [000176] ------------ t176 = * PUTARG_REG long REG rdx
N097 ( 1, 1) [000016] ------------ t16 = LCL_VAR ref V06 tmp2 u:2 rdi (last use) REG rdi <l:$1c1, c:$101>
/--* t16 ref
N099 (???,???) [000177] ------------ t177 = * PUTARG_REG ref REG r8
/--* t175 byref this in rcx
+--* t176 long arg1 in rdx
+--* t177 ref arg2 in r8
N101 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor REG NA $VN.Void
N103 (???,???) [000168] ------------ IL_OFFSET void IL offset: 0x15 REG NA
N105 ( 1, 1) [000047] ------------ t47 = CNS_INT int 0 REG rax $40
/--* t47 int
N107 ( 1, 3) [000049] DA---------- * STORE_LCL_VAR int V03 loc2 d:2 rax REG rax
------------ BB06 [019..02B), preds={BB08} succs={BB07}
N137 (???,???) [000169] ------------ IL_OFFSET void IL offset: 0x19 REG NA
N139 ( 3, 2) [000102] ------------ t102 = LCL_VAR byref (AX) V12 tmp8 rdx REG rdx $480
N141 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V03 loc2 u:3 rax REG rax $3c0
/--* t94 int
N143 ( 2, 3) [000099] ------------ t99 = * CAST long <- int REG rcx $24f
/--* t102 byref
+--* t99 long
N145 ( 8, 8) [000103] -c---------- t103 = * LEA(b+(i*8)+0) byref REG NA
N147 ( 1, 1) [000105] ------------ t105 = CNS_INT int 0 REG r8 $40
/--* t103 byref
+--* t105 int
N149 ( 11, 10) [000106] -A-XG------- * STORE_BLK struct<8> (init) (Unroll) REG NA $1d1
N151 (???,???) [000170] ------------ IL_OFFSET void IL offset: 0x27 REG NA
N153 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V03 loc2 u:3 rax (last use) REG rax $3c0
N155 ( 1, 1) [000109] -c---------- t109 = CNS_INT int 1 REG NA $4b
/--* t108 int
+--* t109 int
N157 ( 3, 3) [000110] ------------ t110 = * ADD int REG rax $2ce
/--* t110 int
N159 ( 3, 3) [000112] DA---------- * STORE_LCL_VAR int V03 loc2 d:4 rax REG rax
------------ BB07 [02B..???), preds={BB05,BB06} succs={BB08}
N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG int V03 loc2 u:4 rax
N002 ( 0, 0) [000149] ------------ t149 = PHI_ARG int V03 loc2 u:2 rax $40
/--* t150 int
+--* t149 int
N003 ( 0, 0) [000144] ------------ t144 = * PHI int
/--* t144 int
N005 ( 0, 0) [000145] DA---------- * STORE_LCL_VAR int V03 loc2 d:3 rax
N111 (???,???) [000171] ------------ IL_OFFSET void IL offset: 0x2b REG NA
N113 ( 1, 1) [000157] ------------ t157 = LCL_VAR long V14 cse0 u:1 rbx REG rbx $1c6
/--* t157 long
N115 ( 3, 2) [000063] n----------- t63 = * IND long REG rdx <l:$284, c:$441>
/--* t63 long
N117 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR long V10 tmp6 d:2 rdx REG rdx
N119 ( 1, 1) [000067] ------------ t67 = LCL_VAR long V10 tmp6 u:2 rdx (last use) REG rdx <l:$284, c:$441>
/--* t67 long
N121 ( 2, 2) [000080] -c---------- t80 = * LEA(b+8) long REG NA
/--* t80 long
N123 ( 4, 4) [000081] ---X-------- t81 = * IND long REG rdx <l:$24c, c:$24b>
------------ BB08 [???..035) -> BB06 (cond), preds={BB07} succs={BB12,BB06}
N127 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V03 loc2 u:3 rax REG rax $3c0
N129 ( 3, 2) [000132] -c---------- t132 = LCL_VAR int (AX) V13 tmp9 NA REG NA $3c1
/--* t50 int
+--* t132 int
N131 ( 5, 4) [000089] J---G--N---- * LT void REG NA $2cd
N133 ( 7, 6) [000090] ----G------- * JTRUE void REG NA
------------ BB12 [035..037) (return), preds={BB08} succs={}
N163 (???,???) [000172] ------------ IL_OFFSET void IL offset: 0x35 REG NA
N165 ( 1, 1) [000163] ------------ t163 = CNS_INT ref null REG rax $VN.Null
/--* t163 ref
N167 ( 2, 2) [000114] ------------ * RETURN ref REG NA $105
-------------------------------------------------------------------------------------------------------------------
Final allocation
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
0.#0 V0 Parm Alloc rsi | | | | | |V0 a| | | |
1.#1 BB1 PredBB0 | | | | | |V0 a| | | |
11.#2 V0 Use Keep rsi | | | | | |V0 a| | | |
12.#3 I9 Def Alloc rdi | | | | | |V0 a|I9 a| | |
13.#4 I9 Use * Keep rdi | | | | | |V0 a|I9 i| | |
14.#5 V6 Def Alloc rdi | | | | | |V0 a|V6 a| | |
19.#6 V0 Use Keep rsi | | | | | |V0 a|V6 a| | |
20.#7 I10 Def Alloc rcx | |I10a| | | |V0 a|V6 a| | |
21.#8 I10 Use * Keep rcx | |I10i| | | |V0 a|V6 a| | |
22.#9 V5 Def Alloc rcx | |V5 a| | | |V0 a|V6 a| | |
27.#10 V5 Use Keep rcx | |V5 a| | | |V0 a|V6 a| | |
28.#11 I11 Def Alloc rbx | |V5 a| |I11a| |V0 a|V6 a| | |
29.#12 I11 Use * Keep rbx | |V5 a| |I11i| |V0 a|V6 a| | |
30.#13 V14 Def Alloc rbx | |V5 a| |V14a| |V0 a|V6 a| | |
33.#14 V14 Use Keep rbx | |V5 a| |V14a| |V0 a|V6 a| | |
34.#15 I12 Def Alloc rdx | |V5 a|I12a|V14a| |V0 a|V6 a| | |
35.#16 I12 Use * Keep rdx | |V5 a|I12i|V14a| |V0 a|V6 a| | |
36.#17 V7 Def Alloc rdx | |V5 a|V7 a|V14a| |V0 a|V6 a| | |
45.#18 V7 Use Keep rdx | |V5 a|V7 a|V14a| |V0 a|V6 a| | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
49.#19 BB2 PredBB1 | |V5 a|V7 a|V14a| |V0 a|V6 a| | |
55.#20 V7 Use * Keep rdx | |V5 a|V7 i|V14a| |V0 a|V6 a| | |
56.#21 I13 Def Alloc rdx | |V5 a|I13a|V14a| |V0 a|V6 a| | |
57.#22 I13 Use * Keep rdx | |V5 a|I13i|V14a| |V0 a|V6 a| | |
58.#23 V15 Def Alloc rdx | |V5 a|V15a|V14a| |V0 a|V6 a| | |
63.#24 V15 Use Keep rdx | |V5 a|V15a|V14a| |V0 a|V6 a| | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
67.#25 BB3 PredBB2 | | |V15a|V14a| |V0 a|V6 a| | |
71.#26 V15 Use * Keep rdx | | |V15i|V14a| |V0 a|V6 a| | |
72.#27 V8 Def Alloc rdx | | |V8 a|V14a| |V0 a|V6 a| | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
73.#28 BB4 PredBB1 | |V5 a| |V14a| |V0 a|V6 a| | |
77.#29 rcx Fixd Keep rcx | |V5 a| |V14a| |V0 a|V6 a| | |
77.#30 V5 Use * Keep rcx | |V5 i| |V14a| |V0 a|V6 a| | |
78.#31 rcx Fixd Keep rcx | | | |V14a| |V0 a|V6 a| | |
78.#32 I14 Def Alloc rcx | |I14a| |V14a| |V0 a|V6 a| | |
80.#33 C15 Def Alloc rdx | |I14a|C15a|V14a| |V0 a|V6 a| | |
81.#34 rdx Fixd Keep rdx | |I14a|C15a|V14a| |V0 a|V6 a| | |
81.#35 C15 Use * Keep rdx | |I14a|C15i|V14a| |V0 a|V6 a| | |
82.#36 rdx Fixd Keep rdx | |I14a| |V14a| |V0 a|V6 a| | |
82.#37 I16 Def Alloc rdx | |I14a|I16a|V14a| |V0 a|V6 a| | |
83.#38 rcx Fixd Keep rcx | |I14a|I16a|V14a| |V0 a|V6 a| | |
83.#39 I14 Use * Keep rcx | |I14i|I16a|V14a| |V0 a|V6 a| | |
83.#40 rdx Fixd Keep rdx | | |I16a|V14a| |V0 a|V6 a| | |
83.#41 I16 Use * Keep rdx | | |I16i|V14a| |V0 a|V6 a| | |
84.#42 rax Kill Keep rax | | | |V14a| |V0 a|V6 a| | |
84.#43 rcx Kill Keep rcx | | | |V14a| |V0 a|V6 a| | |
84.#44 rdx Kill Keep rdx | | | |V14a| |V0 a|V6 a| | |
84.#45 r8 Kill Keep r8 | | | |V14a| |V0 a|V6 a| | |
84.#46 r9 Kill Keep r9 | | | |V14a| |V0 a|V6 a| | |
84.#47 r10 Kill Keep r10 | | | |V14a| |V0 a|V6 a| | |
84.#48 r11 Kill Keep r11 | | | |V14a| |V0 a|V6 a| | |
84.#49 rax Fixd Keep rax | | | |V14a| |V0 a|V6 a| | |
84.#50 I17 Def Alloc rax |I17a| | |V14a| |V0 a|V6 a| | |
85.#51 I17 Use * Keep rax |I17i| | |V14a| |V0 a|V6 a| | |
86.#52 V8 Def Alloc rdx | | |V8 a|V14a| |V0 a|V6 a| | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
87.#53 BB5 PredBB3 | | |V8 a|V14a| |V0 a|V6 a| | |
90.#54 I18 Def Alloc rcx | |I18a|V8 a|V14a| |V0 a|V6 a| | |
91.#55 rcx Fixd Keep rcx | |I18a|V8 a|V14a| |V0 a|V6 a| | |
91.#56 I18 Use * Keep rcx | |I18i|V8 a|V14a| |V0 a|V6 a| | |
92.#57 rcx Fixd Keep rcx | | |V8 a|V14a| |V0 a|V6 a| | |
92.#58 I19 Def Alloc rcx | |I19a|V8 a|V14a| |V0 a|V6 a| | |
95.#59 rdx Fixd Keep rdx | |I19a|V8 a|V14a| |V0 a|V6 a| | |
95.#60 V8 Use * Keep rdx | |I19a|V8 i|V14a| |V0 a|V6 a| | |
96.#61 rdx Fixd Keep rdx | |I19a| |V14a| |V0 a|V6 a| | |
96.#62 I20 Def Alloc rdx | |I19a|I20a|V14a| |V0 a|V6 a| | |
99.#63 r8 Fixd Keep r8 | |I19a|I20a|V14a| |V0 a|V6 a| | |
99.#64 V6 Use * Copy r8 | |I19a|I20a|V14a| |V0 a|V6 i|V6 i| |
100.#65 r8 Fixd Keep r8 | |I19a|I20a|V14a| |V0 a| | | |
100.#66 I21 Def Alloc r8 | |I19a|I20a|V14a| |V0 a| |I21a| |
101.#67 rcx Fixd Keep rcx | |I19a|I20a|V14a| |V0 a| |I21a| |
101.#68 I19 Use * Keep rcx | |I19i|I20a|V14a| |V0 a| |I21a| |
101.#69 rdx Fixd Keep rdx | | |I20a|V14a| |V0 a| |I21a| |
101.#70 I20 Use * Keep rdx | | |I20i|V14a| |V0 a| |I21a| |
101.#71 r8 Fixd Keep r8 | | | |V14a| |V0 a| |I21a| |
101.#72 I21 Use * Keep r8 | | | |V14a| |V0 a| |I21i| |
102.#73 rax Kill Keep rax | | | |V14a| |V0 a| | | |
102.#74 rcx Kill Keep rcx | | | |V14a| |V0 a| | | |
102.#75 rdx Kill Keep rdx | | | |V14a| |V0 a| | | |
102.#76 r8 Kill Keep r8 | | | |V14a| |V0 a| | | |
102.#77 r9 Kill Keep r9 | | | |V14a| |V0 a| | | |
102.#78 r10 Kill Keep r10 | | | |V14a| |V0 a| | | |
102.#79 r11 Kill Keep r11 | | | |V14a| |V0 a| | | |
106.#80 C22 Def Alloc rax |C22a| | |V14a| |V0 a| | | |
107.#81 C22 Use * Keep rax |C22i| | |V14a| |V0 a| | | |
108.#82 V3 Def Alloc rax |V3 a| | |V14a| |V0 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
109.#83 BB7 PredBB5 |V3 a| | |V14a| |V0 a| | | |
115.#84 V14 Use Keep rbx |V3 a| | |V14a| |V0 a| | | |
116.#85 I23 Def Alloc rdx |V3 a| |I23a|V14a| |V0 a| | | |
117.#86 I23 Use * Keep rdx |V3 a| |I23i|V14a| |V0 a| | | |
118.#87 V10 Def Alloc rdx |V3 a| |V10a|V14a| |V0 a| | | |
123.#88 V10 Use * Keep rdx |V3 a| |V10i|V14a| |V0 a| | | |
124.#89 I24 Def * Alloc rdx |V3 a| |I24i|V14a| |V0 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
125.#90 BB8 PredBB7 |V3 a| | |V14a| |V0 a| | | |
131.#91 V3 Use Keep rax |V3 a| | |V14a| |V0 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
135.#92 BB6 PredBB8 |V3 a| | |V14a| |V0 a| | | |
140.#93 I25 Def Alloc rdx |V3 a| |I25a|V14a| |V0 a| | | |
143.#94 V3 Use Keep rax |V3 a| |I25a|V14a| |V0 a| | | |
144.#95 I26 Def Alloc rcx |V3 a|I26a|I25a|V14a| |V0 a| | | |
148.#96 C27 Def Alloc r8 |V3 a|I26a|I25a|V14a| |V0 a| |C27a| |
149.#97 I25 Use * Keep rdx |V3 a|I26a|I25i|V14a| |V0 a| |C27a| |
149.#98 I26 Use * Keep rcx |V3 a|I26i| |V14a| |V0 a| |C27a| |
149.#99 C27 Use * Keep r8 |V3 a| | |V14a| |V0 a| |C27i| |
157.#100 V3 Use * Keep rax |V3 i| | |V14a| |V0 a| | | |
158.#101 I28 Def Alloc rax |I28a| | |V14a| |V0 a| | | |
159.#102 I28 Use * Keep rax |I28i| | |V14a| |V0 a| | | |
160.#103 V3 Def Alloc rax |V3 a| | |V14a| |V0 a| | | |
161.#104 V3 ExpU |V3 a| | |V14a| |V0 a| | | |
161.#105 V14 ExpU |V3 a| | |V14a| |V0 a| | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |
--------------------------------+----+----+----+----+----+----+----+----+----+
161.#106 BB12 PredBB8 | | | | | |V0 a| | | |
166.#107 C29 Def Alloc rax |C29a| | | | |V0 a| | | |
167.#108 rax Fixd Keep rax |C29a| | | | |V0 a| | | |
167.#109 C29 Use * Keep rax |C29i| | | | |V0 a| | | |
169.#110 V0 ExpU | | | | | |V0 a| | | |
169.#111 V0 ExpU | | | | | |V0 a| | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 11
Total Reg Cand Vars: 9
Total number of Intervals: 29
Total number of RefPositions: 111
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: V00(rcx=>rsi)
BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04}
=====
N003. IL_OFFSET IL offset: 0x0
N005. IL_OFFSET IL offset: 0x8
N007. V00(rsi)
N009. STK = LEA(b+16); rsi
N011. rdi = IND ; STK
* N013. V06(rdi); rdi
N015. IL_OFFSET IL offset: 0x8
N017. V00(rsi)
N019. rcx = IND ; rsi
* N021. V05(rcx); rcx
N023. V05(rcx)
N025. STK = LEA(b+56); rcx
N027. rbx = IND ; STK
* N029. V14(rbx); rbx
N031. V14(rbx)
N033. rdx = IND ; rbx
* N035. V07(rdx); rdx
N037. V07(rdx)
N039. STK = LEA(b+8) ; rdx
N041. STK = IND ; STK
N043. CNS_INT 96
N045. LE ; STK
N047. JTRUE
Var=Reg end of BB01: V00=rsi V14=rbx V07=rdx V05=rcx V06=rdi
BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB02: V00=rsi V14=rbx V07=rdx V05=rcx V06=rdi
N051. V07(rdx*)
N053. STK = LEA(b+96); rdx*
N055. rdx = IND ; STK
* N057. V15(rdx); rdx
N059. V15(rdx)
N061. CNS_INT 0
N063. EQ ; rdx
N065. JTRUE
Var=Reg end of BB02: V00=rsi V14=rbx V05=rcx V06=rdi V15=rdx
BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05}
=====
Predecessor for variable locations: BB02
Var=Reg beg of BB03: V00=rsi V14=rbx V06=rdi V15=rdx
N069. V15(rdx*)
* N071. V08(rdx); rdx*
Var=Reg end of BB03: V00=rsi V14=rbx V06=rdi V08=rdx
BB04 [???..???), preds={BB01,BB02} succs={BB05}
=====
Predecessor for variable locations: BB01
Var=Reg beg of BB04: V00=rsi V14=rbx V05=rcx V06=rdi
N075. V05(rcx*)
N077. rcx = PUTARG_REG; rcx*
N079. rdx = CNS_INT(h) 0x7ff9f1337fe8 token
N081. rdx = PUTARG_REG; rdx
N083. rax = CALL help; rcx,rdx
* N085. V08(rdx); rax
Var=Reg end of BB04: V00=rsi V14=rbx V06=rdi V08=rdx
BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07}
=====
Predecessor for variable locations: BB03
Var=Reg beg of BB05: V00=rsi V14=rbx V06=rdi V08=rdx
N089. rcx = LCL_VAR_ADDR V02 loc1 rcx
byref V02._pointer (offs=0x00) -> V12 tmp8
int V02._length (offs=0x08) -> V13 tmp9
N091. rcx = PUTARG_REG; rcx
N093. V08(rdx*)
N095. rdx = PUTARG_REG; rdx*
N097. V06(rdi*)
N099. r8 = PUTARG_REG; rdi*
N101. CALL ; rcx,rdx,r8
N103. IL_OFFSET IL offset: 0x15
N105. rax = CNS_INT 0
* N107. V03(rax); rax
Var=Reg end of BB05: V03=rax V00=rsi V14=rbx
BB07 [02B..???), preds={BB05,BB06} succs={BB08}
=====
Predecessor for variable locations: BB05
Var=Reg beg of BB07: V03=rax V00=rsi V14=rbx
N111. IL_OFFSET IL offset: 0x2b
N113. V14(rbx)
N115. rdx = IND ; rbx
* N117. V10(rdx); rdx
N119. V10(rdx*)
N121. STK = LEA(b+8) ; rdx*
* N123. rdx = IND ; STK
Var=Reg end of BB07: V03=rax V00=rsi V14=rbx
BB08 [???..035) -> BB06 (cond), preds={BB07} succs={BB12,BB06}
=====
Predecessor for variable locations: BB07
Var=Reg beg of BB08: V03=rax V00=rsi V14=rbx
N127. V03(rax)
N129. V13 MEM
N131. LT ; rax
N133. JTRUE
Var=Reg end of BB08: V03=rax V00=rsi V14=rbx
BB06 [019..02B), preds={BB08} succs={BB07}
=====
Predecessor for variable locations: BB08
Var=Reg beg of BB06: V03=rax V00=rsi V14=rbx
N137. IL_OFFSET IL offset: 0x19
N139. rdx = V12 MEM
N141. V03(rax)
N143. rcx = CAST ; rax
N145. STK = LEA(b+(i*8)+0); rdx,rcx
N147. r8 = CNS_INT 0
N149. STORE_BLK; STK,r8
N151. IL_OFFSET IL offset: 0x27
N153. V03(rax*)
N155. CNS_INT 1
N157. rax = ADD ; rax*
* N159. V03(rax); rax
Var=Reg end of BB06: V03=rax V00=rsi V14=rbx
BB12 [035..037) (return), preds={BB08} succs={}
=====
Predecessor for variable locations: BB08
Var=Reg beg of BB12: V00=rsi
N163. IL_OFFSET IL offset: 0x35
N165. rax = CNS_INT null
N167. RETURN ; rax
Var=Reg end of BB12: V00=rsi
*************** Finishing PHASE Linear scan register alloc
*************** In genGenerateCode()
-----------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
-----------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..015)-> BB04 ( cond ) i label target LIR
BB02 [0006] 1 BB01 0.40 [???..???)-> BB04 ( cond ) i LIR
BB03 [0007] 1 BB02 0.40 [???..???)-> BB05 (always) i LIR
BB04 [0008] 2 BB01,BB02 0.10 [???..???) i label target hascall LIR
BB05 [0004] 2 BB03,BB04 1 [015..019)-> BB07 (always) i label target hascall LIR
BB06 [0001] 1 BB08 2 0 [019..02B) i Loop Loop0 label target bwd bwd-target LIR
BB07 [0002] 2 BB05,BB06 8 0 [02B..???) i label target bwd LIR
BB08 [0011] 1 BB07 8 0 [???..035)-> BB06 ( cond ) i target bwd LIR
BB12 [0003] 1 BB08 1 [035..037) (return) i LIR
-----------------------------------------------------------------------------------------------------------------------------------------
*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
Recording Var Locations at start of BB01
V00(rsi)
Modified regs: [rax rcx rdx rbx rsi rdi r8-r11]
Callee-saved registers pushed: 3 [rbx rsi rdi]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Reporting this as generic context: referenced
Assign V02 loc1, size=16, stkOffs=-0x38
Assign V04 OutArgs, size=32, stkOffs=-0x58
--- delta bump 8 for RA
--- delta bump 88 for RSP frame
--- virtual stack offset to actual stack offset delta is 96
-- V00 was 0, now 96
-- V02 was -56, now 40
-- V04 was -88, now 8
; Final local variable assignments
;
; V00 this [V00,T03] ( 4, 4 ) ref -> rsi this class-hnd
;* V01 loc0 [V01,T10] ( 0, 0 ) ref -> zero-ref ld-addr-op class-hnd
; V02 loc1 [V02 ] ( 3, 11 ) struct (16) [rsp+0x28] do-not-enreg[XS] must-init addr-exposed ld-addr-op
; V03 loc2 [V03,T02] ( 5, 15 ) int -> rax
; V04 OutArgs [V04 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace"
; V05 tmp1 [V05,T06] ( 3, 4.20) long -> rcx "impRuntimeLookup slot"
; V06 tmp2 [V06,T07] ( 2, 4 ) ref -> rdi class-hnd "impAppendStmt"
; V07 tmp3 [V07,T05] ( 3, 4.80) long -> rdx "impRuntimeLookup indirectOffset"
; V08 tmp4 [V08,T08] ( 3, 3 ) long -> rdx "spilling Runtime Lookup tree"
;* V09 tmp5 [V09,T01] ( 0, 0 ) long -> zero-ref "impRuntimeLookup slot"
; V10 tmp6 [V10,T00] ( 2, 32 ) long -> rdx "impRuntimeLookup indirectOffset"
;* V11 tmp7 [V11 ] ( 0, 0 ) long -> zero-ref "spilling Runtime Lookup tree"
; V12 tmp8 [V12 ] ( 2, 3 ) byref -> [rsp+0x28] do-not-enreg[X] addr-exposed V02._pointer(offs=0x00) P-DEP "field V02._pointer (fldOffset=0x0)"
; V13 tmp9 [V13 ] ( 2, 9 ) int -> [rsp+0x30] do-not-enreg[X] addr-exposed V02._length(offs=0x08) P-DEP "field V02._length (fldOffset=0x8)"
; V14 cse0 [V14,T04] ( 3, 10 ) long -> rbx "CSE - aggressive"
; V15 cse1 [V15,T09] ( 3, 1.20) long -> rdx "CSE - conservative"
;
; Lcl frame size = 64
Setting stack level from -572662307 to 0
=============== Generating BB01 [000..015) -> BB04 (cond), preds={} succs={BB02,BB04} flags=0x00000000.40030020: i label target LIR
BB01 IN (1)={V00 } + ByrefExposed + GcHeap
OUT(5)={V00 V14 V07 V05 V06} + ByrefExposed + GcHeap
Recording Var Locations at start of BB01
V00(rsi)
Change life 0000000000000000 {} -> 0000000000000008 {V00}
V00 in reg rsi is becoming live [------]
Live regs: 00000000 {} => 00000040 {rsi}
Live regs: (unchanged) 00000040 {rsi}
GC regs: (unchanged) 00000040 {rsi}
Byref regs: (unchanged) 00000000 {}
L_M53660_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}
Scope info: begin block BB01, IL range [000..015)
Scope info: open scopes =
0 (V00 this) [000..037)
Added IP mapping: 0x0000 STACK_EMPTY (G_M53660_IG02,ins#0,ofs#0) label
Generating: N003 (???,???) [000165] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Added IP mapping: 0x0008 STACK_EMPTY (G_M53660_IG02,ins#0,ofs#0)
Generating: N005 (???,???) [000166] ------------ IL_OFFSET void IL offset: 0x8 REG NA
Generating: N007 ( 1, 1) [000007] ------------ t7 = LCL_VAR ref V00 this u:1 rsi REG rsi $80
/--* t7 ref
Generating: N009 ( 2, 2) [000135] -c---------- t135 = * LEA(b+16) byref REG NA
/--* t135 byref
Generating: N011 ( 4, 4) [000008] ---XG------- t8 = * IND ref REG rdi <l:$1c4, c:$1c3>
IN0001: mov rdi, gword ptr [rsi+16]
GC regs: 00000040 {rsi} => 000000C0 {rsi rdi}
/--* t8 ref
Generating: N013 ( 4, 4) [000015] DA-XG------- * STORE_LCL_VAR ref V06 tmp2 d:2 rdi REG rdi
GC regs: 000000C0 {rsi rdi} => 00000040 {rsi}
V06 in reg rdi is becoming live [000015]
Live regs: 00000040 {rsi} => 000000C0 {rsi rdi}
Live vars: {V00} => {V00 V06}
GC regs: 00000040 {rsi} => 000000C0 {rsi rdi}
genIPmappingAdd: ignoring duplicate IL offset 0x8
Generating: N015 (???,???) [000167] ------------ IL_OFFSET void IL offset: 0x8 REG NA
Generating: N017 ( 1, 1) [000010] !----------- t10 = LCL_VAR ref V00 this u:1 rsi REG rsi $80
/--* t10 ref
Generating: N019 ( 3, 2) [000011] #----O------ t11 = * IND long REG rcx $1c5
IN0002: mov rcx, qword ptr [rsi]
/--* t11 long
Generating: N021 ( 3, 3) [000013] DA---O------ * STORE_LCL_VAR long V05 tmp1 d:2 rcx REG rcx
V05 in reg rcx is becoming live [000013]
Live regs: 000000C0 {rsi rdi} => 000000C2 {rcx rsi rdi}
Live vars: {V00 V06} => {V00 V05 V06}
Generating: N023 ( 1, 1) [000018] ------------ t18 = LCL_VAR long V05 tmp1 u:2 rcx REG rcx $1c5
/--* t18 long
Generating: N025 ( 2, 2) [000020] -c---------- t20 = * LEA(b+56) long REG NA
/--* t20 long
Generating: N027 ( 4, 4) [000021] #----------- t21 = * IND long REG rbx $1c6
IN0003: mov rbx, qword ptr [rcx+56]
/--* t21 long
Generating: N029 ( 4, 4) [000154] DA---------- * STORE_LCL_VAR long V14 cse0 d:1 rbx REG rbx
V14 in reg rbx is becoming live [000154]
Live regs: 000000C2 {rcx rsi rdi} => 000000CA {rcx rbx rsi rdi}
Live vars: {V00 V05 V06} => {V00 V05 V06 V14}
Generating: N031 ( 1, 1) [000155] ------------ t155 = LCL_VAR long V14 cse0 u:1 rbx REG rbx $1c6
/--* t155 long
Generating: N033 ( 8, 7) [000022] n----------- t22 = * IND long REG rdx <l:$280, c:$201>
IN0004: mov rdx, qword ptr [rbx]
/--* t22 long
Generating: N035 ( 8, 7) [000024] DA---------- * STORE_LCL_VAR long V07 tmp3 d:2 rdx REG rdx
V07 in reg rdx is becoming live [000024]
Live regs: 000000CA {rcx rbx rsi rdi} => 000000CE {rcx rdx rbx rsi rdi}
Live vars: {V00 V05 V06 V14} => {V00 V05 V06 V07 V14}
Generating: N037 ( 1, 1) [000026] ------------ t26 = LCL_VAR long V07 tmp3 u:2 rdx REG rdx <l:$280, c:$201>
/--* t26 long
Generating: N039 ( 2, 2) [000039] -c---------- t39 = * LEA(b+8) long REG NA
/--* t39 long
Generating: N041 ( 4, 4) [000040] -c-X-------- t40 = * IND long REG NA <l:$244, c:$243>
Generating: N043 ( 1, 1) [000041] -c---------- t41 = CNS_INT long 96 REG NA $c4
/--* t40 long
+--* t41 long
Generating: N045 ( 6, 6) [000042] J--X---N---- * LE void REG NA <l:$2c3, c:$2c2>
IN0005: cmp qword ptr [rdx+8], 96
Generating: N047 ( 8, 8) [000115] ---X-------- * JTRUE void REG NA
IN0006: jle L_M53660_BB04
Scope info: end block BB01, IL range [000..015)
Scope info: open scopes =
0 (V00 this) [000..037)
=============== Generating BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} flags=0x00000000.40000020: i LIR
BB02 IN (5)={V00 V14 V07 V05 V06 } + ByrefExposed + GcHeap
OUT(5)={V00 V14 V05 V06 V15} + ByrefExposed + GcHeap
Recording Var Locations at start of BB02
V00(rsi) V14(rbx) V07(rdx) V05(rcx) V06(rdi)
Liveness not changing: 00000000000000F8 {V00 V05 V06 V07 V14}
Live regs: 00000000 {} => 000000CE {rcx rdx rbx rsi rdi}
GC regs: 00000000 {} => 000000C0 {rsi rdi}
Byref regs: (unchanged) 00000000 {}
L_M53660_BB02:
G_M53660_IG02: ; offs=000000H, funclet=00, bbWeight=1
Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}
Scope info: begin block BB02, IL range [???..???)
Scope info: ignoring block beginning
Generating: N051 ( 1, 1) [000025] ------------ t25 = LCL_VAR long V07 tmp3 u:2 rdx (last use) REG rdx <l:$280, c:$201>
/--* t25 long
Generating: N053 ( 2, 2) [000028] -c---------- t28 = * LEA(b+96) long REG NA
/--* t28 long
Generating: N055 ( 4, 4) [000029] n----------- t29 = * IND long REG rdx <l:$282, c:$204>
V07 in reg rdx is becoming dead [000025]
Live regs: 000000CE {rcx rdx rbx rsi rdi} => 000000CA {rcx rbx rsi rdi}
Live vars: {V00 V05 V06 V07 V14} => {V00 V05 V06 V14}
IN0007: mov rdx, qword ptr [rdx+96]
/--* t29 long
Generating: N057 ( 8, 7) [000159] DA---------- * STORE_LCL_VAR long V15 cse1 d:1 rdx REG rdx
V15 in reg rdx is becoming live [000159]
Live regs: 000000CA {rcx rbx rsi rdi} => 000000CE {rcx rdx rbx rsi rdi}
Live vars: {V00 V05 V06 V14} => {V00 V05 V06 V14 V15}
Generating: N059 ( 3, 2) [000160] ------------ t160 = LCL_VAR long V15 cse1 u:1 rdx REG rdx <l:$282, c:$204>
Generating: N061 ( 1, 1) [000032] -c---------- t32 = CNS_INT long 0 REG NA $c0
/--* t160 long
+--* t32 long
Generating: N063 ( 13, 11) [000033] J------N---- * EQ void REG NA <l:$2c5, c:$2c4>
IN0008: test rdx, rdx
Generating: N065 ( 15, 13) [000116] ------------ * JTRUE void REG NA
IN0009: je L_M53660_BB04
Scope info: end block BB02, IL range [???..???)
Scope info: ignoring block end
=============== Generating BB03 [???..???) -> BB05 (always), preds={BB02} succs={BB05} flags=0x00000000.40000020: i LIR
BB03 IN (4)={V00 V14 V06 V15} + ByrefExposed + GcHeap
OUT(4)={V00 V14 V06 V08 } + ByrefExposed + GcHeap
Recording Var Locations at start of BB03
V00(rsi) V14(rbx) V06(rdi) V15(rdx)
Change life 00000000000002D8 {V00 V05 V06 V14 V15} -> 0000000000000298 {V00 V06 V14 V15}
V05 in reg rcx is becoming dead [------]
Live regs: (unchanged) 00000000 {}
Live regs: 00000000 {} => 000000CC {rdx rbx rsi rdi}
GC regs: 00000000 {} => 000000C0 {rsi rdi}
Byref regs: (unchanged) 00000000 {}
L_M53660_BB03:
Scope info: begin block BB03, IL range [???..???)
Scope info: ignoring block beginning
Generating: N069 ( 3, 2) [000162] ------------ t162 = LCL_VAR long V15 cse1 u:1 rdx (last use) REG rdx <l:$282, c:$204>
/--* t162 long
Generating: N071 ( 3, 3) [000118] DA---------- * STORE_LCL_VAR long V08 tmp4 d:4 rdx REG rdx
V15 in reg rdx is becoming dead [000162]
Live regs: 000000CC {rdx rbx rsi rdi} => 000000C8 {rbx rsi rdi}
Live vars: {V00 V06 V14 V15} => {V00 V06 V14}
V08 in reg rdx is becoming live [000118]
Live regs: 000000C8 {rbx rsi rdi} => 000000CC {rdx rbx rsi rdi}
Live vars: {V00 V06 V14} => {V00 V06 V08 V14}
Scope info: end block BB03, IL range [???..???)
Scope info: ignoring block end
IN000a: jmp L_M53660_BB05
=============== Generating BB04 [???..???), preds={BB01,BB02} succs={BB05} flags=0x00000004.40030020: i label target hascall LIR
BB04 IN (4)={V00 V14 V05 V06 } + ByrefExposed + GcHeap
OUT(4)={V00 V14 V06 V08} + ByrefExposed + GcHeap
Recording Var Locations at start of BB04
V00(rsi) V14(rbx) V05(rcx) V06(rdi)
Change life 0000000000000198 {V00 V06 V08 V14} -> 00000000000000D8 {V00 V05 V06 V14}
V08 in reg rdx is becoming dead [------]
Live regs: (unchanged) 00000000 {}
V05 in reg rcx is becoming live [------]
Live regs: 00000000 {} => 00000002 {rcx}
Live regs: 00000002 {rcx} => 000000CA {rcx rbx rsi rdi}
GC regs: 00000000 {} => 000000C0 {rsi rdi}
Byref regs: (unchanged) 00000000 {}
L_M53660_BB04:
G_M53660_IG03: ; offs=000019H, funclet=00, bbWeight=0.40
Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}
Scope info: begin block BB04, IL range [???..???)
Scope info: ignoring block beginning
Generating: N075 ( 1, 1) [000017] ------------ t17 = LCL_VAR long V05 tmp1 u:2 rcx (last use) REG rcx $1c5
/--* t17 long
Generating: N077 (???,???) [000173] ------------ t173 = * PUTARG_REG long REG rcx
V05 in reg rcx is becoming dead [000017]
Live regs: 000000CA {rcx rbx rsi rdi} => 000000C8 {rbx rsi rdi}
Live vars: {V00 V05 V06 V14} => {V00 V06 V14}
Generating: N079 ( 2, 10) [000030] ------------ t30 = CNS_INT(h) long 0x7ff9f1337fe8 token REG rdx $181
IN000b: mov rdx, 0x7FF9F1337FE8
/--* t30 long
Generating: N081 (???,???) [000174] ------------ t174 = * PUTARG_REG long REG rdx
/--* t173 long arg0 in rcx
+--* t174 long arg1 in rdx
Generating: N083 ( 17, 18) [000031] --C-G------- t31 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG rax $247
Call: GCvars=0000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}
IN000c: call CORINFO_HELP_RUNTIMEHANDLE_CLASS
/--* t31 long
Generating: N085 ( 17, 18) [000120] DA--G------- * STORE_LCL_VAR long V08 tmp4 d:3 rdx REG rdx
IN000d: mov rdx, rax
V08 in reg rdx is becoming live [000120]
Live regs: 000000C8 {rbx rsi rdi} => 000000CC {rdx rbx rsi rdi}
Live vars: {V00 V06 V14} => {V00 V06 V08 V14}
Scope info: end block BB04, IL range [???..???)
Scope info: ignoring block end
=============== Generating BB05 [015..019) -> BB07 (always), preds={BB03,BB04} succs={BB07} flags=0x00000004.40030020: i label target hascall LIR
BB05 IN (4)={ V00 V14 V06 V08} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14 } + ByrefExposed + GcHeap
Recording Var Locations at start of BB05
V00(rsi) V14(rbx) V06(rdi) V08(rdx)
Liveness not changing: 0000000000000198 {V00 V06 V08 V14}
Live regs: 00000000 {} => 000000CC {rdx rbx rsi rdi}
GC regs: 00000000 {} => 000000C0 {rsi rdi}
Byref regs: (unchanged) 00000000 {}
L_M53660_BB05:
G_M53660_IG04: ; offs=00002BH, funclet=00, bbWeight=0.10
Label: IG05, GCvars=0000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}
Scope info: begin block BB05, IL range [015..019)
Scope info: open scopes =
0 (V00 this) [000..037)
Generating: N089 ( 3, 2) [000005] -------N---- t5 = LCL_VAR_ADDR byref V02 loc1 rcx
* byref V02._pointer (offs=0x00) -> V12 tmp8
* int V02._length (offs=0x08) -> V13 tmp9 REG rcx
IN000e: lea rcx, bword ptr [V02 rsp+28H]
Byref regs: 00000000 {} => 00000002 {rcx}
/--* t5 byref
Generating: N091 (???,???) [000175] ------------ t175 = * PUTARG_REG byref REG rcx
Byref regs: 00000002 {rcx} => 00000000 {}
Byref regs: 00000000 {} => 00000002 {rcx}
Generating: N093 ( 1, 1) [000045] ------------ t45 = LCL_VAR long V08 tmp4 u:2 rdx (last use) REG rdx $283
/--* t45 long
Generating: N095 (???,???) [000176] ------------ t176 = * PUTARG_REG long REG rdx
V08 in reg rdx is becoming dead [000045]
Live regs: 000000CC {rdx rbx rsi rdi} => 000000C8 {rbx rsi rdi}
Live vars: {V00 V06 V08 V14} => {V00 V06 V14}
Generating: N097 ( 1, 1) [000016] ------------ t16 = LCL_VAR ref V06 tmp2 u:2 rdi (last use) REG rdi <l:$1c1, c:$101>
/--* t16 ref
Generating: N099 (???,???) [000177] ------------ t177 = * PUTARG_REG ref REG r8
V06 in reg rdi is becoming dead [000016]
Live regs: 000000C8 {rbx rsi rdi} => 00000048 {rbx rsi}
Live vars: {V00 V06 V14} => {V00 V14}
GC regs: 000000C0 {rsi rdi} => 00000040 {rsi}
IN000f: mov r8, rdi
GC regs: 00000040 {rsi} => 00000140 {rsi r8}
/--* t175 byref this in rcx
+--* t176 long arg1 in rdx
+--* t177 ref arg2 in r8
Generating: N101 ( 19, 14) [000009] --CXG------- * CALL void System.Span`1[__Canon][System.__Canon]..ctor REG NA $VN.Void
Byref regs: 00000002 {rcx} => 00000000 {}
GC regs: 00000140 {rsi r8} => 00000040 {rsi}
Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}
IN0010: call System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this
Added IP mapping: 0x0015 STACK_EMPTY (G_M53660_IG05,ins#3,ofs#13) label
Generating: N103 (???,???) [000168] ------------ IL_OFFSET void IL offset: 0x15 REG NA
Generating: N105 ( 1, 1) [000047] ------------ t47 = CNS_INT int 0 REG rax $40
IN0011: xor eax, eax
/--* t47 int
Generating: N107 ( 1, 3) [000049] DA---------- * STORE_LCL_VAR int V03 loc2 d:2 rax REG rax
V03 in reg rax is becoming live [000049]
Live regs: 00000048 {rbx rsi} => 00000049 {rax rbx rsi}
Live vars: {V00 V14} => {V00 V03 V14}
Scope info: end block BB05, IL range [015..019)
Scope info: open scopes =
0 (V00 this) [000..037)
IN0012: jmp L_M53660_BB07
=============== Generating BB06 [019..02B), preds={BB08} succs={BB07} flags=0x00000010.42036020: i Loop Loop0 label target bwd bwd-target LIR
BB06 IN (3)={V03 V00 V14} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14} + ByrefExposed + GcHeap
Recording Var Locations at start of BB06
V03(rax) V00(rsi) V14(rbx)
Liveness not changing: 000000000000001C {V00 V03 V14}
Live regs: 00000000 {} => 00000049 {rax rbx rsi}
GC regs: 00000000 {} => 00000040 {rsi}
Byref regs: (unchanged) 00000000 {}
L_M53660_BB06:
G_M53660_IG05: ; offs=00003DH, funclet=00, bbWeight=1
Label: IG06, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}
Scope info: begin block BB06, IL range [019..02B)
Scope info: open scopes =
0 (V00 this) [000..037)
3 (V03 loc2) [000..037)
Added IP mapping: 0x0019 STACK_EMPTY (G_M53660_IG06,ins#0,ofs#0) label
Generating: N137 (???,???) [000169] ------------ IL_OFFSET void IL offset: 0x19 REG NA
Generating: N139 ( 3, 2) [000102] ------------ t102 = LCL_VAR byref (AX) V12 tmp8 rdx REG rdx $480
IN0013: mov rdx, bword ptr [V12 rsp+28H]
Byref regs: 00000000 {} => 00000004 {rdx}
Generating: N141 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V03 loc2 u:3 rax REG rax $3c0
/--* t94 int
Generating: N143 ( 2, 3) [000099] ------------ t99 = * CAST long <- int REG rcx $24f
IN0014: movsxd rcx, eax
/--* t102 byref
+--* t99 long
Generating: N145 ( 8, 8) [000103] -c---------- t103 = * LEA(b+(i*8)+0) byref REG NA
Generating: N147 ( 1, 1) [000105] ------------ t105 = CNS_INT int 0 REG r8 $40
IN0015: xor r8d, r8d
/--* t103 byref
+--* t105 int
Generating: N149 ( 11, 10) [000106] -A-XG------- * STORE_BLK struct<8> (init) (Unroll) REG NA $1d1
Byref regs: 00000004 {rdx} => 00000000 {}
IN0016: mov qword ptr [rdx+8*rcx], r8
Added IP mapping: 0x0027 STACK_EMPTY (G_M53660_IG06,ins#4,ofs#15)
Generating: N151 (???,???) [000170] ------------ IL_OFFSET void IL offset: 0x27 REG NA
Generating: N153 ( 1, 1) [000108] ------------ t108 = LCL_VAR int V03 loc2 u:3 rax (last use) REG rax $3c0
Generating: N155 ( 1, 1) [000109] -c---------- t109 = CNS_INT int 1 REG NA $4b
/--* t108 int
+--* t109 int
Generating: N157 ( 3, 3) [000110] ------------ t110 = * ADD int REG rax $2ce
V03 in reg rax is becoming dead [000108]
Live regs: 00000049 {rax rbx rsi} => 00000048 {rbx rsi}
Live vars: {V00 V03 V14} => {V00 V14}
IN0017: inc eax
/--* t110 int
Generating: N159 ( 3, 3) [000112] DA---------- * STORE_LCL_VAR int V03 loc2 d:4 rax REG rax
V03 in reg rax is becoming live [000112]
Live regs: 00000048 {rbx rsi} => 00000049 {rax rbx rsi}
Live vars: {V00 V14} => {V00 V03 V14}
Scope info: end block BB06, IL range [019..02B)
Scope info: open scopes =
0 (V00 this) [000..037)
=============== Generating BB07 [02B..???), preds={BB05,BB06} succs={BB08} flags=0x00000000.42030020: i label target bwd LIR
BB07 IN (3)={V03 V00 V14} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14} + ByrefExposed + GcHeap
Recording Var Locations at start of BB07
V03(rax) V00(rsi) V14(rbx)
Liveness not changing: 000000000000001C {V00 V03 V14}
Live regs: 00000000 {} => 00000049 {rax rbx rsi}
GC regs: 00000000 {} => 00000040 {rsi}
Byref regs: (unchanged) 00000000 {}
L_M53660_BB07:
G_M53660_IG06: ; offs=000051H, funclet=00, bbWeight=2
Label: IG07, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}
Scope info: begin block BB07, IL range [02B..???)
Scope info: open scopes =
0 (V00 this) [000..037)
3 (V03 loc2) [000..037)
Added IP mapping: 0x002B STACK_EMPTY (G_M53660_IG07,ins#0,ofs#0) label
Generating: N111 (???,???) [000171] ------------ IL_OFFSET void IL offset: 0x2b REG NA
Generating: N113 ( 1, 1) [000157] ------------ t157 = LCL_VAR long V14 cse0 u:1 rbx REG rbx $1c6
/--* t157 long
Generating: N115 ( 3, 2) [000063] n----------- t63 = * IND long REG rdx <l:$284, c:$441>
IN0018: mov rdx, qword ptr [rbx]
/--* t63 long
Generating: N117 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR long V10 tmp6 d:2 rdx REG rdx
V10 in reg rdx is becoming live [000065]
Live regs: 00000049 {rax rbx rsi} => 0000004D {rax rdx rbx rsi}
Live vars: {V00 V03 V14} => {V00 V03 V10 V14}
Generating: N119 ( 1, 1) [000067] ------------ t67 = LCL_VAR long V10 tmp6 u:2 rdx (last use) REG rdx <l:$284, c:$441>
/--* t67 long
Generating: N121 ( 2, 2) [000080] -c---------- t80 = * LEA(b+8) long REG NA
/--* t80 long
Generating: N123 ( 4, 4) [000081] ---X-------- t81 = * IND long REG rdx <l:$24c, c:$24b>
V10 in reg rdx is becoming dead [000067]
Live regs: 0000004D {rax rdx rbx rsi} => 00000049 {rax rbx rsi}
Live vars: {V00 V03 V10 V14} => {V00 V03 V14}
IN0019: mov rdx, qword ptr [rdx+8]
Scope info: end block BB07, IL range [02B..???)
Scope info: ignoring block end
=============== Generating BB08 [???..035) -> BB06 (cond), preds={BB07} succs={BB12,BB06} flags=0x00000000.42020020: i target bwd LIR
BB08 IN (3)={V03 V00 V14} + ByrefExposed + GcHeap
OUT(3)={V03 V00 V14} + ByrefExposed + GcHeap
Recording Var Locations at start of BB08
V03(rax) V00(rsi) V14(rbx)
Liveness not changing: 000000000000001C {V00 V03 V14}
Live regs: 00000000 {} => 00000049 {rax rbx rsi}
GC regs: 00000000 {} => 00000040 {rsi}
Byref regs: (unchanged) 00000000 {}
L_M53660_BB08:
G_M53660_IG07: ; offs=000062H, funclet=00, bbWeight=8
Label: IG08, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}
Scope info: begin block BB08, IL range [???..035)
Scope info: ignoring block beginning
Generating: N127 ( 1, 1) [000050] ------------ t50 = LCL_VAR int V03 loc2 u:3 rax REG rax $3c0
Generating: N129 ( 3, 2) [000132] -c---------- t132 = LCL_VAR int (AX) V13 tmp9 NA REG NA $3c1
/--* t50 int
+--* t132 int
Generating: N131 ( 5, 4) [000089] J---G--N---- * LT void REG NA $2cd
IN001a: cmp eax, dword ptr [V13 rsp+30H]
Generating: N133 ( 7, 6) [000090] ----G------- * JTRUE void REG NA
IN001b: jl SHORT L_M53660_BB06
Scope info: end block BB08, IL range [???..035)
Scope info: open scopes =
0 (V00 this) [000..037)
3 (V03 loc2) [000..037)
=============== Generating BB12 [035..037) (return), preds={BB08} succs={} flags=0x00000000.40000020: i LIR
BB12 IN (1)={V00}
OUT(1)={V00}
Recording Var Locations at start of BB12
V00(rsi)
Change life 000000000000001C {V00 V03 V14} -> 0000000000000008 {V00}
V03 in reg rax is becoming dead [------]
Live regs: (unchanged) 00000000 {}
V14 in reg rbx is becoming dead [------]
Live regs: (unchanged) 00000000 {}
Live regs: 00000000 {} => 00000040 {rsi}
GC regs: 00000000 {} => 00000040 {rsi}
Byref regs: (unchanged) 00000000 {}
L_M53660_BB12:
G_M53660_IG08: ; offs=000069H, funclet=00, bbWeight=8
Label: IG09, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}
Scope info: begin block BB12, IL range [035..037)
Scope info: open scopes =
0 (V00 this) [000..037)
Added IP mapping: 0x0035 STACK_EMPTY (G_M53660_IG09,ins#0,ofs#0) label
Generating: N163 (???,???) [000172] ------------ IL_OFFSET void IL offset: 0x35 REG NA
Generating: N165 ( 1, 1) [000163] ------------ t163 = CNS_INT ref null REG rax $VN.Null
IN001c: xor rax, rax
GC regs: 00000040 {rsi} => 00000041 {rax rsi}
/--* t163 ref
Generating: N167 ( 2, 2) [000114] ------------ * RETURN ref REG NA $105
GC regs: 00000041 {rax rsi} => 00000040 {rsi}
Scope info: end block BB12, IL range [035..037)
Scope info: ending scope, LVnum=1 [000..037)
Scope info: ending scope, LVnum=2 [000..037)
siEndScope: Failed to end scope for V02
Scope info: ending scope, LVnum=3 [000..037)
Scope info: ending scope, LVnum=0 [000..037)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M53660_IG09,ins#1,ofs#2) label
GC regs: 00000040 {rsi} => 00000041 {rax rsi}
Extending return value GC liveness to epilog
Reserving epilog IG for block BB12
G_M53660_IG09: ; offs=00006FH, funclet=00, bbWeight=1
*************** After placeholder IG creation
G_M53660_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M53660_IG02: ; offs=000000H, size=0019H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG03: ; offs=000019H, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref
G_M53660_IG04: ; offs=00002BH, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref
G_M53660_IG05: ; offs=00003DH, size=0014H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref
G_M53660_IG06: ; offs=000051H, size=0011H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG07: ; offs=000062H, size=0007H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG08: ; offs=000069H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG09: ; offs=00006FH, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG10: ; epilog placeholder, next placeholder=<END>, BB12 [0003], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000040 {rsi}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000040 {rsi}, InitByrefRegs=00000000 {}
Change life 0000000000000008 {V00} -> 0000000000000000 {}
V00 in reg rsi is becoming dead [------]
Live regs: 00000040 {rsi} => 00000000 {}
# compCycleEstimate = 130, compSizeEstimate = 122 System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this
; Final local variable assignments
;
; V00 this [V00,T03] ( 4, 4 ) ref -> rsi this class-hnd
;* V01 loc0 [V01,T10] ( 0, 0 ) ref -> zero-ref ld-addr-op class-hnd
; V02 loc1 [V02 ] ( 3, 11 ) struct (16) [rsp+0x28] do-not-enreg[XS] must-init addr-exposed ld-addr-op
; V03 loc2 [V03,T02] ( 5, 15 ) int -> rax
; V04 OutArgs [V04 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace"
; V05 tmp1 [V05,T06] ( 3, 4.20) long -> rcx "impRuntimeLookup slot"
; V06 tmp2 [V06,T07] ( 2, 4 ) ref -> rdi class-hnd "impAppendStmt"
; V07 tmp3 [V07,T05] ( 3, 4.80) long -> rdx "impRuntimeLookup indirectOffset"
; V08 tmp4 [V08,T08] ( 3, 3 ) long -> rdx "spilling Runtime Lookup tree"
;* V09 tmp5 [V09,T01] ( 0, 0 ) long -> zero-ref "impRuntimeLookup slot"
; V10 tmp6 [V10,T00] ( 2, 32 ) long -> rdx "impRuntimeLookup indirectOffset"
;* V11 tmp7 [V11 ] ( 0, 0 ) long -> zero-ref "spilling Runtime Lookup tree"
; V12 tmp8 [V12 ] ( 2, 3 ) byref -> [rsp+0x28] do-not-enreg[X] addr-exposed V02._pointer(offs=0x00) P-DEP "field V02._pointer (fldOffset=0x0)"
; V13 tmp9 [V13 ] ( 2, 9 ) int -> [rsp+0x30] do-not-enreg[X] addr-exposed V02._length(offs=0x08) P-DEP "field V02._length (fldOffset=0x8)"
; V14 cse0 [V14,T04] ( 3, 10 ) long -> rbx "CSE - aggressive"
; V15 cse1 [V15,T09] ( 3, 1.20) long -> rdx "CSE - conservative"
;
; Lcl frame size = 64
*************** Before prolog / epilog generation
G_M53660_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M53660_IG02: ; offs=000000H, size=0019H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG03: ; offs=000019H, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref
G_M53660_IG04: ; offs=00002BH, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref
G_M53660_IG05: ; offs=00003DH, size=0014H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref
G_M53660_IG06: ; offs=000051H, size=0011H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG07: ; offs=000062H, size=0007H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG08: ; offs=000069H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG09: ; offs=00006FH, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG10: ; epilog placeholder, next placeholder=<END>, BB12 [0003], epilog, extend <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000040 {rsi}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000040 {rsi}, InitByrefRegs=00000000 {}
Recording Var Locations at start of BB01
V00(rsi)
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M53660_IG01,ins#0,ofs#0) label
__prolog:
Found 4 lvMustInit int-sized stack slots, frame offsets -40 through -56
IN001d: push rdi
IN001e: push rsi
IN001f: push rbx
IN0020: sub rsp, 64
IN0021: xor rax, rax
IN0022: mov qword ptr [V02 rsp+28H], rax
IN0023: mov qword ptr [V02+0x8 rsp+30H], rax
Reporting this as generic context: referenced
IN0024: mov qword ptr [rsp+38H], rcx
*************** In genFnPrologCalleeRegArgs() for int regs
IN0025: mov rsi, rcx
*************** In genEnregisterIncomingStackArgs()
G_M53660_IG01: ; offs=000000H, funclet=00, bbWeight=1
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000040 {rsi}, gcRegByrefSetCur=00000000 {}
IN0026: add rsp, 64
IN0027: pop rbx
IN0028: pop rsi
IN0029: pop rdi
IN002a: ret
G_M53660_IG10: ; offs=000071H, funclet=00, bbWeight=1
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M53660_IG01: ; func=00, offs=000000H, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M53660_IG02: ; offs=00001BH, size=0019H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG03: ; offs=000034H, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref
G_M53660_IG04: ; offs=000046H, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref
G_M53660_IG05: ; offs=000058H, size=0014H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref
G_M53660_IG06: ; offs=00006CH, size=0011H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG07: ; offs=00007DH, size=0007H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG08: ; offs=000084H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG09: ; offs=00008AH, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
G_M53660_IG10: ; offs=00008CH, size=0008H, epilog, nogc, extend
*************** In emitJumpDistBind()
Binding: IN0006: 000000 jle L_M53660_BB04
Binding L_M53660_BB04 to G_M53660_IG04
Estimate of fwd jump [6D38934C/006]: 002E -> 0046 = 0016
Shrinking jump [6D38934C/006]
Adjusted offset of BB03 from 0034 to 0030
Binding: IN0009: 000000 je L_M53660_BB04
Binding L_M53660_BB04 to G_M53660_IG04
Estimate of fwd jump [6D389534/009]: 0037 -> 0042 = 0009
Shrinking jump [6D389534/009]
Binding: IN000a: 000000 jmp L_M53660_BB05
Binding L_M53660_BB05 to G_M53660_IG05
Estimate of fwd jump [6D38956C/010]: 0039 -> 0050 = 0015
Shrinking jump [6D38956C/010]
Adjusted offset of BB04 from 0046 to 003B
Adjusted offset of BB05 from 0058 to 004D
Binding: IN0012: 000000 jmp L_M53660_BB07
Binding L_M53660_BB07 to G_M53660_IG07
Estimate of fwd jump [6D38995C/018]: 005C -> 0072 = 0014
Shrinking jump [6D38995C/018]
Adjusted offset of BB06 from 006C to 005E
Adjusted offset of BB07 from 007D to 006F
Adjusted offset of BB08 from 0084 to 0076
Binding: IN001b: 000000 jl SHORT L_M53660_BB06
Binding L_M53660_BB06 to G_M53660_IG06
Estimate of bwd jump [6D389E64/027]: 007A -> 005E = 001E
Shrinking jump [6D389E64/027]
Adjusted offset of BB09 from 008A to 007C
Adjusted offset of BB10 from 008C to 007E
Total shrinkage = 14, min extra jump size = 4294967295
*************** Finishing PHASE Generate code
*************** Starting PHASE Emit code
Hot code size = 0x86 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0xc)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M53660_IG01: ; func=00, offs=000000H, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN001d: 000000 57 push rdi
IN001e: 000001 56 push rsi
IN001f: 000002 53 push rbx
IN0020: 000003 4883EC40 sub rsp, 64
IN0021: 000007 33C0 xor rax, rax
IN0022: 000009 4889442428 mov qword ptr [rsp+28H], rax
IN0023: 00000E 4889442430 mov qword ptr [rsp+30H], rax
IN0024: 000013 48894C2438 mov qword ptr [rsp+38H], rcx
gcrReg +[rsi]
IN0025: 000018 488BF1 mov rsi, rcx
;; bbWeight=1 PerfScore 6.75
G_M53660_IG02: ; func=00, offs=00001BH, size=0015H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref, isz
gcrReg +[rdi]
IN0001: 00001B 488B7E10 mov rdi, gword ptr [rsi+16]
IN0002: 00001F 488B0E mov rcx, qword ptr [rsi]
IN0003: 000022 488B5938 mov rbx, qword ptr [rcx+56]
IN0004: 000026 488B13 mov rdx, qword ptr [rbx]
IN0005: 000029 48837A0860 cmp qword ptr [rdx+8], 96
IN0006: 00002E 7E0B jle SHORT G_M53660_IG04
;; bbWeight=1 PerfScore 11.00
G_M53660_IG03: ; func=00, offs=000030H, size=000BH, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref, isz
IN0007: 000030 488B5260 mov rdx, qword ptr [rdx+96]
IN0008: 000034 4885D2 test rdx, rdx
IN0009: 000037 7402 je SHORT G_M53660_IG04
IN000a: 000039 EB12 jmp SHORT G_M53660_IG05
;; bbWeight=0.40 PerfScore 2.10
G_M53660_IG04: ; func=00, offs=00003BH, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref
IN000b: 00003B 48BAE87F33F1F97F0000 mov rdx, 0x7FF9F1337FE8
[6D38A500] ptr arg pop 0
IN000c: 000045 E87647065F call CORINFO_HELP_RUNTIMEHANDLE_CLASS
IN000d: 00004A 488BD0 mov rdx, rax
;; bbWeight=0.10 PerfScore 0.15
G_M53660_IG05: ; func=00, offs=00004DH, size=0011H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref, isz
byrReg +[rcx]
IN000e: 00004D 488D4C2428 lea rcx, bword ptr [rsp+28H]
gcrReg +[r8]
IN000f: 000052 4C8BC7 mov r8, rdi
New gcrReg live regs=00000040 {rsi}
gcrReg -[rdi]
gcrReg -[r8]
New byrReg live regs=00000000 {}
byrReg -[rcx]
[6D38A5C0] ptr arg pop 0
IN0010: 000055 E896F5FEFF call System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this
IN0011: 00005A 33C0 xor eax, eax
IN0012: 00005C EB11 jmp SHORT G_M53660_IG07
;; bbWeight=1 PerfScore 4.00
G_M53660_IG06: ; func=00, offs=00005EH, size=0011H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
byrReg +[rdx]
IN0013: 00005E 488B542428 mov rdx, bword ptr [rsp+28H]
IN0014: 000063 4863C8 movsxd rcx, eax
IN0015: 000066 4533C0 xor r8d, r8d
IN0016: 000069 4C8904CA mov qword ptr [rdx+8*rcx], r8
IN0017: 00006D FFC0 inc eax
;; bbWeight=2 PerfScore 5.50
G_M53660_IG07: ; func=00, offs=00006FH, size=0007H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
New byrReg live regs=00000000 {}
byrReg -[rdx]
IN0018: 00006F 488B13 mov rdx, qword ptr [rbx]
IN0019: 000072 488B5208 mov rdx, qword ptr [rdx+8]
;; bbWeight=8 PerfScore 32.00
G_M53660_IG08: ; func=00, offs=000076H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref, isz
IN001a: 000076 3B442430 cmp eax, dword ptr [rsp+30H]
IN001b: 00007A 7CE2 jl SHORT G_M53660_IG06
;; bbWeight=8 PerfScore 16.00
G_M53660_IG09: ; func=00, offs=00007CH, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
gcrReg +[rax]
IN001c: 00007C 33C0 xor rax, rax
;; bbWeight=1 PerfScore 0.25
G_M53660_IG10: ; func=00, offs=00007EH, size=0008H, epilog, nogc, extend
IN0026: 00007E 4883C440 add rsp, 64
IN0027: 000082 5B pop rbx
IN0028: 000083 5E pop rsi
IN0029: 000084 5F pop rdi
IN002a: 000085 C3 ret
;; bbWeight=1 PerfScore 2.75New gcrReg live regs=00000000 {}
gcrReg -[rax]
gcrReg -[rsi]
Allocated method code size = 134 , actual size = 134
; Total bytes of code 134, prolog size 27, PerfScore 93.90, (MethodHash=992e2e63) for method System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this
; ============================================================
*************** After end code gen, before unwindEmit()
G_M53660_IG01: ; func=00, offs=000000H, size=001BH, bbWeight=1 PerfScore 6.75, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN001d: 000000 push rdi
IN001e: 000001 push rsi
IN001f: 000002 push rbx
IN0020: 000003 sub rsp, 64
IN0021: 000007 xor rax, rax
IN0022: 000009 mov qword ptr [V02 rsp+28H], rax
IN0023: 00000E mov qword ptr [V02+0x8 rsp+30H], rax
IN0024: 000013 mov qword ptr [rsp+38H], rcx
IN0025: 000018 mov rsi, rcx
G_M53660_IG02: ; offs=00001BH, size=0015H, bbWeight=1 PerfScore 11.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref, isz
IN0001: 00001B mov rdi, gword ptr [rsi+16]
IN0002: 00001F mov rcx, qword ptr [rsi]
IN0003: 000022 mov rbx, qword ptr [rcx+56]
IN0004: 000026 mov rdx, qword ptr [rbx]
IN0005: 000029 cmp qword ptr [rdx+8], 96
IN0006: 00002E jle SHORT G_M53660_IG04
G_M53660_IG03: ; offs=000030H, size=000BH, bbWeight=0.40 PerfScore 2.10, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref, isz
IN0007: 000030 mov rdx, qword ptr [rdx+96]
IN0008: 000034 test rdx, rdx
IN0009: 000037 je SHORT G_M53660_IG04
IN000a: 000039 jmp SHORT G_M53660_IG05
G_M53660_IG04: ; offs=00003BH, size=0012H, bbWeight=0.10 PerfScore 0.15, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref
IN000b: 00003B mov rdx, 0x7FF9F1337FE8
IN000c: 000045 call CORINFO_HELP_RUNTIMEHANDLE_CLASS
IN000d: 00004A mov rdx, rax
G_M53660_IG05: ; offs=00004DH, size=0011H, bbWeight=1 PerfScore 4.00, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref, isz
IN000e: 00004D lea rcx, bword ptr [V02 rsp+28H]
IN000f: 000052 mov r8, rdi
IN0010: 000055 call System.Span`1[__Canon][System.__Canon]:.ctor(System.__Canon[]):this
IN0011: 00005A xor eax, eax
IN0012: 00005C jmp SHORT G_M53660_IG07
G_M53660_IG06: ; offs=00005EH, size=0011H, bbWeight=2 PerfScore 5.50, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
IN0013: 00005E mov rdx, bword ptr [V12 rsp+28H]
IN0014: 000063 movsxd rcx, eax
IN0015: 000066 xor r8d, r8d
IN0016: 000069 mov qword ptr [rdx+8*rcx], r8
IN0017: 00006D inc eax
G_M53660_IG07: ; offs=00006FH, size=0007H, bbWeight=8 PerfScore 32.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
IN0018: 00006F mov rdx, qword ptr [rbx]
IN0019: 000072 mov rdx, qword ptr [rdx+8]
G_M53660_IG08: ; offs=000076H, size=0006H, bbWeight=8 PerfScore 16.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref, isz
IN001a: 000076 cmp eax, dword ptr [V13 rsp+30H]
IN001b: 00007A jl SHORT G_M53660_IG06
G_M53660_IG09: ; offs=00007CH, size=0002H, bbWeight=1 PerfScore 0.25, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref
IN001c: 00007C xor rax, rax
G_M53660_IG10: ; offs=00007EH, size=0008H, bbWeight=1 PerfScore 2.75, epilog, nogc, extend
IN0026: 00007E add rsp, 64
IN0027: 000082 pop rbx
IN0028: 000083 pop rsi
IN0029: 000084 pop rdi
IN002a: 000085 ret
*************** Finishing PHASE Emit code
*************** Starting PHASE Emit GC+EH tables
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x000086 (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x07
CountOfUnwindCodes: 4
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x07 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 7 * 8 + 8 = 64 = 0x40
CodeOffset: 0x03 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3)
CodeOffset: 0x02 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rsi (6)
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rdi (7)
allocUnwindInfo(pHotCode=0x00007FF9F1139310, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x86, unwindSize=0xc, pUnwindBlock=0x000001626D2EDBA4, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 8
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x0000001B ( STACK_EMPTY )
IL offs 0x0015 : 0x0000005A ( STACK_EMPTY )
IL offs 0x0019 : 0x0000005E ( STACK_EMPTY )
IL offs 0x0027 : 0x0000006D ( STACK_EMPTY )
IL offs 0x002B : 0x0000006F ( STACK_EMPTY )
IL offs 0x0035 : 0x0000007C ( STACK_EMPTY )
IL offs EPILOG : 0x0000007E ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 4
*************** Variable debug info
4 live ranges
0( UNKNOWN) : From 00000000h to 0000001Bh, in rcx
3( UNKNOWN) : From 0000005Eh to 0000006Dh, in rax
3( UNKNOWN) : From 0000006Fh to 0000007Ch, in rax
0( UNKNOWN) : From 0000001Bh to 0000007Eh, in rsi
*************** In gcInfoBlockHdrSave()
Set code length to 134.
Set ReturnKind to Object.
Reporting this as generic context: referenced
Set generic instantiation context stack slot to -40, type is THIS.
Reporting this as generic context: referenced
Set prolog size 0x1b.
Set Outgoing stack arg area size to 32.
Stack slot id for offset 40 (0x28) (sp) (byref, untracked) = 0.
Reporting this as generic context: referenced
Stack slot id for offset 56 (0x38) (sp) (untracked) = 1.
Register slot id for reg rsi = 2.
Register slot id for reg rdi = 3.
Register slot id for reg rcx (byref) = 4.
Register slot id for reg r8 = 5.
Register slot id for reg rdx (byref) = 6.
Register slot id for reg rax = 7.
Set state of slot 2 at instr offset 0x1b to Live.
Set state of slot 3 at instr offset 0x1f to Live.
Set state of slot 4 at instr offset 0x52 to Live.
Set state of slot 5 at instr offset 0x55 to Live.
Set state of slot 3 at instr offset 0x5a to Dead.
Set state of slot 5 at instr offset 0x5a to Dead.
Set state of slot 4 at instr offset 0x5a to Dead.
Set state of slot 6 at instr offset 0x63 to Live.
Set state of slot 6 at instr offset 0x6f to Dead.
Set state of slot 7 at instr offset 0x7e to Live.
Set state of slot 7 at instr offset 0x86 to Dead.
Set state of slot 2 at instr offset 0x86 to Dead.
Defining interruptible range: [0x1b, 0x7e).
*************** Finishing PHASE Emit GC+EH tables
Method code size: 134
Allocations for System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this (MethodHash=992e2e63)
count: 2587, size: 169282, max = 3072
allocateMemory: 196608, nraUsed: 176488
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 6460 | 3.82%
ASTNode | 22688 | 13.40%
InstDesc | 5284 | 3.12%
ImpStack | 384 | 0.23%
BasicBlock | 6368 | 3.76%
fgArgInfo | 392 | 0.23%
fgArgInfoPtrArr | 56 | 0.03%
FlowList | 640 | 0.38%
TreeStatementList | 192 | 0.11%
SiScope | 352 | 0.21%
DominatorMemory | 624 | 0.37%
LSRA | 3888 | 2.30%
LSRA_Interval | 2400 | 1.42%
LSRA_RefPosition | 7168 | 4.23%
Reachability | 16 | 0.01%
SSA | 3056 | 1.81%
ValueNumber | 17397 | 10.28%
LvaTable | 2040 | 1.21%
UnwindInfo | 0 | 0.00%
hashBv | 568 | 0.34%
bitset | 440 | 0.26%
FixedBitVect | 36 | 0.02%
Generic | 3064 | 1.81%
LocalAddressVisitor | 512 | 0.30%
FieldSeqStore | 176 | 0.10%
ZeroOffsetFieldMap | 120 | 0.07%
ArrayInfoMap | 40 | 0.02%
MemoryPhiArg | 32 | 0.02%
CSE | 2752 | 1.63%
GC | 3016 | 1.78%
CorTailCallInfo | 0 | 0.00%
Inlining | 1632 | 0.96%
ArrayStack | 256 | 0.15%
DebugInfo | 448 | 0.26%
DebugOnly | 66909 | 39.53%
Codegen | 1176 | 0.69%
LoopOpt | 2560 | 1.51%
LoopHoist | 0 | 0.00%
Unknown | 604 | 0.36%
RangeCheck | 3648 | 2.15%
CopyProp | 1488 | 0.88%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
VariableLiveRanges | 0 | 0.00%
ClassLayout | 112 | 0.07%
TailMergeThrows | 0 | 0.00%
EarlyProp | 0 | 0.00%
ZeroInit | 288 | 0.17%
****** DONE compiling System.Collections.IndexerSet`1[__Canon][System.__Canon]:Span():System.__Canon:this
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