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tthtlc/compilation of blinky example for ICE40 HX8K example

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compilation of blinky example for ICE40 HX8K example
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compilation of blinky example for ICE40 HX8K example
Download the git repository:
https://github.com/nesl/ice40_examples
and then go to "blinky" subdirectory:
make
# if build folder doesn't exist, create it
mkdir -p ./build
# synthesize using Yosys
yosys -p "synth_ice40 -top top -blif ./build/blinky.blif" top.v
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.8+618 (git sha1 acd8bc0, clang 3.8.0-2ubuntu4 -fPIC -Os)
-- Parsing `top.v' using frontend `verilog' --
1. Executing Verilog-2005 frontend: top.v
Parsing Verilog input from `top.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.
-- Running command `synth_ice40 -top top -blif ./build/blinky.blif' --
2. Executing SYNTH_ICE40 pass.
2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_sim.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\SB_IO'.
Generating RTLIL representation for module `\SB_GB_IO'.
Generating RTLIL representation for module `\SB_GB'.
Generating RTLIL representation for module `\SB_LUT4'.
Generating RTLIL representation for module `\SB_CARRY'.
Generating RTLIL representation for module `$__ICE40_FULL_ADDER'.
Generating RTLIL representation for module `\SB_DFF'.
Generating RTLIL representation for module `\SB_DFFE'.
Generating RTLIL representation for module `\SB_DFFSR'.
Generating RTLIL representation for module `\SB_DFFR'.
Generating RTLIL representation for module `\SB_DFFSS'.
Generating RTLIL representation for module `\SB_DFFS'.
Generating RTLIL representation for module `\SB_DFFESR'.
Generating RTLIL representation for module `\SB_DFFER'.
Generating RTLIL representation for module `\SB_DFFESS'.
Generating RTLIL representation for module `\SB_DFFES'.
Generating RTLIL representation for module `\SB_DFFN'.
Generating RTLIL representation for module `\SB_DFFNE'.
Generating RTLIL representation for module `\SB_DFFNSR'.
Generating RTLIL representation for module `\SB_DFFNR'.
Generating RTLIL representation for module `\SB_DFFNSS'.
Generating RTLIL representation for module `\SB_DFFNS'.
Generating RTLIL representation for module `\SB_DFFNESR'.
Generating RTLIL representation for module `\SB_DFFNER'.
Generating RTLIL representation for module `\SB_DFFNESS'.
Generating RTLIL representation for module `\SB_DFFNES'.
Generating RTLIL representation for module `\SB_RAM40_4K'.
Generating RTLIL representation for module `\SB_RAM40_4KNR'.
Generating RTLIL representation for module `\SB_RAM40_4KNW'.
Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
Generating RTLIL representation for module `\ICESTORM_LC'.
Generating RTLIL representation for module `\SB_PLL40_CORE'.
Generating RTLIL representation for module `\SB_PLL40_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
Generating RTLIL representation for module `\SB_WARMBOOT'.
Generating RTLIL representation for module `\SB_SPRAM256KA'.
Generating RTLIL representation for module `\SB_HFOSC'.
Generating RTLIL representation for module `\SB_LFOSC'.
Generating RTLIL representation for module `\SB_RGBA_DRV'.
Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
Generating RTLIL representation for module `\SB_RGB_DRV'.
Generating RTLIL representation for module `\SB_I2C'.
Generating RTLIL representation for module `\SB_SPI'.
Generating RTLIL representation for module `\SB_LEDDA_IP'.
Generating RTLIL representation for module `\SB_FILTER_50NS'.
Generating RTLIL representation for module `\SB_IO_I3C'.
Generating RTLIL representation for module `\SB_IO_OD'.
Generating RTLIL representation for module `\SB_MAC16'.
Successfully finished Verilog frontend.
2.2. Executing HIERARCHY pass (managing design hierarchy).
2.2.1. Analyzing design hierarchy..
Top module: \top
2.2.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
2.3. Executing PROC pass (convert processes to netlists).
2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 2 assignments to connections.
2.3.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\top.$proc$top.v:16$3'.
Set init value: \counter = 0
2.3.5. Executing PROC_ARST pass (detect async resets in processes).
2.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\top.$proc$top.v:16$3'.
Creating decoders for process `\top.$proc$top.v:29$1'.
2.3.7. Executing PROC_DLATCH pass (convert process syncs to latches).
2.3.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\top.\counter' using process `\top.$proc$top.v:29$1'.
created $dff cell `$procdff$12' with positive edge clock.
2.3.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$proc$top.v:16$3'.
Removing empty process `top.$proc$top.v:29$1'.
Cleaned up 0 empty switches.
2.4. Executing FLATTEN pass (flatten design).
No more expansions possible.
2.5. Executing TRIBUF pass.
2.6. Executing DEMINOUT pass (demote inout ports to input or output).
2.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>
2.9. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
2.10. Executing OPT pass (performing simple optimizations).
2.10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.10.6. Executing OPT_RMDFF pass (remove dff with constant values).
2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.10.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.10.9. Finished OPT passes. (There is nothing left to do.)
2.11. Executing WREDUCE pass (reducing word size of cells).
Removed top 31 bits (of 32) from port B of cell top.$add$top.v:30$2 ($add).
2.12. Executing PEEPOPT pass (run peephole optimizers).
2.13. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.14. Executing SHARE pass (SAT-based resource sharing).
2.15. Executing TECHMAP pass (map to technology primitives).
2.15.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
2.15.2. Continuing TECHMAP pass.
No more expansions possible.
2.16. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.18. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
creating $macc model for $add$top.v:30$2 ($add).
creating $alu model for $macc $add$top.v:30$2.
creating $alu cell for $add$top.v:30$2: $auto$alumacc.cc:474:replace_alu$13
created 1 $alu and 0 $macc cells.
2.19. Executing OPT pass (performing simple optimizations).
2.19.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.19.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.19.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.19.6. Executing OPT_RMDFF pass (remove dff with constant values).
2.19.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.19.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.19.9. Finished OPT passes. (There is nothing left to do.)
2.20. Executing FSM pass (extract and optimize FSM).
2.20.1. Executing FSM_DETECT pass (finding FSMs in design).
2.20.2. Executing FSM_EXTRACT pass (extracting FSM from design).
2.20.3. Executing FSM_OPT pass (simple optimizations of FSMs).
2.20.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.20.5. Executing FSM_OPT pass (simple optimizations of FSMs).
2.20.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
2.20.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
2.20.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
2.21. Executing OPT pass (performing simple optimizations).
2.21.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.21.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.21.3. Executing OPT_RMDFF pass (remove dff with constant values).
2.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.21.5. Finished fast OPT passes.
2.22. Executing MEMORY pass.
2.22.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
2.22.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.22.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
2.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.22.5. Executing MEMORY_COLLECT pass (generating $mem cells).
2.23. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
2.25. Executing TECHMAP pass (map to technology primitives).
2.25.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/brams_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_RAM4K'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'.
Successfully finished Verilog frontend.
2.25.2. Continuing TECHMAP pass.
No more expansions possible.
2.26. Executing ICE40_BRAMINIT pass.
2.27. Executing OPT pass (performing simple optimizations).
2.27.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.27.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.27.3. Executing OPT_RMDFF pass (remove dff with constant values).
2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.27.5. Finished fast OPT passes.
2.28. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
2.29. Executing OPT pass (performing simple optimizations).
2.29.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.29.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.29.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.29.6. Executing OPT_RMDFF pass (remove dff with constant values).
2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.29.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.29.9. Finished OPT passes. (There is nothing left to do.)
2.30. Executing TECHMAP pass (map to technology primitives).
2.30.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
2.30.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.
2.30.3. Continuing TECHMAP pass.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $pos.
No more expansions possible.
<suppressed ~21 debug messages>
2.31. Executing ICE40_OPT pass (performing simple optimizations).
2.31.1. Running ICE40 specific optimizations.
2.31.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~63 debug messages>
2.31.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.31.4. Executing OPT_RMDFF pass (remove dff with constant values).
2.31.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 52 unused cells and 17 unused wires.
<suppressed ~53 debug messages>
2.31.6. Rerunning OPT passes. (Removed registers in this run.)
2.31.7. Running ICE40 specific optimizations.
Optimized away SB_CARRY cell top.$auto$alumacc.cc:474:replace_alu$13.slice[0].carry: CO=\counter [0]
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[1].adder back to logic.
2.31.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~20 debug messages>
2.31.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.31.10. Executing OPT_RMDFF pass (remove dff with constant values).
2.31.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
<suppressed ~1 debug messages>
2.31.12. Rerunning OPT passes. (Removed registers in this run.)
2.31.13. Running ICE40 specific optimizations.
2.31.14. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.31.15. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.31.16. Executing OPT_RMDFF pass (remove dff with constant values).
2.31.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.31.18. Finished OPT passes. (There is nothing left to do.)
2.32. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).
2.33. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
Selected cell types for direct conversion:
$_DFF_PP1_ -> $__DFFE_PP1
$_DFF_PP0_ -> $__DFFE_PP0
$_DFF_PN1_ -> $__DFFE_PN1
$_DFF_PN0_ -> $__DFFE_PN0
$_DFF_NP1_ -> $__DFFE_NP1
$_DFF_NP0_ -> $__DFFE_NP0
$_DFF_NN1_ -> $__DFFE_NN1
$_DFF_NN0_ -> $__DFFE_NN0
$_DFF_N_ -> $_DFFE_NP_
$_DFF_P_ -> $_DFFE_PP_
Transforming FF to FF+Enable cells in module top:
converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$70 to $_DFFE_PP_ for $0\counter[31:0] [1] -> \counter [1].
2.34. Executing TECHMAP pass (map to technology primitives).
2.34.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Successfully finished Verilog frontend.
2.34.2. Continuing TECHMAP pass.
Using template \$_DFF_P_ for cells of type $_DFF_P_.
Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
No more expansions possible.
<suppressed ~26 debug messages>
2.35. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>
2.36. Executing SIMPLEMAP pass (map simple cells to gate primitives).
2.37. Executing ICE40_FFINIT pass (implement FF init values).
Handling FF init values in top.
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$76 (SB_DFF): \counter [7] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$69 (SB_DFF): \counter [0] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$70 (SB_DFFE): \counter [1] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$71 (SB_DFF): \counter [2] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$72 (SB_DFF): \counter [3] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$73 (SB_DFF): \counter [4] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$74 (SB_DFF): \counter [5] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$94 (SB_DFF): \counter [25] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$75 (SB_DFF): \counter [6] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$77 (SB_DFF): \counter [8] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$78 (SB_DFF): \counter [9] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$79 (SB_DFF): \counter [10] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$80 (SB_DFF): \counter [11] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$81 (SB_DFF): \counter [12] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$82 (SB_DFF): \counter [13] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$83 (SB_DFF): \counter [14] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$84 (SB_DFF): \counter [15] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$85 (SB_DFF): \counter [16] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$86 (SB_DFF): \counter [17] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$87 (SB_DFF): \counter [18] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$88 (SB_DFF): \counter [19] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$89 (SB_DFF): \counter [20] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$90 (SB_DFF): \counter [21] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$91 (SB_DFF): \counter [22] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$92 (SB_DFF): \counter [23] = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$93 (SB_DFF): \counter [24] = 0
2.38. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).
Merging set/reset $_MUX_ cells into SB_FFs in top.
2.39. Executing ICE40_OPT pass (performing simple optimizations).
2.39.1. Running ICE40 specific optimizations.
2.39.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
2.39.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.39.4. Executing OPT_RMDFF pass (remove dff with constant values).
2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 82 unused wires.
<suppressed ~1 debug messages>
2.39.6. Finished OPT passes. (There is nothing left to do.)
2.40. Executing TECHMAP pass (map to technology primitives).
2.40.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.
2.40.2. Continuing TECHMAP pass.
No more expansions possible.
2.41. Executing ABC pass (technology mapping using ABC).
2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs.
2.41.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
ABC: + strash
ABC: + ifraig
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + retime
ABC: + strash
ABC: + dch -f
ABC: + if
ABC: + mfs2
ABC: + lutpack -S 1
ABC: + dress
ABC: Total number of equiv classes = 2.
ABC: Participating nodes from both networks = 2.
ABC: Participating nodes from the first network = 1. ( 50.00 % of nodes)
ABC: Participating nodes from the second network = 1. ( 50.00 % of nodes)
ABC: Node pairs (any polarity) = 1. ( 50.00 % of names can be moved)
ABC: Node pairs (same polarity) = 1. ( 50.00 % of names can be moved)
ABC: Total runtime = 0.00 sec
ABC: + write_blif <abc-temp-dir>/output.blif
2.41.1.2. Re-integrating ABC results.
ABC RESULTS: $lut cells: 1
ABC RESULTS: internal signals: 0
ABC RESULTS: input signals: 1
ABC RESULTS: output signals: 1
Removing temp directory.
Removed 0 unused cells and 2 unused wires.
2.42. Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[0].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[10].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[11].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[12].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[13].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[14].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[15].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[16].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[17].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[18].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[19].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[20].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[21].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[22].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[23].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[24].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[25].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[2].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[3].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[4].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[5].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[6].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[7].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[8].adder to $lut.
Mapping SB_LUT4 cell top.$auto$alumacc.cc:474:replace_alu$13.slice[9].adder to $lut.
2.42.1. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Number of LUTs: 26
1-LUT 2
2-LUT 1
3-LUT 23
with \SB_CARRY 23
Eliminating LUTs.
Number of LUTs: 26
1-LUT 2
2-LUT 1
3-LUT 23
with \SB_CARRY 23
Combining LUTs.
Number of LUTs: 26
1-LUT 2
2-LUT 1
3-LUT 23
with \SB_CARRY 23
Eliminated 0 LUTs.
Combined 0 LUTs.
<suppressed ~75 debug messages>
2.42.2. Executing TECHMAP pass (map to technology primitives).
2.42.2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
2.42.2.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
No more expansions possible.
<suppressed ~48 debug messages>
Removed 0 unused cells and 52 unused wires.
2.42.3. Executing HIERARCHY pass (managing design hierarchy).
2.42.3.1. Analyzing design hierarchy..
Top module: \top
2.42.3.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
2.42.4. Printing statistics.
=== top ===
Number of wires: 12
Number of wire bits: 105
Number of public wires: 10
Number of public wire bits: 41
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 76
SB_CARRY 24
SB_DFF 25
SB_DFFE 1
SB_LUT4 26
2.42.5. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
2.42.6. Executing BLIF backend.
End of script. Logfile hash: 40cf75b657
CPU: user 0.21s system 0.02s, MEM: 46.45 MB total, 15.89 MB resident
Yosys 0.8+618 (git sha1 acd8bc0, clang 3.8.0-2ubuntu4 -fPIC -Os)
Time spent: 50% 10x read_verilog (0 sec), 12% 1x share (0 sec), ...
# Place and route using arachne
arachne-pnr -d 8k -P ct256 -o ./build/blinky.asc -p pinmap.pcf ./build/blinky.blif
seed: 1
device: 8k
read_chipdb +/share/arachne-pnr/chipdb-8k.bin...
supported packages: bg121, bg121:4k, cb132, cb132:4k, cm121, cm121:4k, cm225, cm225:4k, cm81, cm81:4k, ct256, tq144:4k
read_blif ./build/blinky.blif...
prune...
read_pcf pinmap.pcf...
instantiate_io...
pack...
After packing:
IOs 9 / 206
GBs 0 / 8
GB_IOs 0 / 8
LCs 28 / 7680
DFF 3
CARRY 2
CARRY, DFF 23
DFF PASS 0
CARRY PASS 1
BRAMs 0 / 32
WARMBOOTs 0 / 1
PLLs 0 / 2
place_constraints...
promote_globals...
promoted hwclk$2, 26 / 26
promoted 1 nets
1 clk
1 globals
1 clk
realize_constants...
place...
initial wire length = 408
at iteration #50: temp = 21.4018, wire length = 229
at iteration #100: temp = 8.47754, wire length = 79
at iteration #150: temp = 1.58422, wire length = 41
final wire length = 33
After placement:
PIOs 7 / 206
PLBs 6 / 960
BRAMs 0 / 32
place time 0.02s
route...
pass 1, 0 shared.
After routing:
span_4 16 / 29696
span_12 1 / 5632
route time 0.03s
write_txt ./build/blinky.asc...
# Convert to bitstream using IcePack
icepack ./build/blinky.asc ./build/blinky.bin
=========================================================================
make burn
iceprog ./build/blinky.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0xBA 0x16 0x10 0x00 0x00 0x23 0x71 0x32 0x74 0x15 0x00 0x80 0x00 0x46 0x18 0x05 0x17 0xAB 0xBD
file size: 135100
erase 64kB sector at 0x000000..
erase 64kB sector at 0x010000..
erase 64kB sector at 0x020000..
programming..
reading..
VERIFY OK
cdone: high
Bye.
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