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@ttsiodras
Created July 18, 2022 20:17
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uiCA experiments on my mandelbrot
ttsiod@mbair ~/Github/uiCA
(master)*$ as mandel.asm -o mandel.o
ttsiod@mbair ~/Github/uiCA
(master)*$ ./uiCA.py mandel.o
Throughput (in cycles per iteration): 12.00 - 15.07
- 12.00 on BDW
- 14.00 on HSW, IVB, SNB
- 14.50 on CLX
- 14.64 on CFL, KBL, SKL, SKX
- 15.07 on ICL, RKL, TGL
ttsiod@mbair ~/Github/uiCA
(master)*$ grep test mandel.asm
test eax,eax
test eax,eax
test eax,eax
ttsiod@mbair ~/Github/uiCA
(master)*$ sed -i 's/test eax,eax/or eax,eax/' mandel.asm
ttsiod@mbair ~/Github/uiCA
(master)*$ as mandel.asm -o mandel.o
ttsiod@mbair ~/Github/uiCA
(master)*$ ./uiCA.py mandel.o
Throughput (in cycles per iteration): 12.00 - 15.07
- 12.00 on BDW
- 14.00 on HSW, IVB
- 14.47 on CFL, KBL, SKL, SKX
- 14.93 on ICL, RKL, TGL
- 15.00 on SNB
- 15.07 on CLX
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