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ttys3/cpu_caches.csv

Forked from teivah/cpu_caches.csv
Created May 30, 2020 03:37
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cpu_caches.csv
Cache Latency CPU cycles Size
L1 access ~1.2 ns ~4 Between 32 KB and 512 KB
L2 access ~3 ns ~10 Between 128 KB and 24 MB
L3 access ~12 ns ~40 Between 2 MB and 32 MB
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