First step is to translate Verilog into a "gate-level netlist" appropriate for an iCE40-family FPGA.
You might make a rough correlation here with compiling C code down to assembly for a family of processors.
$ yosys -ql blink_count_shift.log \
> -p 'synth_ice40 -top top -json blink_count_shift.json' blink_count_shift.v
-top specifies the top-level block to be translated.
Since blocks may embed other blocks, it's important to identify which block is top-level.
If there is a default value for this, I am unaware of it.