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Clk fix with new firmware
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| j7200-evm login: reo oot | |
| [174846.646502] audit: type=1006 audit(1707106527.116:14): pid=2336 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=3 res=1 | |
| [174846.660206] audit: type=1300 audit(1707106527.116:14): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=fffffbe01a68 a2=1 a3=0 items=0 ppid=1 pid=2336 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="(systemd)" exe="/lib/systemd/systemd" key=(null) | |
| [174846.686135] audit: type=1327 audit(1707106527.116:14): proctitle="(systemd)" | |
| [174846.693632] audit: type=1334 audit(1707106527.132:15): prog-id=13 op=LOAD | |
| [174846.701130] audit: type=1300 audit(1707106527.132:15): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=ffffc57abea0 a2=78 a3=0 items=0 ppid=1 pid=2336 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/lib/systemd/systemd" key=(null) | |
| [174846.727115] audit: type=1327 audit(1707106527.132:15): proctitle="(systemd)" | |
| [174846.734712] audit: type=1334 audit(1707106527.156:16): prog-id=13 op=UNLOAD | |
| [174846.742062] audit: type=1334 audit(1707106527.156:17): prog-id=14 op=LOAD | |
| [174846.749230] audit: type=1300 audit(1707106527.156:17): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=ffffc57abf40 a2=78 a3=0 items=0 ppid=1 pid=2336 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/lib/systemd/systemd" key=(null) | |
| [174846.774964] audit: type=1327 audit(1707106527.156:17): proctitle="(systemd)" | |
| root@j7200-evm:~# clear | |
| root@j7200-evm:~# umount /dev/mmcblk1p1 | |
| root@j7200-evm:~# cd /boot/ | |
| root@j7200-evm:/boot# clear | |
| root@j7200-evm:/boot# cat copy.sh | |
| scp udit@172.24.227.18:/home/udit/workarea/build/ti-linux-kernel/arch/arm64/boot/Image . | |
| root@j7200-evm:/boot# scp udit@172.24.227.18:/home/udit/workarea/build/ti-linux-kernel/arch/arm64/boot/Image .ernelupstream/linux-next/arch/arm64/boot/Image . | |
| udit@172.24.227.18's password: | |
| Image 0% 0 0.0KB/s --:-- ETAImage 9% 4100KB 4.0MB/s 00:09 ETAImage 16% 7196KB 3.9MB/s 00:08 ETAImage 28% 12MB 4.0MB/s 00:07 ETAImage 43% 18MB 4.2MB/s 00:05 ETAImage 60% 25MB 4.5MB/s 00:03 ETAImage 71% 30MB 4.5MB/s 00:02 ETAImage 81% 34MB 4.5MB/s 00:01 ETAImage 100% 42MB 5.2MB/s 00:08 | |
| root@j7200-evm:/boot# reboot | |
| Stopping Session c2 of User root... | |
| [ OK ] Removed slice Slice /system/modprobe. | |
| [ OK ] Stopped target Graphical Interface. | |
| [ OK ] Stopped target Multi-User System. | |
| [ OK ] Stopped target Login Prompts. | |
| [ OK ] Stopped target RPC Port Mapper. | |
| [ OK ] Stopped target Timer Units. | |
| [ OK ] Stopped Daily rotation of log files. | |
| [ OK ] Stopped Daily Cleanup of Temporary Directories. | |
| [ OK ] Stopped target System Time Set. | |
| [ OK ] Closed Process Core Dump Socket. | |
| Stopping Job spooling tools... | |
| Stopping Avahi mDNS/DNS-SD Stack... | |
| Stopping containerd container runtime... | |
| Stopping Periodic Command Scheduler... | |
| Stopping Getty on tty1... | |
| Stopping irqbalance daemon... | |
| Stopping Reboot and dump vmcore via kexec... | |
| Stopping Lighttpd Daemon... | |
| Stopping Netperf Benchmark Server... | |
| Stopping NFS status monitor for NFSv2/3 locking.... | |
| Stopping Serial Getty on ttyS2... | |
| Stopping strongSwan IPsec �Ev2 daemon using ipsec.conf... | |
| Stopping Load/Save Random Seed... | |
| Stopping TEE Supplicant... | |
| Stopping Telnet Server... | |
| [ OK ] Stopped Job spooling tools. | |
| [ OK ] Stopped Periodic Command Scheduler. | |
| [ OK ] Stopped irqbalance daemon. | |
| [ OK ] Stopped TEE Supplicant. | |
| [ OK ] Stopped Lighttpd Daemon. | |
| [ OK ] Stopped Avahi mDNS/DNS-SD Stack. | |
| [ OK ] Stopped Netperf Benchmark Server. | |
| [ OK ] Stopped NFS status monitor for NFSv2/3 locking.. | |
| [ OK ] Stopped containerd container runtime. | |
| [ OK ] Stopped Getty on tty1. | |
| [ OK ] Stopped Serial Getty on ttyS2. | |
| [ OK ] Stopped Telnet Server. | |
| [ OK ] Stopped Session c2 of User root. | |
| [ OK ] Removed slice Slice /system/getty. | |
| [ OK ] Removed slice Slice /system/serial-getty. | |
| [ OK ] Stopped target Host and Network Name Lookups. | |
| Stopping User Login Management... | |
| Stopping User Manager for UID 0... | |
| [ OK ] Stopped User Manager for UID 0. | |
| Stopping User Runtime Directory /run/user/0... | |
| [ OK ] Unmounted /run/user/0. | |
| [ OK ] Stopped User Login Management. | |
| [ OK ] Stopped User Runtime Directory /run/user/0. | |
| [ OK ] Removed slice User Slice of UID 0. | |
| Stopping Permit User Sessions... | |
| [ OK ] Stopped Permit User Sessions. | |
| [ OK ] Stopped target Network. | |
| [ OK ] Stopped target Remote File Systems. | |
| Stopping Network Name Resolution... | |
| [ OK ] Stopped Network Name Resolution. | |
| Stopping Network Configuration... | |
| [ OK ] Stopped Network Configuration. | |
| [ OK ] Stopped target Preparation for Network. | |
| [ OK ] Stopped IPv6 Packet Filtering Framework. | |
| [ OK ] Stopped IPv4 Packet Filtering Framework. | |
| [ OK ] Stopped Reboot and dump vmcore via kexec. | |
| [ OK ] Stopped strongSwan IPsec I�IKEv2 daemon using ipsec.conf. | |
| [ OK ] Stopped Load/Save Random Seed. | |
| [ OK ] Stopped target Basic System. | |
| [ OK ] Stopped target Path Units. | |
| [ OK ] Stopped Dispatch Password �ts to Console Directory Watch. | |
| [ OK ] Stopped Forward Password R�uests to Wall Directory Watch. | |
| [ OK ] Stopped target Slice Units. | |
| [ OK ] Removed slice User and Session Slice. | |
| [ OK ] Stopped target Socket Units. | |
| [ OK ] Closed Avahi mDNS/DNS-SD Stack Activation Socket. | |
| [ OK ] Closed Docker Socket for the API. | |
| [ OK ] Closed dropbear.socket. | |
| [ OK ] Closed PC/SC Smart Card Daemon Activation Socket. | |
| [ OK ] Closed Network Service Netlink Socket. | |
| [ OK ] Closed Weston socket. | |
| Stopping D-Bus System Message Bus... | |
| [ OK ] Stopped D-Bus System Message Bus. | |
| [ OK ] Closed D-Bus System Message Bus Socket. | |
| [ OK ] Stopped target System Initialization. | |
| [ OK ] Stopped Apply Kernel Variables. | |
| Stopping Network Time Synchronization... | |
| [ OK ] Stopped Network Time Synchronization. | |
| [ OK ] Stopped Create Volatile Files and Directories. | |
| [ OK ] Stopped target Local File Systems. | |
| Unmounting /media/ram... | |
| Unmounting Temporary Directory /tmp... | |
| Unmounting /var/volatile... | |
| [ OK ] Unmounted /media/ram. | |
| [ OK ] Unmounted Temporary Directory /tmp. | |
| [ OK ] Unmounted /var/volatile. | |
| [ OK ] Stopped target Preparation for Local File Systems. | |
| [ OK ] Stopped target Swaps. | |
| [ OK ] Reached target Unmount All Filesystems. | |
| [ OK ] Stopped Remount Root and Kernel File Systems. | |
| [ OK ] Stopped Create Static Device Nodes in /dev. | |
| [ OK ] Reached target System Shutdown. | |
| [ OK ] Reached target Late Shutdown Services. | |
| [ OK ] Finished System Reboot. | |
| [ OK ] Reached target System Reboot. | |
| [175009.414191] kauditd_printk_skb: 1 callbacks suppressed | |
| [175009.414202] audit: type=1334 audit(1707106689.888:19): prog-id=10 op=UNLOAD | |
| [175009.427156] audit: type=1334 audit(1707106689.888:20): prog-id=9 op=UNLOAD | |
| [175009.434166] audit: type=1334 audit(1707106689.896:21): prog-id=4 op=UNLOAD | |
| [175009.441170] audit: type=1334 audit(1707106689.896:22): prog-id=3 op=UNLOAD | |
| [175009.448146] audit: type=1334 audit(1707106689.900:23): prog-id=6 op=UNLOAD | |
| [175009.455167] audit: type=1334 audit(1707106689.900:24): prog-id=5 op=UNLOAD | |
| [175009.462191] audit: type=1334 audit(1707106689.904:25): prog-id=8 op=UNLOAD | |
| [175009.469183] audit: type=1334 audit(1707106689.904:26): prog-id=7 op=UNLOAD | |
| [175009.481617] systemd-shutdown[1]: Syncing filesystems and block devices. | |
| [175009.499564] systemd-shutdown[1]: Sending SIGTERM to remaining processes... | |
| [175009.518032] systemd-journald[152]: Received SIGTERM from PID 1 (systemd-shutdow). | |
| [175009.527361] audit: type=1335 audit(1707106690.000:27): pid=152 uid=0 auid=4294967295 tty=(none) ses=4294967295 comm="systemd-journal" exe="/lib/systemd/systemd-journald" nl-mcgrp=1 op=disconnect res=1 | |
| [175009.547192] systemd-shutdown[1]: Sending SIGKILL to remaining processes... | |
| [175009.558132] systemd-shutdown[1]: Unmounting file systems. | |
| [175009.565432] [2396]: Remounting '/' read-only with options 'n/a'. | |
| [175009.580539] EXT4-fs (mmcblk1p2): re-mounted. Quota mode: none. | |
| [175009.601662] systemd-shutdown[1]: All filesystems unmounted. | |
| [175009.607372] systemd-shutdown[1]: Deactivating swaps. | |
| [175009.612643] systemd-shutdown[1]: All swaps deactivated. | |
| [175009.618017] systemd-shutdown[1]: Detaching loop devices. | |
| [175009.625785] systemd-shutdown[1]: All loop devices detached. | |
| [175009.631461] systemd-shutdown[1]: Stopping MD devices. | |
| [175009.636779] systemd-shutdown[1]: All MD devices stopped. | |
| [175009.642176] systemd-shutdown[1]: Detaching DM devices. | |
| [175009.647613] systemd-shutdown[1]: All DM devices detached. | |
| [175009.653169] systemd-shutdown[1]: All filesystems, swaps, loop devices, MD devices and DM devices detached. | |
| [175009.673465] systemd-shutdown[1]: Syncing filesystems and block devices. | |
| [175009.680401] systemd-shutdown[1]: Rebooting. | |
| [175009.684759] kvm: exiting hardware virtualization | |
| [175009.753437] reboot: Restarting system | |
| U-Boot SPL 2023.04-dirty (Jan 31 2024 - 23:05:06 +0530) | |
| SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| AVS finally voltage is 800000 | |
| Trying to boot from MMC2 | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Loading Environment from nowhere... OK | |
| Starting ATF on ARM64 core... | |
| NOTICE: BL31: v2.8(release):v2.8-226-g2fcd408bb3-dirty | |
| NOTICE: BL31: Built : 00:42:57, Jan 13 2023 | |
| I/TC: | |
| I/TC: OP-TEE version: 3.20.0 (gcc version 11.3.0 (GCC)) #1 Fri Jan 20 15:42:54 UTC 2023 aarch64 | |
| I/TC: WARNING: This OP-TEE configuration might be insecure! | |
| I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html | |
| I/TC: Primary CPU initializing | |
| I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| I/TC: HUK Initialized | |
| I/TC: Activated SA2UL device | |
| I/TC: Fixing SA2UL firewall owner for GP device | |
| I/TC: Enabled firewalls for SA2UL TRNG device | |
| I/TC: SA2UL TRNG initialized | |
| I/TC: SA2UL Drivers initialized | |
| I/TC: Primary CPU switching to normal world boot | |
| U-Boot SPL 2023.04-dirty (Jan 31 2024 - 23:05:14 +0530) | |
| SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| Detected: J7X-BASE-CPB rev E3 | |
| Detected: J7X-VSC8514-ETH rev E2 | |
| Trying to boot from MMC2 | |
| am654_sdhci mmc@4fb0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| U-Boot 2023.04-dirty (Jan 31 2024 - 23:05:14 +0530) | |
| SoC: J7200 SR2.0 GP | |
| Model: Texas Instruments K3 J7200 SoC | |
| Board: J7200X-PM2-SOM rev E7 | |
| DRAM: 4 GiB | |
| Core: 85 devices, 32 uclasses, devicetree: separate | |
| Flash: 0 Bytes | |
| MMC: mmc@4f80000: 0, mmc@4fb0000: 1 | |
| Loading Environment from nowhere... OK | |
| In: serial@2800000 | |
| Out: serial@2800000 | |
| Err: serial@2800000 | |
| am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000 | |
| Detected: J7X-BASE-CPB rev E3 | |
| Detected: J7X-VSC8514-ETH rev E2 | |
| Net: eth0: ethernet@46000000port@1 | |
| Hit any key to stop autoboot: 2 1 0 | |
| switch to partitions #0, OK | |
| mmc1 is current device | |
| SD/MMC found on device 1 | |
| Failed to load 'boot.scr' | |
| 574 bytes read in 6 ms (92.8 KiB/s) | |
| Loaded env from uEnv.txt | |
| Importing environment from mmc1 ... | |
| gpio: pin gpio@22_17 (gpio 126) value is 1 | |
| gpio: pin gpio@22_16 (gpio 125) value is 0 | |
| k3_r5f_rproc r5f@41000000: Core 1 is already in use. No rproc commands work | |
| 64508 bytes read in 11 ms (5.6 MiB/s) | |
| Load Remote Processor 1 with data@addr=0x82000000 64508 bytes: Success! | |
| 64508 bytes read in 10 ms (6.2 MiB/s) | |
| Load Remote Processor 2 with data@addr=0x82000000 64508 bytes: Success! | |
| 64508 bytes read in 11 ms (5.6 MiB/s) | |
| Load Remote Processor 3 with data@addr=0x82000000 64508 bytes: Success! | |
| 43653632 bytes read in 460 ms (90.5 MiB/s) | |
| 59061 bytes read in 12 ms (4.7 MiB/s) | |
| Working FDT set to 88000000 | |
| ## Flattened Device Tree blob at 88000000 | |
| Booting using the fdt blob at 0x88000000 | |
| Working FDT set to 88000000 | |
| Loading Device Tree to 000000008feee000, end 000000008fffffff ... OK | |
| Working FDT set to 8feee000 | |
| Starting kernel ... | |
| [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080] | |
| [ 0.000000] Linux version 6.8.0-rc2-next-20240202 (udit@udit-HP-Z2-Tower-G9-Workstation-Desktop-PC) (aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 11.3.Rel1) 11.3.1 20220712, GNU ld (Arm GNU Toolchain 11.3.Rel1) 2.38.20220708) #1 SMP PREEMPT Mon Feb 5 09:47:43 IST 2024 | |
| [ 0.000000] KASLR disabled due to lack of seed | |
| [ 0.000000] Machine model: Texas Instruments J7200 EVM | |
| [ 0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '') | |
| [ 0.000000] printk: legacy bootconsole [ns16550a0] enabled | |
| [ 0.000000] efi: UEFI not found. | |
| [ 0.000000] OF: reserved mem: 0x000000009e800000..0x000000009fffffff (24576 KiB) nomap non-reusable optee@9e800000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a0000000..0x00000000a00fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a0000000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a0100000..0x00000000a0ffffff (15360 KiB) nomap non-reusable r5f-memory@a0100000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a1000000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a1000000..0x00000000a10fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a1000000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-memory@a1100000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a1100000..0x00000000a1ffffff (15360 KiB) nomap non-reusable r5f-memory@a1100000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a2000000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a2000000..0x00000000a20fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a2000000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 15 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-memory@a2100000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a2100000..0x00000000a2ffffff (15360 KiB) nomap non-reusable r5f-memory@a2100000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a3000000, size 1 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a3000000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a3000000..0x00000000a30fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a3000000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a3100000, size 15 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-memory@a3100000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a3100000..0x00000000a3ffffff (15360 KiB) nomap non-reusable r5f-memory@a3100000 | |
| [ 0.000000] OF: reserved mem: 0x00000000a4000000..0x00000000a47fffff (8192 KiB) nomap non-reusable ipc-memories@a4000000 | |
| [ 0.000000] NUMA: No NUMA configuration found | |
| [ 0.000000] NUMA: Faking a node at [mem 0x0000000080000000-0x00000008ffffffff] | |
| [ 0.000000] NUMA: NODE_DATA [mem 0x8ff7e49c0-0x8ff7e6fff] | |
| [ 0.000000] Zone ranges: | |
| [ 0.000000] DMA [mem 0x0000000080000000-0x00000000ffffffff] | |
| [ 0.000000] DMA32 empty | |
| [ 0.000000] Normal [mem 0x0000000100000000-0x00000008ffffffff] | |
| [ 0.000000] Movable zone start for each node | |
| [ 0.000000] Early memory node ranges | |
| [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009e7fffff] | |
| [ 0.000000] node 0: [mem 0x000000009e800000-0x00000000a47fffff] | |
| [ 0.000000] node 0: [mem 0x00000000a4800000-0x00000000ffffffff] | |
| [ 0.000000] node 0: [mem 0x0000000880000000-0x00000008ffffffff] | |
| [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff] | |
| [ 0.000000] cma: Reserved 32 MiB at 0x00000000fe000000 on node -1 | |
| [ 0.000000] psci: probing for conduit method from DT. | |
| [ 0.000000] psci: PSCIv1.1 detected in firmware. | |
| [ 0.000000] psci: Using standard PSCI v0.2 function IDs | |
| [ 0.000000] psci: Trusted OS migration not required | |
| [ 0.000000] psci: SMC Calling Convention v1.2 | |
| [ 0.000000] percpu: Embedded 22 pages/cpu s51368 r8192 d30552 u90112 | |
| [ 0.000000] Detected PIPT I-cache on CPU0 | |
| [ 0.000000] CPU features: detected: GIC system register CPU interface | |
| [ 0.000000] CPU features: detected: Spectre-v3a | |
| [ 0.000000] CPU features: detected: Spectre-BHB | |
| [ 0.000000] CPU features: detected: ARM erratum 1742098 | |
| [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923 | |
| [ 0.000000] alternatives: applying boot alternatives | |
| [ 0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 root=PARTUUID=aa7aea62-02 rw rootfstype=ext4 rootwait | |
| [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) | |
| [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) | |
| [ 0.000000] Fallback order for Node 0: 0 | |
| [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1032192 | |
| [ 0.000000] Policy zone: Normal | |
| [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off | |
| [ 0.000000] software IO TLB: area num 2. | |
| [ 0.000000] software IO TLB: mapped [mem 0x00000000fa000000-0x00000000fe000000] (64MB) | |
| [ 0.000000] Memory: 3873444K/4194304K available (16768K kernel code, 4678K rwdata, 11172K rodata, 9856K init, 608K bss, 288092K reserved, 32768K cma-reserved) | |
| [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 | |
| [ 0.000000] rcu: Preemptible hierarchical RCU implementation. | |
| [ 0.000000] rcu: RCU event tracing is enabled. | |
| [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2. | |
| [ 0.000000] Trampoline variant of Tasks RCU enabled. | |
| [ 0.000000] Tracing variant of Tasks RCU enabled. | |
| [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. | |
| [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 | |
| [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 | |
| [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode | |
| [ 0.000000] GICv3: 960 SPIs implemented | |
| [ 0.000000] GICv3: 0 Extended SPIs implemented | |
| [ 0.000000] Root IRQ handler: gic_handle_irq | |
| [ 0.000000] GICv3: GICv3 features: 16 PPIs | |
| [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000 | |
| [ 0.000000] ITS [mem 0x01820000-0x0182ffff] | |
| [ 0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS | |
| [ 0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19 | |
| [ 0.000000] ITS@0x0000000001820000: allocated 524288 Devices @880800000 (flat, esz 8, psz 64K, shr 0) | |
| [ 0.000000] ITS: using cache flushing for cmd queue | |
| [ 0.000000] GICv3: using LPI property table @0x0000000880040000 | |
| [ 0.000000] GIC: using cache flushing for LPI property table | |
| [ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000880050000 | |
| [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. | |
| [ 0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys). | |
| [ 0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns | |
| [ 0.000000] sched_clock: 58 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns | |
| [ 0.008701] Console: colour dummy device 80x25 | |
| [ 0.013286] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000) | |
| [ 0.023958] pid_max: default: 32768 minimum: 301 | |
| [ 0.028704] LSM: initializing lsm=capability,integrity | |
| [ 0.034013] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) | |
| [ 0.041591] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) | |
| [ 0.050090] cacheinfo: Unable to detect cache hierarchy for CPU 0 | |
| [ 0.056771] RCU Tasks: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1. | |
| [ 0.064030] RCU Tasks Trace: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1. | |
| [ 0.071906] rcu: Hierarchical SRCU implementation. | |
| [ 0.076806] rcu: Max phase no-delay instances is 1000. | |
| [ 0.082318] Platform MSI: msi-controller@1820000 domain created | |
| [ 0.088474] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created | |
| [ 0.097779] fsl-mc MSI: msi-controller@1820000 domain created | |
| [ 0.104434] EFI services will not be available. | |
| [ 0.109170] smp: Bringing up secondary CPUs ... | |
| I/TC: Secondary CPU 1 initializing | |
| I/TC: Secondary CPU 1 switching to normal world boot | |
| [ 0.122314] Detected PIPT I-cache on CPU1 | |
| [ 0.122343] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000 | |
| [ 0.122357] GICv3: CPU1: using allocated LPI pending table @0x0000000880060000 | |
| [ 0.122393] CPU1: Booted secondary processor 0x0000000001 [0x411fd080] | |
| [ 0.122452] smp: Brought up 1 node, 2 CPUs | |
| [ 0.151803] SMP: Total of 2 processors activated. | |
| [ 0.156606] CPU: All CPU(s) started at EL2 | |
| [ 0.160808] CPU features: detected: 32-bit EL0 Support | |
| [ 0.166057] CPU features: detected: 32-bit EL1 Support | |
| [ 0.171305] CPU features: detected: CRC32 instructions | |
| [ 0.176570] alternatives: applying system-wide alternatives | |
| [ 0.183493] devtmpfs: initialized | |
| [ 0.191096] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns | |
| [ 0.201074] futex hash table entries: 512 (order: 3, 32768 bytes, linear) | |
| [ 0.208583] pinctrl core: initialized pinctrl subsystem | |
| [ 0.215124] DMI not present or invalid. | |
| [ 0.219487] NET: Registered PF_NETLINK/PF_ROUTE protocol family | |
| [ 0.225973] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations | |
| [ 0.233287] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations | |
| [ 0.241325] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations | |
| [ 0.249444] audit: initializing netlink subsys (disabled) | |
| [ 0.255060] audit: type=2000 audit(0.164:1): state=initialized audit_enabled=0 res=1 | |
| [ 0.255694] thermal_sys: Registered thermal governor 'step_wise' | |
| [ 0.262986] thermal_sys: Registered thermal governor 'power_allocator' | |
| [ 0.269158] cpuidle: using governor menu | |
| [ 0.279939] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. | |
| [ 0.286906] ASID allocator initialised with 65536 entries | |
| [ 0.293440] Serial: AMBA PL011 UART driver | |
| [ 0.308558] platform a40000.pinctrl: Fixed dependency cycle(s) with /bus@100000/pinctrl@a40000/mcu-cpsw-cpts | |
| [ 0.319567] Modules: 21952 pages in range for non-PLT usage | |
| [ 0.319572] Modules: 513472 pages in range for PLT usage | |
| [ 0.325731] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages | |
| [ 0.338097] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page | |
| [ 0.344500] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages | |
| [ 0.351435] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page | |
| [ 0.357837] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages | |
| [ 0.364772] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page | |
| [ 0.371173] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages | |
| [ 0.378107] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page | |
| [ 0.385465] ACPI: Interpreter disabled. | |
| [ 0.390707] k3-chipinfo 43000014.chipid: Family:J7200 rev:SR2.0 JTAGID[0x1bb6d02f] Detected | |
| [ 0.400063] iommu: Default domain type: Translated | |
| [ 0.404968] iommu: DMA domain TLB invalidation policy: strict mode | |
| [ 0.411459] SCSI subsystem initialized | |
| [ 0.415488] usbcore: registered new interface driver usbfs | |
| [ 0.421109] usbcore: registered new interface driver hub | |
| [ 0.426547] usbcore: registered new device driver usb | |
| [ 0.432247] pps_core: LinuxPPS API ver. 1 registered | |
| [ 0.437324] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> | |
| [ 0.446665] PTP clock support registered | |
| [ 0.450747] EDAC MC: Ver: 3.0.0 | |
| [ 0.454319] scmi_core: SCMI protocol bus registered | |
| [ 0.459888] FPGA manager framework | |
| [ 0.463409] Advanced Linux Sound Architecture Driver Initialized. | |
| [ 0.470128] vgaarb: loaded | |
| [ 0.473143] clocksource: Switched to clocksource arch_sys_counter | |
| [ 0.479504] VFS: Disk quotas dquot_6.6.0 | |
| [ 0.483527] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) | |
| [ 0.490652] pnp: PnP ACPI: disabled | |
| [ 0.497478] NET: Registered PF_INET protocol family | |
| [ 0.502741] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear) | |
| [ 0.511770] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear) | |
| [ 0.520546] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) | |
| [ 0.528472] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear) | |
| [ 0.536697] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear) | |
| [ 0.545436] TCP: Hash tables configured (established 32768 bind 32768) | |
| [ 0.552281] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear) | |
| [ 0.559208] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear) | |
| [ 0.566652] NET: Registered PF_UNIX/PF_LOCAL protocol family | |
| [ 0.572788] RPC: Registered named UNIX socket transport module. | |
| [ 0.578852] RPC: Registered udp transport module. | |
| [ 0.583656] RPC: Registered tcp transport module. | |
| [ 0.588459] RPC: Registered tcp-with-tls transport module. | |
| [ 0.594062] RPC: Registered tcp NFSv4.1 backchannel transport module. | |
| [ 0.600650] PCI: CLS 0 bytes, default 64 | |
| [ 0.604857] kvm [1]: IPA Size Limit: 44 bits | |
| [ 0.610122] kvm [1]: vgic-v2@6f020000 | |
| [ 0.613882] kvm [1]: GIC system register CPU interface enabled | |
| [ 0.619855] kvm [1]: vgic interrupt IRQ9 | |
| [ 0.623873] kvm [1]: Hyp mode initialized successfully | |
| [ 0.629833] Initialise system trusted keyrings | |
| [ 0.634519] workingset: timestamp_bits=42 max_order=20 bucket_order=0 | |
| [ 0.641291] squashfs: version 4.0 (2009/01/31) Phillip Lougher | |
| [ 0.647418] NFS: Registering the id_resolver key type | |
| [ 0.652597] Key type id_resolver registered | |
| [ 0.656869] Key type id_legacy registered | |
| [ 0.660975] nfs4filelayout_init: NFSv4 File Layout Driver Registering... | |
| [ 0.667824] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... | |
| [ 0.675485] 9p: Installing v9fs 9p2000 file system support | |
| [ 0.702018] Key type asymmetric registered | |
| [ 0.706204] Asymmetric key parser 'x509' registered | |
| [ 0.711212] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245) | |
| [ 0.718778] io scheduler mq-deadline registered | |
| [ 0.723405] io scheduler kyber registered | |
| [ 0.727519] io scheduler bfq registered | |
| [ 0.735757] pinctrl-single 4301c000.pinctrl: 13 pins, size 52 | |
| [ 0.741765] pinctrl-single 4301c038.pinctrl: 2 pins, size 8 | |
| [ 0.747558] pinctrl-single 4301c068.pinctrl: 59 pins, size 236 | |
| [ 0.753677] pinctrl-single 4301c174.pinctrl: 8 pins, size 32 | |
| [ 0.759613] pinctrl-single 11c000.pinctrl: 67 pins, size 268 | |
| [ 0.765555] pinctrl-single 11c11c.pinctrl: 3 pins, size 12 | |
| [ 0.771554] pinctrl-single a40000.pinctrl: 512 pins, size 2048 | |
| [ 0.781429] EINJ: ACPI disabled. | |
| [ 0.799663] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled | |
| [ 0.808121] msm_serial: driver initialized | |
| [ 0.812543] SuperH (H)SCI(F) driver initialized | |
| [ 0.817266] STM32 USART driver initialized | |
| [ 0.825478] loop: module loaded | |
| [ 0.829418] megasas: 07.727.03.00-rc1 | |
| [ 0.836748] tun: Universal TUN/TAP device driver, 1.6 | |
| [ 0.842530] thunder_xcv, ver 1.0 | |
| [ 0.845849] thunder_bgx, ver 1.0 | |
| [ 0.849152] nicpf, ver 1.0 | |
| [ 0.852566] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version | |
| [ 0.859951] hns3: Copyright (c) 2017 Huawei Corporation. | |
| [ 0.865402] hclge is initializing | |
| [ 0.868799] e1000: Intel(R) PRO/1000 Network Driver | |
| [ 0.873782] e1000: Copyright (c) 1999-2006 Intel Corporation. | |
| [ 0.879663] e1000e: Intel(R) PRO/1000 Network Driver | |
| [ 0.884732] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. | |
| [ 0.890787] igb: Intel(R) Gigabit Ethernet Network Driver | |
| [ 0.896301] igb: Copyright (c) 2007-2014 Intel Corporation. | |
| [ 0.902002] igbvf: Intel(R) Gigabit Virtual Function Network Driver | |
| [ 0.908414] igbvf: Copyright (c) 2009 - 2012 Intel Corporation. | |
| [ 0.914663] sky2: driver version 1.30 | |
| [ 0.919186] VFIO - User Level meta-driver version: 0.3 | |
| [ 0.926121] usbcore: registered new interface driver usb-storage | |
| [ 0.933929] i2c_dev: i2c /dev entries driver | |
| [ 0.942479] sdhci: Secure Digital Host Controller Interface driver | |
| [ 0.948830] sdhci: Copyright(c) Pierre Ossman | |
| [ 0.953761] Synopsys Designware Multimedia Card Interface Driver | |
| [ 0.960435] sdhci-pltfm: SDHCI platform and OF driver helper | |
| [ 0.967292] ledtrig-cpu: registered to indicate activity on CPUs | |
| [ 0.974336] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping .... | |
| [ 0.981542] usbcore: registered new interface driver usbhid | |
| [ 0.987243] usbhid: USB HID core driver | |
| [ 0.993211] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available | |
| [ 1.002823] optee: probing for conduit method. | |
| I/TC: Reserved shared memory is enabled | |
| I/TC: Dynamic shared memory is enabled | |
| I/TC: Normal World virtualization support is disabled | |
| I/TC: Asynchronous notifications are disabled | |
| [ 1.007393] optee: revision 3.20 (8e74d476) | |
| [ 1.023854] optee: dynamic shared memory is enabled | |
| [ 1.033577] random: crng init done | |
| [ 1.037113] optee: initialized driver | |
| [ 1.043127] NET: Registered PF_PACKET protocol family | |
| [ 1.048355] 9pnet: Installing 9P2000 support | |
| [ 1.052760] Key type dns_resolver registered | |
| [ 1.061190] registered taskstats version 1 | |
| [ 1.065444] Loading compiled-in X.509 certificates | |
| [ 1.087494] ti-sci 44083000.system-controller: ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| [ 1.099678] debugfs: Directory 'pd:240' with parent 'pm_genpd' already present! | |
| [ 1.111664] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=18, clk=13, ret=-19 | |
| [ 1.122359] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=18, clk=14, ret=-19 | |
| [ 1.133040] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=18, clk=15, ret=-19 | |
| [ 1.143719] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=18, clk=16, ret=-19 | |
| [ 1.157785] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=201, clk=12, ret=-19 | |
| [ 1.168546] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=201, clk=13, ret=-19 | |
| [ 1.179291] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=201, clk=14, ret=-19 | |
| [ 1.190032] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=201, clk=15, ret=-19 | |
| [ 1.207577] omap_i2c 42120000.i2c: bus 0 rev0.12 at 400 kHz | |
| [ 1.214217] pca953x 1-0021: supply vcc not found, using dummy regulator | |
| [ 1.221061] pca953x 1-0021: using no AI | |
| [ 1.245580] pca953x 1-0020: supply vcc not found, using dummy regulator | |
| [ 1.252400] pca953x 1-0020: using no AI | |
| [ 1.256955] pca953x 1-0022: supply vcc not found, using dummy regulator | |
| [ 1.263760] pca953x 1-0022: using AI | |
| [ 1.268054] omap_i2c 2000000.i2c: bus 1 rev0.12 at 400 kHz | |
| [ 1.274511] pca953x 2-0020: supply vcc not found, using dummy regulator | |
| [ 1.281360] pca953x 2-0020: using no AI | |
| [ 1.309478] omap_i2c 2010000.i2c: bus 2 rev0.12 at 400 kHz | |
| [ 1.315457] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 137 domain created | |
| [ 1.324160] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 131 domain created | |
| [ 1.333639] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 213 domain created | |
| [ 1.342360] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 209 created | |
| [ 1.353721] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235 | |
| [ 1.363622] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled | |
| [ 1.370383] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64 | |
| [ 1.381302] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[120,200] sci-dev-id:211 | |
| [ 1.391469] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled | |
| [ 1.398229] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64 | |
| [ 1.407071] 40a00000.serial: ttyS1 at MMIO 0x40a00000 (irq = 251, base_baud = 6000000) is a 8250 | |
| [ 1.417542] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 252, base_baud = 3000000) is a 8250 | |
| [ 1.426400] printk: legacy console [ttyS2] enabled | |
| [ 1.426400] printk: legacy console [ttyS2] enabled | |
| [ 1.436075] printk: legacy bootconsole [ns16550a0] disabled | |
| [ 1.436075] printk: legacy bootconsole [ns16550a0] disabled | |
| [ 1.450508] 2810000.serial: ttyS3 at MMIO 0x2810000 (irq = 253, base_baud = 3000000) is a 8250 | |
| [ 1.462643] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode | |
| [ 1.509148] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000 | |
| [ 1.519017] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867 | |
| [ 1.527294] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000 | |
| [ 1.540142] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4 | |
| [ 1.547351] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64 | |
| [ 1.560982] mmc0: CQHCI version 5.10 | |
| [ 1.575588] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8) | |
| [ 1.588909] ti-udma 31150000.dma-controller: Channels: 50 (tchan: 25, rchan: 25, gp-rflow: 8) | |
| [ 1.605408] 7 fixed-partitions partitions found on MTD device 47040000.spi.0 | |
| [ 1.609203] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit | |
| [ 1.612616] Creating 7 MTD partitions on "47040000.spi.0": | |
| [ 1.625493] 0x000000000000-0x000000100000 : "ospi.tiboot3" | |
| [ 1.632193] 0x000000100000-0x000000300000 : "ospi.tispl" | |
| [ 1.638908] 0x000000300000-0x000000700000 : "ospi.u-boot" | |
| [ 1.645526] 0x000000700000-0x000000740000 : "ospi.env" | |
| [ 1.651804] 0x000000740000-0x000000780000 : "ospi.env.backup" | |
| [ 1.658706] 0x000000800000-0x000003fc0000 : "ospi.rootfs" | |
| [ 1.665229] 0x000003fc0000-0x000004000000 : "ospi.phypattern" | |
| [ 1.675428] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode | |
| [ 1.721169] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000 | |
| [ 1.731671] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867 | |
| [ 1.740033] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000 | |
| [ 1.753002] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4 | |
| [ 1.760242] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64 | |
| [ 1.774469] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48 | |
| [ 1.781268] mmc0: Command Queue Engine enabled | |
| [ 1.785746] mmc0: new HS400 MMC card at address 0001 | |
| [ 1.787014] clk: Disabling unused clocks | |
| [ 1.791267] mmcblk0: mmc0:0001 S0J56X 14.8 GiB | |
| [ 1.795082] mmc1: CQHCI version 5.10 | |
| [ 1.804546] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=201, clk=15, ret=-19 | |
| [ 1.815100] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=201, clk=14, ret=-19 | |
| [ 1.825583] mmcblk0: p1 | |
| [ 1.828260] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=201, clk=13, ret=-19 | |
| [ 1.839051] mmcblk0boot0: mmc0:0001 S0J56X 31.5 MiB | |
| [ 1.844018] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=201, clk=12, ret=-19 | |
| [ 1.845180] mmcblk0boot1: mmc0:0001 S0J56X 31.5 MiB | |
| [ 1.854520] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit | |
| [ 1.860460] mmcblk0rpmb: mmc0:0001 S0J56X 4.00 MiB, chardev (234:0) | |
| [ 1.874564] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=18, clk=16, ret=-19 | |
| [ 1.884965] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=18, clk=15, ret=-19 | |
| [ 1.895372] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=18, clk=14, ret=-19 | |
| [ 1.905772] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=18, clk=13, ret=-19 | |
| [ 1.916734] ALSA device list: | |
| [ 1.919718] No soundcards found. | |
| [ 1.923389] Waiting for root device PARTUUID=aa7aea62-02... | |
| [ 1.948860] mmc1: new ultra high speed SDR104 SDHC card at address aaaa | |
| [ 1.956142] mmcblk1: mmc1:aaaa SC16G 14.8 GiB | |
| [ 1.965782] mmcblk1: p1 p2 | |
| [ 1.992538] EXT4-fs (mmcblk1p2): mounted filesystem 4e3e7bf3-fbb1-4666-bc99-003ef4ba86a4 r/w with ordered data mode. Quota mode: none. | |
| [ 2.004715] VFS: Mounted root (ext4 filesystem) on device 179:98. | |
| [ 2.014406] devtmpfs: mounted | |
| [ 2.026600] Freeing unused kernel memory: 9856K | |
| [ 2.031381] Run /sbin/init as init process | |
| [ 2.195571] systemd[1]: System time before build time, advancing clock. | |
| [ 2.230649] systemd[1]: systemd 250.5+ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK +XKBCOMMON +UTMP +SYSVINIT default-hierarchy=hybrid) | |
| [ 2.262364] systemd[1]: Detected architecture arm64. | |
| Welcome to Arago 2023.04! | |
| [ 2.335950] systemd[1]: Hostname set to <j7200-evm>. | |
| [ 2.459869] systemd-sysv-generator[85]: SysV service '/etc/init.d/netopeer2-server' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust. | |
| [ 2.484646] systemd-sysv-generator[85]: SysV service '/etc/init.d/sysrepo' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust. | |
| [ 2.509816] systemd-sysv-generator[85]: SysV service '/etc/init.d/thermal-zone-init' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust. | |
| [ 2.707011] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6. | |
| [ 2.715952] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6. | |
| [ 2.752924] systemd[1]: /lib/systemd/system/bt-enable.service:9: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether. | |
| [ 2.817280] systemd[1]: /etc/systemd/system/sync-clocks.service:11: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether. | |
| [ 2.894458] systemd[1]: Queued start job for default target Graphical Interface. | |
| [ 2.954308] systemd[1]: Created slice Slice /system/getty. | |
| [ OK ] Created slice Slice /system/getty. | |
| [ 2.979971] systemd[1]: Created slice Slice /system/modprobe. | |
| [ OK ] Created slice Slice /system/modprobe. | |
| [ 3.003860] systemd[1]: Created slice Slice /system/serial-getty. | |
| [ OK ] Created slice Slice /system/serial-getty. | |
| [ 3.027371] systemd[1]: Created slice User and Session Slice. | |
| [ OK ] Created slice User and Session Slice. | |
| [ 3.049523] systemd[1]: Started Dispatch Password Requests to Console Directory Watch. | |
| [ OK ] Started Dispatch Password �ts to Console Directory Watch. | |
| [ 3.073450] systemd[1]: Started Forward Password Requests to Wall Directory Watch. | |
| [ OK ] Started Forward Password R�uests to Wall Directory Watch. | |
| [ 3.097637] systemd[1]: Reached target Path Units. | |
| [ OK ] Reached target Path Units. | |
| [ 3.117312] systemd[1]: Reached target Remote File Systems. | |
| [ OK ] Reached target Remote File Systems. | |
| [ 3.137294] systemd[1]: Reached target Slice Units. | |
| [ OK ] Reached target Slice Units. | |
| [ 3.157331] systemd[1]: Reached target Swaps. | |
| [ OK ] Reached target Swaps. | |
| [ 3.214735] systemd[1]: Listening on RPCbind Server Activation Socket. | |
| [ OK ] Listening on RPCbind Server Activation Socket. | |
| [ 3.237413] systemd[1]: Reached target RPC Port Mapper. | |
| [ OK ] Reached target RPC Port Mapper. | |
| [ 3.265390] systemd[1]: Listening on Process Core Dump Socket. | |
| [ OK ] Listening on Process Core Dump Socket. | |
| [ 3.285576] systemd[1]: Listening on initctl Compatibility Named Pipe. | |
| [ OK ] Listening on initctl Compatibility Named Pipe. | |
| [ 3.309931] systemd[1]: Listening on Journal Audit Socket. | |
| [ OK ] Listening on Journal Audit Socket. | |
| [ 3.333727] systemd[1]: Listening on Journal Socket (/dev/log). | |
| [ OK ] Listening on Journal Socket (/dev/log). | |
| [ 3.357769] systemd[1]: Listening on Journal Socket. | |
| [ OK ] Listening on Journal Socket. | |
| [ 3.377927] systemd[1]: Listening on Network Service Netlink Socket. | |
| [ OK ] Listening on Network Service Netlink Socket. | |
| [ 3.401820] systemd[1]: Listening on udev Control Socket. | |
| [ OK ] Listening on udev Control Socket. | |
| [ 3.421604] systemd[1]: Listening on udev Kernel Socket. | |
| [ OK ] Listening on udev Kernel Socket. | |
| [ 3.441652] systemd[1]: Listening on User Database Manager Socket. | |
| [ OK ] Listening on User Database Manager Socket. | |
| [ 3.493622] systemd[1]: Mounting Huge Pages File System... | |
| Mounting Huge Pages File System... | |
| [ 3.518066] systemd[1]: Mounting POSIX Message Queue File System... | |
| Mounting POSIX Message Queue File System... | |
| [ 3.545952] systemd[1]: Mounting Kernel Debug File System... | |
| Mounting Kernel Debug File System... | |
| [ 3.565680] systemd[1]: Kernel Trace File System was skipped because of a failed condition check (ConditionPathExists=/sys/kernel/tracing). | |
| [ 3.597630] systemd[1]: Mounting Temporary Directory /tmp... | |
| Mounting Temporary Directory /tmp... | |
| [ 3.617791] systemd[1]: Create List of Static Device Nodes was skipped because of a failed condition check (ConditionFileNotEmpty=/lib/modules/6.8.0-rc2-next-20240202/modules.devname). | |
| [ 3.638695] systemd[1]: Starting Load Kernel Module configfs... | |
| Starting Load Kernel Module configfs... | |
| [ 3.665610] systemd[1]: Starting Load Kernel Module drm... | |
| Starting Load Kernel Module drm... | |
| [ 3.701873] systemd[1]: Starting Load Kernel Module fuse... | |
| Starting Load Kernel Module fuse... | |
| [ 3.729052] systemd[1]: Starting RPC Bind... | |
| Starting RPC Bind... | |
| [ 3.745569] systemd[1]: File System Check on Root Device was skipped because of a failed condition check (ConditionPathIsReadWrite=!/). | |
| [ 3.766028] systemd[1]: Starting Journal Service... | |
| Starting Journal Service... | |
| [ 3.805957] systemd[1]: Starting Load Kernel Modules... | |
| Starting Load Kernel Modules... | |
| [ 3.830839] systemd[1]: Starting Generate network units from Kernel command line... | |
| Starting Generate network �ts from Kernel command line... | |
| [ 3.881933] systemd[1]: Starting Remount Root and Kernel File Systems... | |
| Starting Remount Root and Kernel File Systems... | |
| [ 3.934059] systemd[1]: Starting Coldplug All udev Devices... | |
| [ 3.934057] EXT4-fs (mmcblk1p2): re-mounted 4e3e7bf3-fbb1-4666-bc99-003ef4ba86a4 r/w. Quota mode: none. | |
| Starting Coldplug All udev Devices... | |
| [ 3.974460] systemd[1]: Started RPC Bind. | |
| [ OK ] Started RPC Bind. | |
| [ 3.989863] systemd[1]: Started Journal Service. | |
| [ OK ] Started Journal Service. | |
| [ OK ] Mounted Huge Pages File System. | |
| [ OK ] Mounted POSIX Message Queue File System. | |
| [ OK ] Mounted Kernel Debug File System. | |
| [ OK ] Mounted Temporary Directory /tmp. | |
| [ OK ] Finished Load Kernel Module configfs. | |
| [ OK ] Finished Load Kernel Module drm. | |
| [ OK ] Finished Load Kernel Module fuse. | |
| [FAILED] Failed to start Load Kernel Modules. | |
| See 'systemctl status systemd-modules-load.service' for details. | |
| [ OK ] Finished Generate network units from Kernel command line. | |
| [ OK ] Finished Remount Root and Kernel File Systems. | |
| Mounting Kernel Configuration File System... | |
| Starting Flush Journal to Persistent Storage... | |
| [ 4.291585] systemd-journald[97]: Received client request to flush runtime journal. | |
| Starting Apply Kernel Variables... | |
| Starting Create Static Device Nodes in /dev... | |
| [ OK ] Mounted Kernel Configuration File System. | |
| [ OK ] Finished Flush Journal to Persistent Storage. | |
| [ OK ] Finished Apply Kernel Variables. | |
| [ OK ] Finished Create Static Device Nodes in /dev. | |
| [ OK ] Reached target Preparation for Local File Systems. | |
| Mounting /media/ram... | |
| Mounting /var/volatile... | |
| [ 4.505277] audit: type=1334 audit(1651167747.304:2): prog-id=5 op=LOAD | |
| [ 4.517259] audit: type=1334 audit(1651167747.304:3): prog-id=6 op=LOAD | |
| Starting Rule-based Manage�for Device Events and Files... | |
| [ OK ] Mounted /media/ram. | |
| [ OK ] Mounted /var/volatile. | |
| Starting Load/Save Random Seed... | |
| [ OK ] Finished Load/Save Random Seed. | |
| [ OK ] Started Rule-based Manager for Device Events and Files. | |
| [ OK ] Finished Coldplug All udev Devices. | |
| [ OK ] Found device /dev/ttyS2. | |
| [ OK ] Found device /dev/disk/by-uuid/81A5-5E73. | |
| Mounting /boot... | |
| [ 7.820788] FAT-fs (mmcblk1p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck. | |
| [ OK ] Mounted /boot. | |
| [ OK ] Reached target Local File Systems. | |
| Starting Create Volatile Files and Directories... | |
| [ OK ] Finished Create Volatile Files and Directories. | |
| Starting Network Time Synchronization... | |
| Starting Record System Boot/Shutdown in UTMP... | |
| [ OK ] Finished Record System Boot/Shutdown in UTMP. | |
| [ 8.247022] systemd-journald[97]: Oldest entry in /run/log/journal/11a1f5339a9b4ed0b552d1cfcc1c31b7/system.journal is older than the configured file retention duration (1month), suggesting rotation. | |
| [ 8.264818] systemd-journald[97]: /run/log/journal/11a1f5339a9b4ed0b552d1cfcc1c31b7/system.journal: Journal header limits reached or header out-of-date, rotating. | |
| [ OK ] Started Network Time Synchronization. | |
| [ OK ] Reached target System Initialization. | |
| [ OK ] Started Daily Cleanup of Temporary Directories. | |
| [ OK ] Reached target System Time Set. | |
| [ OK ] Started Daily rotation of log files. | |
| [ OK ] Reached target Timer Units. | |
| [ OK ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket. | |
| [ OK ] Listening on D-Bus System Message Bus Socket. | |
| Starting Docker Socket for the API... | |
| [ OK ] Listening on dropbear.socket. | |
| [ OK ] Listening on PC/SC Smart Card Daemon Activation Socket. | |
| Starting Weston socket... | |
| Starting D-Bus System Message Bus... | |
| Starting Reboot and dump vmcore via kexec... | |
| [ OK ] Listening on Docker Socket for the API. | |
| [ OK ] Listening on Weston socket. | |
| [ OK ] Finished Reboot and dump vmcore via kexec. | |
| [ OK ] Reached target Socket Units. | |
| [ OK ] Started D-Bus System Message Bus. | |
| [ OK ] Reached target Basic System. | |
| [ OK ] Started Job spooling tools. | |
| [ OK ] Started Periodic Command Scheduler. | |
| Starting Print notice about GPLv3 packages... | |
| Starting IPv6 Packet Filtering Framework... | |
| Starting IPv4 Packet Filtering Framework... | |
| [ OK ] Started irqbalance daemon. | |
| Starting Lighttpd Daemon... | |
| [ OK ] Started strongSwan IPsec I�IKEv2 daemon using ipsec.conf. | |
| [ 8.894183] audit: type=1334 audit(1707106690.212:4): prog-id=7 op=LOAD | |
| [ 8.905233] audit: type=1334 audit(1707106690.220:5): prog-id=8 op=LOAD | |
| Starting User Login Management... | |
| [ OK ] Started TEE Supplicant. | |
| Starting Telnet Server... | |
| [FAILED] Failed to start Print notice about GPLv3 packages. | |
| See 'systemctl status gplv3-notice.service' for details. | |
| [ OK ] Finished IPv6 Packet Filtering Framework. | |
| [ OK ] Finished IPv4 Packet Filtering Framework. | |
| [ OK ] Started Lighttpd Daemon. | |
| [ OK ] Finished Telnet Server. | |
| [ OK ] Reached target Preparation for Network. | |
| Starting Network Configuration... | |
| [ OK ] Started User Login Management. | |
| [ OK ] Started Network Configuration. | |
| [ 9.396003] am65-cpsw-nuss 46000000.ethernet eth0: PHY [46000f00.mdio:00] driver [TI DP83867] (irq=POLL) | |
| [ 9.405538] am65-cpsw-nuss 46000000.ethernet eth0: configuring for phy/rgmii-rxid link mode | |
| Starting Network Name Resolution... | |
| [ OK ] Started Network Name Resolution. | |
| [ OK ] Reached target Network. | |
| [ OK ] Reached target Host and Network Name Lookups. | |
| Starting Avahi mDNS/DNS-SD Stack... | |
| Starting Enable and configure wl18xx bluetooth stack... | |
| Starting containerd container runtime... | |
| [ OK ] Started Netperf Benchmark Server. | |
| [ OK ] Started NFS status monitor for NFSv2/3 locking.. | |
| Starting Permit User Sessions... | |
| [FAILED] Failed to start Enable and�figure wl18xx bluetooth stack. | |
| See 'systemctl status bt-enable.service' for details. | |
| [ OK ] Finished Permit User Sessions. | |
| [ OK ] Started Avahi mDNS/DNS-SD Stack. | |
| [ OK ] Started Getty on tty1. | |
| [ OK ] Started Serial Getty on ttyS2. | |
| [ OK ] Reached target Login Prompts. | |
| Starting Synchronize System and HW clocks... | |
| Starting Weston, a Wayland�ositor, as a system service... | |
| [FAILED] Failed to start Synchronize System and HW clocks. | |
| See 'systemctl status sync-clocks.service' for details. | |
| [ 10.256913] audit: type=1334 audit(1707106691.572:6): prog-id=9 op=LOAD | |
| [ 10.265670] audit: type=1334 audit(1707106691.584:7): prog-id=10 op=LOAD | |
| Starting User Database Manager... | |
| [ OK ] Started User Database Manager. | |
| [ OK ] Created slice User Slice of UID 1000. | |
| Starting User Runtime Directory /run/user/1000... | |
| [ OK ] Finished User Runtime Directory /run/user/1000. | |
| Starting User Manager for UID 1000... | |
| [ 10.645978] audit: type=1006 audit(1707106691.964:8): pid=482 uid=0 old-auid=4294967295 auid=1000 tty=(none) old-ses=4294967295 ses=1 res=1 | |
| [ 10.658745] audit: type=1300 audit(1707106691.964:8): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=ffffdb5a73c8 a2=4 a3=ffffba4d0020 items=0 ppid=1 pid=482 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=1 comm="(systemd)" exe="/lib/systemd/systemd" key=(null) | |
| [ 10.685898] audit: type=1327 audit(1707106691.964:8): proctitle="(systemd)" | |
| [ OK ] Started containerd container runtime. | |
| [ OK ] Started User Manager for UID 1000. | |
| [ OK ] Started Session c1 of User weston. | |
| [ 11.276820] audit: type=1006 audit(1707106692.592:9): pid=471 uid=0 old-auid=4294967295 auid=1000 tty=tty7 old-ses=4294967295 ses=2 res=1 | |
| [ 11.289842] audit: type=1300 audit(1707106692.592:9): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=ffffdb5a73c8 a2=4 a3=ffffba4d0020 items=0 ppid=1 pid=471 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=tty7 ses=2 comm="(weston)" exe="/lib/systemd/systemd" key=(null) | |
| [ 11.316176] audit: type=1327 audit(1707106692.592:9): proctitle="(weston)" | |
| [FAILED] Failed to start Weston, a �mpositor, as a system service. | |
| See 'systemctl status weston.service' for details. | |
| [DEPEND] Dependency failed for Matrix GUI. | |
| [ OK ] Reached target Multi-User System. | |
| [ OK ] Reached target Graphical Interface. | |
| Starting Record Runlevel Change in UTMP... | |
| [ OK ] Finished Record Runlevel Change in UTMP. | |
| _____ _____ _ _ | |
| | _ |___ ___ ___ ___ | _ |___ ___ |_|___ ___| |_ | |
| | | _| .'| . | . | | __| _| . | | | -_| _| _| | |
| |__|__|_| |__,|_ |___| |__| |_| |___|_| |___|___|_| | |
| |___| |___| | |
| Arago Project j7200-evm - | |
| Arago 2023.04 j7200-evm - | |
| j7200-evm login: r[ 13.514366] am65-cpsw-nuss 46000000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx | |
| oot | |
| [ 14.188930] audit: type=1006 audit(1707106695.504:10): pid=497 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=3 res=1 | |
| [ 14.201381] audit: type=1300 audit(1707106695.504:10): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=ffffdb5a73c8 a2=1 a3=ffffba4d0020 items=0 ppid=1 pid=497 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="(systemd)" exe="/lib/systemd/systemd" key=(null) | |
| [ 14.227990] audit: type=1327 audit(1707106695.504:10): proctitle="(systemd)" | |
| [ 14.235452] audit: type=1334 audit(1707106695.520:11): prog-id=11 op=LOAD | |
| [ 14.242331] audit: type=1300 audit(1707106695.520:11): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=ffffed34b3e0 a2=78 a3=0 items=0 ppid=1 pid=497 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/lib/systemd/systemd" key=(null) | |
| [ 14.267879] audit: type=1327 audit(1707106695.520:11): proctitle="(systemd)" | |
| [ 14.275088] audit: type=1334 audit(1707106695.544:12): prog-id=11 op=UNLOAD | |
| [ 14.282131] audit: type=1300 audit(1707106695.544:12): arch=c00000b7 syscall=57 success=yes exit=0 a0=8 a1=ffffba4e8020 a2=0 a3=ffffba4e87e0 items=0 ppid=1 pid=497 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/lib/systemd/systemd" key=(null) | |
| [ 14.308420] audit: type=1327 audit(1707106695.544:12): proctitle="(systemd)" | |
| [ 14.315522] audit: type=1334 audit(1707106695.544:13): prog-id=12 op=LOAD | |
| root@j7200-evm:~# k3d conf dump clocks | |
| |------------------------------------------------------------------------------| | |
| | VERSION INFO | | |
| |------------------------------------------------------------------------------| | |
| | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023) | | |
| | SoC | J7200 SR2.0 | | |
| | SYSFW | ABI: 3.1 (firmware version 0x0009 '9.1.9--v09.01.09 (Kool Koala))') | | |
| |------------------------------------------------------------------------------| | |
| |--------------------------------------------------------------------------------------------------------------------------------------------------| | |
| | Device ID | Clock ID | Clock Name | Status | Clock Frequency | | |
| |--------------------------------------------------------------------------------------------------------------------------------------------------| | |
| | 4 | 0 | DEV_A72SS0_CORE0_ARM_CLK_CLK | CLK_STATE_READY | 748800000 | | |
| | 4 | 1 | DEV_A72SS0_CORE0_MSMC_CLK | CLK_STATE_READY | 1000000000 | | |
| | 4 | 2 | DEV_A72SS0_CORE0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | |
| | 202 | 2 | DEV_A72SS0_CORE0_0_ARM_CLK_CLK | CLK_STATE_READY | 748800000 | | |
| | 203 | 0 | DEV_A72SS0_CORE0_1_ARM_CLK_CLK | CLK_STATE_READY | 748800000 | | |
| | 2 | 0 | DEV_ATL0_VBUS_CLK | CLK_STATE_READY | 250000000 | | |
| | 2 | 1 | DEV_ATL0_ATL_CLK | CLK_STATE_READY | 294912000 | | |
| | 2 | 2 | DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK | CLK_STATE_READY | 294912000 | | |
| | 2 | 3 | DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 2 | 6 | DEV_ATL0_ATL_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT7_CLK | CLK_STATE_READY | 200000000 | | |
| | 2 | 7 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 2 | 8 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 2 | 10 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_READY | 0 | | |
| | 2 | 11 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_READY | 0 | | |
| | 2 | 12 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_READY | 0 | | |
| | 2 | 13 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 1 | DEV_BOARD0_I2C1_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 2 | DEV_BOARD0_MCASP0_ACLKR_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 3 | DEV_BOARD0_SPI2_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 4 | DEV_BOARD0_I2C3_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 5 | DEV_BOARD0_OBSCLK2_IN | CLK_STATE_READY | 500000000 | | |
| | 157 | 6 | DEV_BOARD0_MCU_I3C0_SCL_IN | CLK_STATE_READY | 0 | | |
| | 157 | 7 | DEV_BOARD0_MCU_HYPERBUS0_CKN_IN | CLK_STATE_READY | 0 | | |
| | 157 | 8 | DEV_BOARD0_I2C4_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 9 | DEV_BOARD0_RGMII3_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 11 | DEV_BOARD0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 12 | DEV_BOARD0_SPI1_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 13 | DEV_BOARD0_GPMC0_CLKOUT_IN | CLK_STATE_READY | 0 | | |
| | 157 | 14 | DEV_BOARD0_MCU_OBSCLK0_IN | CLK_STATE_READY | 1000000000 | | |
| | 157 | 15 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 | CLK_STATE_READY | 1000000000 | | |
| | 157 | 16 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 157 | 31 | DEV_BOARD0_MCU_I3C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 32 | DEV_BOARD0_SPI3_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 33 | DEV_BOARD0_MCASP0_ACLKX_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 34 | DEV_BOARD0_MCASP1_ACLKR_IN | CLK_STATE_READY | 0 | | |
| | 157 | 35 | DEV_BOARD0_CLKOUT_IN | CLK_STATE_READY | 50000000 | | |
| | 157 | 36 | DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5 | CLK_STATE_READY | 50000000 | | |
| | 157 | 37 | DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10 | CLK_STATE_READY | 25000000 | | |
| | 157 | 38 | DEV_BOARD0_OBSCLK1_IN | CLK_STATE_READY | 500000000 | | |
| | 157 | 39 | DEV_BOARD0_MCU_RMII1_REF_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 40 | DEV_BOARD0_GPMC0_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 41 | DEV_BOARD0_I3C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 43 | DEV_BOARD0_TCK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 44 | DEV_BOARD0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 45 | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 46 | DEV_BOARD0_I2C6_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 48 | DEV_BOARD0_I2C5_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 49 | DEV_BOARD0_MCU_OSPI0_DQS_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 52 | DEV_BOARD0_RGMII2_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 53 | DEV_BOARD0_MCASP2_ACLKX_IN | CLK_STATE_READY | 0 | | |
| | 157 | 54 | DEV_BOARD0_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 57 | DEV_BOARD0_MCU_HYPERBUS0_CK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 59 | DEV_BOARD0_MCASP1_ACLKX_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 61 | DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 62 | DEV_BOARD0_MDIO0_MDC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 63 | DEV_BOARD0_RGMII1_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 65 | DEV_BOARD0_MMC1_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 66 | DEV_BOARD0_MCASP2_ACLKR_IN | CLK_STATE_READY | 0 | | |
| | 157 | 68 | DEV_BOARD0_WKUP_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 69 | DEV_BOARD0_MCU_CLKOUT0_IN | CLK_STATE_READY | 50000000 | | |
| | 157 | 70 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5 | CLK_STATE_READY | 50000000 | | |
| | 157 | 71 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10 | CLK_STATE_READY | 25000000 | | |
| | 157 | 73 | DEV_BOARD0_MCASP0_ACLKR_IN | CLK_STATE_READY | 0 | | |
| | 157 | 74 | DEV_BOARD0_MCU_MDIO0_MDC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 77 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 78 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 79 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 80 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 90 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 91 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 92 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 102 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 103 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 104 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 105 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 106 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 157 | 110 | DEV_BOARD0_MCU_OSPI0_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 114 | DEV_BOARD0_MCU_SYSCLKOUT0_IN | CLK_STATE_READY | 1000000000 | | |
| | 157 | 115 | DEV_BOARD0_RGMII1_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 116 | DEV_BOARD0_LED_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 118 | DEV_BOARD0_RGMII2_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 119 | DEV_BOARD0_I3C0_SCL_IN | CLK_STATE_READY | 0 | | |
| | 157 | 120 | DEV_BOARD0_MCU_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 122 | DEV_BOARD0_SPI6_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 123 | DEV_BOARD0_WKUP_I2C0_SCL_IN | CLK_STATE_READY | 0 | | |
| | 157 | 124 | DEV_BOARD0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 126 | DEV_BOARD0_MCU_SPI1_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 127 | DEV_BOARD0_MCASP0_ACLKX_IN | CLK_STATE_READY | 0 | | |
| | 157 | 128 | DEV_BOARD0_MCASP1_ACLKX_IN | CLK_STATE_READY | 0 | | |
| | 157 | 130 | DEV_BOARD0_MCU_SPI0_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 131 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 132 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 133 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 134 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 144 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 145 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 146 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 156 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 157 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 158 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 159 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 160 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 157 | 164 | DEV_BOARD0_MCU_RGMII1_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 165 | DEV_BOARD0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 166 | DEV_BOARD0_MCU_I2C1_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 168 | DEV_BOARD0_MCASP2_ACLKR_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 169 | DEV_BOARD0_MCU_I2C0_SCL_IN | CLK_STATE_READY | 0 | | |
| | 157 | 170 | DEV_BOARD0_RMII_REF_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 171 | DEV_BOARD0_GPMC0_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 172 | DEV_BOARD0_TRC_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 174 | DEV_BOARD0_MCASP2_ACLKX_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 176 | DEV_BOARD0_RGMII4_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 177 | DEV_BOARD0_SYSCLKOUT0_IN | CLK_STATE_READY | 500000000 | | |
| | 157 | 178 | DEV_BOARD0_MCASP1_ACLKR_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 179 | DEV_BOARD0_SPI5_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 180 | DEV_BOARD0_MCU_RGMII1_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 181 | DEV_BOARD0_RGMII3_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 183 | DEV_BOARD0_SPI0_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 184 | DEV_BOARD0_GPMC0_FCLK_MUX_IN | CLK_STATE_READY | 133333333 | | |
| | 157 | 185 | DEV_BOARD0_I2C2_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 186 | DEV_BOARD0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 187 | DEV_BOARD0_MCU_OSPI0_LBCLKO_IN | CLK_STATE_READY | 0 | | |
| | 157 | 189 | DEV_BOARD0_SPI7_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 190 | DEV_BOARD0_RGMII4_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 191 | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 192 | DEV_BOARD0_OBSCLK0_IN | CLK_STATE_READY | 500000000 | | |
| | 157 | 193 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK | CLK_STATE_READY | 500000000 | | |
| | 157 | 194 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK | CLK_STATE_READY | 192000000 | | |
| | 157 | 195 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK | CLK_STATE_READY | 1800000000 | | |
| | 157 | 196 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK | CLK_STATE_READY | 250000000 | | |
| | 157 | 197 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | |
| | 157 | 205 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK | CLK_STATE_READY | 666491803 | | |
| | 157 | 206 | DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 207 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK | CLK_STATE_READY | 1000000000 | | |
| | 157 | 219 | DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 157 | 220 | DEV_BOARD0_OBSCLK0_IN_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 157 | 221 | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 222 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 | CLK_STATE_READY | 500000000 | | |
| | 157 | 223 | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 224 | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 123 | 0 | DEV_CMPEVENT_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | |
| | 3 | 0 | DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | |
| | 3 | 2 | DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DBG_CLK | CLK_STATE_READY | 250000000 | | |
| | 3 | 3 | DEV_COMPUTE_CLUSTER0_TB_SOC_GIC_CLK | CLK_STATE_READY | 250000000 | | |
| | 3 | 4 | DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_DDR_PLL_CLK | CLK_STATE_READY | 666491803 | | |
| | 3 | 5 | DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_CFG_CLK | CLK_STATE_READY | 125000000 | | |
| | 3 | 6 | DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DMSC_CLK | CLK_STATE_READY | 125000000 | | |
| | 17 | 4 | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 19 | 0 | DEV_CPSW0_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | |
| | 19 | 1 | DEV_CPSW0_GMII3_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 2 | DEV_CPSW0_GMII2_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 3 | DEV_CPSW0_SERDES4_RXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 4 | DEV_CPSW0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 19 | 5 | DEV_CPSW0_PRE_RGMII4_TCLK | CLK_STATE_READY | 0 | | |
| | 19 | 6 | DEV_CPSW0_RGMII3_RXC_I | CLK_STATE_READY | 0 | | |
| | 19 | 7 | DEV_CPSW0_RGMII4_RXC_I | CLK_STATE_READY | 0 | | |
| | 19 | 8 | DEV_CPSW0_PRE_RGMII3_TCLK | CLK_STATE_READY | 0 | | |
| | 19 | 9 | DEV_CPSW0_RGMII1_RXC_I | CLK_STATE_READY | 0 | | |
| | 19 | 10 | DEV_CPSW0_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | |
| | 19 | 11 | DEV_CPSW0_GMII4_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 13 | DEV_CPSW0_GMII3_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 14 | DEV_CPSW0_SERDES4_RXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 15 | DEV_CPSW0_CPTS_RFT_CLK | CLK_STATE_READY | 200000000 | | |
| | 19 | 16 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 19 | 17 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 19 | 18 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 19 | 19 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 19 | 20 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 19 | 21 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 19 | 22 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 23 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 24 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 25 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 30 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 19 | 31 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 19 | 32 | DEV_CPSW0_SERDES1_TXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 33 | DEV_CPSW0_CPPI_CLK_CLK | CLK_STATE_READY | 320000000 | | |
| | 19 | 34 | DEV_CPSW0_SERDES2_RXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 35 | DEV_CPSW0_SERDES1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 36 | DEV_CPSW0_GMII_RFT_CLK | CLK_STATE_READY | 125000000 | | |
| | 19 | 37 | DEV_CPSW0_SERDES1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 38 | DEV_CPSW0_SERDES1_REFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 39 | DEV_CPSW0_RMII_MHZ_50_CLK | CLK_STATE_READY | 0 | | |
| | 19 | 40 | DEV_CPSW0_GMII4_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 41 | DEV_CPSW0_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | |
| | 19 | 42 | DEV_CPSW0_SERDES3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 43 | DEV_CPSW0_SERDES3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 45 | DEV_CPSW0_PRE_RGMII2_TCLK | CLK_STATE_READY | 0 | | |
| | 19 | 46 | DEV_CPSW0_SERDES2_TXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 47 | DEV_CPSW0_SERDES1_RXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 48 | DEV_CPSW0_SERDES1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 49 | DEV_CPSW0_RGMII2_RXC_I | CLK_STATE_READY | 0 | | |
| | 19 | 50 | DEV_CPSW0_SERDES2_TXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 51 | DEV_CPSW0_PRE_RGMII1_TCLK | CLK_STATE_READY | 0 | | |
| | 19 | 52 | DEV_CPSW0_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | |
| | 19 | 53 | DEV_CPSW0_GMII2_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 54 | DEV_CPSW0_SERDES4_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 55 | DEV_CPSW0_SERDES3_TXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 56 | DEV_CPSW0_SERDES2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 57 | DEV_CPSW0_GMII1_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 58 | DEV_CPSW0_SERDES4_REFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 59 | DEV_CPSW0_SERDES3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 60 | DEV_CPSW0_SERDES2_REFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 61 | DEV_CPSW0_SERDES3_REFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 62 | DEV_CPSW0_SERDES3_RXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 63 | DEV_CPSW0_GMII1_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 64 | DEV_CPSW0_SERDES2_RXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 66 | DEV_CPSW0_SERDES4_TXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 67 | DEV_CPSW0_SERDES4_TXFCLK | CLK_STATE_READY | 0 | | |
| | 26 | 0 | DEV_CPSW_TX_RGMII0_IO__RGMII4_TXC__A | CLK_STATE_READY | 0 | | |
| | 26 | 1 | DEV_CPSW_TX_RGMII0_IO__RGMII3_TXC__A | CLK_STATE_READY | 0 | | |
| | 26 | 2 | DEV_CPSW_TX_RGMII0_IO__RGMII2_TXC__A | CLK_STATE_READY | 0 | | |
| | 26 | 3 | DEV_CPSW_TX_RGMII0_IO__RGMII1_TXC__A | CLK_STATE_READY | 0 | | |
| | 26 | 4 | DEV_CPSW_TX_RGMII0_PRE_RGMII2_TCLK | CLK_STATE_READY | 0 | | |
| | 26 | 5 | DEV_CPSW_TX_RGMII0_PRE_RGMII4_TCLK | CLK_STATE_READY | 0 | | |
| | 26 | 6 | DEV_CPSW_TX_RGMII0_PRE_RGMII3_TCLK | CLK_STATE_READY | 0 | | |
| | 26 | 7 | DEV_CPSW_TX_RGMII0_PRE_RGMII1_TCLK | CLK_STATE_READY | 0 | | |
| | 20 | 0 | DEV_CPT2_AGGR0_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 21 | 0 | DEV_CPT2_AGGR1_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 23 | 0 | DEV_CPT2_AGGR2_VCLK_CLK | CLK_STATE_READY | 250000000 | | |
| | 25 | 0 | DEV_CPT2_AGGR3_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 30 | 0 | DEV_DCC0_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | |
| | 30 | 1 | DEV_DCC0_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 30 | 2 | DEV_DCC0_DCC_CLKSRC2_CLK | CLK_STATE_READY | 133333333 | | |
| | 30 | 4 | DEV_DCC0_DCC_CLKSRC0_CLK | CLK_STATE_READY | 200000000 | | |
| | 30 | 5 | DEV_DCC0_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 30 | 6 | DEV_DCC0_DCC_CLKSRC4_CLK | CLK_STATE_READY | 19200000 | | |
| | 30 | 7 | DEV_DCC0_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | |
| | 30 | 8 | DEV_DCC0_DCC_CLKSRC3_CLK | CLK_STATE_READY | 80000000 | | |
| | 30 | 9 | DEV_DCC0_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 30 | 10 | DEV_DCC0_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | |
| | 30 | 11 | DEV_DCC0_DCC_CLKSRC6_CLK | CLK_STATE_READY | 500000000 | | |
| | 30 | 12 | DEV_DCC0_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 31 | 0 | DEV_DCC1_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | |
| | 31 | 1 | DEV_DCC1_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 31 | 2 | DEV_DCC1_DCC_CLKSRC2_CLK | CLK_STATE_READY | 200000000 | | |
| | 31 | 4 | DEV_DCC1_DCC_CLKSRC0_CLK | CLK_STATE_READY | 50000000 | | |
| | 31 | 5 | DEV_DCC1_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 31 | 6 | DEV_DCC1_DCC_CLKSRC4_CLK | CLK_STATE_READY | 320000000 | | |
| | 31 | 7 | DEV_DCC1_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | |
| | 31 | 8 | DEV_DCC1_DCC_CLKSRC3_CLK | CLK_STATE_READY | 192000000 | | |
| | 31 | 9 | DEV_DCC1_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 31 | 10 | DEV_DCC1_DCC_CLKSRC5_CLK | CLK_STATE_READY | 192000000 | | |
| | 31 | 11 | DEV_DCC1_DCC_CLKSRC6_CLK | CLK_STATE_READY | 192000000 | | |
| | 31 | 12 | DEV_DCC1_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 32 | 0 | DEV_DCC2_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | |
| | 32 | 1 | DEV_DCC2_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 32 | 2 | DEV_DCC2_DCC_CLKSRC2_CLK | CLK_STATE_READY | 200000000 | | |
| | 32 | 3 | DEV_DCC2_DCC_CLKSRC7_CLK | CLK_STATE_READY | 250000000 | | |
| | 32 | 4 | DEV_DCC2_DCC_CLKSRC0_CLK | CLK_STATE_READY | 24000000 | | |
| | 32 | 5 | DEV_DCC2_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 32 | 6 | DEV_DCC2_DCC_CLKSRC4_CLK | CLK_STATE_READY | 450000000 | | |
| | 32 | 8 | DEV_DCC2_DCC_CLKSRC3_CLK | CLK_STATE_READY | 100000000 | | |
| | 32 | 9 | DEV_DCC2_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 32 | 10 | DEV_DCC2_DCC_CLKSRC5_CLK | CLK_STATE_READY | 300000000 | | |
| | 32 | 11 | DEV_DCC2_DCC_CLKSRC6_CLK | CLK_STATE_READY | 200000000 | | |
| | 32 | 12 | DEV_DCC2_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 33 | 0 | DEV_DCC3_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | |
| | 33 | 1 | DEV_DCC3_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 33 | 2 | DEV_DCC3_DCC_CLKSRC2_CLK | CLK_STATE_READY | 196608000 | | |
| | 33 | 3 | DEV_DCC3_DCC_CLKSRC7_CLK | CLK_STATE_READY | 93600000 | | |
| | 33 | 4 | DEV_DCC3_DCC_CLKSRC0_CLK | CLK_STATE_READY | 196608000 | | |
| | 33 | 5 | DEV_DCC3_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 33 | 6 | DEV_DCC3_DCC_CLKSRC4_CLK | CLK_STATE_READY | 125000000 | | |
| | 33 | 8 | DEV_DCC3_DCC_CLKSRC3_CLK | CLK_STATE_READY | 200000000 | | |
| | 33 | 9 | DEV_DCC3_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 33 | 10 | DEV_DCC3_DCC_CLKSRC5_CLK | CLK_STATE_READY | 83 | | |
| | 33 | 11 | DEV_DCC3_DCC_CLKSRC6_CLK | CLK_STATE_READY | 250000000 | | |
| | 33 | 12 | DEV_DCC3_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 34 | 0 | DEV_DCC4_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | |
| | 34 | 1 | DEV_DCC4_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 2 | DEV_DCC4_DCC_CLKSRC2_CLK | CLK_STATE_READY | 166622950 | | |
| | 34 | 3 | DEV_DCC4_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 4 | DEV_DCC4_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 5 | DEV_DCC4_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 34 | 6 | DEV_DCC4_DCC_CLKSRC4_CLK | CLK_STATE_READY | 250000000 | | |
| | 34 | 7 | DEV_DCC4_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 8 | DEV_DCC4_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 9 | DEV_DCC4_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 34 | 10 | DEV_DCC4_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 11 | DEV_DCC4_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 12 | DEV_DCC4_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 36 | 0 | DEV_DCC5_DCC_INPUT10_CLK | CLK_STATE_READY | 500000000 | | |
| | 36 | 1 | DEV_DCC5_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 4 | DEV_DCC5_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 5 | DEV_DCC5_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 36 | 6 | DEV_DCC5_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 7 | DEV_DCC5_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 9 | DEV_DCC5_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 36 | 11 | DEV_DCC5_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 12 | DEV_DCC5_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 37 | 0 | DEV_DCC6_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | |
| | 37 | 1 | DEV_DCC6_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 2 | DEV_DCC6_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 3 | DEV_DCC6_DCC_CLKSRC7_CLK | CLK_STATE_READY | 200000000 | | |
| | 37 | 4 | DEV_DCC6_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 5 | DEV_DCC6_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 37 | 6 | DEV_DCC6_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 7 | DEV_DCC6_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 8 | DEV_DCC6_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 9 | DEV_DCC6_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 37 | 10 | DEV_DCC6_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 11 | DEV_DCC6_DCC_CLKSRC6_CLK | CLK_STATE_READY | 200000000 | | |
| | 37 | 12 | DEV_DCC6_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 8 | 0 | DEV_DDR0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | |
| | 8 | 5 | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 666491803 | | |
| | 304 | 5 | DEV_DEBUGSS_WRAP0_TREXPT_CLK | CLK_STATE_READY | 300000000 | | |
| | 304 | 9 | DEV_DEBUGSS_WRAP0_CORE_CLK | CLK_STATE_READY | 125000000 | | |
| | 304 | 25 | DEV_DEBUGSS_WRAP0_JTAG_TCK | CLK_STATE_READY | 0 | | |
| | 304 | 34 | DEV_DEBUGSS_WRAP0_ATB_CLK | CLK_STATE_READY | 250000000 | | |
| | 304 | 49 | DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK | CLK_STATE_READY | 0 | | |
| | 80 | 0 | DEV_ECAP0_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 81 | 0 | DEV_ECAP1_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 82 | 0 | DEV_ECAP2_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 83 | 0 | DEV_EHRPWM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 84 | 0 | DEV_EHRPWM1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 85 | 0 | DEV_EHRPWM2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 86 | 0 | DEV_EHRPWM3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 87 | 0 | DEV_EHRPWM4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 88 | 0 | DEV_EHRPWM5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 89 | 0 | DEV_ELM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 94 | 0 | DEV_EQEP0_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 95 | 0 | DEV_EQEP1_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 96 | 0 | DEV_EQEP2_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 97 | 0 | DEV_ESM0_CLK | CLK_STATE_READY | 125000000 | | |
| | 105 | 0 | DEV_GPIO0_MMR_CLK | CLK_STATE_READY | 125000000 | | |
| | 107 | 0 | DEV_GPIO2_MMR_CLK | CLK_STATE_READY | 125000000 | | |
| | 109 | 0 | DEV_GPIO4_MMR_CLK | CLK_STATE_READY | 125000000 | | |
| | 111 | 0 | DEV_GPIO6_MMR_CLK | CLK_STATE_READY | 125000000 | | |
| | 131 | 0 | DEV_GPIOMUX_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | |
| | 115 | 0 | DEV_GPMC0_FUNC_CLK | CLK_STATE_READY | 133333333 | | |
| | 115 | 1 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK | CLK_STATE_READY | 133333333 | | |
| | 115 | 2 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6 | CLK_STATE_READY | 100000000 | | |
| | 115 | 3 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4 | CLK_STATE_READY | 150000000 | | |
| | 115 | 4 | DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4 | CLK_STATE_READY | 125000000 | | |
| | 115 | 5 | DEV_GPMC0_VBUSP_CLK | CLK_STATE_READY | 250000000 | | |
| | 115 | 6 | DEV_GPMC0_PO_GPMC_DEV_CLK | CLK_STATE_READY | 0 | | |
| | 115 | 7 | DEV_GPMC0_PI_GPMC_RET_CLK | CLK_STATE_READY | 0 | | |
| | 61 | 0 | DEV_GTC0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 61 | 1 | DEV_GTC0_GTC_CLK | CLK_STATE_READY | 200000000 | | |
| | 61 | 2 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 61 | 3 | DEV_GTC0_GTC_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 61 | 4 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 61 | 5 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 61 | 6 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 61 | 7 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 61 | 8 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 61 | 9 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 61 | 10 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 61 | 11 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 61 | 16 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 61 | 17 | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 187 | 0 | DEV_I2C0_PISCL | CLK_STATE_READY | 0 | | |
| | 187 | 1 | DEV_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 187 | 2 | DEV_I2C0_CLK | CLK_STATE_READY | 125000000 | | |
| | 187 | 3 | DEV_I2C0_PORSCL | CLK_STATE_READY | 0 | | |
| | 188 | 0 | DEV_I2C1_PISCL | CLK_STATE_READY | 0 | | |
| | 188 | 1 | DEV_I2C1_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 188 | 2 | DEV_I2C1_CLK | CLK_STATE_READY | 125000000 | | |
| | 188 | 3 | DEV_I2C1_PORSCL | CLK_STATE_READY | 0 | | |
| | 189 | 0 | DEV_I2C2_PISCL | CLK_STATE_READY | 0 | | |
| | 189 | 1 | DEV_I2C2_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 189 | 2 | DEV_I2C2_CLK | CLK_STATE_READY | 125000000 | | |
| | 189 | 3 | DEV_I2C2_PORSCL | CLK_STATE_READY | 0 | | |
| | 190 | 0 | DEV_I2C3_PISCL | CLK_STATE_READY | 0 | | |
| | 190 | 1 | DEV_I2C3_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 190 | 2 | DEV_I2C3_CLK | CLK_STATE_READY | 125000000 | | |
| | 190 | 3 | DEV_I2C3_PORSCL | CLK_STATE_READY | 0 | | |
| | 191 | 0 | DEV_I2C4_PISCL | CLK_STATE_READY | 0 | | |
| | 191 | 1 | DEV_I2C4_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 191 | 2 | DEV_I2C4_CLK | CLK_STATE_READY | 125000000 | | |
| | 191 | 3 | DEV_I2C4_PORSCL | CLK_STATE_READY | 0 | | |
| | 192 | 0 | DEV_I2C5_PISCL | CLK_STATE_READY | 0 | | |
| | 192 | 1 | DEV_I2C5_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 192 | 2 | DEV_I2C5_CLK | CLK_STATE_READY | 125000000 | | |
| | 192 | 3 | DEV_I2C5_PORSCL | CLK_STATE_READY | 0 | | |
| | 193 | 0 | DEV_I2C6_PISCL | CLK_STATE_READY | 0 | | |
| | 193 | 1 | DEV_I2C6_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 193 | 2 | DEV_I2C6_CLK | CLK_STATE_READY | 125000000 | | |
| | 193 | 3 | DEV_I2C6_PORSCL | CLK_STATE_READY | 0 | | |
| | 116 | 0 | DEV_I3C0_I3C_SCL_DI | CLK_STATE_READY | 0 | | |
| | 116 | 1 | DEV_I3C0_I3C_SCL_DO | CLK_STATE_READY | 0 | | |
| | 116 | 2 | DEV_I3C0_I3C_PCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 116 | 4 | DEV_I3C0_I3C_SCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 127 | 0 | DEV_LED0_LED_CLK | CLK_STATE_READY | 0 | | |
| | 127 | 1 | DEV_LED0_VBUS_CLK | CLK_STATE_READY | 250000000 | | |
| | 156 | 0 | DEV_MCAN0_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 156 | 2 | DEV_MCAN0_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 156 | 3 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 156 | 4 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 156 | 5 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 156 | 6 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 158 | 0 | DEV_MCAN1_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 158 | 2 | DEV_MCAN1_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 158 | 3 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 158 | 4 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 158 | 5 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 158 | 6 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 168 | 0 | DEV_MCAN10_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 168 | 2 | DEV_MCAN10_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 168 | 3 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 168 | 4 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 168 | 5 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 168 | 6 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 169 | 0 | DEV_MCAN11_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 169 | 2 | DEV_MCAN11_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 169 | 3 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 169 | 4 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 169 | 5 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 169 | 6 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 170 | 0 | DEV_MCAN12_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 170 | 2 | DEV_MCAN12_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 170 | 3 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 170 | 4 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 170 | 5 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 170 | 6 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 171 | 0 | DEV_MCAN13_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 171 | 2 | DEV_MCAN13_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 171 | 3 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 171 | 4 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 171 | 5 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 171 | 6 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 150 | 0 | DEV_MCAN14_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 150 | 2 | DEV_MCAN14_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 150 | 3 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 150 | 4 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 150 | 5 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 150 | 6 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 151 | 0 | DEV_MCAN15_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 151 | 2 | DEV_MCAN15_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 151 | 3 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 151 | 4 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 151 | 5 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 151 | 6 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 152 | 0 | DEV_MCAN16_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 152 | 2 | DEV_MCAN16_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 152 | 3 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 152 | 4 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 152 | 5 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 152 | 6 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 153 | 0 | DEV_MCAN17_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 153 | 2 | DEV_MCAN17_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 153 | 3 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 153 | 4 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 153 | 5 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 153 | 6 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 160 | 0 | DEV_MCAN2_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 160 | 2 | DEV_MCAN2_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 160 | 3 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 160 | 4 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 160 | 5 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 160 | 6 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 161 | 0 | DEV_MCAN3_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 161 | 2 | DEV_MCAN3_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 161 | 3 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 161 | 4 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 161 | 5 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 161 | 6 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 162 | 0 | DEV_MCAN4_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 162 | 2 | DEV_MCAN4_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 162 | 3 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 162 | 4 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 162 | 5 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 162 | 6 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 163 | 0 | DEV_MCAN5_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 163 | 2 | DEV_MCAN5_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 163 | 3 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 163 | 4 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 163 | 5 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 163 | 6 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 164 | 0 | DEV_MCAN6_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 164 | 2 | DEV_MCAN6_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 164 | 3 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 164 | 4 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 164 | 5 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 164 | 6 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 165 | 0 | DEV_MCAN7_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 165 | 2 | DEV_MCAN7_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 165 | 3 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 165 | 4 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 165 | 5 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 165 | 6 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 166 | 0 | DEV_MCAN8_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 166 | 2 | DEV_MCAN8_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 166 | 3 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 166 | 4 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 166 | 5 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 166 | 6 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 167 | 0 | DEV_MCAN9_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 167 | 2 | DEV_MCAN9_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 167 | 3 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 167 | 4 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 167 | 5 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 167 | 6 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 174 | 0 | DEV_MCASP0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 174 | 2 | DEV_MCASP0_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | |
| | 174 | 3 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 4 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 174 | 5 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 6 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 11 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 12 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 13 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 14 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 19 | DEV_MCASP0_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | |
| | 174 | 21 | DEV_MCASP0_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | |
| | 174 | 22 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 23 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 174 | 24 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 25 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 30 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 31 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 32 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 33 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 38 | DEV_MCASP0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 174 | 39 | DEV_MCASP0_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | |
| | 174 | 40 | DEV_MCASP0_AUX_CLK | CLK_STATE_READY | 196608000 | | |
| | 174 | 41 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | |
| | 174 | 42 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 174 | 45 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 46 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 47 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 48 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 49 | DEV_MCASP0_VBUSP_CLK | CLK_STATE_READY | 250000000 | | |
| | 174 | 50 | DEV_MCASP0_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | |
| | 174 | 51 | DEV_MCASP0_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | |
| | 175 | 0 | DEV_MCASP1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 175 | 2 | DEV_MCASP1_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | |
| | 175 | 3 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 4 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 175 | 5 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 6 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 11 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 12 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 13 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 14 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 19 | DEV_MCASP1_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | |
| | 175 | 21 | DEV_MCASP1_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | |
| | 175 | 22 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 23 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 175 | 24 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 25 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 30 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 31 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 32 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 33 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 38 | DEV_MCASP1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 175 | 39 | DEV_MCASP1_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | |
| | 175 | 40 | DEV_MCASP1_AUX_CLK | CLK_STATE_READY | 196608000 | | |
| | 175 | 41 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | |
| | 175 | 42 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 175 | 45 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 46 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 47 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 48 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 49 | DEV_MCASP1_VBUSP_CLK | CLK_STATE_READY | 250000000 | | |
| | 175 | 50 | DEV_MCASP1_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | |
| | 175 | 51 | DEV_MCASP1_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | |
| | 176 | 0 | DEV_MCASP2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 176 | 2 | DEV_MCASP2_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | |
| | 176 | 3 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 4 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 176 | 5 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 6 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 11 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 12 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 13 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 14 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 19 | DEV_MCASP2_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | |
| | 176 | 21 | DEV_MCASP2_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | |
| | 176 | 22 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 23 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 176 | 24 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 25 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 30 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 31 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 32 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 33 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 38 | DEV_MCASP2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 176 | 39 | DEV_MCASP2_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | |
| | 176 | 40 | DEV_MCASP2_AUX_CLK | CLK_STATE_READY | 196608000 | | |
| | 176 | 41 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | |
| | 176 | 42 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 176 | 45 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 46 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 47 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 48 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 49 | DEV_MCASP2_VBUSP_CLK | CLK_STATE_READY | 250000000 | | |
| | 176 | 50 | DEV_MCASP2_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | |
| | 176 | 51 | DEV_MCASP2_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | |
| | 266 | 3 | DEV_MCSPI0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 266 | 4 | DEV_MCSPI0_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 266 | 5 | DEV_MCSPI0_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 267 | 3 | DEV_MCSPI1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 267 | 4 | DEV_MCSPI1_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 267 | 5 | DEV_MCSPI1_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 268 | 3 | DEV_MCSPI2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 268 | 4 | DEV_MCSPI2_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 268 | 5 | DEV_MCSPI2_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 269 | 0 | DEV_MCSPI3_IO_CLKSPII_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 269 | 1 | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 269 | 3 | DEV_MCSPI3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 269 | 4 | DEV_MCSPI3_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 269 | 5 | DEV_MCSPI3_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 270 | 0 | DEV_MCSPI4_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | |
| | 270 | 1 | DEV_MCSPI4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 270 | 2 | DEV_MCSPI4_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 270 | 3 | DEV_MCSPI4_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 271 | 3 | DEV_MCSPI5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 271 | 4 | DEV_MCSPI5_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 271 | 5 | DEV_MCSPI5_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 272 | 3 | DEV_MCSPI6_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 272 | 4 | DEV_MCSPI6_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 272 | 5 | DEV_MCSPI6_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 273 | 3 | DEV_MCSPI7_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 273 | 4 | DEV_MCSPI7_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 273 | 5 | DEV_MCSPI7_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 0 | 0 | DEV_MCU_ADC0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 0 | 1 | DEV_MCU_ADC0_ADC_CLK | CLK_STATE_READY | 19200000 | | |
| | 0 | 2 | DEV_MCU_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 0 | 3 | DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | CLK_STATE_READY | 60000000 | | |
| | 0 | 4 | DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | CLK_STATE_READY | 58823529 | | |
| | 0 | 5 | DEV_MCU_ADC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 0 | 6 | DEV_MCU_ADC0_VBUS_CLK | CLK_STATE_READY | 333333333 | | |
| | 1 | 0 | DEV_MCU_ADC1_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 1 | 1 | DEV_MCU_ADC1_ADC_CLK | CLK_STATE_READY | 19200000 | | |
| | 1 | 2 | DEV_MCU_ADC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 1 | 3 | DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | CLK_STATE_READY | 60000000 | | |
| | 1 | 4 | DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | CLK_STATE_READY | 58823529 | | |
| | 1 | 5 | DEV_MCU_ADC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 1 | 6 | DEV_MCU_ADC1_VBUS_CLK | CLK_STATE_READY | 333333333 | | |
| | 18 | 0 | DEV_MCU_CPSW0_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | |
| | 18 | 2 | DEV_MCU_CPSW0_CPTS_RFT_CLK | CLK_STATE_READY | 500000000 | | |
| | 18 | 3 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 18 | 4 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 18 | 5 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 18 | 6 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 18 | 7 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 18 | 8 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 18 | 9 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 18 | 10 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 18 | 11 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 18 | 12 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 18 | 17 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 18 | 18 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2 | CLK_STATE_READY | 500000000 | | |
| | 18 | 20 | DEV_MCU_CPSW0_GMII1_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 18 | 21 | DEV_MCU_CPSW0_CPPI_CLK_CLK | CLK_STATE_READY | 333333333 | | |
| | 18 | 22 | DEV_MCU_CPSW0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 18 | 24 | DEV_MCU_CPSW0_GMII_RFT_CLK | CLK_STATE_READY | 125000000 | | |
| | 18 | 27 | DEV_MCU_CPSW0_GMII1_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 18 | 28 | DEV_MCU_CPSW0_RGMII1_TXC_O | CLK_STATE_READY | 0 | | |
| | 18 | 29 | DEV_MCU_CPSW0_RMII_MHZ_50_CLK | CLK_STATE_READY | 0 | | |
| | 18 | 30 | DEV_MCU_CPSW0_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | |
| | 18 | 31 | DEV_MCU_CPSW0_RGMII1_RXC_I | CLK_STATE_READY | 0 | | |
| | 18 | 32 | DEV_MCU_CPSW0_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | |
| | 18 | 33 | DEV_MCU_CPSW0_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | |
| | 24 | 0 | DEV_MCU_CPT2_AGGR0_VCLK_CLK | CLK_STATE_READY | 333333333 | | |
| | 44 | 0 | DEV_MCU_DCC0_DCC_INPUT10_CLK | CLK_STATE_READY | 333333333 | | |
| | 44 | 1 | DEV_MCU_DCC0_DCC_INPUT01_CLK | CLK_STATE_READY | 83 | | |
| | 44 | 2 | DEV_MCU_DCC0_DCC_CLKSRC2_CLK | CLK_STATE_READY | 80000000 | | |
| | 44 | 3 | DEV_MCU_DCC0_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | |
| | 44 | 4 | DEV_MCU_DCC0_DCC_CLKSRC0_CLK | CLK_STATE_READY | 200000000 | | |
| | 44 | 5 | DEV_MCU_DCC0_VBUS_CLK | CLK_STATE_READY | 166666666 | | |
| | 44 | 6 | DEV_MCU_DCC0_DCC_CLKSRC4_CLK | CLK_STATE_READY | 133333333 | | |
| | 44 | 7 | DEV_MCU_DCC0_DCC_CLKSRC1_CLK | CLK_STATE_READY | 60000000 | | |
| | 44 | 8 | DEV_MCU_DCC0_DCC_CLKSRC3_CLK | CLK_STATE_READY | 96000000 | | |
| | 44 | 9 | DEV_MCU_DCC0_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 44 | 10 | DEV_MCU_DCC0_DCC_CLKSRC5_CLK | CLK_STATE_READY | 83 | | |
| | 44 | 11 | DEV_MCU_DCC0_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | |
| | 44 | 12 | DEV_MCU_DCC0_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 45 | 0 | DEV_MCU_DCC1_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | |
| | 45 | 1 | DEV_MCU_DCC1_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 45 | 2 | DEV_MCU_DCC1_DCC_CLKSRC2_CLK | CLK_STATE_READY | 80000000 | | |
| | 45 | 3 | DEV_MCU_DCC1_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | |
| | 45 | 4 | DEV_MCU_DCC1_DCC_CLKSRC0_CLK | CLK_STATE_READY | 250000000 | | |
| | 45 | 5 | DEV_MCU_DCC1_VBUS_CLK | CLK_STATE_READY | 166666666 | | |
| | 45 | 6 | DEV_MCU_DCC1_DCC_CLKSRC4_CLK | CLK_STATE_READY | 250000000 | | |
| | 45 | 7 | DEV_MCU_DCC1_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | |
| | 45 | 8 | DEV_MCU_DCC1_DCC_CLKSRC3_CLK | CLK_STATE_READY | 166666666 | | |
| | 45 | 9 | DEV_MCU_DCC1_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 45 | 10 | DEV_MCU_DCC1_DCC_CLKSRC5_CLK | CLK_STATE_READY | 58823529 | | |
| | 45 | 11 | DEV_MCU_DCC1_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | |
| | 45 | 12 | DEV_MCU_DCC1_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 46 | 0 | DEV_MCU_DCC2_DCC_INPUT10_CLK | CLK_STATE_READY | 333333333 | | |
| | 46 | 1 | DEV_MCU_DCC2_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 46 | 3 | DEV_MCU_DCC2_DCC_CLKSRC7_CLK | CLK_STATE_READY | 19200000 | | |
| | 46 | 4 | DEV_MCU_DCC2_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | |
| | 46 | 5 | DEV_MCU_DCC2_VBUS_CLK | CLK_STATE_READY | 166666666 | | |
| | 46 | 7 | DEV_MCU_DCC2_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | |
| | 46 | 8 | DEV_MCU_DCC2_DCC_CLKSRC3_CLK | CLK_STATE_READY | 192000000 | | |
| | 46 | 9 | DEV_MCU_DCC2_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 46 | 11 | DEV_MCU_DCC2_DCC_CLKSRC6_CLK | CLK_STATE_READY | 12500000 | | |
| | 46 | 12 | DEV_MCU_DCC2_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 98 | 0 | DEV_MCU_ESM0_CLK | CLK_STATE_READY | 166666666 | | |
| | 101 | 0 | DEV_MCU_FSS0_FSAS_0_GCLK | CLK_STATE_READY | 1000000000 | | |
| | 102 | 0 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N | CLK_STATE_READY | 0 | | |
| | 102 | 1 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK | CLK_STATE_READY | 166666666 | | |
| | 102 | 2 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK | CLK_STATE_READY | 83333333 | | |
| | 102 | 4 | DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK | CLK_STATE_READY | 1000000000 | | |
| | 102 | 5 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK | CLK_STATE_READY | 166666666 | | |
| | 102 | 7 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK | CLK_STATE_READY | 83333333 | | |
| | 102 | 10 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P | CLK_STATE_READY | 0 | | |
| | 103 | 0 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 103 | 1 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK | CLK_STATE_READY | 133333333 | | |
| | 103 | 2 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK | CLK_STATE_READY | 166666666 | | |
| | 103 | 3 | DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 103 | 4 | DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK | CLK_STATE_READY | 0 | | |
| | 103 | 5 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK | CLK_STATE_READY | 0 | | |
| | 103 | 6 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT | CLK_STATE_READY | 0 | | |
| | 103 | 7 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 103 | 8 | DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 103 | 9 | DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK | CLK_STATE_READY | 0 | | |
| | 104 | 0 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK | CLK_STATE_READY | 133333333 | | |
| | 104 | 1 | DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 104 | 7 | DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 194 | 0 | DEV_MCU_I2C0_PISCL | CLK_STATE_READY | 0 | | |
| | 194 | 1 | DEV_MCU_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 194 | 2 | DEV_MCU_I2C0_CLK | CLK_STATE_READY | 166666666 | | |
| | 195 | 0 | DEV_MCU_I2C1_PISCL | CLK_STATE_READY | 0 | | |
| | 195 | 1 | DEV_MCU_I2C1_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 195 | 2 | DEV_MCU_I2C1_CLK | CLK_STATE_READY | 166666666 | | |
| | 195 | 3 | DEV_MCU_I2C1_PORSCL | CLK_STATE_READY | 0 | | |
| | 117 | 0 | DEV_MCU_I3C0_I3C_SCL_DI | CLK_STATE_READY | 0 | | |
| | 117 | 1 | DEV_MCU_I3C0_I3C_SCL_DO | CLK_STATE_READY | 0 | | |
| | 117 | 2 | DEV_MCU_I3C0_I3C_PCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 117 | 4 | DEV_MCU_I3C0_I3C_SCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 118 | 2 | DEV_MCU_I3C1_I3C_PCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 118 | 4 | DEV_MCU_I3C1_I3C_SCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 172 | 0 | DEV_MCU_MCAN0_MCANSS_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 172 | 2 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 172 | 3 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | CLK_STATE_READY | 80000000 | | |
| | 172 | 4 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 172 | 5 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | CLK_STATE_READY | 80000000 | | |
| | 172 | 6 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 173 | 0 | DEV_MCU_MCAN1_MCANSS_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 173 | 2 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 173 | 3 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | CLK_STATE_READY | 80000000 | | |
| | 173 | 4 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 173 | 5 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | CLK_STATE_READY | 80000000 | | |
| | 173 | 6 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 274 | 3 | DEV_MCU_MCSPI0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 274 | 4 | DEV_MCU_MCSPI0_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 274 | 5 | DEV_MCU_MCSPI0_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 275 | 0 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 275 | 1 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 275 | 3 | DEV_MCU_MCSPI1_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 275 | 4 | DEV_MCU_MCSPI1_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 275 | 5 | DEV_MCU_MCSPI1_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 276 | 0 | DEV_MCU_MCSPI2_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | |
| | 276 | 1 | DEV_MCU_MCSPI2_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 276 | 2 | DEV_MCU_MCSPI2_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 276 | 3 | DEV_MCU_MCSPI2_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 237 | 0 | DEV_MCU_NAVSS0_INTR_0_INTR_CLK | CLK_STATE_READY | 1000000000 | | |
| | 238 | 0 | DEV_MCU_NAVSS0_MCRC_0_CLK | CLK_STATE_READY | 1000000000 | | |
| | 302 | 0 | DEV_MCU_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 1000000000 | | |
| | 234 | 0 | DEV_MCU_NAVSS0_PROXY0_CLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 235 | 0 | DEV_MCU_NAVSS0_RINGACC0_SYS_CLK | CLK_STATE_READY | 1000000000 | | |
| | 236 | 0 | DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK | CLK_STATE_READY | 1000000000 | | |
| | 303 | 0 | DEV_MCU_NAVSS0_UDMASS_VD2CLK | CLK_STATE_READY | 1000000000 | | |
| | 233 | 0 | DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK | CLK_STATE_READY | 1000000000 | | |
| | 142 | 1 | DEV_MCU_PBIST0_CLK7_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 2 | DEV_MCU_PBIST0_CLK3_CLK | CLK_STATE_READY | 166666666 | | |
| | 142 | 3 | DEV_MCU_PBIST0_CLK5_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 4 | DEV_MCU_PBIST0_CLK1_CLK | CLK_STATE_READY | 500000000 | | |
| | 142 | 5 | DEV_MCU_PBIST0_CLK8_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 6 | DEV_MCU_PBIST0_CLK6_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 8 | DEV_MCU_PBIST0_CLK4_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 9 | DEV_MCU_PBIST0_CLK2_CLK | CLK_STATE_READY | 333333333 | | |
| | 143 | 1 | DEV_MCU_PBIST1_CLK7_CLK | CLK_STATE_READY | 83333333 | | |
| | 143 | 2 | DEV_MCU_PBIST1_CLK3_CLK | CLK_STATE_READY | 83333333 | | |
| | 143 | 3 | DEV_MCU_PBIST1_CLK5_CLK | CLK_STATE_READY | 166666666 | | |
| | 143 | 4 | DEV_MCU_PBIST1_CLK1_CLK | CLK_STATE_READY | 500000000 | | |
| | 143 | 5 | DEV_MCU_PBIST1_CLK8_CLK | CLK_STATE_READY | 83333333 | | |
| | 143 | 6 | DEV_MCU_PBIST1_CLK6_CLK | CLK_STATE_READY | 83333333 | | |
| | 143 | 8 | DEV_MCU_PBIST1_CLK4_CLK | CLK_STATE_READY | 333333333 | | |
| | 143 | 9 | DEV_MCU_PBIST1_CLK2_CLK | CLK_STATE_READY | 400000000 | | |
| | 144 | 1 | DEV_MCU_PBIST2_CLK7_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 2 | DEV_MCU_PBIST2_CLK3_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 3 | DEV_MCU_PBIST2_CLK5_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 4 | DEV_MCU_PBIST2_CLK1_CLK | CLK_STATE_READY | 1000000000 | | |
| | 144 | 5 | DEV_MCU_PBIST2_CLK8_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 6 | DEV_MCU_PBIST2_CLK6_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 8 | DEV_MCU_PBIST2_CLK4_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 9 | DEV_MCU_PBIST2_CLK2_CLK | CLK_STATE_READY | 83333333 | | |
| | 250 | 0 | DEV_MCU_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | |
| | 250 | 1 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 250 | 2 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | CLK_STATE_READY | 333333333 | | |
| | 250 | 3 | DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | |
| | 250 | 4 | DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 333333333 | | |
| | 251 | 0 | DEV_MCU_R5FSS0_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | |
| | 251 | 1 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 251 | 2 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | CLK_STATE_READY | 333333333 | | |
| | 251 | 3 | DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | |
| | 251 | 4 | DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE | CLK_STATE_READY | 333333333 | | |
| | 262 | 0 | DEV_MCU_RTI0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 262 | 1 | DEV_MCU_RTI0_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 262 | 2 | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 262 | 3 | DEV_MCU_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 262 | 4 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 262 | 5 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 263 | 0 | DEV_MCU_RTI1_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 263 | 1 | DEV_MCU_RTI1_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 263 | 2 | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 263 | 3 | DEV_MCU_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 263 | 4 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 263 | 5 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 265 | 0 | DEV_MCU_SA2_UL0_X2_CLK | CLK_STATE_READY | 333333333 | | |
| | 265 | 1 | DEV_MCU_SA2_UL0_PKA_IN_CLK | CLK_STATE_READY | 400000000 | | |
| | 265 | 2 | DEV_MCU_SA2_UL0_X1_CLK | CLK_STATE_READY | 166666666 | | |
| | 35 | 0 | DEV_MCU_TIMER0_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 35 | 1 | DEV_MCU_TIMER0_TIMER_TCLK_CLK | CLK_STATE_READY | 62500000 | | |
| | 35 | 2 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 35 | 3 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 35 | 4 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 35 | 5 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 35 | 6 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 35 | 7 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 35 | 8 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 35 | 9 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 35 | 11 | DEV_MCU_TIMER0_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 71 | 0 | DEV_MCU_TIMER1_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 71 | 1 | DEV_MCU_TIMER1_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 71 | 2 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1 | CLK_STATE_READY | 19200000 | | |
| | 71 | 3 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 308 | 0 | DEV_MCU_TIMER1_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 308 | 1 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 308 | 2 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 308 | 3 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 308 | 4 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 308 | 5 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 308 | 6 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 308 | 7 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 308 | 8 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 72 | 0 | DEV_MCU_TIMER2_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 72 | 1 | DEV_MCU_TIMER2_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 72 | 2 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 72 | 3 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 72 | 4 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 72 | 5 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 72 | 6 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 72 | 7 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 72 | 8 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 72 | 9 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 72 | 11 | DEV_MCU_TIMER2_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 73 | 0 | DEV_MCU_TIMER3_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 73 | 1 | DEV_MCU_TIMER3_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 73 | 2 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3 | CLK_STATE_READY | 19200000 | | |
| | 73 | 3 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 309 | 0 | DEV_MCU_TIMER3_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 309 | 1 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 309 | 2 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 309 | 3 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 309 | 4 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 309 | 5 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 309 | 6 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 309 | 7 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 309 | 8 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 74 | 0 | DEV_MCU_TIMER4_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 74 | 1 | DEV_MCU_TIMER4_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 74 | 2 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 74 | 3 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 74 | 4 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 74 | 5 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 74 | 6 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 74 | 7 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 74 | 8 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 74 | 9 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 74 | 11 | DEV_MCU_TIMER4_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 75 | 0 | DEV_MCU_TIMER5_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 75 | 1 | DEV_MCU_TIMER5_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 75 | 2 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5 | CLK_STATE_READY | 19200000 | | |
| | 75 | 3 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 310 | 0 | DEV_MCU_TIMER5_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 310 | 1 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 310 | 2 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 310 | 3 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 310 | 4 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 310 | 5 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 310 | 6 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 310 | 7 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 310 | 8 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 76 | 0 | DEV_MCU_TIMER6_TIMER_HCLK_CLK | CLK_STATE_READY | 333333333 | | |
| | 76 | 1 | DEV_MCU_TIMER6_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 76 | 2 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 76 | 3 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 76 | 4 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 76 | 5 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 76 | 6 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 76 | 7 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 76 | 8 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 76 | 9 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 76 | 11 | DEV_MCU_TIMER6_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 77 | 0 | DEV_MCU_TIMER7_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 77 | 1 | DEV_MCU_TIMER7_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 77 | 2 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7 | CLK_STATE_READY | 19200000 | | |
| | 77 | 3 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 311 | 0 | DEV_MCU_TIMER7_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 311 | 1 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 311 | 2 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 311 | 3 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 311 | 4 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 311 | 5 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 311 | 6 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 311 | 7 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 311 | 8 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 78 | 0 | DEV_MCU_TIMER8_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 78 | 1 | DEV_MCU_TIMER8_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 78 | 2 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 78 | 3 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 78 | 4 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 78 | 5 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 78 | 6 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 78 | 7 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 78 | 8 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 78 | 9 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 78 | 11 | DEV_MCU_TIMER8_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 79 | 0 | DEV_MCU_TIMER9_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 79 | 1 | DEV_MCU_TIMER9_TIMER_TCLK_CLK | CLK_STATE_READY | 62500000 | | |
| | 79 | 2 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9 | CLK_STATE_READY | 62500000 | | |
| | 79 | 3 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 312 | 0 | DEV_MCU_TIMER9_CLKSEL_VD_CLK | CLK_STATE_READY | 62500000 | | |
| | 312 | 1 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 312 | 2 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 312 | 3 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 312 | 4 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 312 | 5 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 312 | 6 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 312 | 7 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 312 | 8 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 149 | 2 | DEV_MCU_UART0_FCLK_CLK | CLK_STATE_READY | 96000000 | | |
| | 149 | 3 | DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK | CLK_STATE_READY | 96000000 | | |
| | 149 | 4 | DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_1_HSDIVOUT5_CLK | CLK_STATE_READY | 192000000 | | |
| | 149 | 5 | DEV_MCU_UART0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 91 | 0 | DEV_MMCSD0_EMMCSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | |
| | 91 | 3 | DEV_MMCSD0_EMMCSS_XIN_CLK | CLK_STATE_READY | 200000000 | | |
| | 91 | 4 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 91 | 5 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | |
| | 91 | 6 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 91 | 7 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0 | CLK_STATE_READY | 200000000 | | |
| | 92 | 0 | DEV_MMCSD1_EMMCSDSS_IO_CLK_I | CLK_STATE_READY | 0 | | |
| | 92 | 1 | DEV_MMCSD1_EMMCSDSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | |
| | 92 | 2 | DEV_MMCSD1_EMMCSDSS_XIN_CLK | CLK_STATE_READY | 200000000 | | |
| | 92 | 3 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 92 | 4 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | |
| | 92 | 5 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 92 | 6 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0 | CLK_STATE_READY | 200000000 | | |
| | 92 | 7 | DEV_MMCSD1_EMMCSDSS_IO_CLK_O | CLK_STATE_READY | 0 | | |
| | 199 | 0 | DEV_NAVSS0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 199 | 1 | DEV_NAVSS0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 199 | 2 | DEV_NAVSS0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 201 | 0 | DEV_NAVSS0_CPTS_0_VBUSP_GCLK | CLK_STATE_READY | 500000000 | | |
| | 201 | 1 | DEV_NAVSS0_CPTS_0_RCLK | CLK_STATE_READY | 200000000 | | |
| | 201 | 2 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 201 | 3 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 201 | 4 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 201 | 5 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 201 | 6 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 201 | 7 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 201 | 8 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 201 | 9 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 201 | 10 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 201 | 11 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 201 | 16 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 201 | 17 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 201 | 20 | DEV_NAVSS0_CPTS_0_TS_GENF0 | CLK_STATE_READY | 0 | | |
| | 201 | 21 | DEV_NAVSS0_CPTS_0_TS_GENF1 | CLK_STATE_READY | 0 | | |
| | 206 | 0 | DEV_NAVSS0_DTI_0_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 213 | 0 | DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK | CLK_STATE_READY | 500000000 | | |
| | 214 | 0 | DEV_NAVSS0_MAILBOX_0_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 215 | 0 | DEV_NAVSS0_MAILBOX_1_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 224 | 0 | DEV_NAVSS0_MAILBOX_10_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 225 | 0 | DEV_NAVSS0_MAILBOX_11_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 216 | 0 | DEV_NAVSS0_MAILBOX_2_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 217 | 0 | DEV_NAVSS0_MAILBOX_3_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 218 | 0 | DEV_NAVSS0_MAILBOX_4_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 219 | 0 | DEV_NAVSS0_MAILBOX_5_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 220 | 0 | DEV_NAVSS0_MAILBOX_6_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 221 | 0 | DEV_NAVSS0_MAILBOX_7_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 222 | 0 | DEV_NAVSS0_MAILBOX_8_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 223 | 0 | DEV_NAVSS0_MAILBOX_9_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 227 | 0 | DEV_NAVSS0_MCRC_0_CLK | CLK_STATE_READY | 500000000 | | |
| | 299 | 0 | DEV_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 500000000 | | |
| | 207 | 0 | DEV_NAVSS0_MODSS_INTA_0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 208 | 0 | DEV_NAVSS0_MODSS_INTA_1_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 210 | 0 | DEV_NAVSS0_PROXY_0_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 211 | 0 | DEV_NAVSS0_RINGACC_0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 226 | 0 | DEV_NAVSS0_SPINLOCK_0_CLK | CLK_STATE_READY | 500000000 | | |
| | 228 | 0 | DEV_NAVSS0_TBU_0_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 230 | 0 | DEV_NAVSS0_TIMERMGR_0_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 230 | 1 | DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT | CLK_STATE_READY | 0 | | |
| | 231 | 0 | DEV_NAVSS0_TIMERMGR_1_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 231 | 1 | DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT | CLK_STATE_READY | 0 | | |
| | 212 | 0 | DEV_NAVSS0_UDMAP_0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 300 | 0 | DEV_NAVSS0_UDMASS_VD2CLK | CLK_STATE_READY | 500000000 | | |
| | 209 | 0 | DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 301 | 0 | DEV_NAVSS0_VIRTSS_VD2CLK | CLK_STATE_READY | 500000000 | | |
| | 139 | 1 | DEV_PBIST0_CLK7_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 2 | DEV_PBIST0_CLK3_CLK | CLK_STATE_READY | 250000000 | | |
| | 139 | 3 | DEV_PBIST0_CLK5_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 4 | DEV_PBIST0_CLK1_CLK | CLK_STATE_READY | 500000000 | | |
| | 139 | 5 | DEV_PBIST0_CLK8_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 6 | DEV_PBIST0_CLK6_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 8 | DEV_PBIST0_CLK4_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 9 | DEV_PBIST0_CLK2_CLK | CLK_STATE_READY | 250000000 | | |
| | 140 | 1 | DEV_PBIST1_CLK7_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 2 | DEV_PBIST1_CLK3_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 3 | DEV_PBIST1_CLK5_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 4 | DEV_PBIST1_CLK1_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 5 | DEV_PBIST1_CLK8_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 6 | DEV_PBIST1_CLK6_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 8 | DEV_PBIST1_CLK4_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 9 | DEV_PBIST1_CLK2_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 1 | DEV_PBIST2_CLK7_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 2 | DEV_PBIST2_CLK3_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 3 | DEV_PBIST2_CLK5_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 4 | DEV_PBIST2_CLK1_CLK | CLK_STATE_READY | 1000000000 | | |
| | 141 | 5 | DEV_PBIST2_CLK8_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 6 | DEV_PBIST2_CLK6_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 8 | DEV_PBIST2_CLK4_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 9 | DEV_PBIST2_CLK2_CLK | CLK_STATE_READY | 125000000 | | |
| | 240 | 0 | DEV_PCIE1_PCIE_LANE0_TXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 1 | DEV_PCIE1_PCIE_LANE1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 2 | DEV_PCIE1_PCIE_LANE0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 3 | DEV_PCIE1_PCIE_LANE0_TXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 4 | DEV_PCIE1_PCIE_PM_CLK | CLK_STATE_READY | 12500000 | | |
| | 240 | 5 | DEV_PCIE1_PCIE_LANE3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 6 | DEV_PCIE1_PCIE_CBA_CLK | CLK_STATE_READY | 250000000 | | |
| | 240 | 7 | DEV_PCIE1_PCIE_LANE1_REFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 8 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK | CLK_STATE_READY | 200000000 | | |
| | 240 | 9 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 240 | 10 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 240 | 11 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 240 | 12 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 240 | 13 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 240 | 14 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 240 | 15 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 16 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 17 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 18 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 23 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 240 | 24 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 240 | 25 | DEV_PCIE1_PCIE_LANE1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 27 | DEV_PCIE1_PCIE_LANE2_RXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 28 | DEV_PCIE1_PCIE_LANE2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 29 | DEV_PCIE1_PCIE_LANE1_TXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 30 | DEV_PCIE1_PCIE_LANE3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 31 | DEV_PCIE1_PCIE_LANE2_TXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 32 | DEV_PCIE1_PCIE_LANE1_RXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 33 | DEV_PCIE1_PCIE_LANE2_TXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 34 | DEV_PCIE1_PCIE_LANE1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 35 | DEV_PCIE1_PCIE_LANE0_REFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 36 | DEV_PCIE1_PCIE_LANE3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 37 | DEV_PCIE1_PCIE_LANE2_RXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 38 | DEV_PCIE1_PCIE_LANE3_RXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 39 | DEV_PCIE1_PCIE_LANE3_REFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 40 | DEV_PCIE1_PCIE_LANE2_REFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 41 | DEV_PCIE1_PCIE_LANE0_RXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 42 | DEV_PCIE1_PCIE_LANE3_TXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 43 | DEV_PCIE1_PCIE_LANE0_RXCLK | CLK_STATE_READY | 0 | | |
| | 133 | 0 | DEV_PSC0_SLOW_CLK | CLK_STATE_READY | 20833333 | | |
| | 133 | 1 | DEV_PSC0_CLK | CLK_STATE_READY | 125000000 | | |
| | 245 | 0 | DEV_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | |
| | 245 | 1 | DEV_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | |
| | 245 | 2 | DEV_R5FSS0_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 1000000000 | | |
| | 246 | 0 | DEV_R5FSS0_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | |
| | 246 | 1 | DEV_R5FSS0_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | |
| | 246 | 2 | DEV_R5FSS0_CORE1_INTERFACE_PHASE | CLK_STATE_READY | 1000000000 | | |
| | 252 | 0 | DEV_RTI0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 252 | 1 | DEV_RTI0_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 252 | 2 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 252 | 3 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 252 | 4 | DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 252 | 5 | DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 252 | 6 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 252 | 7 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | |
| | 252 | 8 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | |
| | 252 | 9 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | |
| | 253 | 0 | DEV_RTI1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 253 | 1 | DEV_RTI1_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 253 | 2 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 253 | 3 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 253 | 4 | DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 253 | 5 | DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 253 | 6 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 253 | 7 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | |
| | 253 | 8 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | |
| | 253 | 9 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | |
| | 258 | 0 | DEV_RTI28_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 258 | 1 | DEV_RTI28_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 258 | 2 | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 258 | 3 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 258 | 4 | DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 258 | 5 | DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 258 | 6 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 258 | 7 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | |
| | 258 | 8 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | |
| | 258 | 9 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | |
| | 259 | 0 | DEV_RTI29_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 259 | 1 | DEV_RTI29_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 259 | 2 | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 259 | 3 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 259 | 4 | DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 259 | 5 | DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 259 | 6 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 259 | 7 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | |
| | 259 | 8 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | |
| | 259 | 9 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | |
| | 292 | 1 | DEV_SERDES_10G1_IP3_LN1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 3 | DEV_SERDES_10G1_IP2_LN2_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 4 | DEV_SERDES_10G1_IP1_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 6 | DEV_SERDES_10G1_IP3_LN3_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 9 | DEV_SERDES_10G1_IP2_LN2_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 10 | DEV_SERDES_10G1_IP1_LN0_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 11 | DEV_SERDES_10G1_CLK | CLK_STATE_READY | 125000000 | | |
| | 292 | 13 | DEV_SERDES_10G1_IP1_LN3_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 14 | DEV_SERDES_10G1_IP1_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 15 | DEV_SERDES_10G1_IP2_LN0_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 16 | DEV_SERDES_10G1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 19 | DEV_SERDES_10G1_IP3_LN1_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 21 | DEV_SERDES_10G1_IP2_LN3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 22 | DEV_SERDES_10G1_IP1_LN2_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 24 | DEV_SERDES_10G1_IP2_LN1_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 25 | DEV_SERDES_10G1_IP2_LN1_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 29 | DEV_SERDES_10G1_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 32 | DEV_SERDES_10G1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 33 | DEV_SERDES_10G1_IP2_LN1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 34 | DEV_SERDES_10G1_IP1_LN1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 38 | DEV_SERDES_10G1_IP1_LN2_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 40 | DEV_SERDES_10G1_IP2_LN1_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 41 | DEV_SERDES_10G1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 42 | DEV_SERDES_10G1_IP2_LN3_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 43 | DEV_SERDES_10G1_IP2_LN2_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 44 | DEV_SERDES_10G1_IP2_LN2_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 45 | DEV_SERDES_10G1_IP1_LN1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 49 | DEV_SERDES_10G1_IP1_LN0_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 52 | DEV_SERDES_10G1_IP1_LN1_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 55 | DEV_SERDES_10G1_IP1_LN0_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 56 | DEV_SERDES_10G1_IP3_LN3_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 59 | DEV_SERDES_10G1_IP2_LN3_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 61 | DEV_SERDES_10G1_IP2_LN0_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 62 | DEV_SERDES_10G1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 63 | DEV_SERDES_10G1_IP1_LN1_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 65 | DEV_SERDES_10G1_IP1_LN3_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 66 | DEV_SERDES_10G1_IP3_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 67 | DEV_SERDES_10G1_IP2_LN2_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 73 | DEV_SERDES_10G1_IP3_LN1_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 74 | DEV_SERDES_10G1_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 75 | DEV_SERDES_10G1_IP1_LN3_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 77 | DEV_SERDES_10G1_IP1_LN0_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 80 | DEV_SERDES_10G1_IP1_LN2_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 81 | DEV_SERDES_10G1_IP2_LN0_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 82 | DEV_SERDES_10G1_IP2_LN0_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 85 | DEV_SERDES_10G1_CORE_REF_CLK | CLK_STATE_READY | 100000000 | | |
| | 292 | 86 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 292 | 87 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 292 | 88 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 125000000 | | |
| | 292 | 89 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | |
| | 292 | 92 | DEV_SERDES_10G1_IP1_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 95 | DEV_SERDES_10G1_IP2_LN3_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 96 | DEV_SERDES_10G1_IP3_LN3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 98 | DEV_SERDES_10G1_IP3_LN3_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 100 | DEV_SERDES_10G1_IP2_LN1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 102 | DEV_SERDES_10G1_IP3_LN1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 104 | DEV_SERDES_10G1_IP1_LN1_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 107 | DEV_SERDES_10G1_IP3_LN3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 108 | DEV_SERDES_10G1_IP1_LN3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 109 | DEV_SERDES_10G1_IP2_LN3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 111 | DEV_SERDES_10G1_IP1_LN0_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 112 | DEV_SERDES_10G1_IP2_LN0_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 113 | DEV_SERDES_10G1_IP1_LN2_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 118 | DEV_SERDES_10G1_IP1_LN2_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 124 | DEV_SERDES_10G1_IP1_LN3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 126 | DEV_SERDES_10G1_IP3_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 29 | 0 | DEV_STM0_CORE_CLK | CLK_STATE_READY | 250000000 | | |
| | 29 | 1 | DEV_STM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 29 | 2 | DEV_STM0_ATB_CLK | CLK_STATE_READY | 250000000 | | |
| | 49 | 0 | DEV_TIMER0_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 49 | 1 | DEV_TIMER0_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 49 | 2 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 49 | 3 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 4 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 49 | 5 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 49 | 6 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 49 | 7 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 8 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 9 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 10 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 11 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 49 | 12 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 49 | 13 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 49 | 14 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 49 | 15 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 49 | 16 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 49 | 17 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 49 | 26 | DEV_TIMER0_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 50 | 0 | DEV_TIMER1_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 50 | 1 | DEV_TIMER1_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 50 | 2 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1 | CLK_STATE_READY | 19200000 | | |
| | 50 | 3 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 60 | 0 | DEV_TIMER10_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 60 | 1 | DEV_TIMER10_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 60 | 2 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 60 | 3 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 4 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 60 | 5 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 60 | 6 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 60 | 7 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 8 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 9 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 10 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 11 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 60 | 12 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 60 | 13 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 60 | 14 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 60 | 15 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 60 | 16 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 60 | 17 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 60 | 26 | DEV_TIMER10_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 62 | 0 | DEV_TIMER11_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 62 | 1 | DEV_TIMER11_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 62 | 2 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11 | CLK_STATE_READY | 19200000 | | |
| | 62 | 3 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 318 | 0 | DEV_TIMER11_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 318 | 1 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 318 | 2 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 3 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 318 | 4 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 318 | 5 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 318 | 6 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 7 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 8 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 9 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 10 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 318 | 11 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 318 | 12 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 318 | 13 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 318 | 14 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 318 | 15 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 318 | 16 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 63 | 0 | DEV_TIMER12_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 63 | 1 | DEV_TIMER12_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 63 | 2 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 63 | 3 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 4 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 63 | 5 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 63 | 6 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 63 | 7 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 8 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 9 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 10 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 11 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 63 | 12 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 63 | 13 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 63 | 14 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 63 | 15 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 63 | 16 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 63 | 17 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 63 | 26 | DEV_TIMER12_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 64 | 0 | DEV_TIMER13_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 64 | 1 | DEV_TIMER13_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 64 | 2 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13 | CLK_STATE_READY | 19200000 | | |
| | 64 | 3 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 319 | 0 | DEV_TIMER13_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 319 | 1 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 319 | 2 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 3 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 319 | 4 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 319 | 5 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 319 | 6 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 7 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 8 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 9 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 10 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 319 | 11 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 319 | 12 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 319 | 13 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 319 | 14 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 319 | 15 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 319 | 16 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 65 | 0 | DEV_TIMER14_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 65 | 1 | DEV_TIMER14_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 65 | 2 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 65 | 3 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 4 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 65 | 5 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 65 | 6 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 65 | 7 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 8 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 9 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 10 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 11 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 65 | 12 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 65 | 13 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 65 | 14 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 65 | 15 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 65 | 16 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 65 | 17 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 65 | 26 | DEV_TIMER14_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 66 | 0 | DEV_TIMER15_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 66 | 1 | DEV_TIMER15_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 66 | 2 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15 | CLK_STATE_READY | 19200000 | | |
| | 66 | 3 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 320 | 0 | DEV_TIMER15_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 320 | 1 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 320 | 2 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 3 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 320 | 4 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 320 | 5 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 320 | 6 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 7 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 8 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 9 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 10 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 320 | 11 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 320 | 12 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 320 | 13 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 320 | 14 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 320 | 15 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 320 | 16 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 67 | 0 | DEV_TIMER16_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 67 | 1 | DEV_TIMER16_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 67 | 2 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 67 | 3 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 4 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 67 | 5 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 67 | 6 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 67 | 7 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 8 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 9 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 10 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 11 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 67 | 12 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 67 | 13 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 67 | 14 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 67 | 15 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 67 | 16 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 67 | 17 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 67 | 26 | DEV_TIMER16_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 68 | 0 | DEV_TIMER17_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 68 | 1 | DEV_TIMER17_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 68 | 2 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17 | CLK_STATE_READY | 19200000 | | |
| | 68 | 3 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 321 | 0 | DEV_TIMER17_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 321 | 1 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 321 | 2 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 3 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 321 | 4 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 321 | 5 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 321 | 6 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 7 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 8 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 9 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 10 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 321 | 11 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 321 | 12 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 321 | 13 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 321 | 14 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 321 | 15 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 321 | 16 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 69 | 0 | DEV_TIMER18_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 69 | 1 | DEV_TIMER18_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 69 | 2 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 69 | 3 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 4 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 69 | 5 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 69 | 6 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 69 | 7 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 8 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 9 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 10 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 11 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 69 | 12 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 69 | 13 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 69 | 14 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 69 | 15 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 69 | 16 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 69 | 17 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 69 | 26 | DEV_TIMER18_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 70 | 0 | DEV_TIMER19_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 70 | 1 | DEV_TIMER19_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 70 | 2 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19 | CLK_STATE_READY | 19200000 | | |
| | 70 | 3 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 322 | 0 | DEV_TIMER19_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 322 | 1 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 322 | 2 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 3 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 322 | 4 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 322 | 5 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 322 | 6 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 7 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 8 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 9 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 10 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 322 | 11 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 322 | 12 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 322 | 13 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 322 | 14 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 322 | 15 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 322 | 16 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 313 | 0 | DEV_TIMER1_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 313 | 1 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 313 | 2 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 3 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 313 | 4 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 313 | 5 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 313 | 6 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 7 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 8 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 9 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 10 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 313 | 11 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 313 | 12 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 313 | 13 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 313 | 14 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 313 | 15 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 313 | 16 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 51 | 0 | DEV_TIMER2_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 51 | 1 | DEV_TIMER2_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 51 | 2 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 51 | 3 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 4 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 51 | 5 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 51 | 6 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 51 | 7 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 8 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 9 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 10 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 11 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 51 | 12 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 51 | 13 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 51 | 14 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 51 | 15 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 51 | 16 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 51 | 17 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 51 | 26 | DEV_TIMER2_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 52 | 0 | DEV_TIMER3_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 52 | 1 | DEV_TIMER3_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 52 | 2 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3 | CLK_STATE_READY | 19200000 | | |
| | 52 | 3 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 314 | 0 | DEV_TIMER3_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 314 | 1 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 314 | 2 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 3 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 314 | 4 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 314 | 5 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 314 | 6 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 7 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 8 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 9 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 10 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 314 | 11 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 314 | 12 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 314 | 13 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 314 | 14 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 314 | 15 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 314 | 16 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 53 | 0 | DEV_TIMER4_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 53 | 1 | DEV_TIMER4_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 53 | 2 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 53 | 3 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 4 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 53 | 5 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 53 | 6 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 53 | 7 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 8 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 9 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 10 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 11 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 53 | 12 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 53 | 13 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 53 | 14 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 53 | 15 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 53 | 16 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 53 | 17 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 53 | 26 | DEV_TIMER4_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 54 | 0 | DEV_TIMER5_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 54 | 1 | DEV_TIMER5_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 54 | 2 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5 | CLK_STATE_READY | 19200000 | | |
| | 54 | 3 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 315 | 0 | DEV_TIMER5_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 315 | 1 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 315 | 2 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 3 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 315 | 4 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 315 | 5 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 315 | 6 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 7 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 8 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 9 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 10 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 315 | 11 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 315 | 12 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 315 | 13 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 315 | 14 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 315 | 15 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 315 | 16 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 55 | 0 | DEV_TIMER6_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 55 | 1 | DEV_TIMER6_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 55 | 2 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 55 | 3 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 4 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 55 | 5 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 55 | 6 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 55 | 7 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 8 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 9 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 10 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 11 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 55 | 12 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 55 | 13 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 55 | 14 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 55 | 15 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 55 | 16 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 55 | 17 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 55 | 26 | DEV_TIMER6_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 57 | 0 | DEV_TIMER7_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 57 | 1 | DEV_TIMER7_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 57 | 2 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7 | CLK_STATE_READY | 19200000 | | |
| | 57 | 3 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 316 | 0 | DEV_TIMER7_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 316 | 1 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 316 | 2 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 3 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 316 | 4 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 316 | 5 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 316 | 6 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 7 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 8 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 9 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 10 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 316 | 11 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 316 | 12 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 316 | 13 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 316 | 14 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 316 | 15 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 316 | 16 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 58 | 0 | DEV_TIMER8_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 58 | 1 | DEV_TIMER8_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 58 | 2 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 58 | 3 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 58 | 4 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 58 | 5 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 58 | 6 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 58 | 7 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 58 | 8 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 58 | 9 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 58 | 10 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 58 | 11 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 58 | 12 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 58 | 13 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 58 | 14 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 58 | 15 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 58 | 16 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 58 | 17 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 58 | 26 | DEV_TIMER8_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 59 | 0 | DEV_TIMER9_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 59 | 1 | DEV_TIMER9_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 59 | 2 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9 | CLK_STATE_READY | 19200000 | | |
| | 59 | 3 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 317 | 0 | DEV_TIMER9_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 317 | 1 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 317 | 2 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 317 | 3 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 317 | 4 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 317 | 5 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 317 | 6 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 317 | 7 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 317 | 8 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 317 | 9 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 317 | 10 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 317 | 11 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 317 | 12 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 317 | 13 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 317 | 14 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 317 | 15 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 317 | 16 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 146 | 2 | DEV_UART0_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 146 | 3 | DEV_UART0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 278 | 2 | DEV_UART1_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 278 | 3 | DEV_UART1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 279 | 2 | DEV_UART2_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 279 | 3 | DEV_UART2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 280 | 2 | DEV_UART3_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 280 | 3 | DEV_UART3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 281 | 2 | DEV_UART4_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 281 | 3 | DEV_UART4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 282 | 2 | DEV_UART5_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 282 | 3 | DEV_UART5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 283 | 2 | DEV_UART6_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 283 | 3 | DEV_UART6_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 284 | 2 | DEV_UART7_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 284 | 3 | DEV_UART7_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 285 | 2 | DEV_UART8_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 285 | 3 | DEV_UART8_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 286 | 2 | DEV_UART9_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 286 | 3 | DEV_UART9_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 288 | 0 | DEV_USB0_PIPE_REFCLK | CLK_STATE_READY | 0 | | |
| | 288 | 1 | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | |
| | 288 | 2 | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP3_LN3_REFCLK | CLK_STATE_READY | 0 | | |
| | 288 | 3 | DEV_USB0_CLK_LPM_CLK | CLK_STATE_READY | 24000000 | | |
| | 288 | 4 | DEV_USB0_BUF_CLK | CLK_STATE_READY | 250000000 | | |
| | 288 | 5 | DEV_USB0_PIPE_TXFCLK | CLK_STATE_READY | 0 | | |
| | 288 | 6 | DEV_USB0_USB2_APB_PCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 288 | 7 | DEV_USB0_PIPE_RXCLK | CLK_STATE_READY | 0 | | |
| | 288 | 8 | DEV_USB0_PIPE_TXMCLK | CLK_STATE_READY | 0 | | |
| | 288 | 9 | DEV_USB0_PIPE_RXFCLK | CLK_STATE_READY | 0 | | |
| | 288 | 11 | DEV_USB0_PIPE_TXCLK | CLK_STATE_READY | 0 | | |
| | 288 | 12 | DEV_USB0_USB2_REFCLOCK_CLK | CLK_STATE_READY | 19200000 | | |
| | 288 | 13 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 288 | 14 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 288 | 15 | DEV_USB0_PCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 288 | 17 | DEV_USB0_ACLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 145 | 0 | DEV_WKUP_DDPA0_DDPA_CLK | CLK_STATE_READY | 166666666 | | |
| | 99 | 0 | DEV_WKUP_ESM0_CLK | CLK_STATE_READY | 166666666 | | |
| | 113 | 0 | DEV_WKUP_GPIO0_MMR_CLK | CLK_STATE_READY | 166666666 | | |
| | 113 | 1 | DEV_WKUP_GPIO0_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | |
| | 113 | 2 | DEV_WKUP_GPIO0_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6_DUP0 | CLK_STATE_READY | 166666666 | | |
| | 113 | 3 | DEV_WKUP_GPIO0_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 113 | 4 | DEV_WKUP_GPIO0_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 114 | 0 | DEV_WKUP_GPIO1_MMR_CLK | CLK_STATE_READY | 166666666 | | |
| | 114 | 1 | DEV_WKUP_GPIO1_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | |
| | 114 | 2 | DEV_WKUP_GPIO1_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6_DUP0 | CLK[ 44.981289] kauditd_printk_skb: 7 callbacks suppressed | |
| _STATE_READY | 166666666 | | |
| | 114 | 3 | D[ 44.981300] audit: type=1334 audit(1707106726.300:17): prog-id=14 op=UNLOAD | |
| EV_WKUP_GPIO1_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_[ 44.999829] audit: type=1334 audit(1707106726.300:18): prog-id=13 op=UNLOAD | |
| 32K_CLK | CLK_STATE_READY | 32550 | | |
| | 114 | 4 | DEV_WKUP_GPIO1_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 197 | 0 | DEV_WKUP_I2C0_PISCL | CLK_STATE_READY | 0 | | |
| | 197 | 1 | DEV_WKUP_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 197 | 2 | DEV_WKUP_I2C0_CLK | CLK_STATE_READY | 166666666 | | |
| | 197 | 3 | DEV_WKUP_I2C0_PORSCL | CLK_STATE_READY | 0 | | |
| | 132 | 0 | DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK | CLK_STATE_READY | 12500000 | | |
| | 138 | 0 | DEV_WKUP_PSC0_SLOW_CLK | CLK_STATE_READY | 41666666 | | |
| | 138 | 1 | DEV_WKUP_PSC0_CLK | CLK_STATE_READY | 166666666 | | |
| | 287 | 2 | DEV_WKUP_UART0_FCLK_CLK | CLK_STATE_READY | 96000000 | | |
| | 287 | 3 | DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0 | CLK_STATE_READY | 96000000 | | |
| | 287 | 4 | DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 287 | 5 | DEV_WKUP_UART0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 154 | 0 | DEV_WKUP_VTM0_FIX_REF2_CLK | CLK_STATE_READY | 12500000 | | |
| | 154 | 1 | DEV_WKUP_VTM0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 154 | 2 | DEV_WKUP_VTM0_FIX_REF_CLK | CLK_STATE_READY | 19200000 | | |
| | 40 | 0 | DEV_WKUP_WAKEUP0_PLL_CTRL_WKUP_CLK24_CLK | CLK_STATE_READY | 1000000000 | | |
| | 40 | 1 | DEV_WKUP_WAKEUP0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 40 | 2 | DEV_WKUP_WAKEUP0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| |--------------------------------------------------------------------------------------------------------------------------------------------------| | |
| root@j7200-evm:~# car t /sys/kernel/debug/cl | |
| clear_warn_once clk/ | |
| root@j7200-evm:~# cat /sys/kernel/debug/clk/clk_summary | |
| enable prepare protect duty hardware connection | |
| clock count count count rate accuracy phase cycle enable consumer id | |
| --------------------------------------------------------------------------------------------------------------------------------------------- | |
| clk:292:89 0 0 0 100000000 0 0 50000 Y deviceless no_connection_id | |
| clk:292:85 0 0 0 100000000 0 0 50000 Y deviceless no_connection_id | |
| clk:292:88 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id | |
| clk:292:87 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:292:86 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:292:11 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id | |
| clk:288:14 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:288:13 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:288:12 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:288:3 0 0 0 24000000 0 0 50000 Y deviceless no_connection_id | |
| clk:278:2 0 0 0 48000000 0 0 50000 Y deviceless no_connection_id | |
| clk:253:9 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:253:8 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:253:7 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:253:6 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:253:5 0 0 0 32550 0 0 50000 Y deviceless no_connection_id | |
| clk:253:4 0 0 0 12500000 0 0 50000 Y deviceless no_connection_id | |
| clk:253:3 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:253:2 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:253:1 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:252:9 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:252:8 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:252:7 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:252:6 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:252:5 0 0 0 32550 0 0 50000 Y deviceless no_connection_id | |
| clk:252:4 0 0 0 12500000 0 0 50000 Y deviceless no_connection_id | |
| clk:252:3 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:252:2 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:252:1 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:240:6 0 0 0 250000000 0 0 50000 Y deviceless no_connection_id | |
| clk:203:0 0 0 0 748800000 0 0 50000 Y cpu1 no_connection_id | |
| cpu1 no_connection_id | |
| deviceless no_connection_id | |
| clk:202:2 0 0 0 748800000 0 0 50000 Y cpu0 no_connection_id | |
| cpu0 no_connection_id | |
| deviceless no_connection_id | |
| clk:201:17 0 0 0 500000000 0 0 50000 Y deviceless no_connection_id | |
| clk:201:16 0 0 0 500000000 0 0 50000 Y deviceless no_connection_id | |
| clk:201:15 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:14 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:13 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:12 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:11 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:10 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:9 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:8 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:7 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:6 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:5 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:4 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:3 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:201:2 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:201:1 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:197:1 0 0 0 96000000 0 0 50000 Y deviceless no_connection_id | |
| clk:188:1 0 0 0 96000000 0 0 50000 Y deviceless no_connection_id | |
| clk:187:1 0 0 0 96000000 0 0 50000 Y deviceless no_connection_id | |
| clk:149:4 0 0 0 192000000 0 0 50000 Y deviceless no_connection_id | |
| clk:149:3 0 0 0 96000000 0 0 50000 Y deviceless no_connection_id | |
| clk:149:2 0 0 0 96000000 0 0 50000 Y deviceless no_connection_id | |
| clk:146:2 0 0 0 48000000 0 0 50000 Y deviceless no_connection_id | |
| clk:113:4 0 0 0 12500000 0 0 50000 Y deviceless no_connection_id | |
| clk:113:3 0 0 0 32550 0 0 50000 Y deviceless no_connection_id | |
| clk:113:2 0 0 0 166666666 0 0 50000 Y deviceless no_connection_id | |
| clk:113:1 1 1 0 166666666 0 0 50000 Y deviceless no_connection_id | |
| clk:113:0 1 1 0 166666666 0 0 50000 Y 42110000.gpio gpio | |
| deviceless no_connection_id | |
| clk:105:0 1 1 0 125000000 0 0 50000 Y 600000.gpio gpio | |
| deviceless no_connection_id | |
| clk:103:2 0 0 0 166666666 0 0 50000 Y deviceless no_connection_id | |
| clk:103:0 0 0 0 166666666 0 0 50000 Y 47040000.spi no_connection_id | |
| deviceless no_connection_id | |
| clk:103:1 0 0 0 133333333 0 0 50000 Y deviceless no_connection_id | |
| clk:92:6 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:92:5 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:92:4 0 0 0 192000000 0 0 50000 Y deviceless no_connection_id | |
| clk:92:3 1 1 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:92:2 1 1 0 200000000 0 0 50000 Y 4fb0000.mmc clk_xin | |
| deviceless no_connection_id | |
| clk:92:1 0 0 0 250000000 0 0 50000 Y deviceless no_connection_id | |
| clk:91:7 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:91:6 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:91:5 0 0 0 192000000 0 0 50000 Y deviceless no_connection_id | |
| clk:91:4 1 1 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:91:3 1 1 0 200000000 0 0 50000 Y 4f80000.mmc clk_xin | |
| deviceless no_connection_id | |
| clk:91:0 0 0 0 250000000 0 0 50000 Y deviceless no_connection_id | |
| clk:19:16 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:18:21 0 0 0 333333333 0 0 50000 Y 46000f00.mdio fck | |
| 46000000.ethernet fck | |
| deviceless no_connection_id | |
| clk:18:18 0 0 0 500000000 0 0 50000 Y deviceless no_connection_id | |
| clk:18:2 0 0 0 500000000 0 0 50000 Y deviceless no_connection_id | |
| clk:18:17 0 0 0 500000000 0 0 50000 Y deviceless no_connection_id | |
| clk:18:16 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:15 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:14 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:13 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:12 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:11 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:10 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:9 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:8 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:7 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:6 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:5 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:4 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:18:3 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:0:5 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:0:4 0 0 0 58823529 0 0 50000 Y deviceless no_connection_id | |
| clk:0:3 0 0 0 60000000 0 0 50000 Y deviceless no_connection_id | |
| clk:0:2 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:0:1 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| serdes-refclk 0 0 0 100000000 0 0 50000 Y deviceless no_connection_id | |
| root@j7200-evm:~# dmesg | grep 44083000 | |
| [ 1.087494] ti-sci 44083000.system-controller: ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| [ 1.111664] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=18, clk=13, ret=-19 | |
| [ 1.122359] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=18, clk=14, ret=-19 | |
| [ 1.133040] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=18, clk=15, ret=-19 | |
| [ 1.143719] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=18, clk=16, ret=-19 | |
| [ 1.157785] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=201, clk=12, ret=-19 | |
| [ 1.168546] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=201, clk=13, ret=-19 | |
| [ 1.179291] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=201, clk=14, ret=-19 | |
| [ 1.190032] ti-sci-clk 44083000.system-controller:clock-controller: recalc-rate failed for dev=201, clk=15, ret=-19 | |
| [ 1.804546] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=201, clk=15, ret=-19 | |
| [ 1.815100] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=201, clk=14, ret=-19 | |
| [ 1.828260] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=201, clk=13, ret=-19 | |
| [ 1.844018] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=201, clk=12, ret=-19 | |
| [ 1.874564] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=18, clk=16, ret=-19 | |
| [ 1.884965] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=18, clk=15, ret=-19 | |
| [ 1.895372] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=18, clk=14, ret=-19 | |
| [ 1.905772] ti-sci-clk 44083000.system-controller:clock-controller: is_prepared failed for dev=18, clk=13, ret=-19 | |
| root@j7200-evm:~# |
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| root@j7200-evm:~# umount /dev/mmcblk1p 1 p p1 | |
| root@j7200-evm:~# cd /boot/ | |
| root@j7200-evm:/boot# (reverse-i-search)`': u': umount /dev/mmcblk1p1 p': scp udit@172.24.227.18:/home/udit/workarea/upstream/linux-next/arch/arm64/boot/Image .root@j7200-evm:/boot# scp udit@172.24.227.18:/home/udit/workarea/ | |
| udit@172.24.227.18's password: | |
| Image 0% 0 0.0KB/s --:-- ETAImage 19% 8356KB 8.2MB/s 00:04 ETAImage 38% 16MB 8.2MB/s 00:03 ETAImage 67% 28MB 8.5MB/s 00:01 ETAImage 100% 42MB 10.4MB/s 00:04 | |
| root@j7200-evm:/boot# reboot | |
| Stopping Session c2 of User root... | |
| [ OK ] Removed slice Slice /system/modprobe. | |
| [ OK ] Stopped target Graphical Interface. | |
| [ OK ] Stopped target Multi-User System. | |
| [ OK ] Stopped target Login Prompts. | |
| [ OK ] Stopped target RPC Port Mapper. | |
| [ OK ] Stopped target Timer Units. | |
| [ OK ] Stopped Daily rotation of log files. | |
| [ OK ] Stopped Daily Cleanup of Temporary Directories. | |
| [ OK ] Stopped target System Time Set. | |
| [ OK ] Closed Process Core Dump Socket. | |
| Stopping Job spooling tools... | |
| Stopping Avahi mDNS/DNS-SD Stack... | |
| Stopping containerd container runtime... | |
| Stopping Periodic Command Scheduler... | |
| Stopping Getty on tty1... | |
| Stopping irqbalance daemon... | |
| Stopping Reboot and dump vmcore via kexec... | |
| Stopping Lighttpd Daemon... | |
| Stopping Netperf Benchmark Server... | |
| Stopping NFS status monitor for NFSv2/3 locking.... | |
| Stopping Serial Getty on ttyS2... | |
| Stopping Load/Save Random Seed... | |
| Stopping TEE Supplicant... | |
| Stopping Telnet Server... | |
| [ OK ] Stopped Job spooling tools. | |
| [ OK ] Stopped Periodic Command Scheduler. | |
| [ OK ] Stopped irqbalance daemon. | |
| [ OK ] Stopped TEE Supplicant. | |
| [ OK ] Stopped Lighttpd Daemon. | |
| [ OK ] Stopped Avahi mDNS/DNS-SD Stack. | |
| [ OK ] Stopped Netperf Benchmark Server. | |
| [ OK ] Stopped NFS status monitor for NFSv2/3 locking.. | |
| [ OK ] Stopped containerd container runtime. | |
| [ OK ] Stopped Getty on tty1. | |
| [ OK ] Stopped Serial Getty on ttyS2. | |
| [ OK ] Stopped Reboot and dump vmcore via kexec. | |
| [ OK ] Stopped Load/Save Random Seed. | |
| [ OK ] Stopped Telnet Server. | |
| [ OK ] Stopped Session c2 of User root. | |
| [ OK ] Removed slice Slice /system/getty. | |
| [ OK ] Removed slice Slice /system/serial-getty. | |
| [ OK ] Stopped target Host and Network Name Lookups. | |
| Stopping User Login Management... | |
| Stopping User Manager for UID 0... | |
| [ OK ] Stopped User Manager for UID 0. | |
| Stopping User Runtime Directory /run/user/0... | |
| [ OK ] Unmounted /run/user/0. | |
| [ OK ] Stopped User Login Management. | |
| [ OK ] Stopped User Runtime Directory /run/user/0. | |
| [ OK ] Removed slice User Slice of UID 0. | |
| Stopping Permit User Sessions... | |
| [ OK ] Stopped Permit User Sessions. | |
| [ OK ] Stopped target Network. | |
| [ OK ] Stopped target Remote File Systems. | |
| Stopping Network Name Resolution... | |
| [ OK ] Stopped Network Name Resolution. | |
| Stopping Network Configuration... | |
| [ OK ] Stopped Network Configuration. | |
| [ OK ] Stopped target Preparation for Network. | |
| [ OK ] Stopped IPv6 Packet Filtering Framework. | |
| [ OK ] Stopped IPv4 Packet Filtering Framework. | |
| [ OK ] Stopped target Basic System. | |
| [ OK ] Stopped target Path Units. | |
| [ OK ] Stopped Dispatch Password �ts to Console Directory Watch. | |
| [ OK ] Stopped Forward Password R�uests to Wall Directory Watch. | |
| [ OK ] Stopped target Slice Units. | |
| [ OK ] Removed slice User and Session Slice. | |
| [ OK ] Stopped target Socket Units. | |
| [ OK ] Closed Avahi mDNS/DNS-SD Stack Activation Socket. | |
| [ OK ] Closed Docker Socket for the API. | |
| [ OK ] Closed dropbear.socket. | |
| [ OK ] Closed PC/SC Smart Card Daemon Activation Socket. | |
| [ OK ] Closed Network Service Netlink Socket. | |
| [ OK ] Closed Weston socket. | |
| Stopping D-Bus System Message Bus... | |
| [ OK ] Stopped D-Bus System Message Bus. | |
| [ OK ] Closed D-Bus System Message Bus Socket. | |
| [ OK ] Stopped target System Initialization. | |
| [ OK ] Stopped Apply Kernel Variables. | |
| Stopping Network Time Synchronization... | |
| Stopping Record System Boot/Shutdown in UTMP... | |
| [ OK ] Stopped Network Time Synchronization. | |
| [ OK ] Stopped Record System Boot/Shutdown in UTMP. | |
| [ OK ] Stopped Create Volatile Files and Directories. | |
| [ OK ] Stopped target Local File Systems. | |
| Unmounting /media/ram... | |
| Unmounting Temporary Directory /tmp... | |
| Unmounting /var/volatile... | |
| [ OK ] Unmounted /media/ram. | |
| [ OK ] Unmounted Temporary Directory /tmp. | |
| [ OK ] Unmounted /var/volatile. | |
| [ OK ] Stopped target Preparation for Local File Systems. | |
| [ OK ] Stopped target Swaps. | |
| [ OK ] Reached target Unmount All Filesystems. | |
| [ OK ] Stopped Remount Root and Kernel File Systems. | |
| [ OK ] Stopped Create Static Device Nodes in /dev. | |
| [ OK ] Reached target System Shutdown. | |
| [ OK ] Reached target Late Shutdown Services. | |
| [ OK ] Finished System Reboot. | |
| [ OK ] Reached target System Reboot. | |
| [ 170.241511] audit: type=1334 audit(1707106867.308:19): prog-id=8 op=UNLOAD | |
| [ 170.249036] audit: type=1334 audit(1707106867.308:20): prog-id=7 op=UNLOAD | |
| [ 170.256552] audit: type=1334 audit(1707106867.308:21): prog-id=4 op=UNLOAD | |
| [ 170.263472] audit: type=1334 audit(1707106867.308:22): prog-id=3 op=UNLOAD | |
| [ 170.270446] audit: type=1334 audit(1707106867.308:23): prog-id=6 op=UNLOAD | |
| [ 170.277454] audit: type=1334 audit(1707106867.308:24): prog-id=5 op=UNLOAD | |
| [ 170.284408] audit: type=1334 audit(1707106867.316:25): prog-id=10 op=UNLOAD | |
| [ 170.291436] audit: type=1334 audit(1707106867.316:26): prog-id=9 op=UNLOAD | |
| [ 170.851091] systemd-shutdown[1]: Syncing filesystems and block devices. | |
| [ 172.005746] systemd-shutdown[1]: Sending SIGTERM to remaining processes... | |
| [ 172.024417] systemd-journald[97]: Received SIGTERM from PID 1 (systemd-shutdow). | |
| [ 172.035539] audit: type=1335 audit(1707106869.100:27): pid=97 uid=0 auid=4294967295 tty=(none) ses=4294967295 comm="systemd-journal" exe="/lib/systemd/systemd-journald" nl-mcgrp=1 op=disconnect res=1 | |
| [ 172.054295] systemd-shutdown[1]: Sending SIGKILL to remaining processes... | |
| [ 172.070594] systemd-shutdown[1]: Unmounting file systems. | |
| [ 172.078829] [585]: Remounting '/' read-only with options 'n/a'. | |
| [ 172.104758] EXT4-fs (mmcblk1p2): re-mounted 4e3e7bf3-fbb1-4666-bc99-003ef4ba86a4 ro. Quota mode: none. | |
| [ 172.119226] systemd-shutdown[1]: All filesystems unmounted. | |
| [ 172.124857] systemd-shutdown[1]: Deactivating swaps. | |
| [ 172.130130] systemd-shutdown[1]: All swaps deactivated. | |
| [ 172.135392] systemd-shutdown[1]: Detaching loop devices. | |
| [ 172.144401] systemd-shutdown[1]: All loop devices detached. | |
| [ 172.150175] systemd-shutdown[1]: Stopping MD devices. | |
| [ 172.155649] systemd-shutdown[1]: All MD devices stopped. | |
| [ 172.160989] systemd-shutdown[1]: Detaching DM devices. | |
| [ 172.166386] systemd-shutdown[1]: All DM devices detached. | |
| [ 172.171798] systemd-shutdown[1]: All filesystems, swaps, loop devices, MD devices and DM devices detached. | |
| [ 172.192558] systemd-shutdown[1]: Syncing filesystems and block devices. | |
| [ 172.199319] systemd-shutdown[1]: Rebooting. | |
| [ 172.252310] kvm: exiting hardware virtualization | |
| [ 172.256946] reboot: Restarting system | |
| U-Boot SPL 2023.04-dirty (Jan 31 2024 - 23:05:06 +0530) | |
| SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| AVS finally voltage is 800000 | |
| Trying to boot from MMC2 | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Loading Environment from nowhere... OK | |
| Starting ATF on ARM64 core... | |
| NOTICE: BL31: v2.8(release):v2.8-226-g2fcd408bb3-dirty | |
| NOTICE: BL31: Built : 00:42:57, Jan 13 2023 | |
| I/TC: | |
| I/TC: OP-TEE version: 3.20.0 (gcc version 11.3.0 (GCC)) #1 Fri Jan 20 15:42:54 UTC 2023 aarch64 | |
| I/TC: WARNING: This OP-TEE configuration might be insecure! | |
| I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html | |
| I/TC: Primary CPU initializing | |
| I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| I/TC: HUK Initialized | |
| I/TC: Activated SA2UL device | |
| I/TC: Fixing SA2UL firewall owner for GP device | |
| I/TC: Enabled firewalls for SA2UL TRNG device | |
| I/TC: SA2UL TRNG initialized | |
| I/TC: SA2UL Drivers initialized | |
| I/TC: Primary CPU switching to normal world boot | |
| U-Boot SPL 2023.04-dirty (Jan 31 2024 - 23:05:14 +0530) | |
| SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| Detected: J7X-BASE-CPB rev E3 | |
| Detected: J7X-VSC8514-ETH rev E2 | |
| Trying to boot from MMC2 | |
| am654_sdhci mmc@4fb0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| U-Boot 2023.04-dirty (Jan 31 2024 - 23:05:14 +0530) | |
| SoC: J7200 SR2.0 GP | |
| Model: Texas Instruments K3 J7200 SoC | |
| Board: J7200X-PM2-SOM rev E7 | |
| DRAM: 4 GiB | |
| Core: 85 devices, 32 uclasses, devicetree: separate | |
| Flash: 0 Bytes | |
| MMC: mmc@4f80000: 0, mmc@4fb0000: 1 | |
| Loading Environment from nowhere... OK | |
| In: serial@2800000 | |
| Out: serial@2800000 | |
| Err: serial@2800000 | |
| am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000 | |
| Detected: J7X-BASE-CPB rev E3 | |
| Detected: J7X-VSC8514-ETH rev E2 | |
| Net: eth0: ethernet@46000000port@1 | |
| Hit any key to stop autoboot: 2 1 0 | |
| switch to partitions #0, OK | |
| mmc1 is current device | |
| SD/MMC found on device 1 | |
| Failed to load 'boot.scr' | |
| 574 bytes read in 13 ms (43 KiB/s) | |
| Loaded env from uEnv.txt | |
| Importing environment from mmc1 ... | |
| gpio: pin gpio@22_17 (gpio 126) value is 1 | |
| gpio: pin gpio@22_16 (gpio 125) value is 0 | |
| k3_r5f_rproc r5f@41000000: Core 1 is already in use. No rproc commands work | |
| 64508 bytes read in 12 ms (5.1 MiB/s) | |
| Load Remote Processor 1 with data@addr=0x82000000 64508 bytes: Success! | |
| 64508 bytes read in 11 ms (5.6 MiB/s) | |
| Load Remote Processor 2 with data@addr=0x82000000 64508 bytes: Success! | |
| 64508 bytes read in 12 ms (5.1 MiB/s) | |
| Load Remote Processor 3 with data@addr=0x82000000 64508 bytes: Success! | |
| 43653632 bytes read in 461 ms (90.3 MiB/s) | |
| 59061 bytes read in 10 ms (5.6 MiB/s) | |
| Working FDT set to 88000000 | |
| ## Flattened Device Tree blob at 88000000 | |
| Booting using the fdt blob at 0x88000000 | |
| Working FDT set to 88000000 | |
| Loading Device Tree to 000000008feee000, end 000000008fffffff ... OK | |
| Working FDT set to 8feee000 | |
| Starting kernel ... | |
| [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080] | |
| [ 0.000000] Linux version 6.8.0-rc2-next-20240202-00001-ge9c262b773c7 (udit@udit-HP-Z2-Tower-G9-Workstation-Desktop-PC) (aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 11.3.Rel1) 11.3.1 20220712, GNU ld (Arm GNU Toolchain 11.3.Rel1) 2.38.20220708) #2 SMP PREEMPT Mon Feb 5 09:50:38 IST 2024 | |
| [ 0.000000] KASLR disabled due to lack of seed | |
| [ 0.000000] Machine model: Texas Instruments J7200 EVM | |
| [ 0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '') | |
| [ 0.000000] printk: legacy bootconsole [ns16550a0] enabled | |
| [ 0.000000] efi: UEFI not found. | |
| [ 0.000000] OF: reserved mem: 0x000000009e800000..0x000000009fffffff (24576 KiB) nomap non-reusable optee@9e800000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a0000000..0x00000000a00fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a0000000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a0100000..0x00000000a0ffffff (15360 KiB) nomap non-reusable r5f-memory@a0100000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a1000000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a1000000..0x00000000a10fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a1000000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-memory@a1100000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a1100000..0x00000000a1ffffff (15360 KiB) nomap non-reusable r5f-memory@a1100000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a2000000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a2000000..0x00000000a20fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a2000000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 15 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-memory@a2100000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a2100000..0x00000000a2ffffff (15360 KiB) nomap non-reusable r5f-memory@a2100000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a3000000, size 1 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a3000000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a3000000..0x00000000a30fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a3000000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a3100000, size 15 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-memory@a3100000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a3100000..0x00000000a3ffffff (15360 KiB) nomap non-reusable r5f-memory@a3100000 | |
| [ 0.000000] OF: reserved mem: 0x00000000a4000000..0x00000000a47fffff (8192 KiB) nomap non-reusable ipc-memories@a4000000 | |
| [ 0.000000] NUMA: No NUMA configuration found | |
| [ 0.000000] NUMA: Faking a node at [mem 0x0000000080000000-0x00000008ffffffff] | |
| [ 0.000000] NUMA: NODE_DATA [mem 0x8ff7e49c0-0x8ff7e6fff] | |
| [ 0.000000] Zone ranges: | |
| [ 0.000000] DMA [mem 0x0000000080000000-0x00000000ffffffff] | |
| [ 0.000000] DMA32 empty | |
| [ 0.000000] Normal [mem 0x0000000100000000-0x00000008ffffffff] | |
| [ 0.000000] Movable zone start for each node | |
| [ 0.000000] Early memory node ranges | |
| [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009e7fffff] | |
| [ 0.000000] node 0: [mem 0x000000009e800000-0x00000000a47fffff] | |
| [ 0.000000] node 0: [mem 0x00000000a4800000-0x00000000ffffffff] | |
| [ 0.000000] node 0: [mem 0x0000000880000000-0x00000008ffffffff] | |
| [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff] | |
| [ 0.000000] cma: Reserved 32 MiB at 0x00000000fe000000 on node -1 | |
| [ 0.000000] psci: probing for conduit method from DT. | |
| [ 0.000000] psci: PSCIv1.1 detected in firmware. | |
| [ 0.000000] psci: Using standard PSCI v0.2 function IDs | |
| [ 0.000000] psci: Trusted OS migration not required | |
| [ 0.000000] psci: SMC Calling Convention v1.2 | |
| [ 0.000000] percpu: Embedded 22 pages/cpu s51368 r8192 d30552 u90112 | |
| [ 0.000000] Detected PIPT I-cache on CPU0 | |
| [ 0.000000] CPU features: detected: GIC system register CPU interface | |
| [ 0.000000] CPU features: detected: Spectre-v3a | |
| [ 0.000000] CPU features: detected: Spectre-BHB | |
| [ 0.000000] CPU features: detected: ARM erratum 1742098 | |
| [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923 | |
| [ 0.000000] alternatives: applying boot alternatives | |
| [ 0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 root=PARTUUID=aa7aea62-02 rw rootfstype=ext4 rootwait | |
| [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) | |
| [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) | |
| [ 0.000000] Fallback order for Node 0: 0 | |
| [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1032192 | |
| [ 0.000000] Policy zone: Normal | |
| [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off | |
| [ 0.000000] software IO TLB: area num 2. | |
| [ 0.000000] software IO TLB: mapped [mem 0x00000000fa000000-0x00000000fe000000] (64MB) | |
| [ 0.000000] Memory: 3873444K/4194304K available (16768K kernel code, 4678K rwdata, 11172K rodata, 9856K init, 608K bss, 288092K reserved, 32768K cma-reserved) | |
| [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 | |
| [ 0.000000] rcu: Preemptible hierarchical RCU implementation. | |
| [ 0.000000] rcu: RCU event tracing is enabled. | |
| [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2. | |
| [ 0.000000] Trampoline variant of Tasks RCU enabled. | |
| [ 0.000000] Tracing variant of Tasks RCU enabled. | |
| [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. | |
| [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 | |
| [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 | |
| [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode | |
| [ 0.000000] GICv3: 960 SPIs implemented | |
| [ 0.000000] GICv3: 0 Extended SPIs implemented | |
| [ 0.000000] Root IRQ handler: gic_handle_irq | |
| [ 0.000000] GICv3: GICv3 features: 16 PPIs | |
| [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000 | |
| [ 0.000000] ITS [mem 0x01820000-0x0182ffff] | |
| [ 0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS | |
| [ 0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19 | |
| [ 0.000000] ITS@0x0000000001820000: allocated 524288 Devices @880800000 (flat, esz 8, psz 64K, shr 0) | |
| [ 0.000000] ITS: using cache flushing for cmd queue | |
| [ 0.000000] GICv3: using LPI property table @0x0000000880040000 | |
| [ 0.000000] GIC: using cache flushing for LPI property table | |
| [ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000880050000 | |
| [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. | |
| [ 0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys). | |
| [ 0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns | |
| [ 0.000000] sched_clock: 58 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns | |
| [ 0.008697] Console: colour dummy device 80x25 | |
| [ 0.013279] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000) | |
| [ 0.023951] pid_max: default: 32768 minimum: 301 | |
| [ 0.028696] LSM: initializing lsm=capability,integrity | |
| [ 0.034005] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) | |
| [ 0.041583] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) | |
| [ 0.050076] cacheinfo: Unable to detect cache hierarchy for CPU 0 | |
| [ 0.056753] RCU Tasks: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1. | |
| [ 0.064012] RCU Tasks Trace: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1. | |
| [ 0.071884] rcu: Hierarchical SRCU implementation. | |
| [ 0.076782] rcu: Max phase no-delay instances is 1000. | |
| [ 0.082293] Platform MSI: msi-controller@1820000 domain created | |
| [ 0.088449] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created | |
| [ 0.097757] fsl-mc MSI: msi-controller@1820000 domain created | |
| [ 0.104452] EFI services will not be available. | |
| [ 0.109196] smp: Bringing up secondary CPUs ... | |
| I/TC: Secondary CPU 1 initializing | |
| I/TC: Secondary CPU 1 switching to normal world boot | |
| [ 0.122348] Detected PIPT I-cache on CPU1 | |
| [ 0.122378] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000 | |
| [ 0.122393] GICv3: CPU1: using allocated LPI pending table @0x0000000880060000 | |
| [ 0.122426] CPU1: Booted secondary processor 0x0000000001 [0x411fd080] | |
| [ 0.122484] smp: Brought up 1 node, 2 CPUs | |
| [ 0.151833] SMP: Total of 2 processors activated. | |
| [ 0.156637] CPU: All CPU(s) started at EL2 | |
| [ 0.160840] CPU features: detected: 32-bit EL0 Support | |
| [ 0.166090] CPU features: detected: 32-bit EL1 Support | |
| [ 0.171338] CPU features: detected: CRC32 instructions | |
| [ 0.176603] alternatives: applying system-wide alternatives | |
| [ 0.183506] devtmpfs: initialized | |
| [ 0.191047] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns | |
| [ 0.201021] futex hash table entries: 512 (order: 3, 32768 bytes, linear) | |
| [ 0.208521] pinctrl core: initialized pinctrl subsystem | |
| [ 0.215062] DMI not present or invalid. | |
| [ 0.219419] NET: Registered PF_NETLINK/PF_ROUTE protocol family | |
| [ 0.225908] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations | |
| [ 0.233219] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations | |
| [ 0.241256] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations | |
| [ 0.249375] audit: initializing netlink subsys (disabled) | |
| [ 0.254991] audit: type=2000 audit(0.164:1): state=initialized audit_enabled=0 res=1 | |
| [ 0.255628] thermal_sys: Registered thermal governor 'step_wise' | |
| [ 0.262920] thermal_sys: Registered thermal governor 'power_allocator' | |
| [ 0.269092] cpuidle: using governor menu | |
| [ 0.279877] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. | |
| [ 0.286847] ASID allocator initialised with 65536 entries | |
| [ 0.293404] Serial: AMBA PL011 UART driver | |
| [ 0.308672] platform a40000.pinctrl: Fixed dependency cycle(s) with /bus@100000/pinctrl@a40000/mcu-cpsw-cpts | |
| [ 0.319677] Modules: 21952 pages in range for non-PLT usage | |
| [ 0.319681] Modules: 513472 pages in range for PLT usage | |
| [ 0.325844] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages | |
| [ 0.338212] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page | |
| [ 0.344615] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages | |
| [ 0.351549] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page | |
| [ 0.357951] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages | |
| [ 0.364886] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page | |
| [ 0.371287] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages | |
| [ 0.378222] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page | |
| [ 0.385573] ACPI: Interpreter disabled. | |
| [ 0.390826] k3-chipinfo 43000014.chipid: Family:J7200 rev:SR2.0 JTAGID[0x1bb6d02f] Detected | |
| [ 0.400179] iommu: Default domain type: Translated | |
| [ 0.405082] iommu: DMA domain TLB invalidation policy: strict mode | |
| [ 0.411560] SCSI subsystem initialized | |
| [ 0.415588] usbcore: registered new interface driver usbfs | |
| [ 0.421209] usbcore: registered new interface driver hub | |
| [ 0.426648] usbcore: registered new device driver usb | |
| [ 0.432343] pps_core: LinuxPPS API ver. 1 registered | |
| [ 0.437418] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> | |
| [ 0.446759] PTP clock support registered | |
| [ 0.450841] EDAC MC: Ver: 3.0.0 | |
| [ 0.454416] scmi_core: SCMI protocol bus registered | |
| [ 0.459986] FPGA manager framework | |
| [ 0.463506] Advanced Linux Sound Architecture Driver Initialized. | |
| [ 0.470229] vgaarb: loaded | |
| [ 0.473240] clocksource: Switched to clocksource arch_sys_counter | |
| [ 0.479602] VFS: Disk quotas dquot_6.6.0 | |
| [ 0.483626] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) | |
| [ 0.490756] pnp: PnP ACPI: disabled | |
| [ 0.497548] NET: Registered PF_INET protocol family | |
| [ 0.502813] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear) | |
| [ 0.511848] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear) | |
| [ 0.520621] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) | |
| [ 0.528547] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear) | |
| [ 0.536775] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear) | |
| [ 0.545512] TCP: Hash tables configured (established 32768 bind 32768) | |
| [ 0.552354] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear) | |
| [ 0.559288] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear) | |
| [ 0.566720] NET: Registered PF_UNIX/PF_LOCAL protocol family | |
| [ 0.572856] RPC: Registered named UNIX socket transport module. | |
| [ 0.578920] RPC: Registered udp transport module. | |
| [ 0.583723] RPC: Registered tcp transport module. | |
| [ 0.588526] RPC: Registered tcp-with-tls transport module. | |
| [ 0.594129] RPC: Registered tcp NFSv4.1 backchannel transport module. | |
| [ 0.600717] PCI: CLS 0 bytes, default 64 | |
| [ 0.604927] kvm [1]: IPA Size Limit: 44 bits | |
| [ 0.610192] kvm [1]: vgic-v2@6f020000 | |
| [ 0.613953] kvm [1]: GIC system register CPU interface enabled | |
| [ 0.619926] kvm [1]: vgic interrupt IRQ9 | |
| [ 0.623946] kvm [1]: Hyp mode initialized successfully | |
| [ 0.629893] Initialise system trusted keyrings | |
| [ 0.634578] workingset: timestamp_bits=42 max_order=20 bucket_order=0 | |
| [ 0.641357] squashfs: version 4.0 (2009/01/31) Phillip Lougher | |
| [ 0.647477] NFS: Registering the id_resolver key type | |
| [ 0.652660] Key type id_resolver registered | |
| [ 0.656932] Key type id_legacy registered | |
| [ 0.661039] nfs4filelayout_init: NFSv4 File Layout Driver Registering... | |
| [ 0.667888] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... | |
| [ 0.675550] 9p: Installing v9fs 9p2000 file system support | |
| [ 0.702070] Key type asymmetric registered | |
| [ 0.706255] Asymmetric key parser 'x509' registered | |
| [ 0.711265] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245) | |
| [ 0.718829] io scheduler mq-deadline registered | |
| [ 0.723457] io scheduler kyber registered | |
| [ 0.727573] io scheduler bfq registered | |
| [ 0.735830] pinctrl-single 4301c000.pinctrl: 13 pins, size 52 | |
| [ 0.741833] pinctrl-single 4301c038.pinctrl: 2 pins, size 8 | |
| [ 0.747626] pinctrl-single 4301c068.pinctrl: 59 pins, size 236 | |
| [ 0.753740] pinctrl-single 4301c174.pinctrl: 8 pins, size 32 | |
| [ 0.759679] pinctrl-single 11c000.pinctrl: 67 pins, size 268 | |
| [ 0.765617] pinctrl-single 11c11c.pinctrl: 3 pins, size 12 | |
| [ 0.771605] pinctrl-single a40000.pinctrl: 512 pins, size 2048 | |
| [ 0.781518] EINJ: ACPI disabled. | |
| [ 0.800067] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled | |
| [ 0.808542] msm_serial: driver initialized | |
| [ 0.812959] SuperH (H)SCI(F) driver initialized | |
| [ 0.817679] STM32 USART driver initialized | |
| [ 0.825884] loop: module loaded | |
| [ 0.829823] megasas: 07.727.03.00-rc1 | |
| [ 0.837197] tun: Universal TUN/TAP device driver, 1.6 | |
| [ 0.842982] thunder_xcv, ver 1.0 | |
| [ 0.846303] thunder_bgx, ver 1.0 | |
| [ 0.849606] nicpf, ver 1.0 | |
| [ 0.853033] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version | |
| [ 0.860418] hns3: Copyright (c) 2017 Huawei Corporation. | |
| [ 0.865868] hclge is initializing | |
| [ 0.869269] e1000: Intel(R) PRO/1000 Network Driver | |
| [ 0.874250] e1000: Copyright (c) 1999-2006 Intel Corporation. | |
| [ 0.880131] e1000e: Intel(R) PRO/1000 Network Driver | |
| [ 0.885201] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. | |
| [ 0.891257] igb: Intel(R) Gigabit Ethernet Network Driver | |
| [ 0.896771] igb: Copyright (c) 2007-2014 Intel Corporation. | |
| [ 0.902472] igbvf: Intel(R) Gigabit Virtual Function Network Driver | |
| [ 0.908884] igbvf: Copyright (c) 2009 - 2012 Intel Corporation. | |
| [ 0.915135] sky2: driver version 1.30 | |
| [ 0.919670] VFIO - User Level meta-driver version: 0.3 | |
| [ 0.926621] usbcore: registered new interface driver usb-storage | |
| [ 0.934467] i2c_dev: i2c /dev entries driver | |
| [ 0.943066] sdhci: Secure Digital Host Controller Interface driver | |
| [ 0.949415] sdhci: Copyright(c) Pierre Ossman | |
| [ 0.954336] Synopsys Designware Multimedia Card Interface Driver | |
| [ 0.961055] sdhci-pltfm: SDHCI platform and OF driver helper | |
| [ 0.967936] ledtrig-cpu: registered to indicate activity on CPUs | |
| [ 0.974953] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping .... | |
| [ 0.982129] usbcore: registered new interface driver usbhid | |
| [ 0.987831] usbhid: USB HID core driver | |
| [ 0.993817] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available | |
| [ 1.003461] optee: probing for conduit method. | |
| I/TC: Reserved shared memory is enabled | |
| I/TC: Dynamic shared memory is enabled | |
| I/TC: Normal World virtualization support is disabled | |
| I/TC: Asynchronous notifications are disabled | |
| [ 1.008027] optee: revision 3.20 (8e74d476) | |
| [ 1.024478] optee: dynamic shared memory is enabled | |
| [ 1.034193] random: crng init done | |
| [ 1.037738] optee: initialized driver | |
| [ 1.043775] NET: Registered PF_PACKET protocol family | |
| [ 1.049004] 9pnet: Installing 9P2000 support | |
| [ 1.053409] Key type dns_resolver registered | |
| [ 1.061903] registered taskstats version 1 | |
| [ 1.066159] Loading compiled-in X.509 certificates | |
| [ 1.088227] ti-sci 44083000.system-controller: ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| [ 1.100437] debugfs: Directory 'pd:240' with parent 'pm_genpd' already present! | |
| [ 1.126174] omap_i2c 42120000.i2c: bus 0 rev0.12 at 400 kHz | |
| [ 1.132811] pca953x 1-0021: supply vcc not found, using dummy regulator | |
| [ 1.139667] pca953x 1-0021: using no AI | |
| [ 1.165674] pca953x 1-0020: supply vcc not found, using dummy regulator | |
| [ 1.172489] pca953x 1-0020: using no AI | |
| [ 1.177044] pca953x 1-0022: supply vcc not found, using dummy regulator | |
| [ 1.183851] pca953x 1-0022: using AI | |
| [ 1.188147] omap_i2c 2000000.i2c: bus 1 rev0.12 at 400 kHz | |
| [ 1.194621] pca953x 2-0020: supply vcc not found, using dummy regulator | |
| [ 1.201463] pca953x 2-0020: using no AI | |
| [ 1.229568] omap_i2c 2010000.i2c: bus 2 rev0.12 at 400 kHz | |
| [ 1.235547] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 137 domain created | |
| [ 1.244260] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 131 domain created | |
| [ 1.253741] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 213 domain created | |
| [ 1.262476] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 209 created | |
| [ 1.273956] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235 | |
| [ 1.283862] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled | |
| [ 1.290626] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64 | |
| [ 1.301586] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[120,200] sci-dev-id:211 | |
| [ 1.311755] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled | |
| [ 1.318514] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64 | |
| [ 1.327365] 40a00000.serial: ttyS1 at MMIO 0x40a00000 (irq = 251, base_baud = 6000000) is a 8250 | |
| [ 1.337846] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 252, base_baud = 3000000) is a 8250 | |
| [ 1.346706] printk: legacy console [ttyS2] enabled | |
| [ 1.346706] printk: legacy console [ttyS2] enabled | |
| [ 1.356380] printk: legacy bootconsole [ns16550a0] disabled | |
| [ 1.356380] printk: legacy bootconsole [ns16550a0] disabled | |
| [ 1.370596] 2810000.serial: ttyS3 at MMIO 0x2810000 (irq = 253, base_baud = 3000000) is a 8250 | |
| [ 1.382753] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode | |
| [ 1.429245] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000 | |
| [ 1.439098] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867 | |
| [ 1.447376] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000 | |
| [ 1.460225] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4 | |
| [ 1.467434] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64 | |
| [ 1.509351] mmc0: CQHCI version 5.10 | |
| [ 1.525210] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8) | |
| [ 1.538568] ti-udma 31150000.dma-controller: Channels: 50 (tchan: 25, rchan: 25, gp-rflow: 8) | |
| [ 1.553888] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit | |
| [ 1.555252] 7 fixed-partitions partitions found on MTD device 47040000.spi.0 | |
| [ 1.568616] Creating 7 MTD partitions on "47040000.spi.0": | |
| [ 1.574133] 0x000000000000-0x000000100000 : "ospi.tiboot3" | |
| [ 1.580872] 0x000000100000-0x000000300000 : "ospi.tispl" | |
| [ 1.587357] 0x000000300000-0x000000700000 : "ospi.u-boot" | |
| [ 1.594043] 0x000000700000-0x000000740000 : "ospi.env" | |
| [ 1.600379] 0x000000740000-0x000000780000 : "ospi.env.backup" | |
| [ 1.607197] 0x000000800000-0x000003fc0000 : "ospi.rootfs" | |
| [ 1.613710] 0x000003fc0000-0x000004000000 : "ospi.phypattern" | |
| [ 1.624057] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode | |
| [ 1.669272] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000 | |
| [ 1.679922] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867 | |
| [ 1.688275] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000 | |
| [ 1.701267] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4 | |
| [ 1.708499] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64 | |
| [ 1.720447] mmc0: Command Queue Engine enabled | |
| [ 1.724937] mmc0: new HS400 MMC card at address 0001 | |
| [ 1.730484] mmcblk0: mmc0:0001 S0J56X 14.8 GiB | |
| [ 1.736774] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48 | |
| [ 1.745333] mmcblk0: p1 | |
| [ 1.748552] mmcblk0boot0: mmc0:0001 S0J56X 31.5 MiB | |
| [ 1.750092] clk: Disabling unused clocks | |
| [ 1.754168] mmc1: CQHCI version 5.10 | |
| [ 1.760675] ALSA device list: | |
| [ 1.761780] mmcblk0boot1: mmc0:0001 S0J56X 31.5 MiB | |
| [ 1.764075] No soundcards found. | |
| [ 1.770395] mmcblk0rpmb: mmc0:0001 S0J56X 4.00 MiB, chardev (234:0) | |
| [ 1.809137] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit | |
| [ 1.816886] Waiting for root device PARTUUID=aa7aea62-02... | |
| [ 1.874772] mmc1: new ultra high speed SDR104 SDHC card at address aaaa | |
| [ 1.882026] mmcblk1: mmc1:aaaa SC16G 14.8 GiB | |
| [ 1.891600] mmcblk1: p1 p2 | |
| [ 1.921209] EXT4-fs (mmcblk1p2): mounted filesystem 4e3e7bf3-fbb1-4666-bc99-003ef4ba86a4 r/w with ordered data mode. Quota mode: none. | |
| [ 1.933354] VFS: Mounted root (ext4 filesystem) on device 179:98. | |
| [ 1.943050] devtmpfs: mounted | |
| [ 1.955235] Freeing unused kernel memory: 9856K | |
| [ 1.960015] Run /sbin/init as init process | |
| [ 2.125493] systemd[1]: System time before build time, advancing clock. | |
| [ 2.158912] systemd[1]: systemd 250.5+ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK +XKBCOMMON +UTMP +SYSVINIT default-hierarchy=hybrid) | |
| [ 2.190624] systemd[1]: Detected architecture arm64. | |
| Welcome to Arago 2023.04! | |
| [ 2.256033] systemd[1]: Hostname set to <j7200-evm>. | |
| [ 2.381001] systemd-sysv-generator[86]: SysV service '/etc/init.d/netopeer2-server' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust. | |
| [ 2.405772] systemd-sysv-generator[86]: SysV service '/etc/init.d/sysrepo' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust. | |
| [ 2.433168] systemd-sysv-generator[86]: SysV service '/etc/init.d/thermal-zone-init' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust. | |
| [ 2.641583] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6. | |
| [ 2.650531] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6. | |
| [ 2.687033] systemd[1]: /lib/systemd/system/bt-enable.service:9: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether. | |
| [ 2.750608] systemd[1]: /etc/systemd/system/sync-clocks.service:11: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether. | |
| [ 2.827246] systemd[1]: Queued start job for default target Graphical Interface. | |
| [ 2.886835] systemd[1]: Created slice Slice /system/getty. | |
| [ OK ] Created slice Slice /system/getty. | |
| [ 2.912015] systemd[1]: Created slice Slice /system/modprobe. | |
| [ OK ] Created slice Slice /system/modprobe. | |
| [ 2.936010] systemd[1]: Created slice Slice /system/serial-getty. | |
| [ OK ] Created slice Slice /system/serial-getty. | |
| [ 2.959487] systemd[1]: Created slice User and Session Slice. | |
| [ OK ] Created slice User and Session Slice. | |
| [ 2.981643] systemd[1]: Started Dispatch Password Requests to Console Directory Watch. | |
| [ OK ] Started Dispatch Password �ts to Console Directory Watch. | |
| [ 3.005556] systemd[1]: Started Forward Password Requests to Wall Directory Watch. | |
| [ OK ] Started Forward Password R�uests to Wall Directory Watch. | |
| [ 3.029678] systemd[1]: Reached target Path Units. | |
| [ OK ] Reached target Path Units. | |
| [ 3.045404] systemd[1]: Reached target Remote File Systems. | |
| [ OK ] Reached target Remote File Systems. | |
| [ 3.065401] systemd[1]: Reached target Slice Units. | |
| [ OK ] Reached target Slice Units. | |
| [ 3.081487] systemd[1]: Reached target Swaps. | |
| [ OK ] Reached target Swaps. | |
| [ 3.142925] systemd[1]: Listening on RPCbind Server Activation Socket. | |
| [ OK ] Listening on RPCbind Server Activation Socket. | |
| [ 3.165508] systemd[1]: Reached target RPC Port Mapper. | |
| [ OK ] Reached target RPC Port Mapper. | |
| [ 3.193443] systemd[1]: Listening on Process Core Dump Socket. | |
| [ OK ] Listening on Process Core Dump Socket. | |
| [ 3.213681] systemd[1]: Listening on initctl Compatibility Named Pipe. | |
| [ OK ] Listening on initctl Compatibility Named Pipe. | |
| [ 3.238033] systemd[1]: Listening on Journal Audit Socket. | |
| [ OK ] Listening on Journal Audit Socket. | |
| [ 3.261826] systemd[1]: Listening on Journal Socket (/dev/log). | |
| [ OK ] Listening on Journal Socket (/dev/log). | |
| [ 3.285870] systemd[1]: Listening on Journal Socket. | |
| [ OK ] Listening on Journal Socket. | |
| [ 3.306032] systemd[1]: Listening on Network Service Netlink Socket. | |
| [ OK ] Listening on Network Service Netlink Socket. | |
| [ 3.329932] systemd[1]: Listening on udev Control Socket. | |
| [ OK ] Listening on udev Control Socket. | |
| [ 3.349706] systemd[1]: Listening on udev Kernel Socket. | |
| [ OK ] Listening on udev Kernel Socket. | |
| [ 3.369779] systemd[1]: Listening on User Database Manager Socket. | |
| [ OK ] Listening on User Database Manager Socket. | |
| [ 3.417718] systemd[1]: Mounting Huge Pages File System... | |
| Mounting Huge Pages File System... | |
| [ 3.442182] systemd[1]: Mounting POSIX Message Queue File System... | |
| Mounting POSIX Message Queue File System... | |
| [ 3.470263] systemd[1]: Mounting Kernel Debug File System... | |
| Mounting Kernel Debug File System... | |
| [ 3.485838] systemd[1]: Kernel Trace File System was skipped because of a failed condition check (ConditionPathExists=/sys/kernel/tracing). | |
| [ 3.525727] systemd[1]: Mounting Temporary Directory /tmp... | |
| Mounting Temporary Directory /tmp... | |
| [ 3.541862] systemd[1]: Create List of Static Device Nodes was skipped because of a failed condition check (ConditionFileNotEmpty=/lib/modules/6.8.0-rc2-next-20240202-00001-ge9c262b773c7/modules.devname). | |
| [ 3.564523] systemd[1]: Starting Load Kernel Module configfs... | |
| Starting Load Kernel Module configfs... | |
| [ 3.585800] systemd[1]: Starting Load Kernel Module drm... | |
| Starting Load Kernel Module drm... | |
| [ 3.605765] systemd[1]: Starting Load Kernel Module fuse... | |
| Starting Load Kernel Module fuse... | |
| [ 3.629199] systemd[1]: Starting RPC Bind... | |
| Starting RPC Bind... | |
| [ 3.645649] systemd[1]: File System Check on Root Device was skipped because of a failed condition check (ConditionPathIsReadWrite=!/). | |
| [ 3.690113] systemd[1]: Starting Journal Service... | |
| Starting Journal Service... | |
| [ 3.746262] systemd[1]: Starting Load Kernel Modules... | |
| Starting Load Kernel Modules... | |
| [ 3.770597] systemd[1]: Starting Generate network units from Kernel command line... | |
| Starting Generate network �ts from Kernel command line... | |
| [ 3.803323] systemd[1]: Starting Remount Root and Kernel File Systems... | |
| Starting Remount Root and Kernel File Systems... | |
| [ 3.826841] systemd[1]: Starting Coldplug All udev Devices... | |
| Starting Coldplug All udev Devices... | |
| [ 3.868642] systemd[1]: Started RPC Bind. | |
| [ OK ] Started RPC Bind. | |
| [ 3.882453] EXT4-fs (mmcblk1p2): re-mounted 4e3e7bf3-fbb1-4666-bc99-003ef4ba86a4 r/w. Quota mode: none. | |
| [ 3.894503] systemd[1]: Started Journal Service. | |
| [ OK ] Started Journal Service. | |
| [ OK ] Mounted Huge Pages File System. | |
| [ OK ] Mounted POSIX Message Queue File System. | |
| [ OK ] Mounted Kernel Debug File System. | |
| [ OK ] Mounted Temporary Directory /tmp. | |
| [ OK ] Finished Load Kernel Module configfs. | |
| [ OK ] Finished Load Kernel Module drm. | |
| [ OK ] Finished Load Kernel Module fuse. | |
| [FAILED] Failed to start Load Kernel Modules. | |
| See 'systemctl status systemd-modules-load.service' for details. | |
| [ OK ] Finished Generate network units from Kernel command line. | |
| [ OK ] Finished Remount Root and Kernel File Systems. | |
| Mounting Kernel Configuration File System... | |
| Starting Flush Journal to Persistent Storage... | |
| [ 4.161866] systemd-journald[100]: Received client request to flush runtime journal. | |
| Starting Apply Kernel Variables... | |
| Starting Create Static Device Nodes in /dev... | |
| [ OK ] Mounted Kernel Configuration File System. | |
| [ OK ] Finished Flush Journal to Persistent Storage. | |
| [ OK ] Finished Apply Kernel Variables. | |
| [ OK ] Finished Create Static Device Nodes in /dev. | |
| [ OK ] Reached target Preparation for Local File Systems. | |
| Mounting /media/ram... | |
| Mounting /var/volatile... | |
| [ 4.390415] audit: type=1334 audit(1651167747.264:2): prog-id=5 op=LOAD | |
| [ 4.397746] audit: type=1334 audit(1651167747.272:3): prog-id=6 op=LOAD | |
| Starting Rule-based Manage�for Device Events and Files... | |
| [ OK ] Mounted /media/ram. | |
| [ OK ] Mounted /var/volatile. | |
| Starting Load/Save Random Seed... | |
| [ OK ] Finished Load/Save Random Seed. | |
| [ OK ] Started Rule-based Manager for Device Events and Files. | |
| [ OK ] Finished Coldplug All udev Devices. | |
| [ OK ] Found device /dev/ttyS2. | |
| [ OK ] Found device /dev/disk/by-uuid/81A5-5E73. | |
| Mounting /boot... | |
| [ 7.796213] FAT-fs (mmcblk1p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck. | |
| [ OK ] Mounted /boot. | |
| [ OK ] Reached target Local File Systems. | |
| Starting Create Volatile Files and Directories... | |
| [ OK ] Finished Create Volatile Files and Directories. | |
| Starting Network Time Synchronization... | |
| Starting Record System Boot/Shutdown in UTMP... | |
| [ OK ] Finished Record System Boot/Shutdown in UTMP. | |
| [ 8.215715] systemd-journald[100]: Oldest entry in /run/log/journal/11a1f5339a9b4ed0b552d1cfcc1c31b7/system.journal is older than the configured file retention duration (1month), suggesting rotation. | |
| [ 8.233589] systemd-journald[100]: /run/log/journal/11a1f5339a9b4ed0b552d1cfcc1c31b7/system.journal: Journal header limits reached or header out-of-date, rotating. | |
| [ OK ] Started Network Time Synchronization. | |
| [ OK ] Reached target System Initialization. | |
| [ OK ] Started Daily Cleanup of Temporary Directories. | |
| [ OK ] Reached target System Time Set. | |
| [ OK ] Started Daily rotation of log files. | |
| [ OK ] Reached target Timer Units. | |
| [ OK ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket. | |
| [ OK ] Listening on D-Bus System Message Bus Socket. | |
| Starting Docker Socket for the API... | |
| [ OK ] Listening on dropbear.socket. | |
| [ OK ] Listening on PC/SC Smart Card Daemon Activation Socket. | |
| Starting Weston socket... | |
| Starting D-Bus System Message Bus... | |
| Starting Reboot and dump vmcore via kexec... | |
| [ OK ] Listening on Docker Socket for the API. | |
| [ OK ] Listening on Weston socket. | |
| [ OK ] Finished Reboot and dump vmcore via kexec. | |
| [ OK ] Reached target Socket Units. | |
| [ OK ] Started D-Bus System Message Bus. | |
| [ OK ] Reached target Basic System. | |
| [ OK ] Started Job spooling tools. | |
| [ OK ] Started Periodic Command Scheduler. | |
| Starting Print notice about GPLv3 packages... | |
| Starting IPv6 Packet Filtering Framework... | |
| Starting IPv4 Packet Filtering Framework... | |
| [ OK ] Started irqbalance daemon. | |
| Starting Lighttpd Daemon... | |
| [ OK ] Started strongSwan IPsec I�IKEv2 daemon using ipsec.conf. | |
| [ 8.870881] audit: type=1334 audit(1707106867.544:4): prog-id=7 op=LOAD | |
| [ 8.878191] audit: type=1334 audit(1707106867.552:5): prog-id=8 op=LOAD | |
| Starting User Login Management... | |
| [ OK ] Started TEE Supplicant. | |
| Starting Telnet Server... | |
| [FAILED] Failed to start Print notice about GPLv3 packages. | |
| See 'systemctl status gplv3-notice.service' for details. | |
| [ OK ] Finished IPv6 Packet Filtering Framework. | |
| [ OK ] Finished IPv4 Packet Filtering Framework. | |
| [ OK ] Started Lighttpd Daemon. | |
| [ OK ] Finished Telnet Server. | |
| [ OK ] Reached target Preparation for Network. | |
| Starting Network Configuration... | |
| [ OK ] Started User Login Management. | |
| [ OK ] Started Network Configuration. | |
| [ 9.384095] am65-cpsw-nuss 46000000.ethernet eth0: PHY [46000f00.mdio:00] driver [TI DP83867] (irq=POLL) | |
| [ 9.393623] am65-cpsw-nuss 46000000.ethernet eth0: configuring for phy/rgmii-rxid link mode | |
| Starting Network Name Resolution... | |
| [ OK ] Started Network Name Resolution. | |
| [ OK ] Reached target Network. | |
| [ OK ] Reached target Host and Network Name Lookups. | |
| Starting Avahi mDNS/DNS-SD Stack... | |
| Starting Enable and configure wl18xx bluetooth stack... | |
| Starting containerd container runtime... | |
| [ OK ] Started Netperf Benchmark Server. | |
| [ OK ] Started NFS status monitor for NFSv2/3 locking.. | |
| Starting Permit User Sessions... | |
| [FAILED] Failed to start Enable and�figure wl18xx bluetooth stack. | |
| See 'systemctl status bt-enable.service' for details. | |
| [ OK ] Finished Permit User Sessions. | |
| [ OK ] Started Avahi mDNS/DNS-SD Stack. | |
| [ OK ] Started Getty on tty1. | |
| [ OK ] Started Serial Getty on ttyS2. | |
| [ OK ] Reached target Login Prompts. | |
| Starting Synchronize System and HW clocks... | |
| Starting Weston, a Wayland�ositor, as a system service... | |
| [FAILED] Failed to start Synchronize System and HW clocks. | |
| See 'systemctl status sync-clocks.service' for details. | |
| [ 10.284202] audit: type=1334 audit(1707106868.956:6): prog-id=9 op=LOAD | |
| [ 10.293642] audit: type=1334 audit(1707106868.964:7): prog-id=10 op=LOAD | |
| Starting User Database Manager... | |
| [ OK ] Started User Database Manager. | |
| [ OK ] Created slice User Slice of UID 1000. | |
| Starting User Runtime Directory /run/user/1000... | |
| [ OK ] Finished User Runtime Directory /run/user/1000. | |
| Starting User Manager for UID 1000... | |
| [ 10.672322] audit: type=1006 audit(1707106869.344:8): pid=486 uid=0 old-auid=4294967295 auid=1000 tty=(none) old-ses=4294967295 ses=1 res=1 | |
| [ 10.684915] audit: type=1300 audit(1707106869.344:8): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=ffffc5150cb8 a2=4 a3=ffffa07fe020 items=0 ppid=1 pid=486 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=1 comm="(systemd)" exe="/lib/systemd/systemd" key=(null) | |
| [ 10.713893] audit: type=1327 audit(1707106869.344:8): proctitle="(systemd)" | |
| [ OK ] Started containerd container runtime. | |
| [ OK ] Started User Manager for UID 1000. | |
| [ OK ] Started Session c1 of User weston. | |
| [ 11.343792] audit: type=1006 audit(1707106870.016:9): pid=476 uid=0 old-auid=4294967295 auid=1000 tty=tty7 old-ses=4294967295 ses=2 res=1 | |
| [ 11.356317] audit: type=1300 audit(1707106870.016:9): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=ffffc5150cb8 a2=4 a3=ffffa07fe020 items=0 ppid=1 pid=476 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=tty7 ses=2 comm="(weston)" exe="/lib/systemd/systemd" key=(null) | |
| [ 11.382802] audit: type=1327 audit(1707106870.016:9): proctitle="(weston)" | |
| [FAILED] Failed to start Weston, a �mpositor, as a system service. | |
| See 'systemctl status weston.service' for details. | |
| [DEPEND] Dependency failed for Matrix GUI. | |
| [ OK ] Reached target Multi-User System. | |
| [ OK ] Reached target Graphical Interface. | |
| Starting Record Runlevel Change in UTMP... | |
| [ OK ] Finished Record Runlevel Change in UTMP. | |
| _____ _____ _ _ | |
| | _ |___ ___ ___ ___ | _ |___ ___ |_|___ ___| |_ | |
| | | _| .'| . | . | | __| _| . | | | -_| _| _| | |
| |__|__|_| |__,|_ |___| |__| |_| |___|_| |___|___|_| | |
| |___| |___| | |
| Arago Project j7200-evm - | |
| Arago 2023.04 j7200-evm - | |
| j7200-evm login: [ 13.482465] am65-cpsw-nuss 46000000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx | |
| [ 14.558338] audit: type=1334 audit(1707106873.232:10): prog-id=11 op=LOAD | |
| [ 14.565461] audit: type=1334 audit(1707106873.240:11): prog-id=12 op=LOAD | |
| j7200-evm login: root | |
| [ 24.022221] audit: type=1006 audit(1707106882.692:12): pid=508 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=3 res=1 | |
| [ 24.034685] audit: type=1300 audit(1707106882.692:12): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=ffffc5150cb8 a2=1 a3=ffffa07fe020 items=0 ppid=1 pid=508 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="(systemd)" exe="/lib/systemd/systemd" key=(null) | |
| [ 24.061664] audit: type=1327 audit(1707106882.692:12): proctitle="(systemd)" | |
| [ 24.069522] audit: type=1334 audit(1707106882.720:13): prog-id=13 op=LOAD | |
| [ 24.076919] audit: type=1300 audit(1707106882.720:13): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=ffffdcef1d80 a2=78 a3=0 items=0 ppid=1 pid=508 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/lib/systemd/systemd" key=(null) | |
| [ 24.102935] audit: type=1327 audit(1707106882.720:13): proctitle="(systemd)" | |
| [ 24.110478] audit: type=1334 audit(1707106882.732:14): prog-id=13 op=UNLOAD | |
| [ 24.118019] audit: type=1300 audit(1707106882.732:14): arch=c00000b7 syscall=57 success=yes exit=0 a0=8 a1=ffffb4c92020 a2=0 a3=ffffb4c927e0 items=0 ppid=1 pid=508 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/lib/systemd/systemd" key=(null) | |
| [ 24.144559] audit: type=1327 audit(1707106882.732:14): proctitle="(systemd)" | |
| [ 24.151984] audit: type=1334 audit(1707106882.736:15): prog-id=14 op=LOAD | |
| root@j7200-evm:~# cat k3dum conf dump clock | |
| |------------------------------------------------------------------------------| | |
| | VERSION INFO | | |
| |------------------------------------------------------------------------------| | |
| | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023) | | |
| | SoC | J7200 SR2.0 | | |
| | SYSFW | ABI: 3.1 (firmware version 0x0009 '9.1.9--v09.01.09 (Kool Koala))') | | |
| |------------------------------------------------------------------------------| | |
| |--------------------------------------------------------------------------------------------------------------------------------------------------| | |
| | Device ID | Clock ID | Clock Name | Status | Clock Frequency | | |
| |--------------------------------------------------------------------------------------------------------------------------------------------------| | |
| | 4 | 0 | DEV_A72SS0_CORE0_ARM_CLK_CLK | CLK_STATE_READY | 748800000 | | |
| | 4 | 1 | DEV_A72SS0_CORE0_MSMC_CLK | CLK_STATE_READY | 1000000000 | | |
| | 4 | 2 | DEV_A72SS0_CORE0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | |
| | 202 | 2 | DEV_A72SS0_CORE0_0_ARM_CLK_CLK | CLK_STATE_READY | 748800000 | | |
| | 203 | 0 | DEV_A72SS0_CORE0_1_ARM_CLK_CLK | CLK_STATE_READY | 748800000 | | |
| | 2 | 0 | DEV_ATL0_VBUS_CLK | CLK_STATE_READY | 250000000 | | |
| | 2 | 1 | DEV_ATL0_ATL_CLK | CLK_STATE_READY | 294912000 | | |
| | 2 | 2 | DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK | CLK_STATE_READY | 294912000 | | |
| | 2 | 3 | DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 2 | 6 | DEV_ATL0_ATL_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT7_CLK | CLK_STATE_READY | 200000000 | | |
| | 2 | 7 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 2 | 8 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 2 | 10 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_READY | 0 | | |
| | 2 | 11 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_READY | 0 | | |
| | 2 | 12 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_READY | 0 | | |
| | 2 | 13 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 1 | DEV_BOARD0_I2C1_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 2 | DEV_BOARD0_MCASP0_ACLKR_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 3 | DEV_BOARD0_SPI2_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 4 | DEV_BOARD0_I2C3_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 5 | DEV_BOARD0_OBSCLK2_IN | CLK_STATE_READY | 500000000 | | |
| | 157 | 6 | DEV_BOARD0_MCU_I3C0_SCL_IN | CLK_STATE_READY | 0 | | |
| | 157 | 7 | DEV_BOARD0_MCU_HYPERBUS0_CKN_IN | CLK_STATE_READY | 0 | | |
| | 157 | 8 | DEV_BOARD0_I2C4_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 9 | DEV_BOARD0_RGMII3_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 11 | DEV_BOARD0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 12 | DEV_BOARD0_SPI1_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 13 | DEV_BOARD0_GPMC0_CLKOUT_IN | CLK_STATE_READY | 0 | | |
| | 157 | 14 | DEV_BOARD0_MCU_OBSCLK0_IN | CLK_STATE_READY | 1000000000 | | |
| | 157 | 15 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 | CLK_STATE_READY | 1000000000 | | |
| | 157 | 16 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 157 | 31 | DEV_BOARD0_MCU_I3C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 32 | DEV_BOARD0_SPI3_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 33 | DEV_BOARD0_MCASP0_ACLKX_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 34 | DEV_BOARD0_MCASP1_ACLKR_IN | CLK_STATE_READY | 0 | | |
| | 157 | 35 | DEV_BOARD0_CLKOUT_IN | CLK_STATE_READY | 50000000 | | |
| | 157 | 36 | DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5 | CLK_STATE_READY | 50000000 | | |
| | 157 | 37 | DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10 | CLK_STATE_READY | 25000000 | | |
| | 157 | 38 | DEV_BOARD0_OBSCLK1_IN | CLK_STATE_READY | 500000000 | | |
| | 157 | 39 | DEV_BOARD0_MCU_RMII1_REF_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 40 | DEV_BOARD0_GPMC0_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 41 | DEV_BOARD0_I3C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 43 | DEV_BOARD0_TCK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 44 | DEV_BOARD0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 45 | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 46 | DEV_BOARD0_I2C6_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 48 | DEV_BOARD0_I2C5_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 49 | DEV_BOARD0_MCU_OSPI0_DQS_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 52 | DEV_BOARD0_RGMII2_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 53 | DEV_BOARD0_MCASP2_ACLKX_IN | CLK_STATE_READY | 0 | | |
| | 157 | 54 | DEV_BOARD0_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 57 | DEV_BOARD0_MCU_HYPERBUS0_CK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 59 | DEV_BOARD0_MCASP1_ACLKX_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 61 | DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 62 | DEV_BOARD0_MDIO0_MDC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 63 | DEV_BOARD0_RGMII1_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 65 | DEV_BOARD0_MMC1_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 66 | DEV_BOARD0_MCASP2_ACLKR_IN | CLK_STATE_READY | 0 | | |
| | 157 | 68 | DEV_BOARD0_WKUP_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 69 | DEV_BOARD0_MCU_CLKOUT0_IN | CLK_STATE_READY | 50000000 | | |
| | 157 | 70 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5 | CLK_STATE_READY | 50000000 | | |
| | 157 | 71 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10 | CLK_STATE_READY | 25000000 | | |
| | 157 | 73 | DEV_BOARD0_MCASP0_ACLKR_IN | CLK_STATE_READY | 0 | | |
| | 157 | 74 | DEV_BOARD0_MCU_MDIO0_MDC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 77 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 78 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 79 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 80 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 90 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 91 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 92 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 102 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 103 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 104 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 105 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 106 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 157 | 110 | DEV_BOARD0_MCU_OSPI0_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 114 | DEV_BOARD0_MCU_SYSCLKOUT0_IN | CLK_STATE_READY | 1000000000 | | |
| | 157 | 115 | DEV_BOARD0_RGMII1_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 116 | DEV_BOARD0_LED_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 118 | DEV_BOARD0_RGMII2_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 119 | DEV_BOARD0_I3C0_SCL_IN | CLK_STATE_READY | 0 | | |
| | 157 | 120 | DEV_BOARD0_MCU_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 122 | DEV_BOARD0_SPI6_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 123 | DEV_BOARD0_WKUP_I2C0_SCL_IN | CLK_STATE_READY | 0 | | |
| | 157 | 124 | DEV_BOARD0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 126 | DEV_BOARD0_MCU_SPI1_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 127 | DEV_BOARD0_MCASP0_ACLKX_IN | CLK_STATE_READY | 0 | | |
| | 157 | 128 | DEV_BOARD0_MCASP1_ACLKX_IN | CLK_STATE_READY | 0 | | |
| | 157 | 130 | DEV_BOARD0_MCU_SPI0_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 131 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 132 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 133 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 134 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 144 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 145 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 146 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 156 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 157 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 158 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 159 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 160 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 157 | 164 | DEV_BOARD0_MCU_RGMII1_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 165 | DEV_BOARD0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 166 | DEV_BOARD0_MCU_I2C1_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 168 | DEV_BOARD0_MCASP2_ACLKR_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 169 | DEV_BOARD0_MCU_I2C0_SCL_IN | CLK_STATE_READY | 0 | | |
| | 157 | 170 | DEV_BOARD0_RMII_REF_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 171 | DEV_BOARD0_GPMC0_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 172 | DEV_BOARD0_TRC_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 174 | DEV_BOARD0_MCASP2_ACLKX_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 176 | DEV_BOARD0_RGMII4_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 177 | DEV_BOARD0_SYSCLKOUT0_IN | CLK_STATE_READY | 500000000 | | |
| | 157 | 178 | DEV_BOARD0_MCASP1_ACLKR_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 179 | DEV_BOARD0_SPI5_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 180 | DEV_BOARD0_MCU_RGMII1_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 181 | DEV_BOARD0_RGMII3_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 183 | DEV_BOARD0_SPI0_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 184 | DEV_BOARD0_GPMC0_FCLK_MUX_IN | CLK_STATE_READY | 133333333 | | |
| | 157 | 185 | DEV_BOARD0_I2C2_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 186 | DEV_BOARD0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 187 | DEV_BOARD0_MCU_OSPI0_LBCLKO_IN | CLK_STATE_READY | 0 | | |
| | 157 | 189 | DEV_BOARD0_SPI7_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 190 | DEV_BOARD0_RGMII4_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 191 | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 192 | DEV_BOARD0_OBSCLK0_IN | CLK_STATE_READY | 500000000 | | |
| | 157 | 193 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK | CLK_STATE_READY | 500000000 | | |
| | 157 | 194 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK | CLK_STATE_READY | 192000000 | | |
| | 157 | 195 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK | CLK_STATE_READY | 1800000000 | | |
| | 157 | 196 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK | CLK_STATE_READY | 250000000 | | |
| | 157 | 197 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | |
| | 157 | 205 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK | CLK_STATE_READY | 666491803 | | |
| | 157 | 206 | DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 207 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK | CLK_STATE_READY | 1000000000 | | |
| | 157 | 219 | DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 157 | 220 | DEV_BOARD0_OBSCLK0_IN_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 157 | 221 | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 222 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 | CLK_STATE_READY | 500000000 | | |
| | 157 | 223 | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 224 | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 123 | 0 | DEV_CMPEVENT_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | |
| | 3 | 0 | DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | |
| | 3 | 2 | DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DBG_CLK | CLK_STATE_READY | 250000000 | | |
| | 3 | 3 | DEV_COMPUTE_CLUSTER0_TB_SOC_GIC_CLK | CLK_STATE_READY | 250000000 | | |
| | 3 | 4 | DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_DDR_PLL_CLK | CLK_STATE_READY | 666491803 | | |
| | 3 | 5 | DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_CFG_CLK | CLK_STATE_READY | 125000000 | | |
| | 3 | 6 | DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DMSC_CLK | CLK_STATE_READY | 125000000 | | |
| | 17 | 4 | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 19 | 0 | DEV_CPSW0_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | |
| | 19 | 1 | DEV_CPSW0_GMII3_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 2 | DEV_CPSW0_GMII2_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 3 | DEV_CPSW0_SERDES4_RXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 4 | DEV_CPSW0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 19 | 5 | DEV_CPSW0_PRE_RGMII4_TCLK | CLK_STATE_READY | 0 | | |
| | 19 | 6 | DEV_CPSW0_RGMII3_RXC_I | CLK_STATE_READY | 0 | | |
| | 19 | 7 | DEV_CPSW0_RGMII4_RXC_I | CLK_STATE_READY | 0 | | |
| | 19 | 8 | DEV_CPSW0_PRE_RGMII3_TCLK | CLK_STATE_READY | 0 | | |
| | 19 | 9 | DEV_CPSW0_RGMII1_RXC_I | CLK_STATE_READY | 0 | | |
| | 19 | 10 | DEV_CPSW0_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | |
| | 19 | 11 | DEV_CPSW0_GMII4_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 13 | DEV_CPSW0_GMII3_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 14 | DEV_CPSW0_SERDES4_RXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 15 | DEV_CPSW0_CPTS_RFT_CLK | CLK_STATE_READY | 200000000 | | |
| | 19 | 16 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 19 | 17 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 19 | 18 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 19 | 19 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 19 | 20 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 19 | 21 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 19 | 22 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 23 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 24 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 25 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 30 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 19 | 31 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 19 | 32 | DEV_CPSW0_SERDES1_TXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 33 | DEV_CPSW0_CPPI_CLK_CLK | CLK_STATE_READY | 320000000 | | |
| | 19 | 34 | DEV_CPSW0_SERDES2_RXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 35 | DEV_CPSW0_SERDES1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 36 | DEV_CPSW0_GMII_RFT_CLK | CLK_STATE_READY | 125000000 | | |
| | 19 | 37 | DEV_CPSW0_SERDES1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 38 | DEV_CPSW0_SERDES1_REFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 39 | DEV_CPSW0_RMII_MHZ_50_CLK | CLK_STATE_READY | 0 | | |
| | 19 | 40 | DEV_CPSW0_GMII4_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 41 | DEV_CPSW0_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | |
| | 19 | 42 | DEV_CPSW0_SERDES3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 43 | DEV_CPSW0_SERDES3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 45 | DEV_CPSW0_PRE_RGMII2_TCLK | CLK_STATE_READY | 0 | | |
| | 19 | 46 | DEV_CPSW0_SERDES2_TXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 47 | DEV_CPSW0_SERDES1_RXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 48 | DEV_CPSW0_SERDES1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 49 | DEV_CPSW0_RGMII2_RXC_I | CLK_STATE_READY | 0 | | |
| | 19 | 50 | DEV_CPSW0_SERDES2_TXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 51 | DEV_CPSW0_PRE_RGMII1_TCLK | CLK_STATE_READY | 0 | | |
| | 19 | 52 | DEV_CPSW0_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | |
| | 19 | 53 | DEV_CPSW0_GMII2_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 54 | DEV_CPSW0_SERDES4_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 55 | DEV_CPSW0_SERDES3_TXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 56 | DEV_CPSW0_SERDES2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 57 | DEV_CPSW0_GMII1_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 58 | DEV_CPSW0_SERDES4_REFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 59 | DEV_CPSW0_SERDES3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 60 | DEV_CPSW0_SERDES2_REFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 61 | DEV_CPSW0_SERDES3_REFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 62 | DEV_CPSW0_SERDES3_RXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 63 | DEV_CPSW0_GMII1_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 64 | DEV_CPSW0_SERDES2_RXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 66 | DEV_CPSW0_SERDES4_TXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 67 | DEV_CPSW0_SERDES4_TXFCLK | CLK_STATE_READY | 0 | | |
| | 26 | 0 | DEV_CPSW_TX_RGMII0_IO__RGMII4_TXC__A | CLK_STATE_READY | 0 | | |
| | 26 | 1 | DEV_CPSW_TX_RGMII0_IO__RGMII3_TXC__A | CLK_STATE_READY | 0 | | |
| | 26 | 2 | DEV_CPSW_TX_RGMII0_IO__RGMII2_TXC__A | CLK_STATE_READY | 0 | | |
| | 26 | 3 | DEV_CPSW_TX_RGMII0_IO__RGMII1_TXC__A | CLK_STATE_READY | 0 | | |
| | 26 | 4 | DEV_CPSW_TX_RGMII0_PRE_RGMII2_TCLK | CLK_STATE_READY | 0 | | |
| | 26 | 5 | DEV_CPSW_TX_RGMII0_PRE_RGMII4_TCLK | CLK_STATE_READY | 0 | | |
| | 26 | 6 | DEV_CPSW_TX_RGMII0_PRE_RGMII3_TCLK | CLK_STATE_READY | 0 | | |
| | 26 | 7 | DEV_CPSW_TX_RGMII0_PRE_RGMII1_TCLK | CLK_STATE_READY | 0 | | |
| | 20 | 0 | DEV_CPT2_AGGR0_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 21 | 0 | DEV_CPT2_AGGR1_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 23 | 0 | DEV_CPT2_AGGR2_VCLK_CLK | CLK_STATE_READY | 250000000 | | |
| | 25 | 0 | DEV_CPT2_AGGR3_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 30 | 0 | DEV_DCC0_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | |
| | 30 | 1 | DEV_DCC0_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 30 | 2 | DEV_DCC0_DCC_CLKSRC2_CLK | CLK_STATE_READY | 133333333 | | |
| | 30 | 4 | DEV_DCC0_DCC_CLKSRC0_CLK | CLK_STATE_READY | 200000000 | | |
| | 30 | 5 | DEV_DCC0_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 30 | 6 | DEV_DCC0_DCC_CLKSRC4_CLK | CLK_STATE_READY | 19200000 | | |
| | 30 | 7 | DEV_DCC0_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | |
| | 30 | 8 | DEV_DCC0_DCC_CLKSRC3_CLK | CLK_STATE_READY | 80000000 | | |
| | 30 | 9 | DEV_DCC0_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 30 | 10 | DEV_DCC0_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | |
| | 30 | 11 | DEV_DCC0_DCC_CLKSRC6_CLK | CLK_STATE_READY | 500000000 | | |
| | 30 | 12 | DEV_DCC0_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 31 | 0 | DEV_DCC1_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | |
| | 31 | 1 | DEV_DCC1_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 31 | 2 | DEV_DCC1_DCC_CLKSRC2_CLK | CLK_STATE_READY | 200000000 | | |
| | 31 | 4 | DEV_DCC1_DCC_CLKSRC0_CLK | CLK_STATE_READY | 50000000 | | |
| | 31 | 5 | DEV_DCC1_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 31 | 6 | DEV_DCC1_DCC_CLKSRC4_CLK | CLK_STATE_READY | 320000000 | | |
| | 31 | 7 | DEV_DCC1_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | |
| | 31 | 8 | DEV_DCC1_DCC_CLKSRC3_CLK | CLK_STATE_READY | 192000000 | | |
| | 31 | 9 | DEV_DCC1_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 31 | 10 | DEV_DCC1_DCC_CLKSRC5_CLK | CLK_STATE_READY | 192000000 | | |
| | 31 | 11 | DEV_DCC1_DCC_CLKSRC6_CLK | CLK_STATE_READY | 192000000 | | |
| | 31 | 12 | DEV_DCC1_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 32 | 0 | DEV_DCC2_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | |
| | 32 | 1 | DEV_DCC2_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 32 | 2 | DEV_DCC2_DCC_CLKSRC2_CLK | CLK_STATE_READY | 200000000 | | |
| | 32 | 3 | DEV_DCC2_DCC_CLKSRC7_CLK | CLK_STATE_READY | 250000000 | | |
| | 32 | 4 | DEV_DCC2_DCC_CLKSRC0_CLK | CLK_STATE_READY | 24000000 | | |
| | 32 | 5 | DEV_DCC2_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 32 | 6 | DEV_DCC2_DCC_CLKSRC4_CLK | CLK_STATE_READY | 450000000 | | |
| | 32 | 8 | DEV_DCC2_DCC_CLKSRC3_CLK | CLK_STATE_READY | 100000000 | | |
| | 32 | 9 | DEV_DCC2_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 32 | 10 | DEV_DCC2_DCC_CLKSRC5_CLK | CLK_STATE_READY | 300000000 | | |
| | 32 | 11 | DEV_DCC2_DCC_CLKSRC6_CLK | CLK_STATE_READY | 200000000 | | |
| | 32 | 12 | DEV_DCC2_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 33 | 0 | DEV_DCC3_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | |
| | 33 | 1 | DEV_DCC3_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 33 | 2 | DEV_DCC3_DCC_CLKSRC2_CLK | CLK_STATE_READY | 196608000 | | |
| | 33 | 3 | DEV_DCC3_DCC_CLKSRC7_CLK | CLK_STATE_READY | 93600000 | | |
| | 33 | 4 | DEV_DCC3_DCC_CLKSRC0_CLK | CLK_STATE_READY | 196608000 | | |
| | 33 | 5 | DEV_DCC3_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 33 | 6 | DEV_DCC3_DCC_CLKSRC4_CLK | CLK_STATE_READY | 125000000 | | |
| | 33 | 8 | DEV_DCC3_DCC_CLKSRC3_CLK | CLK_STATE_READY | 200000000 | | |
| | 33 | 9 | DEV_DCC3_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 33 | 10 | DEV_DCC3_DCC_CLKSRC5_CLK | CLK_STATE_READY | 83 | | |
| | 33 | 11 | DEV_DCC3_DCC_CLKSRC6_CLK | CLK_STATE_READY | 250000000 | | |
| | 33 | 12 | DEV_DCC3_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 34 | 0 | DEV_DCC4_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | |
| | 34 | 1 | DEV_DCC4_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 2 | DEV_DCC4_DCC_CLKSRC2_CLK | CLK_STATE_READY | 166622950 | | |
| | 34 | 3 | DEV_DCC4_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 4 | DEV_DCC4_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 5 | DEV_DCC4_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 34 | 6 | DEV_DCC4_DCC_CLKSRC4_CLK | CLK_STATE_READY | 250000000 | | |
| | 34 | 7 | DEV_DCC4_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 8 | DEV_DCC4_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 9 | DEV_DCC4_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 34 | 10 | DEV_DCC4_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 11 | DEV_DCC4_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 12 | DEV_DCC4_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 36 | 0 | DEV_DCC5_DCC_INPUT10_CLK | CLK_STATE_READY | 500000000 | | |
| | 36 | 1 | DEV_DCC5_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 4 | DEV_DCC5_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 5 | DEV_DCC5_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 36 | 6 | DEV_DCC5_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 7 | DEV_DCC5_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 9 | DEV_DCC5_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 36 | 11 | DEV_DCC5_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 12 | DEV_DCC5_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 37 | 0 | DEV_DCC6_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | |
| | 37 | 1 | DEV_DCC6_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 2 | DEV_DCC6_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 3 | DEV_DCC6_DCC_CLKSRC7_CLK | CLK_STATE_READY | 200000000 | | |
| | 37 | 4 | DEV_DCC6_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 5 | DEV_DCC6_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 37 | 6 | DEV_DCC6_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 7 | DEV_DCC6_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 8 | DEV_DCC6_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 9 | DEV_DCC6_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 37 | 10 | DEV_DCC6_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 11 | DEV_DCC6_DCC_CLKSRC6_CLK | CLK_STATE_READY | 200000000 | | |
| | 37 | 12 | DEV_DCC6_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 8 | 0 | DEV_DDR0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | |
| | 8 | 5 | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 666491803 | | |
| | 304 | 5 | DEV_DEBUGSS_WRAP0_TREXPT_CLK | CLK_STATE_READY | 300000000 | | |
| | 304 | 9 | DEV_DEBUGSS_WRAP0_CORE_CLK | CLK_STATE_READY | 125000000 | | |
| | 304 | 25 | DEV_DEBUGSS_WRAP0_JTAG_TCK | CLK_STATE_READY | 0 | | |
| | 304 | 34 | DEV_DEBUGSS_WRAP0_ATB_CLK | CLK_STATE_READY | 250000000 | | |
| | 304 | 49 | DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK | CLK_STATE_READY | 0 | | |
| | 80 | 0 | DEV_ECAP0_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 81 | 0 | DEV_ECAP1_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 82 | 0 | DEV_ECAP2_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 83 | 0 | DEV_EHRPWM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 84 | 0 | DEV_EHRPWM1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 85 | 0 | DEV_EHRPWM2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 86 | 0 | DEV_EHRPWM3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 87 | 0 | DEV_EHRPWM4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 88 | 0 | DEV_EHRPWM5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 89 | 0 | DEV_ELM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 94 | 0 | DEV_EQEP0_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 95 | 0 | DEV_EQEP1_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 96 | 0 | DEV_EQEP2_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 97 | 0 | DEV_ESM0_CLK | CLK_STATE_READY | 125000000 | | |
| | 105 | 0 | DEV_GPIO0_MMR_CLK | CLK_STATE_READY | 125000000 | | |
| | 107 | 0 | DEV_GPIO2_MMR_CLK | CLK_STATE_READY | 125000000 | | |
| | 109 | 0 | DEV_GPIO4_MMR_CLK | CLK_STATE_READY | 125000000 | | |
| | 111 | 0 | DEV_GPIO6_MMR_CLK | CLK_STATE_READY | 125000000 | | |
| | 131 | 0 | DEV_GPIOMUX_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | |
| | 115 | 0 | DEV_GPMC0_FUNC_CLK | CLK_STATE_READY | 133333333 | | |
| | 115 | 1 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK | CLK_STATE_READY | 133333333 | | |
| | 115 | 2 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6 | CLK_STATE_READY | 100000000 | | |
| | 115 | 3 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4 | CLK_STATE_READY | 150000000 | | |
| | 115 | 4 | DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4 | CLK_STATE_READY | 125000000 | | |
| | 115 | 5 | DEV_GPMC0_VBUSP_CLK | CLK_STATE_READY | 250000000 | | |
| | 115 | 6 | DEV_GPMC0_PO_GPMC_DEV_CLK | CLK_STATE_READY | 0 | | |
| | 115 | 7 | DEV_GPMC0_PI_GPMC_RET_CLK | CLK_STATE_READY | 0 | | |
| | 61 | 0 | DEV_GTC0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 61 | 1 | DEV_GTC0_GTC_CLK | CLK_STATE_READY | 200000000 | | |
| | 61 | 2 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 61 | 3 | DEV_GTC0_GTC_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 61 | 4 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 61 | 5 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 61 | 6 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 61 | 7 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 61 | 8 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 61 | 9 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 61 | 10 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 61 | 11 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 61 | 16 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 61 | 17 | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 187 | 0 | DEV_I2C0_PISCL | CLK_STATE_READY | 0 | | |
| | 187 | 1 | DEV_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 187 | 2 | DEV_I2C0_CLK | CLK_STATE_READY | 125000000 | | |
| | 187 | 3 | DEV_I2C0_PORSCL | CLK_STATE_READY | 0 | | |
| | 188 | 0 | DEV_I2C1_PISCL | CLK_STATE_READY | 0 | | |
| | 188 | 1 | DEV_I2C1_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 188 | 2 | DEV_I2C1_CLK | CLK_STATE_READY | 125000000 | | |
| | 188 | 3 | DEV_I2C1_PORSCL | CLK_STATE_READY | 0 | | |
| | 189 | 0 | DEV_I2C2_PISCL | CLK_STATE_READY | 0 | | |
| | 189 | 1 | DEV_I2C2_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 189 | 2 | DEV_I2C2_CLK | CLK_STATE_READY | 125000000 | | |
| | 189 | 3 | DEV_I2C2_PORSCL | CLK_STATE_READY | 0 | | |
| | 190 | 0 | DEV_I2C3_PISCL | CLK_STATE_READY | 0 | | |
| | 190 | 1 | DEV_I2C3_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 190 | 2 | DEV_I2C3_CLK | CLK_STATE_READY | 125000000 | | |
| | 190 | 3 | DEV_I2C3_PORSCL | CLK_STATE_READY | 0 | | |
| | 191 | 0 | DEV_I2C4_PISCL | CLK_STATE_READY | 0 | | |
| | 191 | 1 | DEV_I2C4_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 191 | 2 | DEV_I2C4_CLK | CLK_STATE_READY | 125000000 | | |
| | 191 | 3 | DEV_I2C4_PORSCL | CLK_STATE_READY | 0 | | |
| | 192 | 0 | DEV_I2C5_PISCL | CLK_STATE_READY | 0 | | |
| | 192 | 1 | DEV_I2C5_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 192 | 2 | DEV_I2C5_CLK | CLK_STATE_READY | 125000000 | | |
| | 192 | 3 | DEV_I2C5_PORSCL | CLK_STATE_READY | 0 | | |
| | 193 | 0 | DEV_I2C6_PISCL | CLK_STATE_READY | 0 | | |
| | 193 | 1 | DEV_I2C6_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 193 | 2 | DEV_I2C6_CLK | CLK_STATE_READY | 125000000 | | |
| | 193 | 3 | DEV_I2C6_PORSCL | CLK_STATE_READY | 0 | | |
| | 116 | 0 | DEV_I3C0_I3C_SCL_DI | CLK_STATE_READY | 0 | | |
| | 116 | 1 | DEV_I3C0_I3C_SCL_DO | CLK_STATE_READY | 0 | | |
| | 116 | 2 | DEV_I3C0_I3C_PCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 116 | 4 | DEV_I3C0_I3C_SCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 127 | 0 | DEV_LED0_LED_CLK | CLK_STATE_READY | 0 | | |
| | 127 | 1 | DEV_LED0_VBUS_CLK | CLK_STATE_READY | 250000000 | | |
| | 156 | 0 | DEV_MCAN0_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 156 | 2 | DEV_MCAN0_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 156 | 3 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 156 | 4 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 156 | 5 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 156 | 6 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 158 | 0 | DEV_MCAN1_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 158 | 2 | DEV_MCAN1_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 158 | 3 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 158 | 4 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 158 | 5 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 158 | 6 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 168 | 0 | DEV_MCAN10_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 168 | 2 | DEV_MCAN10_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 168 | 3 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 168 | 4 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 168 | 5 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 168 | 6 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 169 | 0 | DEV_MCAN11_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 169 | 2 | DEV_MCAN11_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 169 | 3 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 169 | 4 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 169 | 5 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 169 | 6 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 170 | 0 | DEV_MCAN12_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 170 | 2 | DEV_MCAN12_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 170 | 3 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 170 | 4 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 170 | 5 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 170 | 6 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 171 | 0 | DEV_MCAN13_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 171 | 2 | DEV_MCAN13_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 171 | 3 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 171 | 4 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 171 | 5 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 171 | 6 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 150 | 0 | DEV_MCAN14_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 150 | 2 | DEV_MCAN14_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 150 | 3 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 150 | 4 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 150 | 5 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 150 | 6 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 151 | 0 | DEV_MCAN15_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 151 | 2 | DEV_MCAN15_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 151 | 3 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 151 | 4 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 151 | 5 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 151 | 6 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 152 | 0 | DEV_MCAN16_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 152 | 2 | DEV_MCAN16_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 152 | 3 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 152 | 4 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 152 | 5 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 152 | 6 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 153 | 0 | DEV_MCAN17_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 153 | 2 | DEV_MCAN17_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 153 | 3 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 153 | 4 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 153 | 5 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 153 | 6 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 160 | 0 | DEV_MCAN2_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 160 | 2 | DEV_MCAN2_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 160 | 3 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 160 | 4 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 160 | 5 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 160 | 6 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 161 | 0 | DEV_MCAN3_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 161 | 2 | DEV_MCAN3_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 161 | 3 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 161 | 4 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 161 | 5 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 161 | 6 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 162 | 0 | DEV_MCAN4_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 162 | 2 | DEV_MCAN4_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 162 | 3 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 162 | 4 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 162 | 5 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 162 | 6 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 163 | 0 | DEV_MCAN5_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 163 | 2 | DEV_MCAN5_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 163 | 3 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 163 | 4 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 163 | 5 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 163 | 6 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 164 | 0 | DEV_MCAN6_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 164 | 2 | DEV_MCAN6_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 164 | 3 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 164 | 4 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 164 | 5 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 164 | 6 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 165 | 0 | DEV_MCAN7_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 165 | 2 | DEV_MCAN7_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 165 | 3 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 165 | 4 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 165 | 5 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 165 | 6 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 166 | 0 | DEV_MCAN8_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 166 | 2 | DEV_MCAN8_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 166 | 3 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 166 | 4 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 166 | 5 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 166 | 6 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 167 | 0 | DEV_MCAN9_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 167 | 2 | DEV_MCAN9_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 167 | 3 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 167 | 4 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 167 | 5 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 167 | 6 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 174 | 0 | DEV_MCASP0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 174 | 2 | DEV_MCASP0_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | |
| | 174 | 3 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 4 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 174 | 5 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 6 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 11 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 12 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 13 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 14 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 19 | DEV_MCASP0_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | |
| | 174 | 21 | DEV_MCASP0_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | |
| | 174 | 22 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 23 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 174 | 24 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 25 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 30 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 31 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 32 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 33 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 38 | DEV_MCASP0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 174 | 39 | DEV_MCASP0_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | |
| | 174 | 40 | DEV_MCASP0_AUX_CLK | CLK_STATE_READY | 196608000 | | |
| | 174 | 41 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | |
| | 174 | 42 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 174 | 45 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 46 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 47 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 48 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 49 | DEV_MCASP0_VBUSP_CLK | CLK_STATE_READY | 250000000 | | |
| | 174 | 50 | DEV_MCASP0_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | |
| | 174 | 51 | DEV_MCASP0_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | |
| | 175 | 0 | DEV_MCASP1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 175 | 2 | DEV_MCASP1_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | |
| | 175 | 3 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 4 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 175 | 5 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 6 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 11 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 12 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 13 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 14 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 19 | DEV_MCASP1_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | |
| | 175 | 21 | DEV_MCASP1_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | |
| | 175 | 22 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 23 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 175 | 24 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 25 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 30 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 31 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 32 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 33 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 38 | DEV_MCASP1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 175 | 39 | DEV_MCASP1_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | |
| | 175 | 40 | DEV_MCASP1_AUX_CLK | CLK_STATE_READY | 196608000 | | |
| | 175 | 41 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | |
| | 175 | 42 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 175 | 45 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 46 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 47 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 48 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 49 | DEV_MCASP1_VBUSP_CLK | CLK_STATE_READY | 250000000 | | |
| | 175 | 50 | DEV_MCASP1_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | |
| | 175 | 51 | DEV_MCASP1_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | |
| | 176 | 0 | DEV_MCASP2_MCASP_AHCLKX_POUT [ 44.905370] kauditd_printk_skb: 5 callbacks suppressed | |
| | CLK_STATE_READY | 0 [ 44.905382] audit: type=1334 audit(1707106903.580:17): prog-id=12 op=UNLOAD | |
| | | |
| | 176 | 2 | DEV_MCASP2_MCASP_AHCLKR_PIN[ 44.926275] audit: type=1334 audit(1707106903.580:18): prog-id=11 op=UNLOAD | |
| | CLK_STATE_READY | 0 | | |
| | 176 | 3 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 4 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 176 | 5 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 6 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 11 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 12 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 13 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 14 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 19 | DEV_MCASP2_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | |
| | 176 | 21 | DEV_MCASP2_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | |
| | 176 | 22 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 23 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 176 | 24 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 25 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 30 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 31 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 32 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 33 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 38 | DEV_MCASP2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 176 | 39 | DEV_MCASP2_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | |
| | 176 | 40 | DEV_MCASP2_AUX_CLK | CLK_STATE_READY | 196608000 | | |
| | 176 | 41 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | |
| | 176 | 42 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 176 | 45 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 46 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 47 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 48 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 49 | DEV_MCASP2_VBUSP_CLK | CLK_STATE_READY | 250000000 | | |
| | 176 | 50 | DEV_MCASP2_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | |
| | 176 | 51 | DEV_MCASP2_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | |
| | 266 | 3 | DEV_MCSPI0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 266 | 4 | DEV_MCSPI0_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 266 | 5 | DEV_MCSPI0_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 267 | 3 | DEV_MCSPI1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 267 | 4 | DEV_MCSPI1_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 267 | 5 | DEV_MCSPI1_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 268 | 3 | DEV_MCSPI2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 268 | 4 | DEV_MCSPI2_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 268 | 5 | DEV_MCSPI2_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 269 | 0 | DEV_MCSPI3_IO_CLKSPII_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 269 | 1 | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 269 | 3 | DEV_MCSPI3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 269 | 4 | DEV_MCSPI3_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 269 | 5 | DEV_MCSPI3_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 270 | 0 | DEV_MCSPI4_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | |
| | 270 | 1 | DEV_MCSPI4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 270 | 2 | DEV_MCSPI4_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 270 | 3 | DEV_MCSPI4_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 271 | 3 | DEV_MCSPI5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 271 | 4 | DEV_MCSPI5_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 271 | 5 | DEV_MCSPI5_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 272 | 3 | DEV_MCSPI6_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 272 | 4 | DEV_MCSPI6_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 272 | 5 | DEV_MCSPI6_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 273 | 3 | DEV_MCSPI7_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 273 | 4 | DEV_MCSPI7_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 273 | 5 | DEV_MCSPI7_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 0 | 0 | DEV_MCU_ADC0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 0 | 1 | DEV_MCU_ADC0_ADC_CLK | CLK_STATE_READY | 19200000 | | |
| | 0 | 2 | DEV_MCU_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 0 | 3 | DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | CLK_STATE_READY | 60000000 | | |
| | 0 | 4 | DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | CLK_STATE_READY | 58823529 | | |
| | 0 | 5 | DEV_MCU_ADC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 0 | 6 | DEV_MCU_ADC0_VBUS_CLK | CLK_STATE_READY | 333333333 | | |
| | 1 | 0 | DEV_MCU_ADC1_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 1 | 1 | DEV_MCU_ADC1_ADC_CLK | CLK_STATE_READY | 19200000 | | |
| | 1 | 2 | DEV_MCU_ADC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 1 | 3 | DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | CLK_STATE_READY | 60000000 | | |
| | 1 | 4 | DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | CLK_STATE_READY | 58823529 | | |
| | 1 | 5 | DEV_MCU_ADC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 1 | 6 | DEV_MCU_ADC1_VBUS_CLK | CLK_STATE_READY | 333333333 | | |
| | 18 | 0 | DEV_MCU_CPSW0_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | |
| | 18 | 2 | DEV_MCU_CPSW0_CPTS_RFT_CLK | CLK_STATE_READY | 500000000 | | |
| | 18 | 3 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 18 | 4 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 18 | 5 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 18 | 6 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 18 | 7 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 18 | 8 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 18 | 9 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 18 | 10 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 18 | 11 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 18 | 12 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 18 | 17 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 18 | 18 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2 | CLK_STATE_READY | 500000000 | | |
| | 18 | 20 | DEV_MCU_CPSW0_GMII1_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 18 | 21 | DEV_MCU_CPSW0_CPPI_CLK_CLK | CLK_STATE_READY | 333333333 | | |
| | 18 | 22 | DEV_MCU_CPSW0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 18 | 24 | DEV_MCU_CPSW0_GMII_RFT_CLK | CLK_STATE_READY | 125000000 | | |
| | 18 | 27 | DEV_MCU_CPSW0_GMII1_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 18 | 28 | DEV_MCU_CPSW0_RGMII1_TXC_O | CLK_STATE_READY | 0 | | |
| | 18 | 29 | DEV_MCU_CPSW0_RMII_MHZ_50_CLK | CLK_STATE_READY | 0 | | |
| | 18 | 30 | DEV_MCU_CPSW0_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | |
| | 18 | 31 | DEV_MCU_CPSW0_RGMII1_RXC_I | CLK_STATE_READY | 0 | | |
| | 18 | 32 | DEV_MCU_CPSW0_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | |
| | 18 | 33 | DEV_MCU_CPSW0_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | |
| | 24 | 0 | DEV_MCU_CPT2_AGGR0_VCLK_CLK | CLK_STATE_READY | 333333333 | | |
| | 44 | 0 | DEV_MCU_DCC0_DCC_INPUT10_CLK | CLK_STATE_READY | 333333333 | | |
| | 44 | 1 | DEV_MCU_DCC0_DCC_INPUT01_CLK | CLK_STATE_READY | 83 | | |
| | 44 | 2 | DEV_MCU_DCC0_DCC_CLKSRC2_CLK | CLK_STATE_READY | 80000000 | | |
| | 44 | 3 | DEV_MCU_DCC0_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | |
| | 44 | 4 | DEV_MCU_DCC0_DCC_CLKSRC0_CLK | CLK_STATE_READY | 200000000 | | |
| | 44 | 5 | DEV_MCU_DCC0_VBUS_CLK | CLK_STATE_READY | 166666666 | | |
| | 44 | 6 | DEV_MCU_DCC0_DCC_CLKSRC4_CLK | CLK_STATE_READY | 133333333 | | |
| | 44 | 7 | DEV_MCU_DCC0_DCC_CLKSRC1_CLK | CLK_STATE_READY | 60000000 | | |
| | 44 | 8 | DEV_MCU_DCC0_DCC_CLKSRC3_CLK | CLK_STATE_READY | 96000000 | | |
| | 44 | 9 | DEV_MCU_DCC0_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 44 | 10 | DEV_MCU_DCC0_DCC_CLKSRC5_CLK | CLK_STATE_READY | 83 | | |
| | 44 | 11 | DEV_MCU_DCC0_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | |
| | 44 | 12 | DEV_MCU_DCC0_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 45 | 0 | DEV_MCU_DCC1_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | |
| | 45 | 1 | DEV_MCU_DCC1_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 45 | 2 | DEV_MCU_DCC1_DCC_CLKSRC2_CLK | CLK_STATE_READY | 80000000 | | |
| | 45 | 3 | DEV_MCU_DCC1_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | |
| | 45 | 4 | DEV_MCU_DCC1_DCC_CLKSRC0_CLK | CLK_STATE_READY | 250000000 | | |
| | 45 | 5 | DEV_MCU_DCC1_VBUS_CLK | CLK_STATE_READY | 166666666 | | |
| | 45 | 6 | DEV_MCU_DCC1_DCC_CLKSRC4_CLK | CLK_STATE_READY | 250000000 | | |
| | 45 | 7 | DEV_MCU_DCC1_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | |
| | 45 | 8 | DEV_MCU_DCC1_DCC_CLKSRC3_CLK | CLK_STATE_READY | 166666666 | | |
| | 45 | 9 | DEV_MCU_DCC1_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 45 | 10 | DEV_MCU_DCC1_DCC_CLKSRC5_CLK | CLK_STATE_READY | 58823529 | | |
| | 45 | 11 | DEV_MCU_DCC1_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | |
| | 45 | 12 | DEV_MCU_DCC1_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 46 | 0 | DEV_MCU_DCC2_DCC_INPUT10_CLK | CLK_STATE_READY | 333333333 | | |
| | 46 | 1 | DEV_MCU_DCC2_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 46 | 3 | DEV_MCU_DCC2_DCC_CLKSRC7_CLK | CLK_STATE_READY | 19200000 | | |
| | 46 | 4 | DEV_MCU_DCC2_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | |
| | 46 | 5 | DEV_MCU_DCC2_VBUS_CLK | CLK_STATE_READY | 166666666 | | |
| | 46 | 7 | DEV_MCU_DCC2_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | |
| | 46 | 8 | DEV_MCU_DCC2_DCC_CLKSRC3_CLK | CLK_STATE_READY | 192000000 | | |
| | 46 | 9 | DEV_MCU_DCC2_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 46 | 11 | DEV_MCU_DCC2_DCC_CLKSRC6_CLK | CLK_STATE_READY | 12500000 | | |
| | 46 | 12 | DEV_MCU_DCC2_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 98 | 0 | DEV_MCU_ESM0_CLK | CLK_STATE_READY | 166666666 | | |
| | 101 | 0 | DEV_MCU_FSS0_FSAS_0_GCLK | CLK_STATE_READY | 1000000000 | | |
| | 102 | 0 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N | CLK_STATE_READY | 0 | | |
| | 102 | 1 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK | CLK_STATE_READY | 166666666 | | |
| | 102 | 2 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK | CLK_STATE_READY | 83333333 | | |
| | 102 | 4 | DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK | CLK_STATE_READY | 1000000000 | | |
| | 102 | 5 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK | CLK_STATE_READY | 166666666 | | |
| | 102 | 7 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK | CLK_STATE_READY | 83333333 | | |
| | 102 | 10 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P | CLK_STATE_READY | 0 | | |
| | 103 | 0 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 103 | 1 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK | CLK_STATE_READY | 133333333 | | |
| | 103 | 2 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK | CLK_STATE_READY | 166666666 | | |
| | 103 | 3 | DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 103 | 4 | DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK | CLK_STATE_READY | 0 | | |
| | 103 | 5 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK | CLK_STATE_READY | 0 | | |
| | 103 | 6 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT | CLK_STATE_READY | 0 | | |
| | 103 | 7 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 103 | 8 | DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 103 | 9 | DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK | CLK_STATE_READY | 0 | | |
| | 104 | 0 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK | CLK_STATE_READY | 133333333 | | |
| | 104 | 1 | DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 104 | 7 | DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 194 | 0 | DEV_MCU_I2C0_PISCL | CLK_STATE_READY | 0 | | |
| | 194 | 1 | DEV_MCU_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 194 | 2 | DEV_MCU_I2C0_CLK | CLK_STATE_READY | 166666666 | | |
| | 195 | 0 | DEV_MCU_I2C1_PISCL | CLK_STATE_READY | 0 | | |
| | 195 | 1 | DEV_MCU_I2C1_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 195 | 2 | DEV_MCU_I2C1_CLK | CLK_STATE_READY | 166666666 | | |
| | 195 | 3 | DEV_MCU_I2C1_PORSCL | CLK_STATE_READY | 0 | | |
| | 117 | 0 | DEV_MCU_I3C0_I3C_SCL_DI | CLK_STATE_READY | 0 | | |
| | 117 | 1 | DEV_MCU_I3C0_I3C_SCL_DO | CLK_STATE_READY | 0 | | |
| | 117 | 2 | DEV_MCU_I3C0_I3C_PCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 117 | 4 | DEV_MCU_I3C0_I3C_SCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 118 | 2 | DEV_MCU_I3C1_I3C_PCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 118 | 4 | DEV_MCU_I3C1_I3C_SCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 172 | 0 | DEV_MCU_MCAN0_MCANSS_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 172 | 2 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 172 | 3 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | CLK_STATE_READY | 80000000 | | |
| | 172 | 4 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 172 | 5 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | CLK_STATE_READY | 80000000 | | |
| | 172 | 6 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 173 | 0 | DEV_MCU_MCAN1_MCANSS_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 173 | 2 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 173 | 3 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | CLK_STATE_READY | 80000000 | | |
| | 173 | 4 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 173 | 5 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | CLK_STATE_READY | 80000000 | | |
| | 173 | 6 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 274 | 3 | DEV_MCU_MCSPI0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 274 | 4 | DEV_MCU_MCSPI0_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 274 | 5 | DEV_MCU_MCSPI0_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 275 | 0 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 275 | 1 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 275 | 3 | DEV_MCU_MCSPI1_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 275 | 4 | DEV_MCU_MCSPI1_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 275 | 5 | DEV_MCU_MCSPI1_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 276 | 0 | DEV_MCU_MCSPI2_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | |
| | 276 | 1 | DEV_MCU_MCSPI2_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 276 | 2 | DEV_MCU_MCSPI2_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 276 | 3 | DEV_MCU_MCSPI2_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 237 | 0 | DEV_MCU_NAVSS0_INTR_0_INTR_CLK | CLK_STATE_READY | 1000000000 | | |
| | 238 | 0 | DEV_MCU_NAVSS0_MCRC_0_CLK | CLK_STATE_READY | 1000000000 | | |
| | 302 | 0 | DEV_MCU_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 1000000000 | | |
| | 234 | 0 | DEV_MCU_NAVSS0_PROXY0_CLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 235 | 0 | DEV_MCU_NAVSS0_RINGACC0_SYS_CLK | CLK_STATE_READY | 1000000000 | | |
| | 236 | 0 | DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK | CLK_STATE_READY | 1000000000 | | |
| | 303 | 0 | DEV_MCU_NAVSS0_UDMASS_VD2CLK | CLK_STATE_READY | 1000000000 | | |
| | 233 | 0 | DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK | CLK_STATE_READY | 1000000000 | | |
| | 142 | 1 | DEV_MCU_PBIST0_CLK7_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 2 | DEV_MCU_PBIST0_CLK3_CLK | CLK_STATE_READY | 166666666 | | |
| | 142 | 3 | DEV_MCU_PBIST0_CLK5_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 4 | DEV_MCU_PBIST0_CLK1_CLK | CLK_STATE_READY | 500000000 | | |
| | 142 | 5 | DEV_MCU_PBIST0_CLK8_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 6 | DEV_MCU_PBIST0_CLK6_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 8 | DEV_MCU_PBIST0_CLK4_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 9 | DEV_MCU_PBIST0_CLK2_CLK | CLK_STATE_READY | 333333333 | | |
| | 143 | 1 | DEV_MCU_PBIST1_CLK7_CLK | CLK_STATE_READY | 83333333 | | |
| | 143 | 2 | DEV_MCU_PBIST1_CLK3_CLK | CLK_STATE_READY | 83333333 | | |
| | 143 | 3 | DEV_MCU_PBIST1_CLK5_CLK | CLK_STATE_READY | 166666666 | | |
| | 143 | 4 | DEV_MCU_PBIST1_CLK1_CLK | CLK_STATE_READY | 500000000 | | |
| | 143 | 5 | DEV_MCU_PBIST1_CLK8_CLK | CLK_STATE_READY | 83333333 | | |
| | 143 | 6 | DEV_MCU_PBIST1_CLK6_CLK | CLK_STATE_READY | 83333333 | | |
| | 143 | 8 | DEV_MCU_PBIST1_CLK4_CLK | CLK_STATE_READY | 333333333 | | |
| | 143 | 9 | DEV_MCU_PBIST1_CLK2_CLK | CLK_STATE_READY | 400000000 | | |
| | 144 | 1 | DEV_MCU_PBIST2_CLK7_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 2 | DEV_MCU_PBIST2_CLK3_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 3 | DEV_MCU_PBIST2_CLK5_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 4 | DEV_MCU_PBIST2_CLK1_CLK | CLK_STATE_READY | 1000000000 | | |
| | 144 | 5 | DEV_MCU_PBIST2_CLK8_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 6 | DEV_MCU_PBIST2_CLK6_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 8 | DEV_MCU_PBIST2_CLK4_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 9 | DEV_MCU_PBIST2_CLK2_CLK | CLK_STATE_READY | 83333333 | | |
| | 250 | 0 | DEV_MCU_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | |
| | 250 | 1 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 250 | 2 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | CLK_STATE_READY | 333333333 | | |
| | 250 | 3 | DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | |
| | 250 | 4 | DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 333333333 | | |
| | 251 | 0 | DEV_MCU_R5FSS0_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | |
| | 251 | 1 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 251 | 2 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | CLK_STATE_READY | 333333333 | | |
| | 251 | 3 | DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | |
| | 251 | 4 | DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE | CLK_STATE_READY | 333333333 | | |
| | 262 | 0 | DEV_MCU_RTI0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 262 | 1 | DEV_MCU_RTI0_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 262 | 2 | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 262 | 3 | DEV_MCU_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 262 | 4 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 262 | 5 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 263 | 0 | DEV_MCU_RTI1_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 263 | 1 | DEV_MCU_RTI1_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 263 | 2 | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 263 | 3 | DEV_MCU_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 263 | 4 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 263 | 5 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 265 | 0 | DEV_MCU_SA2_UL0_X2_CLK | CLK_STATE_READY | 333333333 | | |
| | 265 | 1 | DEV_MCU_SA2_UL0_PKA_IN_CLK | CLK_STATE_READY | 400000000 | | |
| | 265 | 2 | DEV_MCU_SA2_UL0_X1_CLK | CLK_STATE_READY | 166666666 | | |
| | 35 | 0 | DEV_MCU_TIMER0_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 35 | 1 | DEV_MCU_TIMER0_TIMER_TCLK_CLK | CLK_STATE_READY | 62500000 | | |
| | 35 | 2 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 35 | 3 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 35 | 4 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 35 | 5 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 35 | 6 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 35 | 7 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 35 | 8 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 35 | 9 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 35 | 11 | DEV_MCU_TIMER0_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 71 | 0 | DEV_MCU_TIMER1_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 71 | 1 | DEV_MCU_TIMER1_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 71 | 2 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1 | CLK_STATE_READY | 19200000 | | |
| | 71 | 3 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 308 | 0 | DEV_MCU_TIMER1_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 308 | 1 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 308 | 2 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 308 | 3 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 308 | 4 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 308 | 5 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 308 | 6 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 308 | 7 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 308 | 8 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 72 | 0 | DEV_MCU_TIMER2_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 72 | 1 | DEV_MCU_TIMER2_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 72 | 2 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 72 | 3 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 72 | 4 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 72 | 5 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 72 | 6 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 72 | 7 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 72 | 8 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 72 | 9 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 72 | 11 | DEV_MCU_TIMER2_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 73 | 0 | DEV_MCU_TIMER3_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 73 | 1 | DEV_MCU_TIMER3_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 73 | 2 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3 | CLK_STATE_READY | 19200000 | | |
| | 73 | 3 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 309 | 0 | DEV_MCU_TIMER3_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 309 | 1 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 309 | 2 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 309 | 3 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 309 | 4 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 309 | 5 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 309 | 6 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 309 | 7 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 309 | 8 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 74 | 0 | DEV_MCU_TIMER4_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 74 | 1 | DEV_MCU_TIMER4_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 74 | 2 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 74 | 3 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 74 | 4 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 74 | 5 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 74 | 6 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 74 | 7 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 74 | 8 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 74 | 9 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 74 | 11 | DEV_MCU_TIMER4_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 75 | 0 | DEV_MCU_TIMER5_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 75 | 1 | DEV_MCU_TIMER5_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 75 | 2 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5 | CLK_STATE_READY | 19200000 | | |
| | 75 | 3 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 310 | 0 | DEV_MCU_TIMER5_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 310 | 1 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 310 | 2 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 310 | 3 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 310 | 4 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 310 | 5 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 310 | 6 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 310 | 7 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 310 | 8 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 76 | 0 | DEV_MCU_TIMER6_TIMER_HCLK_CLK | CLK_STATE_READY | 333333333 | | |
| | 76 | 1 | DEV_MCU_TIMER6_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 76 | 2 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 76 | 3 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 76 | 4 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 76 | 5 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 76 | 6 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 76 | 7 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 76 | 8 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 76 | 9 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 76 | 11 | DEV_MCU_TIMER6_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 77 | 0 | DEV_MCU_TIMER7_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 77 | 1 | DEV_MCU_TIMER7_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 77 | 2 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7 | CLK_STATE_READY | 19200000 | | |
| | 77 | 3 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 311 | 0 | DEV_MCU_TIMER7_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 311 | 1 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 311 | 2 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 311 | 3 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 311 | 4 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 311 | 5 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 311 | 6 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 311 | 7 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 311 | 8 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 78 | 0 | DEV_MCU_TIMER8_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 78 | 1 | DEV_MCU_TIMER8_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 78 | 2 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 78 | 3 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 78 | 4 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 78 | 5 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 78 | 6 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 78 | 7 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 78 | 8 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 78 | 9 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 78 | 11 | DEV_MCU_TIMER8_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 79 | 0 | DEV_MCU_TIMER9_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 79 | 1 | DEV_MCU_TIMER9_TIMER_TCLK_CLK | CLK_STATE_READY | 62500000 | | |
| | 79 | 2 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9 | CLK_STATE_READY | 62500000 | | |
| | 79 | 3 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 312 | 0 | DEV_MCU_TIMER9_CLKSEL_VD_CLK | CLK_STATE_READY | 62500000 | | |
| | 312 | 1 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 312 | 2 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 312 | 3 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 312 | 4 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 312 | 5 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 312 | 6 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 312 | 7 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 312 | 8 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 149 | 2 | DEV_MCU_UART0_FCLK_CLK | CLK_STATE_READY | 96000000 | | |
| | 149 | 3 | DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK | CLK_STATE_READY | 96000000 | | |
| | 149 | 4 | DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_1_HSDIVOUT5_CLK | CLK_STATE_READY | 192000000 | | |
| | 149 | 5 | DEV_MCU_UART0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 91 | 0 | DEV_MMCSD0_EMMCSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | |
| | 91 | 3 | DEV_MMCSD0_EMMCSS_XIN_CLK | CLK_STATE_READY | 200000000 | | |
| | 91 | 4 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 91 | 5 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | |
| | 91 | 6 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 91 | 7 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0 | CLK_STATE_READY | 200000000 | | |
| | 92 | 0 | DEV_MMCSD1_EMMCSDSS_IO_CLK_I | CLK_STATE_READY | 0 | | |
| | 92 | 1 | DEV_MMCSD1_EMMCSDSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | |
| | 92 | 2 | DEV_MMCSD1_EMMCSDSS_XIN_CLK | CLK_STATE_READY | 200000000 | | |
| | 92 | 3 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 92 | 4 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | |
| | 92 | 5 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 92 | 6 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0 | CLK_STATE_READY | 200000000 | | |
| | 92 | 7 | DEV_MMCSD1_EMMCSDSS_IO_CLK_O | CLK_STATE_READY | 0 | | |
| | 199 | 0 | DEV_NAVSS0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 199 | 1 | DEV_NAVSS0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 199 | 2 | DEV_NAVSS0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 201 | 0 | DEV_NAVSS0_CPTS_0_VBUSP_GCLK | CLK_STATE_READY | 500000000 | | |
| | 201 | 1 | DEV_NAVSS0_CPTS_0_RCLK | CLK_STATE_READY | 200000000 | | |
| | 201 | 2 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 201 | 3 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 201 | 4 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 201 | 5 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 201 | 6 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 201 | 7 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 201 | 8 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 201 | 9 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 201 | 10 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 201 | 11 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 201 | 16 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 201 | 17 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 201 | 20 | DEV_NAVSS0_CPTS_0_TS_GENF0 | CLK_STATE_READY | 0 | | |
| | 201 | 21 | DEV_NAVSS0_CPTS_0_TS_GENF1 | CLK_STATE_READY | 0 | | |
| | 206 | 0 | DEV_NAVSS0_DTI_0_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 213 | 0 | DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK | CLK_STATE_READY | 500000000 | | |
| | 214 | 0 | DEV_NAVSS0_MAILBOX_0_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 215 | 0 | DEV_NAVSS0_MAILBOX_1_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 224 | 0 | DEV_NAVSS0_MAILBOX_10_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 225 | 0 | DEV_NAVSS0_MAILBOX_11_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 216 | 0 | DEV_NAVSS0_MAILBOX_2_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 217 | 0 | DEV_NAVSS0_MAILBOX_3_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 218 | 0 | DEV_NAVSS0_MAILBOX_4_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 219 | 0 | DEV_NAVSS0_MAILBOX_5_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 220 | 0 | DEV_NAVSS0_MAILBOX_6_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 221 | 0 | DEV_NAVSS0_MAILBOX_7_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 222 | 0 | DEV_NAVSS0_MAILBOX_8_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 223 | 0 | DEV_NAVSS0_MAILBOX_9_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 227 | 0 | DEV_NAVSS0_MCRC_0_CLK | CLK_STATE_READY | 500000000 | | |
| | 299 | 0 | DEV_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 500000000 | | |
| | 207 | 0 | DEV_NAVSS0_MODSS_INTA_0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 208 | 0 | DEV_NAVSS0_MODSS_INTA_1_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 210 | 0 | DEV_NAVSS0_PROXY_0_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 211 | 0 | DEV_NAVSS0_RINGACC_0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 226 | 0 | DEV_NAVSS0_SPINLOCK_0_CLK | CLK_STATE_READY | 500000000 | | |
| | 228 | 0 | DEV_NAVSS0_TBU_0_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 230 | 0 | DEV_NAVSS0_TIMERMGR_0_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 230 | 1 | DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT | CLK_STATE_READY | 0 | | |
| | 231 | 0 | DEV_NAVSS0_TIMERMGR_1_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 231 | 1 | DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT | CLK_STATE_READY | 0 | | |
| | 212 | 0 | DEV_NAVSS0_UDMAP_0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 300 | 0 | DEV_NAVSS0_UDMASS_VD2CLK | CLK_STATE_READY | 500000000 | | |
| | 209 | 0 | DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 301 | 0 | DEV_NAVSS0_VIRTSS_VD2CLK | CLK_STATE_READY | 500000000 | | |
| | 139 | 1 | DEV_PBIST0_CLK7_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 2 | DEV_PBIST0_CLK3_CLK | CLK_STATE_READY | 250000000 | | |
| | 139 | 3 | DEV_PBIST0_CLK5_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 4 | DEV_PBIST0_CLK1_CLK | CLK_STATE_READY | 500000000 | | |
| | 139 | 5 | DEV_PBIST0_CLK8_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 6 | DEV_PBIST0_CLK6_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 8 | DEV_PBIST0_CLK4_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 9 | DEV_PBIST0_CLK2_CLK | CLK_STATE_READY | 250000000 | | |
| | 140 | 1 | DEV_PBIST1_CLK7_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 2 | DEV_PBIST1_CLK3_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 3 | DEV_PBIST1_CLK5_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 4 | DEV_PBIST1_CLK1_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 5 | DEV_PBIST1_CLK8_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 6 | DEV_PBIST1_CLK6_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 8 | DEV_PBIST1_CLK4_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 9 | DEV_PBIST1_CLK2_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 1 | DEV_PBIST2_CLK7_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 2 | DEV_PBIST2_CLK3_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 3 | DEV_PBIST2_CLK5_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 4 | DEV_PBIST2_CLK1_CLK | CLK_STATE_READY | 1000000000 | | |
| | 141 | 5 | DEV_PBIST2_CLK8_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 6 | DEV_PBIST2_CLK6_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 8 | DEV_PBIST2_CLK4_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 9 | DEV_PBIST2_CLK2_CLK | CLK_STATE_READY | 125000000 | | |
| | 240 | 0 | DEV_PCIE1_PCIE_LANE0_TXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 1 | DEV_PCIE1_PCIE_LANE1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 2 | DEV_PCIE1_PCIE_LANE0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 3 | DEV_PCIE1_PCIE_LANE0_TXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 4 | DEV_PCIE1_PCIE_PM_CLK | CLK_STATE_READY | 12500000 | | |
| | 240 | 5 | DEV_PCIE1_PCIE_LANE3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 6 | DEV_PCIE1_PCIE_CBA_CLK | CLK_STATE_READY | 250000000 | | |
| | 240 | 7 | DEV_PCIE1_PCIE_LANE1_REFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 8 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK | CLK_STATE_READY | 200000000 | | |
| | 240 | 9 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 240 | 10 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 240 | 11 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 240 | 12 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 240 | 13 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 240 | 14 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 240 | 15 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 16 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 17 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 18 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 23 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 240 | 24 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 240 | 25 | DEV_PCIE1_PCIE_LANE1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 27 | DEV_PCIE1_PCIE_LANE2_RXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 28 | DEV_PCIE1_PCIE_LANE2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 29 | DEV_PCIE1_PCIE_LANE1_TXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 30 | DEV_PCIE1_PCIE_LANE3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 31 | DEV_PCIE1_PCIE_LANE2_TXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 32 | DEV_PCIE1_PCIE_LANE1_RXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 33 | DEV_PCIE1_PCIE_LANE2_TXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 34 | DEV_PCIE1_PCIE_LANE1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 35 | DEV_PCIE1_PCIE_LANE0_REFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 36 | DEV_PCIE1_PCIE_LANE3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 37 | DEV_PCIE1_PCIE_LANE2_RXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 38 | DEV_PCIE1_PCIE_LANE3_RXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 39 | DEV_PCIE1_PCIE_LANE3_REFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 40 | DEV_PCIE1_PCIE_LANE2_REFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 41 | DEV_PCIE1_PCIE_LANE0_RXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 42 | DEV_PCIE1_PCIE_LANE3_TXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 43 | DEV_PCIE1_PCIE_LANE0_RXCLK | CLK_STATE_READY | 0 | | |
| | 133 | 0 | DEV_PSC0_SLOW_CLK | CLK_STATE_READY | 20833333 | | |
| | 133 | 1 | DEV_PSC0_CLK | CLK_STATE_READY | 125000000 | | |
| | 245 | 0 | DEV_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | |
| | 245 | 1 | DEV_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | |
| | 245 | 2 | DEV_R5FSS0_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 1000000000 | | |
| | 246 | 0 | DEV_R5FSS0_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | |
| | 246 | 1 | DEV_R5FSS0_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | |
| | 246 | 2 | DEV_R5FSS0_CORE1_INTERFACE_PHASE | CLK_STATE_READY | 1000000000 | | |
| | 252 | 0 | DEV_RTI0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 252 | 1 | DEV_RTI0_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 252 | 2 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 252 | 3 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 252 | 4 | DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 252 | 5 | DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 252 | 6 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 252 | 7 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | |
| | 252 | 8 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | |
| | 252 | 9 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | |
| | 253 | 0 | DEV_RTI1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 253 | 1 | DEV_RTI1_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 253 | 2 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 253 | 3 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 253 | 4 | DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 253 | 5 | DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 253 | 6 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 253 | 7 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | |
| | 253 | 8 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | |
| | 253 | 9 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | |
| | 258 | 0 | DEV_RTI28_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 258 | 1 | DEV_RTI28_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 258 | 2 | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 258 | 3 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 258 | 4 | DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 258 | 5 | DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 258 | 6 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 258 | 7 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | |
| | 258 | 8 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | |
| | 258 | 9 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | |
| | 259 | 0 | DEV_RTI29_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 259 | 1 | DEV_RTI29_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 259 | 2 | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 259 | 3 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 259 | 4 | DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 259 | 5 | DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 259 | 6 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 259 | 7 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | |
| | 259 | 8 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | |
| | 259 | 9 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | |
| | 292 | 1 | DEV_SERDES_10G1_IP3_LN1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 3 | DEV_SERDES_10G1_IP2_LN2_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 4 | DEV_SERDES_10G1_IP1_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 6 | DEV_SERDES_10G1_IP3_LN3_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 9 | DEV_SERDES_10G1_IP2_LN2_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 10 | DEV_SERDES_10G1_IP1_LN0_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 11 | DEV_SERDES_10G1_CLK | CLK_STATE_READY | 125000000 | | |
| | 292 | 13 | DEV_SERDES_10G1_IP1_LN3_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 14 | DEV_SERDES_10G1_IP1_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 15 | DEV_SERDES_10G1_IP2_LN0_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 16 | DEV_SERDES_10G1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 19 | DEV_SERDES_10G1_IP3_LN1_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 21 | DEV_SERDES_10G1_IP2_LN3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 22 | DEV_SERDES_10G1_IP1_LN2_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 24 | DEV_SERDES_10G1_IP2_LN1_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 25 | DEV_SERDES_10G1_IP2_LN1_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 29 | DEV_SERDES_10G1_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 32 | DEV_SERDES_10G1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 33 | DEV_SERDES_10G1_IP2_LN1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 34 | DEV_SERDES_10G1_IP1_LN1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 38 | DEV_SERDES_10G1_IP1_LN2_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 40 | DEV_SERDES_10G1_IP2_LN1_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 41 | DEV_SERDES_10G1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 42 | DEV_SERDES_10G1_IP2_LN3_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 43 | DEV_SERDES_10G1_IP2_LN2_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 44 | DEV_SERDES_10G1_IP2_LN2_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 45 | DEV_SERDES_10G1_IP1_LN1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 49 | DEV_SERDES_10G1_IP1_LN0_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 52 | DEV_SERDES_10G1_IP1_LN1_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 55 | DEV_SERDES_10G1_IP1_LN0_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 56 | DEV_SERDES_10G1_IP3_LN3_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 59 | DEV_SERDES_10G1_IP2_LN3_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 61 | DEV_SERDES_10G1_IP2_LN0_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 62 | DEV_SERDES_10G1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 63 | DEV_SERDES_10G1_IP1_LN1_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 65 | DEV_SERDES_10G1_IP1_LN3_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 66 | DEV_SERDES_10G1_IP3_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 67 | DEV_SERDES_10G1_IP2_LN2_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 73 | DEV_SERDES_10G1_IP3_LN1_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 74 | DEV_SERDES_10G1_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 75 | DEV_SERDES_10G1_IP1_LN3_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 77 | DEV_SERDES_10G1_IP1_LN0_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 80 | DEV_SERDES_10G1_IP1_LN2_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 81 | DEV_SERDES_10G1_IP2_LN0_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 82 | DEV_SERDES_10G1_IP2_LN0_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 85 | DEV_SERDES_10G1_CORE_REF_CLK | CLK_STATE_READY | 100000000 | | |
| | 292 | 86 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 292 | 87 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 292 | 88 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 125000000 | | |
| | 292 | 89 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | |
| | 292 | 92 | DEV_SERDES_10G1_IP1_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 95 | DEV_SERDES_10G1_IP2_LN3_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 96 | DEV_SERDES_10G1_IP3_LN3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 98 | DEV_SERDES_10G1_IP3_LN3_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 100 | DEV_SERDES_10G1_IP2_LN1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 102 | DEV_SERDES_10G1_IP3_LN1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 104 | DEV_SERDES_10G1_IP1_LN1_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 107 | DEV_SERDES_10G1_IP3_LN3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 108 | DEV_SERDES_10G1_IP1_LN3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 109 | DEV_SERDES_10G1_IP2_LN3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 111 | DEV_SERDES_10G1_IP1_LN0_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 112 | DEV_SERDES_10G1_IP2_LN0_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 113 | DEV_SERDES_10G1_IP1_LN2_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 118 | DEV_SERDES_10G1_IP1_LN2_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 124 | DEV_SERDES_10G1_IP1_LN3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 126 | DEV_SERDES_10G1_IP3_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 29 | 0 | DEV_STM0_CORE_CLK | CLK_STATE_READY | 250000000 | | |
| | 29 | 1 | DEV_STM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 29 | 2 | DEV_STM0_ATB_CLK | CLK_STATE_READY | 250000000 | | |
| | 49 | 0 | DEV_TIMER0_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 49 | 1 | DEV_TIMER0_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 49 | 2 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 49 | 3 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 4 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 49 | 5 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 49 | 6 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 49 | 7 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 8 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 9 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 10 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 11 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 49 | 12 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 49 | 13 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 49 | 14 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 49 | 15 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 49 | 16 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 49 | 17 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 49 | 26 | DEV_TIMER0_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 50 | 0 | DEV_TIMER1_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 50 | 1 | DEV_TIMER1_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 50 | 2 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1 | CLK_STATE_READY | 19200000 | | |
| | 50 | 3 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 60 | 0 | DEV_TIMER10_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 60 | 1 | DEV_TIMER10_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 60 | 2 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 60 | 3 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 4 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 60 | 5 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 60 | 6 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 60 | 7 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 8 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 9 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 10 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 11 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 60 | 12 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 60 | 13 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 60 | 14 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 60 | 15 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 60 | 16 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 60 | 17 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 60 | 26 | DEV_TIMER10_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 62 | 0 | DEV_TIMER11_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 62 | 1 | DEV_TIMER11_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 62 | 2 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11 | CLK_STATE_READY | 19200000 | | |
| | 62 | 3 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 318 | 0 | DEV_TIMER11_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 318 | 1 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 318 | 2 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 3 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 318 | 4 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 318 | 5 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 318 | 6 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 7 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 8 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 9 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 10 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 318 | 11 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 318 | 12 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 318 | 13 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 318 | 14 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 318 | 15 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 318 | 16 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 63 | 0 | DEV_TIMER12_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 63 | 1 | DEV_TIMER12_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 63 | 2 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 63 | 3 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 4 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 63 | 5 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 63 | 6 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 63 | 7 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 8 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 9 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 10 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 11 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 63 | 12 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 63 | 13 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 63 | 14 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 63 | 15 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 63 | 16 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 63 | 17 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 63 | 26 | DEV_TIMER12_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 64 | 0 | DEV_TIMER13_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 64 | 1 | DEV_TIMER13_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 64 | 2 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13 | CLK_STATE_READY | 19200000 | | |
| | 64 | 3 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 319 | 0 | DEV_TIMER13_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 319 | 1 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 319 | 2 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 3 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 319 | 4 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 319 | 5 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 319 | 6 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 7 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 8 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 9 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 10 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 319 | 11 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 319 | 12 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 319 | 13 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 319 | 14 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 319 | 15 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 319 | 16 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 65 | 0 | DEV_TIMER14_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 65 | 1 | DEV_TIMER14_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 65 | 2 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 65 | 3 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 4 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 65 | 5 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 65 | 6 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 65 | 7 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 8 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 9 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 10 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 11 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 65 | 12 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 65 | 13 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 65 | 14 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 65 | 15 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 65 | 16 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 65 | 17 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 65 | 26 | DEV_TIMER14_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 66 | 0 | DEV_TIMER15_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 66 | 1 | DEV_TIMER15_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 66 | 2 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15 | CLK_STATE_READY | 19200000 | | |
| | 66 | 3 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 320 | 0 | DEV_TIMER15_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 320 | 1 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 320 | 2 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 3 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 320 | 4 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 320 | 5 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 320 | 6 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 7 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 8 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 9 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 10 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 320 | 11 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 320 | 12 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 320 | 13 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 320 | 14 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 320 | 15 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 320 | 16 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 67 | 0 | DEV_TIMER16_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 67 | 1 | DEV_TIMER16_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 67 | 2 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 67 | 3 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 4 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 67 | 5 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 67 | 6 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 67 | 7 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 8 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 9 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 10 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 11 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 67 | 12 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 67 | 13 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 67 | 14 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 67 | 15 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 67 | 16 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 67 | 17 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 67 | 26 | DEV_TIMER16_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 68 | 0 | DEV_TIMER17_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 68 | 1 | DEV_TIMER17_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 68 | 2 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17 | CLK_STATE_READY | 19200000 | | |
| | 68 | 3 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 321 | 0 | DEV_TIMER17_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 321 | 1 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 321 | 2 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 3 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 321 | 4 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 321 | 5 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 321 | 6 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 7 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 8 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 9 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 10 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 321 | 11 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 321 | 12 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 321 | 13 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 321 | 14 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 321 | 15 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 321 | 16 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 69 | 0 | DEV_TIMER18_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 69 | 1 | DEV_TIMER18_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 69 | 2 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 69 | 3 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 4 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 69 | 5 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 69 | 6 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 69 | 7 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 8 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 9 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 10 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 11 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 69 | 12 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 69 | 13 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 69 | 14 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 69 | 15 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 69 | 16 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 69 | 17 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 69 | 26 | DEV_TIMER18_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 70 | 0 | DEV_TIMER19_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 70 | 1 | DEV_TIMER19_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 70 | 2 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19 | CLK_STATE_READY | 19200000 | | |
| | 70 | 3 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 322 | 0 | DEV_TIMER19_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 322 | 1 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 322 | 2 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 3 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 322 | 4 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 322 | 5 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 322 | 6 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 7 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 8 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 9 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 10 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 322 | 11 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 322 | 12 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 322 | 13 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 322 | 14 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 322 | 15 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 322 | 16 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 313 | 0 | DEV_TIMER1_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 313 | 1 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 313 | 2 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 3 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 313 | 4 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 313 | 5 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 313 | 6 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 7 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 8 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 9 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 10 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 313 | 11 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 313 | 12 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 313 | 13 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 313 | 14 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 313 | 15 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 313 | 16 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 51 | 0 | DEV_TIMER2_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 51 | 1 | DEV_TIMER2_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 51 | 2 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 51 | 3 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 4 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 51 | 5 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 51 | 6 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 51 | 7 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 8 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 9 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 10 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 11 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 51 | 12 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 51 | 13 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 51 | 14 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 51 | 15 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 51 | 16 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 51 | 17 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 51 | 26 | DEV_TIMER2_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 52 | 0 | DEV_TIMER3_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 52 | 1 | DEV_TIMER3_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 52 | 2 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3 | CLK_STATE_READY | 19200000 | | |
| | 52 | 3 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 314 | 0 | DEV_TIMER3_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 314 | 1 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 314 | 2 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 3 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 314 | 4 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 314 | 5 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 314 | 6 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 7 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 8 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 9 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 10 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 314 | 11 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 314 | 12 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 314 | 13 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 314 | 14 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 314 | 15 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 314 | 16 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 53 | 0 | DEV_TIMER4_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 53 | 1 | DEV_TIMER4_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 53 | 2 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 53 | 3 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 4 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 53 | 5 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 53 | 6 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 53 | 7 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 8 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 9 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 10 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 11 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 53 | 12 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 53 | 13 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 53 | 14 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 53 | 15 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 53 | 16 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 53 | 17 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 53 | 26 | DEV_TIMER4_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 54 | 0 | DEV_TIMER5_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 54 | 1 | DEV_TIMER5_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 54 | 2 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5 | CLK_STATE_READY | 19200000 | | |
| | 54 | 3 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 315 | 0 | DEV_TIMER5_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 315 | 1 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 315 | 2 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 3 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 315 | 4 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 315 | 5 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 315 | 6 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 7 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 8 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 9 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 10 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 315 | 11 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 315 | 12 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 315 | 13 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 315 | 14 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 315 | 15 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 315 | 16 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 55 | 0 | DEV_TIMER6_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 55 | 1 | DEV_TIMER6_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 55 | 2 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 55 | 3 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 4 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 55 | 5 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 55 | 6 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 55 | 7 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 8 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 9 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 10 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 11 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 55 | 12 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 55 | 13 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 55 | 14 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 55 | 15 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 55 | 16 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 55 | 17 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 55 | 26 | DEV_TIMER6_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 57 | 0 | DEV_TIMER7_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 57 | 1 | DEV_TIMER7_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 57 | 2 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7 | CLK_STATE_READY | 19200000 | | |
| | 57 | 3 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 316 | 0 | DEV_TIMER7_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 316 | 1 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 316 | 2 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 3 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 316 | 4 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 316 | 5 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 316 | 6 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 7 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 8 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 9 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 10 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 316 | 11 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 316 | 12 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 316 | 13 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 316 | 14 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 316 | 15 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 316 | 16 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 58 | 0 | DEV_TIMER8_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 58 | 1 | DEV_TIMER8_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 58 | 2 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 58 | 3 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 58 | 4 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 58 | 5 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 58 | 6 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 58 | 7 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 58 | 8 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 58 | 9 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 58 | 10 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 58 | 11 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 58 | 12 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 58 | 13 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 58 | 14 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 58 | 15 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 58 | 16 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 58 | 17 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 58 | 26 | DEV_TIMER8_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 59 | 0 | DEV_TIMER9_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 59 | 1 | DEV_TIMER9_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 59 | 2 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9 | CLK_STATE_READY | 19200000 | | |
| | 59 | 3 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 317 | 0 | DEV_TIMER9_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 317 | 1 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 317 | 2 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 317 | 3 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 317 | 4 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 317 | 5 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 317 | 6 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 317 | 7 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 317 | 8 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 317 | 9 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 317 | 10 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 317 | 11 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 317 | 12 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 317 | 13 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 317 | 14 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 317 | 15 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 317 | 16 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 146 | 2 | DEV_UART0_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 146 | 3 | DEV_UART0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 278 | 2 | DEV_UART1_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 278 | 3 | DEV_UART1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 279 | 2 | DEV_UART2_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 279 | 3 | DEV_UART2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 280 | 2 | DEV_UART3_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 280 | 3 | DEV_UART3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 281 | 2 | DEV_UART4_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 281 | 3 | DEV_UART4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 282 | 2 | DEV_UART5_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 282 | 3 | DEV_UART5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 283 | 2 | DEV_UART6_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 283 | 3 | DEV_UART6_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 284 | 2 | DEV_UART7_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 284 | 3 | DEV_UART7_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 285 | 2 | DEV_UART8_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 285 | 3 | DEV_UART8_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 286 | 2 | DEV_UART9_FCLK_CLK | CLK_STATE_READY | 48000000 | | |
| | 286 | 3 | DEV_UART9_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 288 | 0 | DEV_USB0_PIPE_REFCLK | CLK_STATE_READY | 0 | | |
| | 288 | 1 | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | |
| | 288 | 2 | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP3_LN3_REFCLK | CLK_STATE_READY | 0 | | |
| | 288 | 3 | DEV_USB0_CLK_LPM_CLK | CLK_STATE_READY | 24000000 | | |
| | 288 | 4 | DEV_USB0_BUF_CLK | CLK_STATE_READY | 250000000 | | |
| | 288 | 5 | DEV_USB0_PIPE_TXFCLK | CLK_STATE_READY | 0 | | |
| | 288 | 6 | DEV_USB0_USB2_APB_PCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 288 | 7 | DEV_USB0_PIPE_RXCLK | CLK_STATE_READY | 0 | | |
| | 288 | 8 | DEV_USB0_PIPE_TXMCLK | CLK_STATE_READY | 0 | | |
| | 288 | 9 | DEV_USB0_PIPE_RXFCLK | CLK_STATE_READY | 0 | | |
| | 288 | 11 | DEV_USB0_PIPE_TXCLK | CLK_STATE_READY | 0 | | |
| | 288 | 12 | DEV_USB0_USB2_REFCLOCK_CLK | CLK_STATE_READY | 19200000 | | |
| | 288 | 13 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 288 | 14 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 288 | 15 | DEV_USB0_PCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 288 | 17 | DEV_USB0_ACLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 145 | 0 | DEV_WKUP_DDPA0_DDPA_CLK | CLK_STATE_READY | 166666666 | | |
| | 99 | 0 | DEV_WKUP_ESM0_CLK | CLK_STATE_READY | 166666666 | | |
| | 113 | 0 | DEV_WKUP_GPIO0_MMR_CLK | CLK_STATE_READY | 166666666 | | |
| | 113 | 1 | DEV_WKUP_GPIO0_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | |
| | 113 | 2 | DEV_WKUP_GPIO0_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6_DUP0 | CLK_STATE_READY | 166666666 | | |
| | 113 | 3 | DEV_WKUP_GPIO0_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 113 | 4 | DEV_WKUP_GPIO0_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 114 | 0 | DEV_WKUP_GPIO1_MMR_CLK | CLK_STATE_READY | 166666666 | | |
| | 114 | 1 | DEV_WKUP_GPIO1_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | |
| | 114 | 2 | DEV_WKUP_GPIO1_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6_DUP0 | CLK_STATE_READY | 166666666 | | |
| | 114 | 3 | DEV_WKUP_GPIO1_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 114 | 4 | DEV_WKUP_GPIO1_MMR_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 197 | 0 | DEV_WKUP_I2C0_PISCL | CLK_STATE_READY | 0 | | |
| | 197 | 1 | DEV_WKUP_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 197 | 2 | DEV_WKUP_I2C0_CLK | CLK_STATE_READY | 166666666 | | |
| | 197 | 3 | DEV_WKUP_I2C0_PORSCL | CLK_STATE_READY | 0 | | |
| | 132 | 0 | DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK | CLK_STATE_READY | 12500000 | | |
| | 138 | 0 | DEV_WKUP_PSC0_SLOW_CLK | CLK_STATE_READY | 41666666 | | |
| | 138 | 1 | DEV_WKUP_PSC0_CLK | CLK_STATE_READY | 166666666 | | |
| | 287 | 2 | DEV_WKUP_UART0_FCLK_CLK | CLK_STATE_READY | 96000000 | | |
| | 287 | 3 | DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0 | CLK_STATE_READY | 96000000 | | |
| | 287 | 4 | DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 287 | 5 | DEV_WKUP_UART0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 154 | 0 | DEV_WKUP_VTM0_FIX_REF2_CLK | CLK_STATE_READY | 12500000 | | |
| | 154 | 1 | DEV_WKUP_VTM0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 154 | 2 | DEV_WKUP_VTM0_FIX_REF_CLK | CLK_STATE_READY | 19200000 | | |
| | 40 | 0 | DEV_WKUP_WAKEUP0_PLL_CTRL_WKUP_CLK24_CLK | CLK_STATE_READY | 1000000000 | | |
| | 40 | 1 | DEV_WKUP_WAKEUP0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 40 | 2 | DEV_WKUP_WAKEUP0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| |--------------------------------------------------------------------------------------------------------------------------------------------------| | |
| root@j7200-evm:~# cat /sys/class/ kernel/debug/cl | |
| clear_warn_once clk/ | |
| root@j7200-evm:~# cat /sys/kernel/debug/clk/clk_S summary | |
| enable prepare protect duty hardware connection | |
| clock count count count rate accuracy phase cycle enable consumer id | |
| --------------------------------------------------------------------------------------------------------------------------------------------- | |
| clk:292:89 0 0 0 100000000 0 0 50000 Y deviceless no_connection_id | |
| clk:292:85 0 0 0 100000000 0 0 50000 Y deviceless no_connection_id | |
| clk:292:88 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id | |
| clk:292:87 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:292:86 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:292:11 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id | |
| clk:288:14 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:288:13 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:288:12 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:288:3 0 0 0 24000000 0 0 50000 Y deviceless no_connection_id | |
| clk:278:2 0 0 0 48000000 0 0 50000 Y deviceless no_connection_id | |
| clk:253:9 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:253:8 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:253:7 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:253:6 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:253:5 0 0 0 32550 0 0 50000 Y deviceless no_connection_id | |
| clk:253:4 0 0 0 12500000 0 0 50000 Y deviceless no_connection_id | |
| clk:253:3 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:253:2 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:253:1 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:252:9 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:252:8 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:252:7 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:252:6 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:252:5 0 0 0 32550 0 0 50000 Y deviceless no_connection_id | |
| clk:252:4 0 0 0 12500000 0 0 50000 Y deviceless no_connection_id | |
| clk:252:3 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:252:2 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:252:1 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:240:6 0 0 0 250000000 0 0 50000 Y deviceless no_connection_id | |
| clk:203:0 0 0 0 748800000 0 0 50000 Y cpu1 no_connection_id | |
| cpu1 no_connection_id | |
| deviceless no_connection_id | |
| clk:202:2 0 0 0 748800000 0 0 50000 Y cpu0 no_connection_id | |
| cpu0 no_connection_id | |
| deviceless no_connection_id | |
| clk:201:21 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:20 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:17 0 0 0 500000000 0 0 50000 Y deviceless no_connection_id | |
| clk:201:16 0 0 0 500000000 0 0 50000 Y deviceless no_connection_id | |
| clk:201:11 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:10 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:9 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:8 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:7 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:6 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:5 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:4 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:201:3 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:201:2 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:201:1 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:197:1 0 0 0 96000000 0 0 50000 Y deviceless no_connection_id | |
| clk:188:1 0 0 0 96000000 0 0 50000 Y deviceless no_connection_id | |
| clk:187:1 0 0 0 96000000 0 0 50000 Y deviceless no_connection_id | |
| clk:149:4 0 0 0 192000000 0 0 50000 Y deviceless no_connection_id | |
| clk:149:3 0 0 0 96000000 0 0 50000 Y deviceless no_connection_id | |
| clk:149:2 0 0 0 96000000 0 0 50000 Y deviceless no_connection_id | |
| clk:146:2 0 0 0 48000000 0 0 50000 Y deviceless no_connection_id | |
| clk:113:4 0 0 0 12500000 0 0 50000 Y deviceless no_connection_id | |
| clk:113:3 0 0 0 32550 0 0 50000 Y deviceless no_connection_id | |
| clk:113:2 0 0 0 166666666 0 0 50000 Y deviceless no_connection_id | |
| clk:113:1 1 1 0 166666666 0 0 50000 Y deviceless no_connection_id | |
| clk:113:0 1 1 0 166666666 0 0 50000 Y 42110000.gpio gpio | |
| deviceless no_connection_id | |
| clk:105:0 1 1 0 125000000 0 0 50000 Y 600000.gpio gpio | |
| deviceless no_connection_id | |
| clk:103:2 0 0 0 166666666 0 0 50000 Y deviceless no_connection_id | |
| clk:103:0 0 0 0 166666666 0 0 50000 Y 47040000.spi no_connection_id | |
| deviceless no_connection_id | |
| clk:103:1 0 0 0 133333333 0 0 50000 Y deviceless no_connection_id | |
| clk:92:6 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:92:5 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:92:4 0 0 0 192000000 0 0 50000 Y deviceless no_connection_id | |
| clk:92:3 1 1 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:92:2 1 1 0 200000000 0 0 50000 Y 4fb0000.mmc clk_xin | |
| deviceless no_connection_id | |
| clk:92:1 0 0 0 250000000 0 0 50000 Y deviceless no_connection_id | |
| clk:91:7 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:91:6 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:91:5 0 0 0 192000000 0 0 50000 Y deviceless no_connection_id | |
| clk:91:4 1 1 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:91:3 1 1 0 200000000 0 0 50000 Y 4f80000.mmc clk_xin | |
| deviceless no_connection_id | |
| clk:91:0 0 0 0 250000000 0 0 50000 Y deviceless no_connection_id | |
| clk:19:16 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:18:22 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:21 0 0 0 333333333 0 0 50000 Y 46000f00.mdio fck | |
| 46000000.ethernet fck | |
| deviceless no_connection_id | |
| clk:18:20 0 0 0 25000000 0 0 50000 Y deviceless no_connection_id | |
| clk:18:18 0 0 0 500000000 0 0 50000 Y deviceless no_connection_id | |
| clk:18:2 0 0 0 500000000 0 0 50000 Y deviceless no_connection_id | |
| clk:18:17 0 0 0 500000000 0 0 50000 Y deviceless no_connection_id | |
| clk:18:12 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:11 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:10 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:9 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:8 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:7 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:6 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:5 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:18:4 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:18:3 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id | |
| clk:0:5 0 0 0 0 0 0 50000 Y deviceless no_connection_id | |
| clk:0:4 0 0 0 58823529 0 0 50000 Y deviceless no_connection_id | |
| clk:0:3 0 0 0 60000000 0 0 50000 Y deviceless no_connection_id | |
| clk:0:2 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| clk:0:1 0 0 0 19200000 0 0 50000 Y deviceless no_connection_id | |
| serdes-refclk 0 0 0 100000000 0 0 50000 Y deviceless no_connection_id | |
| root@j7200-evm:~# dmesg | grep 44083000 | |
| [ 1.088227] ti-sci 44083000.system-controller: ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| root@j7200-evm:~# |
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| root@j7200-evm:~# reboot | |
| Stopping Session c2 of User root... | |
| [ OK ] Removed slice Slice /system/modprobe. | |
| [ OK ] Stopped target Graphical Interface. | |
| [ OK ] Stopped target Multi-User System. | |
| [ OK ] Stopped target Login Prompts. | |
| [ OK ] Stopped target RPC Port Mapper. | |
| [ OK ] Stopped target Timer Units. | |
| [ OK ] Stopped Daily rotation of log files. | |
| [ OK ] Stopped Daily Cleanup of Temporary Directories. | |
| [ OK ] Stopped target System Time Set. | |
| [ OK ] Closed Process Core Dump Socket. | |
| Stopping Job spooling tools... | |
| Stopping Avahi mDNS/DNS-SD Stack... | |
| Stopping containerd container runtime... | |
| Stopping Periodic Command Scheduler... | |
| Stopping Getty on tty1... | |
| Stopping irqbalance daemon... | |
| Stopping Reboot and dump vmcore via kexec... | |
| Stopping Lighttpd Daemon... | |
| Stopping Netperf Benchmark Server... | |
| Stopping NFS status monitor for NFSv2/3 locking.... | |
| Stopping Serial Getty on ttyS2... | |
| Stopping Load/Save Random Seed... | |
| Stopping TEE Supplicant... | |
| Stopping Telnet Server... | |
| [ OK ] Stopped Job spooling tools. | |
| [ OK ] Stopped Periodic Command Scheduler. | |
| [ OK ] Stopped irqbalance daemon. | |
| [ OK ] Stopped TEE Supplicant. | |
| [ OK ] Stopped Lighttpd Daemon. | |
| [ OK ] Stopped Avahi mDNS/DNS-SD Stack. | |
| [ OK ] Stopped Netperf Benchmark Server. | |
| [ OK ] Stopped NFS status monitor for NFSv2/3 locking.. | |
| [ OK ] Stopped containerd container runtime. | |
| [ OK ] Stopped Getty on tty1. | |
| [ OK ] Stopped Serial Getty on ttyS2. | |
| [ OK ] Stopped Reboot and dump vmcore via kexec. | |
| [ OK ] Stopped Load/Save Random Seed. | |
| [ OK ] Stopped Telnet Server. | |
| [ OK ] Stopped Session c2 of User root. | |
| [ OK ] Removed slice Slice /system/getty. | |
| [ OK ] Removed slice Slice /system/serial-getty. | |
| [ OK ] Stopped target Host and Network Name Lookups. | |
| Stopping User Login Management... | |
| Stopping User Manager for UID 0... | |
| [ OK ] Stopped User Manager for UID 0. | |
| [ OK ] Stopped User Login Management. | |
| Stopping User Runtime Directory /run/user/0... | |
| [ OK ] Unmounted /run/user/0. | |
| [ OK ] Stopped User Runtime Directory /run/user/0. | |
| [ OK ] Removed slice User Slice of UID 0. | |
| Stopping Permit User Sessions... | |
| [ OK ] Stopped Permit User Sessions. | |
| [ OK ] Stopped target Network. | |
| [ OK ] Stopped target Remote File Systems. | |
| Stopping Network Name Resolution... | |
| [ OK ] Stopped Network Name Resolution. | |
| Stopping Network Configuration... | |
| [ OK ] Stopped Network Configuration. | |
| [ OK ] Stopped target Preparation for Network. | |
| [ OK ] Stopped IPv6 Packet Filtering Framework. | |
| [ OK ] Stopped IPv4 Packet Filtering Framework. | |
| [ OK ] Stopped target Basic System. | |
| [ OK ] Stopped target Path Units. | |
| [ OK ] Stopped Dispatch Password �ts to Console Directory Watch. | |
| [ OK ] Stopped Forward Password R�uests to Wall Directory Watch. | |
| [ OK ] Stopped target Slice Units. | |
| [ OK ] Removed slice User and Session Slice. | |
| [ OK ] Stopped target Socket Units. | |
| [ OK ] Closed Avahi mDNS/DNS-SD Stack Activation Socket. | |
| [ OK ] Closed Docker Socket for the API. | |
| [ OK ] Closed dropbear.socket. | |
| [ OK ] Closed PC/SC Smart Card Daemon Activation Socket. | |
| [ OK ] Closed Network Service Netlink Socket. | |
| [ OK ] Closed Weston socket. | |
| Stopping D-Bus System Message Bus... | |
| [ OK ] Stopped D-Bus System Message Bus. | |
| [ OK ] Closed D-Bus System Message Bus Socket. | |
| [ OK ] Stopped target System Initialization. | |
| [ OK ] Stopped Apply Kernel Variables. | |
| Stopping Network Time Synchronization... | |
| [ OK ] Stopped Network Time Synchronization. | |
| [ OK ] Stopped Create Volatile Files and Directories. | |
| [ OK ] Stopped target Local File Systems. | |
| Unmounting /boot... | |
| Unmounting /media/ram... | |
| Unmounting Temporary Directory /tmp... | |
| Unmounting /var/volatile... | |
| [ OK ] Unmounted /boot. | |
| [ OK ] Unmounted /media/ram. | |
| [ OK ] Unmounted Temporary Directory /tmp. | |
| [ OK ] Unmounted /var/volatile. | |
| [ OK ] Stopped target Preparation for Local File Systems. | |
| [ OK ] Stopped target Swaps. | |
| [ OK ] Reached target Unmount All Filesystems. | |
| [ OK ] Stopped Remount Root and Kernel File Systems. | |
| [ OK ] Stopped Create Static Device Nodes in /dev. | |
| [ OK ] Reached target System Shutdown. | |
| [ OK ] Reached target Late Shutdown Services. | |
| [ OK ] Finished System Reboot. | |
| [ OK ] Reached target System Reboot. | |
| [ 3801.598640] kauditd_printk_skb: 7 callbacks suppressed | |
| [ 3801.604304] audit: type=1334 audit(1707210059.805:19): prog-id=8 op=UNLOAD | |
| [ 3801.611515] audit: type=1334 audit(1707210059.805:20): prog-id=7 op=UNLOAD | |
| [ 3801.619090] audit: type=1334 audit(1707210059.809:21): prog-id=4 op=UNLOAD | |
| [ 3801.626553] audit: type=1334 audit(1707210059.809:22): prog-id=3 op=UNLOAD | |
| [ 3801.633900] audit: type=1334 audit(1707210059.813:23): prog-id=10 op=UNLOAD | |
| [ 3801.640957] audit: type=1334 audit(1707210059.813:24): prog-id=9 op=UNLOAD | |
| [ 3801.647904] audit: type=1334 audit(1707210059.829:25): prog-id=6 op=UNLOAD | |
| [ 3801.655010] audit: type=1334 audit(1707210059.829:26): prog-id=5 op=UNLOAD | |
| [ 3801.687130] systemd-shutdown[1]: Syncing filesystems and block devices. | |
| [ 3801.727205] systemd-shutdown[1]: Sending SIGTERM to remaining processes... | |
| [ 3801.746488] systemd-journald[100]: Received SIGTERM from PID 1 (systemd-shutdow). | |
| [ 3801.756450] audit: type=1335 audit(1707210059.965:27): pid=100 uid=0 auid=4294967295 tty=(none) ses=4294967295 comm="systemd-journal" exe="/lib/systemd/systemd-journald" nl-mcgrp=1 op=disconnect res=1 | |
| [ 3801.758414] systemd-shutdown[1]: Sending SIGKILL to remaining processes... | |
| [ 3801.788297] systemd-shutdown[1]: Unmounting file systems. | |
| [ 3801.796682] [610]: Remounting '/' read-only with options 'n/a'. | |
| [ 3801.822811] EXT4-fs (mmcblk1p2): re-mounted 4e3e7bf3-fbb1-4666-bc99-003ef4ba86a4 ro. Quota mode: none. | |
| [ 3801.837310] systemd-shutdown[1]: All filesystems unmounted. | |
| [ 3801.842918] systemd-shutdown[1]: Deactivating swaps. | |
| [ 3801.848055] systemd-shutdown[1]: All swaps deactivated. | |
| [ 3801.853305] systemd-shutdown[1]: Detaching loop devices. | |
| [ 3801.862205] systemd-shutdown[1]: All loop devices detached. | |
| [ 3801.867879] systemd-shutdown[1]: Stopping MD devices. | |
| [ 3801.873299] systemd-shutdown[1]: All MD devices stopped. | |
| [ 3801.878660] systemd-shutdown[1]: Detaching DM devices. | |
| [ 3801.884124] systemd-shutdown[1]: All DM devices detached. | |
| [ 3801.889552] systemd-shutdown[1]: All filesystems, swaps, loop devices, MD devices and DM devices detached. | |
| [ 3801.910748] systemd-shutdown[1]: Syncing filesystems and block devices. | |
| [ 3801.917510] systemd-shutdown[1]: Rebooting. | |
| [ 3801.975020] kvm: exiting hardware virtualization | |
| [ 3801.979661] reboot: Restarting system | |
| U-Boot SPL 2023.04-dirty (Jan 31 2024 - 23:05:06 +0530) | |
| SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| AVS finally voltage is 800000 | |
| Trying to boot from MMC2 | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Loading Environment from nowhere... OK | |
| Starting ATF on ARM64 core... | |
| NOTICE: BL31: v2.8(release):v2.8-226-g2fcd408bb3-dirty | |
| NOTICE: BL31: Built : 00:42:57, Jan 13 2023 | |
| I/TC: | |
| I/TC: OP-TEE version: 3.20.0 (gcc version 11.3.0 (GCC)) #1 Fri Jan 20 15:42:54 UTC 2023 aarch64 | |
| I/TC: WARNING: This OP-TEE configuration might be insecure! | |
| I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html | |
| I/TC: Primary CPU initializing | |
| I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| I/TC: HUK Initialized | |
| I/TC: Activated SA2UL device | |
| I/TC: Fixing SA2UL firewall owner for GP device | |
| I/TC: Enabled firewalls for SA2UL TRNG device | |
| I/TC: SA2UL TRNG initialized | |
| I/TC: SA2UL Drivers initialized | |
| I/TC: Primary CPU switching to normal world boot | |
| U-Boot SPL 2023.04-dirty (Jan 31 2024 - 23:05:14 +0530) | |
| SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| Detected: J7X-BASE-CPB rev E3 | |
| Detected: J7X-VSC8514-ETH rev E2 | |
| Trying to boot from MMC2 | |
| am654_sdhci mmc@4fb0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted | |
| U-Boot 2023.04-dirty (Jan 31 2024 - 23:05:14 +0530) | |
| SoC: J7200 SR2.0 GP | |
| Model: Texas Instruments K3 J7200 SoC | |
| Board: J7200X-PM2-SOM rev E7 | |
| DRAM: 4 GiB | |
| Core: 85 devices, 32 uclasses, devicetree: separate | |
| Flash: 0 Bytes | |
| MMC: mmc@4f80000: 0, mmc@4fb0000: 1 | |
| Loading Environment from nowhere... OK | |
| In: serial@2800000 | |
| Out: serial@2800000 | |
| Err: serial@2800000 | |
| am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000 | |
| Detected: J7X-BASE-CPB rev E3 | |
| Detected: J7X-VSC8514-ETH rev E2 | |
| Net: eth0: ethernet@46000000port@1 | |
| Hit any key to stop autoboot: 2 1 0 | |
| switch to partitions #0, OK | |
| mmc1 is current device | |
| SD/MMC found on device 1 | |
| Failed to load 'boot.scr' | |
| 574 bytes read in 13 ms (43 KiB/s) | |
| Loaded env from uEnv.txt | |
| Importing environment from mmc1 ... | |
| gpio: pin gpio@22_17 (gpio 126) value is 1 | |
| gpio: pin gpio@22_16 (gpio 125) value is 0 | |
| k3_r5f_rproc r5f@41000000: Core 1 is already in use. No rproc commands work | |
| 64508 bytes read in 12 ms (5.1 MiB/s) | |
| Load Remote Processor 1 with data@addr=0x82000000 64508 bytes: Success! | |
| 64508 bytes read in 12 ms (5.1 MiB/s) | |
| Load Remote Processor 2 with data@addr=0x82000000 64508 bytes: Success! | |
| 64508 bytes read in 11 ms (5.6 MiB/s) | |
| Load Remote Processor 3 with data@addr=0x82000000 64508 bytes: Success! | |
| 43653632 bytes read in 461 ms (90.3 MiB/s) | |
| 59061 bytes read in 12 ms (4.7 MiB/s) | |
| Working FDT set to 88000000 | |
| ## Flattened Device Tree blob at 88000000 | |
| Booting using the fdt blob at 0x88000000 | |
| Working FDT set to 88000000 | |
| Loading Device Tree to 000000008feee000, end 000000008fffffff ... OK | |
| Working FDT set to 8feee000 | |
| Starting kernel ... | |
| [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080] | |
| [ 0.000000] Linux version 6.8.0-rc2-next-20240202-00001-gd1dc624810e3 (udit@udit-HP-Z2-Tower-G9-Workstation-Desktop-PC) (aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 11.3.Rel1) 11.3.1 20220712, GNU ld (Arm GNU Toolchain 11.3.Rel1) 2.38.20220708) #11 SMP PREEMPT Tue Feb 6 13:26:56 IST 2024 | |
| [ 0.000000] KASLR disabled due to lack of seed | |
| [ 0.000000] Machine model: Texas Instruments J7200 EVM | |
| [ 0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '') | |
| [ 0.000000] printk: legacy bootconsole [ns16550a0] enabled | |
| [ 0.000000] efi: UEFI not found. | |
| [ 0.000000] OF: reserved mem: 0x000000009e800000..0x000000009fffffff (24576 KiB) nomap non-reusable optee@9e800000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a0000000..0x00000000a00fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a0000000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a0100000..0x00000000a0ffffff (15360 KiB) nomap non-reusable r5f-memory@a0100000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a1000000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a1000000..0x00000000a10fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a1000000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-memory@a1100000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a1100000..0x00000000a1ffffff (15360 KiB) nomap non-reusable r5f-memory@a1100000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a2000000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a2000000..0x00000000a20fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a2000000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 15 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-memory@a2100000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a2100000..0x00000000a2ffffff (15360 KiB) nomap non-reusable r5f-memory@a2100000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a3000000, size 1 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a3000000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a3000000..0x00000000a30fffff (1024 KiB) nomap non-reusable r5f-dma-memory@a3000000 | |
| [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a3100000, size 15 MiB | |
| [ 0.000000] OF: reserved mem: initialized node r5f-memory@a3100000, compatible id shared-dma-pool | |
| [ 0.000000] OF: reserved mem: 0x00000000a3100000..0x00000000a3ffffff (15360 KiB) nomap non-reusable r5f-memory@a3100000 | |
| [ 0.000000] OF: reserved mem: 0x00000000a4000000..0x00000000a47fffff (8192 KiB) nomap non-reusable ipc-memories@a4000000 | |
| [ 0.000000] NUMA: No NUMA configuration found | |
| [ 0.000000] NUMA: Faking a node at [mem 0x0000000080000000-0x00000008ffffffff] | |
| [ 0.000000] NUMA: NODE_DATA [mem 0x8ff7e49c0-0x8ff7e6fff] | |
| [ 0.000000] Zone ranges: | |
| [ 0.000000] DMA [mem 0x0000000080000000-0x00000000ffffffff] | |
| [ 0.000000] DMA32 empty | |
| [ 0.000000] Normal [mem 0x0000000100000000-0x00000008ffffffff] | |
| [ 0.000000] Movable zone start for each node | |
| [ 0.000000] Early memory node ranges | |
| [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009e7fffff] | |
| [ 0.000000] node 0: [mem 0x000000009e800000-0x00000000a47fffff] | |
| [ 0.000000] node 0: [mem 0x00000000a4800000-0x00000000ffffffff] | |
| [ 0.000000] node 0: [mem 0x0000000880000000-0x00000008ffffffff] | |
| [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff] | |
| [ 0.000000] cma: Reserved 32 MiB at 0x00000000fe000000 on node -1 | |
| [ 0.000000] psci: probing for conduit method from DT. | |
| [ 0.000000] psci: PSCIv1.1 detected in firmware. | |
| [ 0.000000] psci: Using standard PSCI v0.2 function IDs | |
| [ 0.000000] psci: Trusted OS migration not required | |
| [ 0.000000] psci: SMC Calling Convention v1.2 | |
| [ 0.000000] percpu: Embedded 22 pages/cpu s51368 r8192 d30552 u90112 | |
| [ 0.000000] Detected PIPT I-cache on CPU0 | |
| [ 0.000000] CPU features: detected: GIC system register CPU interface | |
| [ 0.000000] CPU features: detected: Spectre-v3a | |
| [ 0.000000] CPU features: detected: Spectre-BHB | |
| [ 0.000000] CPU features: detected: ARM erratum 1742098 | |
| [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923 | |
| [ 0.000000] alternatives: applying boot alternatives | |
| [ 0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 root=PARTUUID=aa7aea62-02 rw rootfstype=ext4 rootwait | |
| [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) | |
| [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) | |
| [ 0.000000] Fallback order for Node 0: 0 | |
| [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1032192 | |
| [ 0.000000] Policy zone: Normal | |
| [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off | |
| [ 0.000000] software IO TLB: area num 2. | |
| [ 0.000000] software IO TLB: mapped [mem 0x00000000fa000000-0x00000000fe000000] (64MB) | |
| [ 0.000000] Memory: 3873444K/4194304K available (16768K kernel code, 4678K rwdata, 11172K rodata, 9856K init, 608K bss, 288092K reserved, 32768K cma-reserved) | |
| [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 | |
| [ 0.000000] rcu: Preemptible hierarchical RCU implementation. | |
| [ 0.000000] rcu: RCU event tracing is enabled. | |
| [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2. | |
| [ 0.000000] Trampoline variant of Tasks RCU enabled. | |
| [ 0.000000] Tracing variant of Tasks RCU enabled. | |
| [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. | |
| [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 | |
| [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 | |
| [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode | |
| [ 0.000000] GICv3: 960 SPIs implemented | |
| [ 0.000000] GICv3: 0 Extended SPIs implemented | |
| [ 0.000000] Root IRQ handler: gic_handle_irq | |
| [ 0.000000] GICv3: GICv3 features: 16 PPIs | |
| [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000 | |
| [ 0.000000] ITS [mem 0x01820000-0x0182ffff] | |
| [ 0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS | |
| [ 0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19 | |
| [ 0.000000] ITS@0x0000000001820000: allocated 524288 Devices @880800000 (flat, esz 8, psz 64K, shr 0) | |
| [ 0.000000] ITS: using cache flushing for cmd queue | |
| [ 0.000000] GICv3: using LPI property table @0x0000000880040000 | |
| [ 0.000000] GIC: using cache flushing for LPI property table | |
| [ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000880050000 | |
| [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. | |
| [ 0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys). | |
| [ 0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns | |
| [ 0.000000] sched_clock: 58 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns | |
| [ 0.008699] Console: colour dummy device 80x25 | |
| [ 0.013282] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000) | |
| [ 0.023954] pid_max: default: 32768 minimum: 301 | |
| [ 0.028701] LSM: initializing lsm=capability,integrity | |
| [ 0.034011] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) | |
| [ 0.041589] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) | |
| [ 0.050076] cacheinfo: Unable to detect cache hierarchy for CPU 0 | |
| [ 0.056745] RCU Tasks: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1. | |
| [ 0.064002] RCU Tasks Trace: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1. | |
| [ 0.071878] rcu: Hierarchical SRCU implementation. | |
| [ 0.076778] rcu: Max phase no-delay instances is 1000. | |
| [ 0.082290] Platform MSI: msi-controller@1820000 domain created | |
| [ 0.088446] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created | |
| [ 0.097750] fsl-mc MSI: msi-controller@1820000 domain created | |
| [ 0.104412] EFI services will not be available. | |
| [ 0.109152] smp: Bringing up secondary CPUs ... | |
| I/TC: Secondary CPU 1 initializing | |
| I/TC: Secondary CPU 1 switching to normal world boot | |
| [ 0.122309] Detected PIPT I-cache on CPU1 | |
| [ 0.122337] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000 | |
| [ 0.122353] GICv3: CPU1: using allocated LPI pending table @0x0000000880060000 | |
| [ 0.122387] CPU1: Booted secondary processor 0x0000000001 [0x411fd080] | |
| [ 0.122449] smp: Brought up 1 node, 2 CPUs | |
| [ 0.151800] SMP: Total of 2 processors activated. | |
| [ 0.156604] CPU: All CPU(s) started at EL2 | |
| [ 0.160806] CPU features: detected: 32-bit EL0 Support | |
| [ 0.166056] CPU features: detected: 32-bit EL1 Support | |
| [ 0.171304] CPU features: detected: CRC32 instructions | |
| [ 0.176571] alternatives: applying system-wide alternatives | |
| [ 0.183477] devtmpfs: initialized | |
| [ 0.191027] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns | |
| [ 0.201002] futex hash table entries: 512 (order: 3, 32768 bytes, linear) | |
| [ 0.208531] pinctrl core: initialized pinctrl subsystem | |
| [ 0.215141] DMI not present or invalid. | |
| [ 0.219509] NET: Registered PF_NETLINK/PF_ROUTE protocol family | |
| [ 0.225995] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations | |
| [ 0.233312] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations | |
| [ 0.241351] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations | |
| [ 0.249469] audit: initializing netlink subsys (disabled) | |
| [ 0.255082] audit: type=2000 audit(0.164:1): state=initialized audit_enabled=0 res=1 | |
| [ 0.255721] thermal_sys: Registered thermal governor 'step_wise' | |
| [ 0.263010] thermal_sys: Registered thermal governor 'power_allocator' | |
| [ 0.269185] cpuidle: using governor menu | |
| [ 0.279966] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. | |
| [ 0.286934] ASID allocator initialised with 65536 entries | |
| [ 0.293478] Serial: AMBA PL011 UART driver | |
| [ 0.308670] platform a40000.pinctrl: Fixed dependency cycle(s) with /bus@100000/pinctrl@a40000/mcu-cpsw-cpts | |
| [ 0.319681] Modules: 21952 pages in range for non-PLT usage | |
| [ 0.319685] Modules: 513472 pages in range for PLT usage | |
| [ 0.325847] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages | |
| [ 0.338215] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page | |
| [ 0.344618] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages | |
| [ 0.351553] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page | |
| [ 0.357955] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages | |
| [ 0.364889] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page | |
| [ 0.371291] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages | |
| [ 0.378225] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page | |
| [ 0.385575] ACPI: Interpreter disabled. | |
| [ 0.390803] k3-chipinfo 43000014.chipid: Family:J7200 rev:SR2.0 JTAGID[0x1bb6d02f] Detected | |
| [ 0.400156] iommu: Default domain type: Translated | |
| [ 0.405061] iommu: DMA domain TLB invalidation policy: strict mode | |
| [ 0.411554] SCSI subsystem initialized | |
| [ 0.415582] usbcore: registered new interface driver usbfs | |
| [ 0.421205] usbcore: registered new interface driver hub | |
| [ 0.426644] usbcore: registered new device driver usb | |
| [ 0.432333] pps_core: LinuxPPS API ver. 1 registered | |
| [ 0.437408] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> | |
| [ 0.446749] PTP clock support registered | |
| [ 0.450830] EDAC MC: Ver: 3.0.0 | |
| [ 0.454407] scmi_core: SCMI protocol bus registered | |
| [ 0.459981] FPGA manager framework | |
| [ 0.463501] Advanced Linux Sound Architecture Driver Initialized. | |
| [ 0.470215] vgaarb: loaded | |
| [ 0.473232] clocksource: Switched to clocksource arch_sys_counter | |
| [ 0.479594] VFS: Disk quotas dquot_6.6.0 | |
| [ 0.483617] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) | |
| [ 0.490745] pnp: PnP ACPI: disabled | |
| [ 0.497539] NET: Registered PF_INET protocol family | |
| [ 0.502803] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear) | |
| [ 0.511830] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear) | |
| [ 0.520605] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) | |
| [ 0.528532] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear) | |
| [ 0.536755] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear) | |
| [ 0.545490] TCP: Hash tables configured (established 32768 bind 32768) | |
| [ 0.552333] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear) | |
| [ 0.559265] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear) | |
| [ 0.566705] NET: Registered PF_UNIX/PF_LOCAL protocol family | |
| [ 0.572836] RPC: Registered named UNIX socket transport module. | |
| [ 0.578897] RPC: Registered udp transport module. | |
| [ 0.583701] RPC: Registered tcp transport module. | |
| [ 0.588504] RPC: Registered tcp-with-tls transport module. | |
| [ 0.594108] RPC: Registered tcp NFSv4.1 backchannel transport module. | |
| [ 0.600696] PCI: CLS 0 bytes, default 64 | |
| [ 0.604907] kvm [1]: IPA Size Limit: 44 bits | |
| [ 0.610171] kvm [1]: vgic-v2@6f020000 | |
| [ 0.613931] kvm [1]: GIC system register CPU interface enabled | |
| [ 0.619904] kvm [1]: vgic interrupt IRQ9 | |
| [ 0.623923] kvm [1]: Hyp mode initialized successfully | |
| [ 0.629885] Initialise system trusted keyrings | |
| [ 0.634570] workingset: timestamp_bits=42 max_order=20 bucket_order=0 | |
| [ 0.641351] squashfs: version 4.0 (2009/01/31) Phillip Lougher | |
| [ 0.647482] NFS: Registering the id_resolver key type | |
| [ 0.652661] Key type id_resolver registered | |
| [ 0.656932] Key type id_legacy registered | |
| [ 0.661039] nfs4filelayout_init: NFSv4 File Layout Driver Registering... | |
| [ 0.667889] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... | |
| [ 0.675554] 9p: Installing v9fs 9p2000 file system support | |
| [ 0.702080] Key type asymmetric registered | |
| [ 0.706265] Asymmetric key parser 'x509' registered | |
| [ 0.711276] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245) | |
| [ 0.718841] io scheduler mq-deadline registered | |
| [ 0.723468] io scheduler kyber registered | |
| [ 0.727582] io scheduler bfq registered | |
| [ 0.735811] pinctrl-single 4301c000.pinctrl: 13 pins, size 52 | |
| [ 0.741814] pinctrl-single 4301c038.pinctrl: 2 pins, size 8 | |
| [ 0.747607] pinctrl-single 4301c068.pinctrl: 59 pins, size 236 | |
| [ 0.753721] pinctrl-single 4301c174.pinctrl: 8 pins, size 32 | |
| [ 0.759660] pinctrl-single 11c000.pinctrl: 67 pins, size 268 | |
| [ 0.765599] pinctrl-single 11c11c.pinctrl: 3 pins, size 12 | |
| [ 0.771595] pinctrl-single a40000.pinctrl: 512 pins, size 2048 | |
| [ 0.781415] EINJ: ACPI disabled. | |
| [ 0.799893] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled | |
| [ 0.808357] msm_serial: driver initialized | |
| [ 0.812775] SuperH (H)SCI(F) driver initialized | |
| [ 0.817498] STM32 USART driver initialized | |
| [ 0.825712] loop: module loaded | |
| [ 0.829676] megasas: 07.727.03.00-rc1 | |
| [ 0.837041] tun: Universal TUN/TAP device driver, 1.6 | |
| [ 0.842823] thunder_xcv, ver 1.0 | |
| [ 0.846145] thunder_bgx, ver 1.0 | |
| [ 0.849450] nicpf, ver 1.0 | |
| [ 0.852877] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version | |
| [ 0.860262] hns3: Copyright (c) 2017 Huawei Corporation. | |
| [ 0.865713] hclge is initializing | |
| [ 0.869111] e1000: Intel(R) PRO/1000 Network Driver | |
| [ 0.874094] e1000: Copyright (c) 1999-2006 Intel Corporation. | |
| [ 0.879974] e1000e: Intel(R) PRO/1000 Network Driver | |
| [ 0.885044] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. | |
| [ 0.891104] igb: Intel(R) Gigabit Ethernet Network Driver | |
| [ 0.896619] igb: Copyright (c) 2007-2014 Intel Corporation. | |
| [ 0.902320] igbvf: Intel(R) Gigabit Virtual Function Network Driver | |
| [ 0.908727] igbvf: Copyright (c) 2009 - 2012 Intel Corporation. | |
| [ 0.914977] sky2: driver version 1.30 | |
| [ 0.919518] VFIO - User Level meta-driver version: 0.3 | |
| [ 0.926451] usbcore: registered new interface driver usb-storage | |
| [ 0.934254] i2c_dev: i2c /dev entries driver | |
| [ 0.942805] sdhci: Secure Digital Host Controller Interface driver | |
| [ 0.949155] sdhci: Copyright(c) Pierre Ossman | |
| [ 0.954077] Synopsys Designware Multimedia Card Interface Driver | |
| [ 0.960750] sdhci-pltfm: SDHCI platform and OF driver helper | |
| [ 0.967615] ledtrig-cpu: registered to indicate activity on CPUs | |
| [ 0.974632] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping .... | |
| [ 0.981817] usbcore: registered new interface driver usbhid | |
| [ 0.987519] usbhid: USB HID core driver | |
| [ 0.993474] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available | |
| [ 1.003098] optee: probing for conduit method. | |
| I/TC: Reserved shared memory is enabled | |
| I/TC: Dynamic shared memory is enabled | |
| I/TC: Normal World virtualization support is disabled | |
| I/TC: Asynchronous notifications are disabled | |
| [ 1.007664] optee: revision 3.20 (8e74d476) | |
| [ 1.024118] optee: dynamic shared memory is enabled | |
| [ 1.033831] random: crng init done | |
| [ 1.037379] optee: initialized driver | |
| [ 1.043399] NET: Registered PF_PACKET protocol family | |
| [ 1.048631] 9pnet: Installing 9P2000 support | |
| [ 1.053036] Key type dns_resolver registered | |
| [ 1.061475] registered taskstats version 1 | |
| [ 1.065734] Loading compiled-in X.509 certificates | |
| [ 1.087849] ti-sci 44083000.system-controller: ABI: 3.1 (firmware rev 0x0009 '9.1.9--v09.01.09 (Kool Koala)') | |
| [ 1.100059] debugfs: Directory 'pd:240' with parent 'pm_genpd' already present! | |
| [ 1.125379] omap_i2c 42120000.i2c: bus 0 rev0.12 at 400 kHz | |
| [ 1.132022] pca953x 1-0021: supply vcc not found, using dummy regulator | |
| [ 1.138869] pca953x 1-0021: using no AI | |
| [ 1.165661] pca953x 1-0020: supply vcc not found, using dummy regulator | |
| [ 1.172472] pca953x 1-0020: using no AI | |
| [ 1.177028] pca953x 1-0022: supply vcc not found, using dummy regulator | |
| [ 1.183849] pca953x 1-0022: using AI | |
| [ 1.188147] omap_i2c 2000000.i2c: bus 1 rev0.12 at 400 kHz | |
| [ 1.194622] pca953x 2-0020: supply vcc not found, using dummy regulator | |
| [ 1.201454] pca953x 2-0020: using no AI | |
| [ 1.229560] omap_i2c 2010000.i2c: bus 2 rev0.12 at 400 kHz | |
| [ 1.235538] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 137 domain created | |
| [ 1.244257] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 131 domain created | |
| [ 1.253744] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 213 domain created | |
| [ 1.262487] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 209 created | |
| [ 1.273881] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235 | |
| [ 1.283786] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled | |
| [ 1.290550] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64 | |
| [ 1.301514] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[120,200] sci-dev-id:211 | |
| [ 1.311680] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled | |
| [ 1.318439] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64 | |
| [ 1.327251] 40a00000.serial: ttyS1 at MMIO 0x40a00000 (irq = 251, base_baud = 6000000) is a 8250 | |
| [ 1.337737] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 252, base_baud = 3000000) is a 8250 | |
| [ 1.346596] printk: legacy console [ttyS2] enabled | |
| [ 1.346596] printk: legacy console [ttyS2] enabled | |
| [ 1.356275] printk: legacy bootconsole [ns16550a0] disabled | |
| [ 1.356275] printk: legacy bootconsole [ns16550a0] disabled | |
| [ 1.370588] 2810000.serial: ttyS3 at MMIO 0x2810000 (irq = 253, base_baud = 3000000) is a 8250 | |
| [ 1.382704] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode | |
| [ 1.429244] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000 | |
| [ 1.439115] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867 | |
| [ 1.447395] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000 | |
| [ 1.460240] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4 | |
| [ 1.467449] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64 | |
| [ 1.506636] mmc0: CQHCI version 5.10 | |
| [ 1.522592] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8) | |
| [ 1.536143] ti-udma 31150000.dma-controller: Channels: 50 (tchan: 25, rchan: 25, gp-rflow: 8) | |
| [ 1.551951] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit | |
| [ 1.552718] 7 fixed-partitions partitions found on MTD device 47040000.spi.0 | |
| [ 1.566616] Creating 7 MTD partitions on "47040000.spi.0": | |
| [ 1.572123] 0x000000000000-0x000000100000 : "ospi.tiboot3" | |
| [ 1.578938] 0x000000100000-0x000000300000 : "ospi.tispl" | |
| [ 1.585421] 0x000000300000-0x000000700000 : "ospi.u-boot" | |
| [ 1.591947] 0x000000700000-0x000000740000 : "ospi.env" | |
| [ 1.598461] 0x000000740000-0x000000780000 : "ospi.env.backup" | |
| [ 1.605351] 0x000000800000-0x000003fc0000 : "ospi.rootfs" | |
| [ 1.611811] 0x000003fc0000-0x000004000000 : "ospi.phypattern" | |
| [ 1.622156] davinci_mdio 46000f00.mdio: Configuring MDIO in manual mode | |
| [ 1.669258] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000 | |
| [ 1.679863] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867 | |
| [ 1.688222] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000 | |
| [ 1.701174] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4 | |
| [ 1.708414] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64 | |
| [ 1.719652] mmc0: Command Queue Engine enabled | |
| [ 1.724144] mmc0: new HS400 MMC card at address 0001 | |
| [ 1.729701] mmcblk0: mmc0:0001 S0J56X 14.8 GiB | |
| [ 1.737036] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48 | |
| [ 1.745109] mmcblk0: p1 | |
| [ 1.748425] clk: Disabling unused clocks | |
| [ 1.750068] mmc1: CQHCI version 5.10 | |
| [ 1.752904] mmcblk0boot0: mmc0:0001 S0J56X 31.5 MiB | |
| [ 1.759683] ALSA device list: | |
| [ 1.762021] mmcblk0boot1: mmc0:0001 S0J56X 31.5 MiB | |
| [ 1.763833] No soundcards found. | |
| [ 1.769726] mmcblk0rpmb: mmc0:0001 S0J56X 4.00 MiB, chardev (234:0) | |
| [ 1.801338] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit | |
| [ 1.809095] Waiting for root device PARTUUID=aa7aea62-02... | |
| [ 1.861487] mmc1: new ultra high speed SDR104 SDHC card at address aaaa | |
| [ 1.868779] mmcblk1: mmc1:aaaa SC16G 14.8 GiB | |
| [ 1.878353] mmcblk1: p1 p2 | |
| [ 1.904620] EXT4-fs (mmcblk1p2): mounted filesystem 4e3e7bf3-fbb1-4666-bc99-003ef4ba86a4 r/w with ordered data mode. Quota mode: none. | |
| [ 1.916772] VFS: Mounted root (ext4 filesystem) on device 179:98. | |
| [ 1.925330] devtmpfs: mounted | |
| [ 1.937502] Freeing unused kernel memory: 9856K | |
| [ 1.942287] Run /sbin/init as init process | |
| [ 2.109839] systemd[1]: System time before build time, advancing clock. | |
| [ 2.143621] systemd[1]: systemd 250.5+ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK +XKBCOMMON +UTMP +SYSVINIT default-hierarchy=hybrid) | |
| [ 2.175297] systemd[1]: Detected architecture arm64. | |
| Welcome to Arago 2023.04! | |
| [ 2.236029] systemd[1]: Hostname set to <j7200-evm>. | |
| [ 2.348892] systemd-sysv-generator[86]: SysV service '/etc/init.d/netopeer2-server' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust. | |
| [ 2.373671] systemd-sysv-generator[86]: SysV service '/etc/init.d/sysrepo' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust. | |
| [ 2.403223] systemd-sysv-generator[86]: SysV service '/etc/init.d/thermal-zone-init' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust. | |
| [ 2.600828] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6. | |
| [ 2.609770] systemd[1]: Binding to IPv6 address not available since kernel does not support IPv6. | |
| [ 2.646471] systemd[1]: /lib/systemd/system/bt-enable.service:9: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether. | |
| [ 2.710535] systemd[1]: /etc/systemd/system/sync-clocks.service:11: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether. | |
| [ 2.787538] systemd[1]: Queued start job for default target Graphical Interface. | |
| [ 2.850421] systemd[1]: Created slice Slice /system/getty. | |
| [ OK ] Created slice Slice /system/getty. | |
| [ 2.876018] systemd[1]: Created slice Slice /system/modprobe. | |
| [ OK ] Created slice Slice /system/modprobe. | |
| [ 2.900006] systemd[1]: Created slice Slice /system/serial-getty. | |
| [ OK ] Created slice Slice /system/serial-getty. | |
| [ 2.923474] systemd[1]: Created slice User and Session Slice. | |
| [ OK ] Created slice User and Session Slice. | |
| [ 2.945622] systemd[1]: Started Dispatch Password Requests to Console Directory Watch. | |
| [ OK ] Started Dispatch Password �ts to Console Directory Watch. | |
| [ 2.969550] systemd[1]: Started Forward Password Requests to Wall Directory Watch. | |
| [ OK ] Started Forward Password R�uests to Wall Directory Watch. | |
| [ 2.993687] systemd[1]: Reached target Path Units. | |
| [ OK ] Reached target Path Units. | |
| [ 3.009396] systemd[1]: Reached target Remote File Systems. | |
| [ OK ] Reached target Remote File Systems. | |
| [ 3.029372] systemd[1]: Reached target Slice Units. | |
| [ OK ] Reached target Slice Units. | |
| [ 3.045404] systemd[1]: Reached target Swaps. | |
| [ OK ] Reached target Swaps. | |
| [ 3.114900] systemd[1]: Listening on RPCbind Server Activation Socket. | |
| [ OK ] Listening on RPCbind Server Activation Socket. | |
| [ 3.141508] systemd[1]: Reached target RPC Port Mapper. | |
| [ OK ] Reached target RPC Port Mapper. | |
| [ 3.169394] systemd[1]: Listening on Process Core Dump Socket. | |
| [ OK ] Listening on Process Core Dump Socket. | |
| [ 3.189664] systemd[1]: Listening on initctl Compatibility Named Pipe. | |
| [ OK ] Listening on initctl Compatibility Named Pipe. | |
| [ 3.214035] systemd[1]: Listening on Journal Audit Socket. | |
| [ OK ] Listening on Journal Audit Socket. | |
| [ 3.237880] systemd[1]: Listening on Journal Socket (/dev/log). | |
| [ OK ] Listening on Journal Socket (/dev/log). | |
| [ 3.261869] systemd[1]: Listening on Journal Socket. | |
| [ OK ] Listening on Journal Socket. | |
| [ 3.278032] systemd[1]: Listening on Network Service Netlink Socket. | |
| [ OK ] Listening on Network Service Netlink Socket. | |
| [ 3.301913] systemd[1]: Listening on udev Control Socket. | |
| [ OK ] Listening on udev Control Socket. | |
| [ 3.321703] systemd[1]: Listening on udev Kernel Socket. | |
| [ OK ] Listening on udev Kernel Socket. | |
| [ 3.341774] systemd[1]: Listening on User Database Manager Socket. | |
| [ OK ] Listening on User Database Manager Socket. | |
| [ 3.397741] systemd[1]: Mounting Huge Pages File System... | |
| Mounting Huge Pages File System... | |
| [ 3.418270] systemd[1]: Mounting POSIX Message Queue File System... | |
| Mounting POSIX Message Queue File System... | |
| [ 3.473706] systemd[1]: Mounting Kernel Debug File System... | |
| Mounting Kernel Debug File System... | |
| [ 3.489794] systemd[1]: Kernel Trace File System was skipped because of a failed condition check (ConditionPathExists=/sys/kernel/tracing). | |
| [ 3.509891] systemd[1]: Mounting Temporary Directory /tmp... | |
| Mounting Temporary Directory /tmp... | |
| [ 3.525847] systemd[1]: Create List of Static Device Nodes was skipped because of a failed condition check (ConditionFileNotEmpty=/lib/modules/6.8.0-rc2-next-20240202-00001-gd1dc624810e3/modules.devname). | |
| [ 3.548610] systemd[1]: Starting Load Kernel Module configfs... | |
| Starting Load Kernel Module configfs... | |
| [ 3.569852] systemd[1]: Starting Load Kernel Module drm... | |
| Starting Load Kernel Module drm... | |
| [ 3.589760] systemd[1]: Starting Load Kernel Module fuse... | |
| Starting Load Kernel Module fuse... | |
| [ 3.613168] systemd[1]: Starting RPC Bind... | |
| Starting RPC Bind... | |
| [ 3.629638] systemd[1]: File System Check on Root Device was skipped because of a failed condition check (ConditionPathIsReadWrite=!/). | |
| [ 3.670141] systemd[1]: Starting Journal Service... | |
| Starting Journal Service... | |
| [ 3.703372] systemd[1]: Starting Load Kernel Modules... | |
| Starting Load Kernel Modules... | |
| [ 3.733574] systemd[1]: Starting Generate network units from Kernel command line... | |
| Starting Generate network �ts from Kernel command line... | |
| [ 3.790226] systemd[1]: Starting Remount Root and Kernel File Systems... | |
| Starting Remount Root and Kernel File Systems... | |
| [ 3.822808] systemd[1]: Starting Coldplug All udev Devices... | |
| Starting Coldplug All udev Devices... | |
| [ 3.858561] systemd[1]: Started RPC Bind. | |
| [ 3.860573] EXT4-fs (mmcblk1p2): re-mounted 4e3e7bf3-fbb1-4666-bc99-003ef4ba86a4 r/w. Quota mode: none. | |
| [ OK ] Started RPC Bind. | |
| [ 3.884003] systemd[1]: Started Journal Service. | |
| [ OK ] Started Journal Service. | |
| [ OK ] Mounted Huge Pages File System. | |
| [ OK ] Mounted POSIX Message Queue File System. | |
| [ OK ] Mounted Kernel Debug File System. | |
| [ OK ] Mounted Temporary Directory /tmp. | |
| [ OK ] Finished Load Kernel Module configfs. | |
| [ OK ] Finished Load Kernel Module drm. | |
| [ OK ] Finished Load Kernel Module fuse. | |
| [FAILED] Failed to start Load Kernel Modules. | |
| See 'systemctl status systemd-modules-load.service' for details. | |
| [ OK ] Finished Generate network units from Kernel command line. | |
| [ OK ] Finished Remount Root and Kernel File Systems. | |
| Mounting Kernel Configuration File System... | |
| Starting Flush Journal to Persistent Storage... | |
| [ 4.161819] systemd-journald[100]: Received client request to flush runtime journal. | |
| Starting Apply Kernel Variables... | |
| Starting Create Static Device Nodes in /dev... | |
| [ OK ] Mounted Kernel Configuration File System. | |
| [ OK ] Finished Flush Journal to Persistent Storage. | |
| [ OK ] Finished Apply Kernel Variables. | |
| [ OK ] Finished Create Static Device Nodes in /dev. | |
| [ OK ] Reached target Preparation for Local File Systems. | |
| Mounting /media/ram... | |
| Mounting /var/volatile... | |
| [ 4.370388] audit: type=1334 audit(1651167747.260:2): prog-id=5 op=LOAD | |
| [ 4.377705] audit: type=1334 audit(1651167747.264:3): prog-id=6 op=LOAD | |
| Starting Rule-based Manage�for Device Events and Files... | |
| [ OK ] Mounted /media/ram. | |
| [ OK ] Mounted /var/volatile. | |
| Starting Load/Save Random Seed... | |
| [ OK ] Finished Load/Save Random Seed. | |
| [ OK ] Started Rule-based Manager for Device Events and Files. | |
| [ OK ] Finished Coldplug All udev Devices. | |
| [ OK ] Found device /dev/ttyS2. | |
| [ OK ] Found device /dev/disk/by-uuid/81A5-5E73. | |
| Mounting /boot... | |
| [ 7.747439] FAT-fs (mmcblk1p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck. | |
| [ OK ] Mounted /boot. | |
| [ OK ] Reached target Local File Systems. | |
| Starting Create Volatile Files and Directories... | |
| [ OK ] Finished Create Volatile Files and Directories. | |
| Starting Network Time Synchronization... | |
| Starting Record System Boot/Shutdown in UTMP... | |
| [ OK ] Finished Record System Boot/Shutdown in UTMP. | |
| [ 8.182135] systemd-journald[100]: Oldest entry in /run/log/journal/11a1f5339a9b4ed0b552d1cfcc1c31b7/system.journal is older than the configured file retention duration (1month), suggesting rotation. | |
| [ 8.199916] systemd-journald[100]: /run/log/journal/11a1f5339a9b4ed0b552d1cfcc1c31b7/system.journal: Journal header limits reached or header out-of-date, rotating. | |
| [ OK ] Started Network Time Synchronization. | |
| [ OK ] Reached target System Initialization. | |
| [ OK ] Started Daily Cleanup of Temporary Directories. | |
| [ OK ] Reached target System Time Set. | |
| [ OK ] Started Daily rotation of log files. | |
| [ OK ] Reached target Timer Units. | |
| [ OK ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket. | |
| [ OK ] Listening on D-Bus System Message Bus Socket. | |
| Starting Docker Socket for the API... | |
| [ OK ] Listening on dropbear.socket. | |
| [ OK ] Listening on PC/SC Smart Card Daemon Activation Socket. | |
| Starting Weston socket... | |
| Starting D-Bus System Message Bus... | |
| Starting Reboot and dump vmcore via kexec... | |
| [ OK ] Listening on Docker Socket for the API. | |
| [ OK ] Listening on Weston socket. | |
| [ OK ] Finished Reboot and dump vmcore via kexec. | |
| [ OK ] Reached target Socket Units. | |
| [ OK ] Started D-Bus System Message Bus. | |
| [ OK ] Reached target Basic System. | |
| [ OK ] Started Job spooling tools. | |
| [ OK ] Started Periodic Command Scheduler. | |
| Starting Print notice about GPLv3 packages... | |
| Starting IPv6 Packet Filtering Framework... | |
| Starting IPv4 Packet Filtering Framework... | |
| [ OK ] Started irqbalance daemon. | |
| Starting Lighttpd Daemon... | |
| [ OK ] Started strongSwan IPsec I�IKEv2 daemon using ipsec.conf. | |
| [ 8.767545] audit: type=1334 audit(1707210060.005:4): prog-id=7 op=LOAD | |
| [ 8.775922] audit: type=1334 audit(1707210060.013:5): prog-id=8 op=LOAD | |
| Starting User Login Management... | |
| [ OK ] Started TEE Supplicant. | |
| Starting Telnet Server... | |
| [FAILED] Failed to start Print notice about GPLv3 packages. | |
| See 'systemctl status gplv3-notice.service' for details. | |
| [ OK ] Finished IPv6 Packet Filtering Framework. | |
| [ OK ] Finished IPv4 Packet Filtering Framework. | |
| [ OK ] Started Lighttpd Daemon. | |
| [ OK ] Finished Telnet Server. | |
| [ OK ] Reached target Preparation for Network. | |
| Starting Network Configuration... | |
| [ OK ] Started User Login Management. | |
| [ OK ] Started Network Configuration. | |
| [ 9.231898] am65-cpsw-nuss 46000000.ethernet eth0: PHY [46000f00.mdio:00] driver [TI DP83867] (irq=POLL) | |
| [ 9.241482] am65-cpsw-nuss 46000000.ethernet eth0: configuring for phy/rgmii-rxid link mode | |
| Starting Network Name Resolution... | |
| [ OK ] Started Network Name Resolution. | |
| [ OK ] Reached target Network. | |
| [ OK ] Reached target Host and Network Name Lookups. | |
| Starting Avahi mDNS/DNS-SD Stack... | |
| Starting Enable and configure wl18xx bluetooth stack... | |
| Starting containerd container runtime... | |
| [ OK ] Started Netperf Benchmark Server. | |
| [ OK ] Started NFS status monitor for NFSv2/3 locking.. | |
| Starting Permit User Sessions... | |
| [FAILED] Failed to start Enable and�figure wl18xx bluetooth stack. | |
| See 'systemctl status bt-enable.service' for details. | |
| [ OK ] Finished Permit User Sessions. | |
| [ OK ] Started Avahi mDNS/DNS-SD Stack. | |
| [ OK ] Started Getty on tty1. | |
| [ OK ] Started Serial Getty on ttyS2. | |
| [ OK ] Reached target Login Prompts. | |
| Starting Synchronize System and HW clocks... | |
| Starting Weston, a Wayland�ositor, as a system service... | |
| [FAILED] Failed to start Synchronize System and HW clocks. | |
| See 'systemctl status sync-clocks.service' for details. | |
| [ 10.081440] audit: type=1334 audit(1707210061.321:6): prog-id=9 op=LOAD | |
| [ 10.089055] audit: type=1334 audit(1707210061.325:7): prog-id=10 op=LOAD | |
| Starting User Database Manager... | |
| [ OK ] Started User Database Manager. | |
| [ OK ] Created slice User Slice of UID 1000. | |
| Starting User Runtime Directory /run/user/1000... | |
| [ OK ] Finished User Runtime Directory /run/user/1000. | |
| Starting User Manager for UID 1000... | |
| [ 10.460598] audit: type=1006 audit(1707210061.697:8): pid=488 uid=0 old-auid=4294967295 auid=1000 tty=(none) old-ses=4294967295 ses=1 res=1 | |
| [ 10.475341] audit: type=1300 audit(1707210061.697:8): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=fffffb0fc678 a2=4 a3=ffffa19fa020 items=0 ppid=1 pid=488 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=1 comm="(systemd)" exe="/lib/systemd/systemd" key=(null) | |
| [ 10.502531] audit: type=1327 audit(1707210061.697:8): proctitle="(systemd)" | |
| [ OK ] Started User Manager for UID 1000. | |
| [ OK ] Started Session c1 of User weston. | |
| [ OK ] Started containerd container runtime. | |
| [ 11.082276] audit: type=1006 audit(1707210062.321:9): pid=478 uid=0 old-auid=4294967295 auid=1000 tty=tty7 old-ses=4294967295 ses=2 res=1 | |
| [ 11.096514] audit: type=1300 audit(1707210062.321:9): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=fffffb0fc678 a2=4 a3=ffffa19fa020 items=0 ppid=1 pid=478 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=tty7 ses=2 comm="(weston)" exe="/lib/systemd/systemd" key=(null) | |
| [ 11.122855] audit: type=1327 audit(1707210062.321:9): proctitle="(weston)" | |
| [FAILED] Failed to start Weston, a �mpositor, as a system service. | |
| See 'systemctl status weston.service' for details. | |
| [DEPEND] Dependency failed for Matrix GUI. | |
| [ OK ] Reached target Multi-User System. | |
| [ OK ] Reached target Graphical Interface. | |
| Starting Record Runlevel Change in UTMP... | |
| [ OK ] Finished Record Runlevel Change in UTMP. | |
| _____ _____ _ _ | |
| | _ |___ ___ ___ ___ | _ |___ ___ |_|___ ___| |_ | |
| | | _| .'| . | . | | __| _| . | | | -_| _| _| | |
| |__|__|_| |__,|_ |___| |__| |_| |___|_| |___|___|_| | |
| |___| |___| | |
| Arago Project j7200-evm - | |
| Arago 2023.04 j7200-evm - | |
| j7200-evm login: [ 13.354444] am65-cpsw-nuss 46000000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx | |
| [ 14.436173] audit: type=1334 audit(1707210065.673:10): prog-id=11 op=LOAD | |
| [ 14.443033] audit: type=1334 audit(1707210065.673:11): prog-id=12 op=LOAD | |
| [ 44.781730] audit: type=1334 audit(1707210096.021:12): prog-id=12 op=UNLOAD | |
| [ 44.788739] audit: type=1334 audit(1707210096.021:13): prog-id=11 op=UNLOAD | |
| j7200-evm login: root | |
| [ 81.172232] audit: type=1006 audit(1707210148.243:14): pid=506 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=3 res=1 | |
| [ 81.185185] audit: type=1300 audit(1707210148.243:14): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=fffffb0fc678 a2=1 a3=0 items=0 ppid=1 pid=506 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="(systemd)" exe="/lib/systemd/systemd" key=(null) | |
| [ 81.211439] audit: type=1327 audit(1707210148.243:14): proctitle="(systemd)" | |
| [ 81.218570] audit: type=1334 audit(1707210148.267:15): prog-id=13 op=LOAD | |
| [ 81.225452] audit: type=1300 audit(1707210148.267:15): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=ffffd2e46cd0 a2=78 a3=0 items=0 ppid=1 pid=506 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/lib/systemd/systemd" key=(null) | |
| [ 81.251123] audit: type=1327 audit(1707210148.267:15): proctitle="(systemd)" | |
| [ 81.258685] audit: type=1334 audit(1707210148.283:16): prog-id=13 op=UNLOAD | |
| [ 81.266198] audit: type=1300 audit(1707210148.283:16): arch=c00000b7 syscall=57 success=yes exit=0 a0=8 a1=ffff8fb22020 a2=0 a3=ffff8fb227e0 items=0 ppid=1 pid=506 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/lib/systemd/systemd" key=(null) | |
| [ 81.292996] audit: type=1327 audit(1707210148.283:16): proctitle="(systemd)" | |
| [ 81.300874] audit: type=1334 audit(1707210148.283:17): prog-id=14 op=LOAD | |
| root@j7200-evm:~# k3conf dim um p clocks | |
| |------------------------------------------------------------------------------| | |
| | VERSION INFO | | |
| |------------------------------------------------------------------------------| | |
| | K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023) | | |
| | SoC | J7200 SR2.0 | | |
| | SYSFW | ABI: 3.1 (firmware version 0x0009 '9.1.9--v09.01.09 (Kool Koala))') | | |
| |------------------------------------------------------------------------------| | |
| |--------------------------------------------------------------------------------------------------------------------------------------------------| | |
| | Device ID | Clock ID | Clock Name | Status | Clock Frequency | | |
| |--------------------------------------------------------------------------------------------------------------------------------------------------| | |
| | 4 | 0 | DEV_A72SS0_CORE0_ARM_CLK_CLK | CLK_STATE_READY | 748800000 | | |
| | 4 | 1 | DEV_A72SS0_CORE0_MSMC_CLK | CLK_STATE_READY | 1000000000 | | |
| | 4 | 2 | DEV_A72SS0_CORE0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | |
| | 202 | 2 | DEV_A72SS0_CORE0_0_ARM_CLK_CLK | CLK_STATE_READY | 748800000 | | |
| | 203 | 0 | DEV_A72SS0_CORE0_1_ARM_CLK_CLK | CLK_STATE_READY | 748800000 | | |
| | 2 | 0 | DEV_ATL0_VBUS_CLK | CLK_STATE_READY | 250000000 | | |
| | 2 | 1 | DEV_ATL0_ATL_CLK | CLK_STATE_READY | 294912000 | | |
| | 2 | 2 | DEV_ATL0_ATL_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT1_CLK | CLK_STATE_READY | 294912000 | | |
| | 2 | 3 | DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 2 | 6 | DEV_ATL0_ATL_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT7_CLK | CLK_STATE_READY | 200000000 | | |
| | 2 | 7 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 2 | 8 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 2 | 10 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_READY | 0 | | |
| | 2 | 11 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_READY | 0 | | |
| | 2 | 12 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_READY | 0 | | |
| | 2 | 13 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 1 | DEV_BOARD0_I2C1_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 2 | DEV_BOARD0_MCASP0_ACLKR_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 3 | DEV_BOARD0_SPI2_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 4 | DEV_BOARD0_I2C3_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 5 | DEV_BOARD0_OBSCLK2_IN | CLK_STATE_READY | 500000000 | | |
| | 157 | 6 | DEV_BOARD0_MCU_I3C0_SCL_IN | CLK_STATE_READY | 0 | | |
| | 157 | 7 | DEV_BOARD0_MCU_HYPERBUS0_CKN_IN | CLK_STATE_READY | 0 | | |
| | 157 | 8 | DEV_BOARD0_I2C4_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 9 | DEV_BOARD0_RGMII3_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 11 | DEV_BOARD0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 12 | DEV_BOARD0_SPI1_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 13 | DEV_BOARD0_GPMC0_CLKOUT_IN | CLK_STATE_READY | 0 | | |
| | 157 | 14 | DEV_BOARD0_MCU_OBSCLK0_IN | CLK_STATE_READY | 1000000000 | | |
| | 157 | 15 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 | CLK_STATE_READY | 1000000000 | | |
| | 157 | 16 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 157 | 31 | DEV_BOARD0_MCU_I3C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 32 | DEV_BOARD0_SPI3_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 33 | DEV_BOARD0_MCASP0_ACLKX_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 34 | DEV_BOARD0_MCASP1_ACLKR_IN | CLK_STATE_READY | 0 | | |
| | 157 | 35 | DEV_BOARD0_CLKOUT_IN | CLK_STATE_READY | 50000000 | | |
| | 157 | 36 | DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5 | CLK_STATE_READY | 50000000 | | |
| | 157 | 37 | DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10 | CLK_STATE_READY | 25000000 | | |
| | 157 | 38 | DEV_BOARD0_OBSCLK1_IN | CLK_STATE_READY | 500000000 | | |
| | 157 | 39 | DEV_BOARD0_MCU_RMII1_REF_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 40 | DEV_BOARD0_GPMC0_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 41 | DEV_BOARD0_I3C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 43 | DEV_BOARD0_TCK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 44 | DEV_BOARD0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 45 | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 46 | DEV_BOARD0_I2C6_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 48 | DEV_BOARD0_I2C5_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 49 | DEV_BOARD0_MCU_OSPI0_DQS_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 52 | DEV_BOARD0_RGMII2_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 53 | DEV_BOARD0_MCASP2_ACLKX_IN | CLK_STATE_READY | 0 | | |
| | 157 | 54 | DEV_BOARD0_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 57 | DEV_BOARD0_MCU_HYPERBUS0_CK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 59 | DEV_BOARD0_MCASP1_ACLKX_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 61 | DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 62 | DEV_BOARD0_MDIO0_MDC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 63 | DEV_BOARD0_RGMII1_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 65 | DEV_BOARD0_MMC1_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 66 | DEV_BOARD0_MCASP2_ACLKR_IN | CLK_STATE_READY | 0 | | |
| | 157 | 68 | DEV_BOARD0_WKUP_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 69 | DEV_BOARD0_MCU_CLKOUT0_IN | CLK_STATE_READY | 50000000 | | |
| | 157 | 70 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5 | CLK_STATE_READY | 50000000 | | |
| | 157 | 71 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10 | CLK_STATE_READY | 25000000 | | |
| | 157 | 73 | DEV_BOARD0_MCASP0_ACLKR_IN | CLK_STATE_READY | 0 | | |
| | 157 | 74 | DEV_BOARD0_MCU_MDIO0_MDC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 77 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 78 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 79 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 80 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 90 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 91 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 92 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 102 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 103 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 104 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 105 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 106 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 157 | 110 | DEV_BOARD0_MCU_OSPI0_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 114 | DEV_BOARD0_MCU_SYSCLKOUT0_IN | CLK_STATE_READY | 1000000000 | | |
| | 157 | 115 | DEV_BOARD0_RGMII1_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 116 | DEV_BOARD0_LED_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 118 | DEV_BOARD0_RGMII2_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 119 | DEV_BOARD0_I3C0_SCL_IN | CLK_STATE_READY | 0 | | |
| | 157 | 120 | DEV_BOARD0_MCU_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 122 | DEV_BOARD0_SPI6_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 123 | DEV_BOARD0_WKUP_I2C0_SCL_IN | CLK_STATE_READY | 0 | | |
| | 157 | 124 | DEV_BOARD0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 126 | DEV_BOARD0_MCU_SPI1_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 127 | DEV_BOARD0_MCASP0_ACLKX_IN | CLK_STATE_READY | 0 | | |
| | 157 | 128 | DEV_BOARD0_MCASP1_ACLKX_IN | CLK_STATE_READY | 0 | | |
| | 157 | 130 | DEV_BOARD0_MCU_SPI0_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 131 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 132 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 133 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 134 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 144 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 145 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 146 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 157 | 156 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 157 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 158 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 159 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 160 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 157 | 164 | DEV_BOARD0_MCU_RGMII1_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 165 | DEV_BOARD0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 166 | DEV_BOARD0_MCU_I2C1_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 168 | DEV_BOARD0_MCASP2_ACLKR_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 169 | DEV_BOARD0_MCU_I2C0_SCL_IN | CLK_STATE_READY | 0 | | |
| | 157 | 170 | DEV_BOARD0_RMII_REF_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 171 | DEV_BOARD0_GPMC0_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 172 | DEV_BOARD0_TRC_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 174 | DEV_BOARD0_MCASP2_ACLKX_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 176 | DEV_BOARD0_RGMII4_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 177 | DEV_BOARD0_SYSCLKOUT0_IN | CLK_STATE_READY | 500000000 | | |
| | 157 | 178 | DEV_BOARD0_MCASP1_ACLKR_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 179 | DEV_BOARD0_SPI5_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 180 | DEV_BOARD0_MCU_RGMII1_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 181 | DEV_BOARD0_RGMII3_RXC_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 183 | DEV_BOARD0_SPI0_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 184 | DEV_BOARD0_GPMC0_FCLK_MUX_IN | CLK_STATE_READY | 133333333 | | |
| | 157 | 185 | DEV_BOARD0_I2C2_SCL_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 186 | DEV_BOARD0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 187 | DEV_BOARD0_MCU_OSPI0_LBCLKO_IN | CLK_STATE_READY | 0 | | |
| | 157 | 189 | DEV_BOARD0_SPI7_CLK_IN | CLK_STATE_READY | 0 | | |
| | 157 | 190 | DEV_BOARD0_RGMII4_TXC_IN | CLK_STATE_READY | 0 | | |
| | 157 | 191 | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 192 | DEV_BOARD0_OBSCLK0_IN | CLK_STATE_READY | 500000000 | | |
| | 157 | 193 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK | CLK_STATE_READY | 500000000 | | |
| | 157 | 194 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK | CLK_STATE_READY | 192000000 | | |
| | 157 | 195 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK | CLK_STATE_READY | 1800000000 | | |
| | 157 | 196 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK | CLK_STATE_READY | 250000000 | | |
| | 157 | 197 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | |
| | 157 | 205 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK | CLK_STATE_READY | 666491803 | | |
| | 157 | 206 | DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0 | CLK_STATE_NOT_READY | 0 | | |
| | 157 | 207 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK | CLK_STATE_READY | 1000000000 | | |
| | 157 | 219 | DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 157 | 220 | DEV_BOARD0_OBSCLK0_IN_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 157 | 221 | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 222 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 | CLK_STATE_READY | 500000000 | | |
| | 157 | 223 | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 157 | 224 | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 123 | 0 | DEV_CMPEVENT_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | |
| | 3 | 0 | DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | |
| | 3 | 2 | DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DBG_CLK | CLK_STATE_READY | 250000000 | | |
| | 3 | 3 | DEV_COMPUTE_CLUSTER0_TB_SOC_GIC_CLK | CLK_STATE_READY | 250000000 | | |
| | 3 | 4 | DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_DDR_PLL_CLK | CLK_STATE_READY | 666491803 | | |
| | 3 | 5 | DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_CFG_CLK | CLK_STATE_READY | 125000000 | | |
| | 3 | 6 | DEV_COMPUTE_CLUSTER0_TB_SOC_VBUSP_DMSC_CLK | CLK_STATE_READY | 125000000 | | |
| | 17 | 4 | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 19 | 0 | DEV_CPSW0_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | |
| | 19 | 1 | DEV_CPSW0_GMII3_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 2 | DEV_CPSW0_GMII2_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 3 | DEV_CPSW0_SERDES4_RXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 4 | DEV_CPSW0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 19 | 5 | DEV_CPSW0_PRE_RGMII4_TCLK | CLK_STATE_READY | 0 | | |
| | 19 | 6 | DEV_CPSW0_RGMII3_RXC_I | CLK_STATE_READY | 0 | | |
| | 19 | 7 | DEV_CPSW0_RGMII4_RXC_I | CLK_STATE_READY | 0 | | |
| | 19 | 8 | DEV_CPSW0_PRE_RGMII3_TCLK | CLK_STATE_READY | 0 | | |
| | 19 | 9 | DEV_CPSW0_RGMII1_RXC_I | CLK_STATE_READY | 0 | | |
| | 19 | 10 | DEV_CPSW0_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | |
| | 19 | 11 | DEV_CPSW0_GMII4_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 13 | DEV_CPSW0_GMII3_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 14 | DEV_CPSW0_SERDES4_RXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 15 | DEV_CPSW0_CPTS_RFT_CLK | CLK_STATE_READY | 200000000 | | |
| | 19 | 16 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 19 | 17 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 19 | 18 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 19 | 19 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 19 | 20 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 19 | 21 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 19 | 22 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 23 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 24 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 25 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 30 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 19 | 31 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 19 | 32 | DEV_CPSW0_SERDES1_TXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 33 | DEV_CPSW0_CPPI_CLK_CLK | CLK_STATE_READY | 320000000 | | |
| | 19 | 34 | DEV_CPSW0_SERDES2_RXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 35 | DEV_CPSW0_SERDES1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 36 | DEV_CPSW0_GMII_RFT_CLK | CLK_STATE_READY | 125000000 | | |
| | 19 | 37 | DEV_CPSW0_SERDES1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 38 | DEV_CPSW0_SERDES1_REFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 39 | DEV_CPSW0_RMII_MHZ_50_CLK | CLK_STATE_READY | 0 | | |
| | 19 | 40 | DEV_CPSW0_GMII4_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 41 | DEV_CPSW0_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | |
| | 19 | 42 | DEV_CPSW0_SERDES3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 43 | DEV_CPSW0_SERDES3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 45 | DEV_CPSW0_PRE_RGMII2_TCLK | CLK_STATE_READY | 0 | | |
| | 19 | 46 | DEV_CPSW0_SERDES2_TXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 47 | DEV_CPSW0_SERDES1_RXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 48 | DEV_CPSW0_SERDES1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 49 | DEV_CPSW0_RGMII2_RXC_I | CLK_STATE_READY | 0 | | |
| | 19 | 50 | DEV_CPSW0_SERDES2_TXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 51 | DEV_CPSW0_PRE_RGMII1_TCLK | CLK_STATE_READY | 0 | | |
| | 19 | 52 | DEV_CPSW0_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | |
| | 19 | 53 | DEV_CPSW0_GMII2_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 54 | DEV_CPSW0_SERDES4_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 55 | DEV_CPSW0_SERDES3_TXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 56 | DEV_CPSW0_SERDES2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 57 | DEV_CPSW0_GMII1_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 58 | DEV_CPSW0_SERDES4_REFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 59 | DEV_CPSW0_SERDES3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 19 | 60 | DEV_CPSW0_SERDES2_REFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 61 | DEV_CPSW0_SERDES3_REFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 62 | DEV_CPSW0_SERDES3_RXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 63 | DEV_CPSW0_GMII1_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 19 | 64 | DEV_CPSW0_SERDES2_RXFCLK | CLK_STATE_READY | 0 | | |
| | 19 | 66 | DEV_CPSW0_SERDES4_TXCLK | CLK_STATE_READY | 0 | | |
| | 19 | 67 | DEV_CPSW0_SERDES4_TXFCLK | CLK_STATE_READY | 0 | | |
| | 26 | 0 | DEV_CPSW_TX_RGMII0_IO__RGMII4_TXC__A | CLK_STATE_READY | 0 | | |
| | 26 | 1 | DEV_CPSW_TX_RGMII0_IO__RGMII3_TXC__A | CLK_STATE_READY | 0 | | |
| | 26 | 2 | DEV_CPSW_TX_RGMII0_IO__RGMII2_TXC__A | CLK_STATE_READY | 0 | | |
| | 26 | 3 | DEV_CPSW_TX_RGMII0_IO__RGMII1_TXC__A | CLK_STATE_READY | 0 | | |
| | 26 | 4 | DEV_CPSW_TX_RGMII0_PRE_RGMII2_TCLK | CLK_STATE_READY | 0 | | |
| | 26 | 5 | DEV_CPSW_TX_RGMII0_PRE_RGMII4_TCLK | CLK_STATE_READY | 0 | | |
| | 26 | 6 | DEV_CPSW_TX_RGMII0_PRE_RGMII3_TCLK | CLK_STATE_READY | 0 | | |
| | 26 | 7 | DEV_CPSW_TX_RGMII0_PRE_RGMII1_TCLK | CLK_STATE_READY | 0 | | |
| | 20 | 0 | DEV_CPT2_AGGR0_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 21 | 0 | DEV_CPT2_AGGR1_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 23 | 0 | DEV_CPT2_AGGR2_VCLK_CLK | CLK_STATE_READY | 250000000 | | |
| | 25 | 0 | DEV_CPT2_AGGR3_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 30 | 0 | DEV_DCC0_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | |
| | 30 | 1 | DEV_DCC0_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 30 | 2 | DEV_DCC0_DCC_CLKSRC2_CLK | CLK_STATE_READY | 133333333 | | |
| | 30 | 4 | DEV_DCC0_DCC_CLKSRC0_CLK | CLK_STATE_READY | 200000000 | | |
| | 30 | 5 | DEV_DCC0_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 30 | 6 | DEV_DCC0_DCC_CLKSRC4_CLK | CLK_STATE_READY | 19200000 | | |
| | 30 | 7 | DEV_DCC0_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | |
| | 30 | 8 | DEV_DCC0_DCC_CLKSRC3_CLK | CLK_STATE_READY | 80000000 | | |
| | 30 | 9 | DEV_DCC0_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 30 | 10 | DEV_DCC0_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | |
| | 30 | 11 | DEV_DCC0_DCC_CLKSRC6_CLK | CLK_STATE_READY | 500000000 | | |
| | 30 | 12 | DEV_DCC0_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 31 | 0 | DEV_DCC1_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | |
| | 31 | 1 | DEV_DCC1_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 31 | 2 | DEV_DCC1_DCC_CLKSRC2_CLK | CLK_STATE_READY | 200000000 | | |
| | 31 | 4 | DEV_DCC1_DCC_CLKSRC0_CLK | CLK_STATE_READY | 50000000 | | |
| | 31 | 5 | DEV_DCC1_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 31 | 6 | DEV_DCC1_DCC_CLKSRC4_CLK | CLK_STATE_READY | 320000000 | | |
| | 31 | 7 | DEV_DCC1_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | |
| | 31 | 8 | DEV_DCC1_DCC_CLKSRC3_CLK | CLK_STATE_READY | 192000000 | | |
| | 31 | 9 | DEV_DCC1_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 31 | 10 | DEV_DCC1_DCC_CLKSRC5_CLK | CLK_STATE_READY | 192000000 | | |
| | 31 | 11 | DEV_DCC1_DCC_CLKSRC6_CLK | CLK_STATE_READY | 192000000 | | |
| | 31 | 12 | DEV_DCC1_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 32 | 0 | DEV_DCC2_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | |
| | 32 | 1 | DEV_DCC2_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 32 | 2 | DEV_DCC2_DCC_CLKSRC2_CLK | CLK_STATE_READY | 200000000 | | |
| | 32 | 3 | DEV_DCC2_DCC_CLKSRC7_CLK | CLK_STATE_READY | 250000000 | | |
| | 32 | 4 | DEV_DCC2_DCC_CLKSRC0_CLK | CLK_STATE_READY | 24000000 | | |
| | 32 | 5 | DEV_DCC2_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 32 | 6 | DEV_DCC2_DCC_CLKSRC4_CLK | CLK_STATE_READY | 450000000 | | |
| | 32 | 8 | DEV_DCC2_DCC_CLKSRC3_CLK | CLK_STATE_READY | 100000000 | | |
| | 32 | 9 | DEV_DCC2_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 32 | 10 | DEV_DCC2_DCC_CLKSRC5_CLK | CLK_STATE_READY | 300000000 | | |
| | 32 | 11 | DEV_DCC2_DCC_CLKSRC6_CLK | CLK_STATE_READY | 200000000 | | |
| | 32 | 12 | DEV_DCC2_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 33 | 0 | DEV_DCC3_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | |
| | 33 | 1 | DEV_DCC3_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 33 | 2 | DEV_DCC3_DCC_CLKSRC2_CLK | CLK_STATE_READY | 196608000 | | |
| | 33 | 3 | DEV_DCC3_DCC_CLKSRC7_CLK | CLK_STATE_READY | 93600000 | | |
| | 33 | 4 | DEV_DCC3_DCC_CLKSRC0_CLK | CLK_STATE_READY | 196608000 | | |
| | 33 | 5 | DEV_DCC3_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 33 | 6 | DEV_DCC3_DCC_CLKSRC4_CLK | CLK_STATE_READY | 125000000 | | |
| | 33 | 8 | DEV_DCC3_DCC_CLKSRC3_CLK | CLK_STATE_READY | 200000000 | | |
| | 33 | 9 | DEV_DCC3_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 33 | 10 | DEV_DCC3_DCC_CLKSRC5_CLK | CLK_STATE_READY | 83 | | |
| | 33 | 11 | DEV_DCC3_DCC_CLKSRC6_CLK | CLK_STATE_READY | 250000000 | | |
| | 33 | 12 | DEV_DCC3_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 34 | 0 | DEV_DCC4_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | |
| | 34 | 1 | DEV_DCC4_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 2 | DEV_DCC4_DCC_CLKSRC2_CLK | CLK_STATE_READY | 166622950 | | |
| | 34 | 3 | DEV_DCC4_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 4 | DEV_DCC4_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 5 | DEV_DCC4_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 34 | 6 | DEV_DCC4_DCC_CLKSRC4_CLK | CLK_STATE_READY | 250000000 | | |
| | 34 | 7 | DEV_DCC4_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 8 | DEV_DCC4_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 9 | DEV_DCC4_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 34 | 10 | DEV_DCC4_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 11 | DEV_DCC4_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | |
| | 34 | 12 | DEV_DCC4_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 36 | 0 | DEV_DCC5_DCC_INPUT10_CLK | CLK_STATE_READY | 500000000 | | |
| | 36 | 1 | DEV_DCC5_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 4 | DEV_DCC5_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 5 | DEV_DCC5_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 36 | 6 | DEV_DCC5_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 7 | DEV_DCC5_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 9 | DEV_DCC5_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 36 | 11 | DEV_DCC5_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | |
| | 36 | 12 | DEV_DCC5_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 37 | 0 | DEV_DCC6_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | |
| | 37 | 1 | DEV_DCC6_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 2 | DEV_DCC6_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 3 | DEV_DCC6_DCC_CLKSRC7_CLK | CLK_STATE_READY | 200000000 | | |
| | 37 | 4 | DEV_DCC6_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 5 | DEV_DCC6_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 37 | 6 | DEV_DCC6_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 7 | DEV_DCC6_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 8 | DEV_DCC6_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 9 | DEV_DCC6_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 37 | 10 | DEV_DCC6_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | |
| | 37 | 11 | DEV_DCC6_DCC_CLKSRC6_CLK | CLK_STATE_READY | 200000000 | | |
| | 37 | 12 | DEV_DCC6_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 8 | 0 | DEV_DDR0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | |
| | 8 | 5 | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 666491803 | | |
| | 304 | 5 | DEV_DEBUGSS_WRAP0_TREXPT_CLK | CLK_STATE_READY | 300000000 | | |
| | 304 | 9 | DEV_DEBUGSS_WRAP0_CORE_CLK | CLK_STATE_READY | 125000000 | | |
| | 304 | 25 | DEV_DEBUGSS_WRAP0_JTAG_TCK | CLK_STATE_READY | 0 | | |
| | 304 | 34 | DEV_DEBUGSS_WRAP0_ATB_CLK | CLK_STATE_READY | 250000000 | | |
| | 304 | 49 | DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK | CLK_STATE_READY | 0 | | |
| | 80 | 0 | DEV_ECAP0_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 81 | 0 | DEV_ECAP1_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 82 | 0 | DEV_ECAP2_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 83 | 0 | DEV_EHRPWM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 84 | 0 | DEV_EHRPWM1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 85 | 0 | DEV_EHRPWM2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 86 | 0 | DEV_EHRPWM3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 87 | 0 | DEV_EHRPWM4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 88 | 0 | DEV_EHRPWM5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 89 | 0 | DEV_ELM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 94 | 0 | DEV_EQEP0_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 95 | 0 | DEV_EQEP1_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 96 | 0 | DEV_EQEP2_VBUS_CLK | CLK_STATE_READY | 125000000 | | |
| | 97 | 0 | DEV_ESM0_CLK | CLK_STATE_READY | 125000000 | | |
| | 105 | 0 | DEV_GPIO0_MMR_CLK | CLK_STATE_READY | 125000000 | | |
| | 107 | 0 | DEV_GPIO2_MMR_CLK | CLK_STATE_READY | 125000000 | | |
| | 109 | 0 | DEV_GPIO4_MMR_CLK | CLK_STATE_READY | 125000000 | | |
| | 111 | 0 | DEV_GPIO6_MMR_CLK | CLK_STATE_READY | 125000000 | | |
| | 131 | 0 | DEV_GPIOMUX_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | |
| | 115 | 0 | DEV_GPMC0_FUNC_CLK | CLK_STATE_READY | 133333333 | | |
| | 115 | 1 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK | CLK_STATE_READY | 133333333 | | |
| | 115 | 2 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6 | CLK_STATE_READY | 100000000 | | |
| | 115 | 3 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4 | CLK_STATE_READY | 150000000 | | |
| | 115 | 4 | DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4 | CLK_STATE_READY | 125000000 | | |
| | 115 | 5 | DEV_GPMC0_VBUSP_CLK | CLK_STATE_READY | 250000000 | | |
| | 115 | 6 | DEV_GPMC0_PO_GPMC_DEV_CLK | CLK_STATE_READY | 0 | | |
| | 115 | 7 | DEV_GPMC0_PI_GPMC_RET_CLK | CLK_STATE_READY | 0 | | |
| | 61 | 0 | DEV_GTC0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 61 | 1 | DEV_GTC0_GTC_CLK | CLK_STATE_READY | 200000000 | | |
| | 61 | 2 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 61 | 3 | DEV_GTC0_GTC_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 61 | 4 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 61 | 5 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 61 | 6 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 61 | 7 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 61 | 8 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 61 | 9 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 61 | 10 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 61 | 11 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 61 | 16 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 61 | 17 | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 187 | 0 | DEV_I2C0_PISCL | CLK_STATE_READY | 0 | | |
| | 187 | 1 | DEV_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 187 | 2 | DEV_I2C0_CLK | CLK_STATE_READY | 125000000 | | |
| | 187 | 3 | DEV_I2C0_PORSCL | CLK_STATE_READY | 0 | | |
| | 188 | 0 | DEV_I2C1_PISCL | CLK_STATE_READY | 0 | | |
| | 188 | 1 | DEV_I2C1_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 188 | 2 | DEV_I2C1_CLK | CLK_STATE_READY | 125000000 | | |
| | 188 | 3 | DEV_I2C1_PORSCL | CLK_STATE_READY | 0 | | |
| | 189 | 0 | DEV_I2C2_PISCL | CLK_STATE_READY | 0 | | |
| | 189 | 1 | DEV_I2C2_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 189 | 2 | DEV_I2C2_CLK | CLK_STATE_READY | 125000000 | | |
| | 189 | 3 | DEV_I2C2_PORSCL | CLK_STATE_READY | 0 | | |
| | 190 | 0 | DEV_I2C3_PISCL | CLK_STATE_READY | 0 | | |
| | 190 | 1 | DEV_I2C3_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 190 | 2 | DEV_I2C3_CLK | CLK_STATE_READY | 125000000 | | |
| | 190 | 3 | DEV_I2C3_PORSCL | CLK_STATE_READY | 0 | | |
| | 191 | 0 | DEV_I2C4_PISCL | CLK_STATE_READY | 0 | | |
| | 191 | 1 | DEV_I2C4_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 191 | 2 | DEV_I2C4_CLK | CLK_STATE_READY | 125000000 | | |
| | 191 | 3 | DEV_I2C4_PORSCL | CLK_STATE_READY | 0 | | |
| | 192 | 0 | DEV_I2C5_PISCL | CLK_STATE_READY | 0 | | |
| | 192 | 1 | DEV_I2C5_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 192 | 2 | DEV_I2C5_CLK | CLK_STATE_READY | 125000000 | | |
| | 192 | 3 | DEV_I2C5_PORSCL | CLK_STATE_READY | 0 | | |
| | 193 | 0 | DEV_I2C6_PISCL | CLK_STATE_READY | 0 | | |
| | 193 | 1 | DEV_I2C6_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 193 | 2 | DEV_I2C6_CLK | CLK_STATE_READY | 125000000 | | |
| | 193 | 3 | DEV_I2C6_PORSCL | CLK_STATE_READY | 0 | | |
| | 116 | 0 | DEV_I3C0_I3C_SCL_DI | CLK_STATE_READY | 0 | | |
| | 116 | 1 | DEV_I3C0_I3C_SCL_DO | CLK_STATE_READY | 0 | | |
| | 116 | 2 | DEV_I3C0_I3C_PCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 116 | 4 | DEV_I3C0_I3C_SCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 127 | 0 | DEV_LED0_LED_CLK | CLK_STATE_READY | 0 | | |
| | 127 | 1 | DEV_LED0_VBUS_CLK | CLK_STATE_READY | 250000000 | | |
| | 156 | 0 | DEV_MCAN0_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 156 | 2 | DEV_MCAN0_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 156 | 3 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 156 | 4 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 156 | 5 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 156 | 6 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 158 | 0 | DEV_MCAN1_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 158 | 2 | DEV_MCAN1_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 158 | 3 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 158 | 4 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 158 | 5 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 158 | 6 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 168 | 0 | DEV_MCAN10_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 168 | 2 | DEV_MCAN10_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 168 | 3 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 168 | 4 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 168 | 5 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 168 | 6 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 169 | 0 | DEV_MCAN11_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 169 | 2 | DEV_MCAN11_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 169 | 3 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 169 | 4 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 169 | 5 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 169 | 6 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 170 | 0 | DEV_MCAN12_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 170 | 2 | DEV_MCAN12_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 170 | 3 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 170 | 4 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 170 | 5 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 170 | 6 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 171 | 0 | DEV_MCAN13_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 171 | 2 | DEV_MCAN13_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 171 | 3 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 171 | 4 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 171 | 5 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 171 | 6 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 150 | 0 | DEV_MCAN14_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 150 | 2 | DEV_MCAN14_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 150 | 3 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 150 | 4 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 150 | 5 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 150 | 6 | DEV_MCAN14_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 151 | 0 | DEV_MCAN15_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 151 | 2 | DEV_MCAN15_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 151 | 3 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 151 | 4 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 151 | 5 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 151 | 6 | DEV_MCAN15_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 152 | 0 | DEV_MCAN16_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 152 | 2 | DEV_MCAN16_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 152 | 3 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 152 | 4 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 152 | 5 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 152 | 6 | DEV_MCAN16_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 153 | 0 | DEV_MCAN17_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 153 | 2 | DEV_MCAN17_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 153 | 3 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 153 | 4 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 153 | 5 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 153 | 6 | DEV_MCAN17_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 160 | 0 | DEV_MCAN2_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 160 | 2 | DEV_MCAN2_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 160 | 3 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 160 | 4 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 160 | 5 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 160 | 6 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 161 | 0 | DEV_MCAN3_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 161 | 2 | DEV_MCAN3_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 161 | 3 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 161 | 4 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 161 | 5 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 161 | 6 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 162 | 0 | DEV_MCAN4_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 162 | 2 | DEV_MCAN4_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 162 | 3 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 162 | 4 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 162 | 5 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 162 | 6 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 163 | 0 | DEV_MCAN5_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 163 | 2 | DEV_MCAN5_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 163 | 3 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 163 | 4 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 163 | 5 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 163 | 6 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 164 | 0 | DEV_MCAN6_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 164 | 2 | DEV_MCAN6_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 164 | 3 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 164 | 4 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 164 | 5 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 164 | 6 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 165 | 0 | DEV_MCAN7_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 165 | 2 | DEV_MCAN7_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 165 | 3 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 165 | 4 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 165 | 5 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 165 | 6 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 166 | 0 | DEV_MCAN8_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 166 | 2 | DEV_MCAN8_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 166 | 3 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 166 | 4 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 166 | 5 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 166 | 6 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 167 | 0 | DEV_MCAN9_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 167 | 2 | DEV_MCAN9_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 167 | 3 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | |
| | 167 | 4 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 167 | 5 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 167 | 6 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 174 | 0 | DEV_MCASP0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 174 | 2 | DEV_MCASP0_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | |
| | 174 | 3 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 4 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 174 | 5 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 6 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 11 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 12 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 13 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 14 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 19 | DEV_MCASP0_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | |
| | 174 | 21 | DEV_MCASP0_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | |
| | 174 | 22 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 23 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 174 | 24 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 25 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 174 | 30 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 31 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 32 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 33 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 38 | DEV_MCASP0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 174 | 39 | DEV_MCASP0_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | |
| | 174 | 40 | DEV_MCASP0_AUX_CLK | CLK_STATE_READY | 196608000 | | |
| | 174 | 41 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | |
| | 174 | 42 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 174 | 45 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 46 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 47 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 48 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 174 | 49 | DEV_MCASP0_VBUSP_CLK | CLK_STATE_READY | 250000000 | | |
| | 174 | 50 | DEV_MCASP0_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | |
| | 174 | 51 | DEV_MCASP0_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | |
| | 175 | 0 | DEV_MCASP1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 175 | 2 | DEV_MCASP1_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | |
| | 175 | 3 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 4 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 175 | 5 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 6 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 11 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 12 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 13 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 14 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 19 | DEV_MCASP1_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | |
| | 175 | 21 | DEV_MCASP1_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | |
| | 175 | 22 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 23 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 175 | 24 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 25 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 175 | 30 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 31 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 32 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 33 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 38 | DEV_MCASP1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 175 | 39 | DEV_MCASP1_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | |
| | 175 | 40 | DEV_MCASP1_AUX_CLK | CLK_STATE_READY | 196608000 | | |
| | 175 | 41 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | |
| | 175 | 42 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 175 | 45 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 46 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 47 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 48 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 175 | 49 | DEV_MCASP1_VBUSP_CLK | CLK_STATE_READY | 250000000 | | |
| | 175 | 50 | DEV_MCASP1_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | |
| | 175 | 51 | DEV_MCASP1_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | |
| | 176 | 0 | DEV_MCASP2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | |
| | 176 | 2 | DEV_MCASP2_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | |
| | 176 | 3 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 4 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 176 | 5 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 6 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 11 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 12 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 13 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 14 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 19 | DEV_MCASP2_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | |
| | 176 | 21 | DEV_MCASP2_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | |
| | 176 | 22 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 23 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 176 | 24 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 25 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 176 | 30 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 31 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 32 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 33 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 38 | DEV_MCASP2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | |
| | 176 | 39 | DEV_MCASP2_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | |
| | 176 | 40 | DEV_MCASP2_AUX_CLK | CLK_STATE_READY | 196608000 | | |
| | 176 | 41 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | |
| | 176 | 42 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 176 | 45 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 46 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 47 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 48 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | |
| | 176 | 49 | DEV_MCASP2_VBUSP_CLK | CLK_STATE_READY | 250000000 | | |
| | 176 | 50 | DEV_MCASP2_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | |
| | 176 | 51 | DEV_MCASP2_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | |
| | 266 | 3 | DEV_MCSPI0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 266 | 4 | DEV_MCSPI0_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 266 | 5 | DEV_MCSPI0_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 267 | 3 | DEV_MCSPI1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 267 | 4 | DEV_MCSPI1_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 267 | 5 | DEV_MCSPI1_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 268 | 3 | DEV_MCSPI2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 268 | 4 | DEV_MCSPI2_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 268 | 5 | DEV_MCSPI2_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 269 | 0 | DEV_MCSPI3_IO_CLKSPII_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 269 | 1 | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 269 | 3 | DEV_MCSPI3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 269 | 4 | DEV_MCSPI3_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 269 | 5 | DEV_MCSPI3_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 270 | 0 | DEV_MCSPI4_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | |
| | 270 | 1 | DEV_MCSPI4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 270 | 2 | DEV_MCSPI4_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 270 | 3 | DEV_MCSPI4_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 271 | 3 | DEV_MCSPI5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 271 | 4 | DEV_MCSPI5_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 271 | 5 | DEV_MCSPI5_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 272 | 3 | DEV_MCSPI6_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 272 | 4 | DEV_MCSPI6_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 272 | 5 | DEV_MCSPI6_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 273 | 3 | DEV_MCSPI7_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 273 | 4 | DEV_MCSPI7_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 273 | 5 | DEV_MCSPI7_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 0 | 0 | DEV_MCU_ADC0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 0 | 1 | DEV_MCU_ADC0_ADC_CLK | CLK_STATE_READY | 19200000 | | |
| | 0 | 2 | DEV_MCU_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 0 | 3 | DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | CLK_STATE_READY | 60000000 | | |
| | 0 | 4 | DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | CLK_STATE_READY | 58823529 | | |
| | 0 | 5 | DEV_MCU_ADC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 0 | 6 | DEV_MCU_ADC0_VBUS_CLK | CLK_STATE_READY | 333333333 | | |
| | 1 | 0 | DEV_MCU_ADC1_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 1 | 1 | DEV_MCU_ADC1_ADC_CLK | CLK_STATE_READY | 19200000 | | |
| | 1 | 2 | DEV_MCU_ADC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 1 | 3 | DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | CLK_STATE_READY | 60000000 | | |
| | 1 | 4 | DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | CLK_STATE_READY | 58823529 | | |
| | 1 | 5 | DEV_MCU_ADC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 1 | 6 | DEV_MCU_ADC1_VBUS_CLK | CLK_STATE_READY | 333333333 | | |
| | 18 | 0 | DEV_MCU_CPSW0_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | |
| | 18 | 2 | DEV_MCU_CPSW0_CPTS_RFT_CLK | CLK_STATE_READY | 500000000 | | |
| | 18 | 3 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 18 | 4 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 18 | 5 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 18 | 6 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 18 | 7 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 18 | 8 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 18 | 9 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 18 | 10 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 18 | 11 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 18 | 12 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 18 | 17 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 18 | 18 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2 | CLK_STATE_READY | 500000000 | | |
| | 18 | 20 | DEV_MCU_CPSW0_GMII1_MR_CLK | CLK_STATE_READY | 25000000 | | |
| | 18 | 21 | DEV_MCU_CPSW0_CPPI_CLK_CLK | CLK_STATE_READY | 333333333 | | |
| | 18 | 22 | DEV_MCU_CPSW0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 18 | 24 | DEV_MCU_CPSW0_GMII_RFT_CLK | CLK_STATE_READY | 125000000 | | |
| | 18 | 27 | DEV_MCU_CPSW0_GMII1_MT_CLK | CLK_STATE_READY | 25000000 | | |
| | 18 | 28 | DEV_MCU_CPSW0_RGMII1_TXC_O | CLK_STATE_READY | 0 | | |
| | 18 | 29 | DEV_MCU_CPSW0_RMII_MHZ_50_CLK | CLK_STATE_READY | 0 | | |
| | 18 | 30 | DEV_MCU_CPSW0_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | |
| | 18 | 31 | DEV_MCU_CPSW0_RGMII1_RXC_I | CLK_STATE_READY | 0 | | |
| | 18 | 32 | DEV_MCU_CPSW0_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | |
| | 18 | 33 | DEV_MCU_CPSW0_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | |
| | 24 | 0 | DEV_MCU_CPT2_AGGR0_VCLK_CLK | CLK_STATE_READY | 333333333 | | |
| | 44 | 0 | DEV_MCU_DCC0_DCC_INPUT10_CLK | CLK_STATE_READY | 333333333 | | |
| | 44 | 1 | DEV_MCU_DCC0_DCC_INPUT01_CLK | CLK_STATE_READY | 83 | | |
| | 44 | 2 | DEV_MCU_DCC0_DCC_CLKSRC2_CLK | CLK_STATE_READY | 80000000 | | |
| | 44 | 3 | DEV_MCU_DCC0_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | |
| | 44 | 4 | DEV_MCU_DCC0_DCC_CLKSRC0_CLK | CLK_STATE_READY | 200000000 | | |
| | 44 | 5 | DEV_MCU_DCC0_VBUS_CLK | CLK_STATE_READY | 166666666 | | |
| | 44 | 6 | DEV_MCU_DCC0_DCC_CLKSRC4_CLK | CLK_STATE_READY | 133333333 | | |
| | 44 | 7 | DEV_MCU_DCC0_DCC_CLKSRC1_CLK | CLK_STATE_READY | 60000000 | | |
| | 44 | 8 | DEV_MCU_DCC0_DCC_CLKSRC3_CLK | CLK_STATE_READY | 96000000 | | |
| | 44 | 9 | DEV_MCU_DCC0_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 44 | 10 | DEV_MCU_DCC0_DCC_CLKSRC5_CLK | CLK_STATE_READY | 83 | | |
| | 44 | 11 | DEV_MCU_DCC0_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | |
| | 44 | 12 | DEV_MCU_DCC0_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 45 | 0 | DEV_MCU_DCC1_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | |
| | 45 | 1 | DEV_MCU_DCC1_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 45 | 2 | DEV_MCU_DCC1_DCC_CLKSRC2_CLK | CLK_STATE_READY | 80000000 | | |
| | 45 | 3 | DEV_MCU_DCC1_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | |
| | 45 | 4 | DEV_MCU_DCC1_DCC_CLKSRC0_CLK | CLK_STATE_READY | 250000000 | | |
| | 45 | 5 | DEV_MCU_DCC1_VBUS_CLK | CLK_STATE_READY | 166666666 | | |
| | 45 | 6 | DEV_MCU_DCC1_DCC_CLKSRC4_CLK | CLK_STATE_READY | 250000000 | | |
| | 45 | 7 | DEV_MCU_DCC1_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | |
| | 45 | 8 | DEV_MCU_DCC1_DCC_CLKSRC3_CLK | CLK_STATE_READY | 166666666 | | |
| | 45 | 9 | DEV_MCU_DCC1_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 45 | 10 | DEV_MCU_DCC1_DCC_CLKSRC5_CLK | CLK_STATE_READY | 58823529 | | |
| | 45 | 11 | DEV_MCU_DCC1_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | |
| | 45 | 12 | DEV_MCU_DCC1_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 46 | 0 | DEV_MCU_DCC2_DCC_INPUT10_CLK | CLK_STATE_READY | 333333333 | | |
| | 46 | 1 | DEV_MCU_DCC2_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | |
| | 46 | 3 | DEV_MCU_DCC2_DCC_CLKSRC7_CLK | CLK_STATE_READY | 19200000 | | |
| | 46 | 4 | DEV_MCU_DCC2_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | |
| | 46 | 5 | DEV_MCU_DCC2_VBUS_CLK | CLK_STATE_READY | 166666666 | | |
| | 46 | 7 | DEV_MCU_DCC2_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | |
| | 46 | 8 | DEV_MCU_DCC2_DCC_CLKSRC3_CLK | CLK_STATE_READY | 192000000 | | |
| | 46 | 9 | DEV_MCU_DCC2_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | |
| | 46 | 11 | DEV_MCU_DCC2_DCC_CLKSRC6_CLK | CLK_STATE_READY | 12500000 | | |
| | 46 | 12 | DEV_MCU_DCC2_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | |
| | 98 | 0 | DEV_MCU_ESM0_CLK | CLK_STATE_READY | 166666666 | | |
| | 101 | 0 | DEV_MCU_FSS0_FSAS_0_GCLK | CLK_STATE_READY | 1000000000 | | |
| | 102 | 0 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N | CLK_STATE_READY | 0 | | |
| | 102 | 1 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK | CLK_STATE_READY | 166666666 | | |
| | 102 | 2 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK | CLK_STATE_READY | 83333333 | | |
| | 102 | 4 | DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK | CLK_STATE_READY | 1000000000 | | |
| | 102 | 5 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK | CLK_STATE_READY | 166666666 | | |
| | 102 | 7 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK | CLK_STATE_READY | 83333333 | | |
| | 102 | 10 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P | CLK_STATE_READY | 0 | | |
| | 103 | 0 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 103 | 1 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK | CLK_STATE_READY | 133333333 | | |
| | 103 | 2 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK | CLK_STATE_READY | 166666666 | | |
| | 103 | 3 | DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 103 | 4 | DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK | CLK_STATE_READY | 0 | | |
| | 103 | 5 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK | CLK_STATE_READY | 0 | | |
| | 103 | 6 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT | CLK_STATE_READY | 0 | | |
| | 103 | 7 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 103 | 8 | DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 103 | 9 | DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK | CLK_STATE_READY | 0 | | |
| | 104 | 0 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK | CLK_STATE_READY | 133333333 | | |
| | 104 | 1 | DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 104 | 7 | DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 194 | 0 | DEV_MCU_I2C0_PISCL | CLK_STATE_READY | 0 | | |
| | 194 | 1 | DEV_MCU_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 194 | 2 | DEV_MCU_I2C0_CLK | CLK_STATE_READY | 166666666 | | |
| | 195 | 0 | DEV_MCU_I2C1_PISCL | CLK_STATE_READY | 0 | | |
| | 195 | 1 | DEV_MCU_I2C1_PISYS_CLK | CLK_STATE_READY | 96000000 | | |
| | 195 | 2 | DEV_MCU_I2C1_CLK | CLK_STATE_READY | 166666666 | | |
| | 195 | 3 | DEV_MCU_I2C1_PORSCL | CLK_STATE_READY | 0 | | |
| | 117 | 0 | DEV_MCU_I3C0_I3C_SCL_DI | CLK_STATE_READY | 0 | | |
| | 117 | 1 | DEV_MCU_I3C0_I3C_SCL_DO | CLK_STATE_READY | 0 | | |
| | 117 | 2 | DEV_MCU_I3C0_I3C_PCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 117 | 4 | DEV_MCU_I3C0_I3C_SCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 118 | 2 | DEV_MCU_I3C1_I3C_PCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 118 | 4 | DEV_MCU_I3C1_I3C_SCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 172 | 0 | DEV_MCU_MCAN0_MCANSS_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 172 | 2 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 172 | 3 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | CLK_STATE_READY | 80000000 | | |
| | 172 | 4 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 172 | 5 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | CLK_STATE_READY | 80000000 | | |
| | 172 | 6 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 173 | 0 | DEV_MCU_MCAN1_MCANSS_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 173 | 2 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | |
| | 173 | 3 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | CLK_STATE_READY | 80000000 | | |
| | 173 | 4 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 173 | 5 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | CLK_STATE_READY | 80000000 | | |
| | 173 | 6 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 274 | 3 | DEV_MCU_MCSPI0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 274 | 4 | DEV_MCU_MCSPI0_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 274 | 5 | DEV_MCU_MCSPI0_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 275 | 0 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 275 | 1 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | CLK_STATE_NOT_READY | 0 | | |
| | 275 | 3 | DEV_MCU_MCSPI1_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 275 | 4 | DEV_MCU_MCSPI1_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 275 | 5 | DEV_MCU_MCSPI1_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 276 | 0 | DEV_MCU_MCSPI2_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | |
| | 276 | 1 | DEV_MCU_MCSPI2_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 276 | 2 | DEV_MCU_MCSPI2_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | |
| | 276 | 3 | DEV_MCU_MCSPI2_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | |
| | 237 | 0 | DEV_MCU_NAVSS0_INTR_0_INTR_CLK | CLK_STATE_READY | 1000000000 | | |
| | 238 | 0 | DEV_MCU_NAVSS0_MCRC_0_CLK | CLK_STATE_READY | 1000000000 | | |
| | 302 | 0 | DEV_MCU_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 1000000000 | | |
| | 234 | 0 | DEV_MCU_NAVSS0_PROXY0_CLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 235 | 0 | DEV_MCU_NAVSS0_RINGACC0_SYS_CLK | CLK_STATE_READY | 1000000000 | | |
| | 236 | 0 | DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK | CLK_STATE_READY | 1000000000 | | |
| | 303 | 0 | DEV_MCU_NAVSS0_UDMASS_VD2CLK | CLK_STATE_READY | 1000000000 | | |
| | 233 | 0 | DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK | CLK_STATE_READY | 1000000000 | | |
| | 142 | 1 | DEV_MCU_PBIST0_CLK7_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 2 | DEV_MCU_PBIST0_CLK3_CLK | CLK_STATE_READY | 166666666 | | |
| | 142 | 3 | DEV_MCU_PBIST0_CLK5_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 4 | DEV_MCU_PBIST0_CLK1_CLK | CLK_STATE_READY | 500000000 | | |
| | 142 | 5 | DEV_MCU_PBIST0_CLK8_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 6 | DEV_MCU_PBIST0_CLK6_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 8 | DEV_MCU_PBIST0_CLK4_CLK | CLK_STATE_READY | 83333333 | | |
| | 142 | 9 | DEV_MCU_PBIST0_CLK2_CLK | CLK_STATE_READY | 333333333 | | |
| | 143 | 1 | DEV_MCU_PBIST1_CLK7_CLK | CLK_STATE_READY | 83333333 | | |
| | 143 | 2 | DEV_MCU_PBIST1_CLK3_CLK | CLK_STATE_READY | 83333333 | | |
| | 143 | 3 | DEV_MCU_PBIST1_CLK5_CLK | CLK_STATE_READY | 166666666 | | |
| | 143 | 4 | DEV_MCU_PBIST1_CLK1_CLK | CLK_STATE_READY | 500000000 | | |
| | 143 | 5 | DEV_MCU_PBIST1_CLK8_CLK | CLK_STATE_READY | 83333333 | | |
| | 143 | 6 | DEV_MCU_PBIST1_CLK6_CLK | CLK_STATE_READY | 83333333 | | |
| | 143 | 8 | DEV_MCU_PBIST1_CLK4_CLK | CLK_STATE_READY | 333333333 | | |
| | 143 | 9 | DEV_MCU_PBIST1_CLK2_CLK | CLK_STATE_READY | 400000000 | | |
| | 144 | 1 | DEV_MCU_PBIST2_CLK7_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 2 | DEV_MCU_PBIST2_CLK3_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 3 | DEV_MCU_PBIST2_CLK5_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 4 | DEV_MCU_PBIST2_CLK1_CLK | CLK_STATE_READY | 1000000000 | | |
| | 144 | 5 | DEV_MCU_PBIST2_CLK8_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 6 | DEV_MCU_PBIST2_CLK6_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 8 | DEV_MCU_PBIST2_CLK4_CLK | CLK_STATE_READY | 83333333 | | |
| | 144 | 9 | DEV_MCU_PBIST2_CLK2_CLK | CLK_STATE_READY | 83333333 | | |
| | 250 | 0 | DEV_MCU_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | |
| | 250 | 1 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 250 | 2 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | CLK_STATE_READY | 333333333 | | |
| | 250 | 3 | DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | |
| | 250 | 4 | DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 333333333 | | |
| | 251 | 0 | DEV_MCU_R5FSS0_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | |
| | 251 | 1 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 1000000000 | | |
| | 251 | 2 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | CLK_STATE_READY | 333333333 | | |
| | 251 | 3 | DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | |
| | 251 | 4 | DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE | CLK_STATE_READY | 333333333 | | |
| | 262 | 0 | DEV_MCU_RTI0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 262 | 1 | DEV_MCU_RTI0_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 262 | 2 | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 262 | 3 | DEV_MCU_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 262 | 4 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 262 | 5 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 263 | 0 | DEV_MCU_RTI1_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 263 | 1 | DEV_MCU_RTI1_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 263 | 2 | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 263 | 3 | DEV_MCU_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 263 | 4 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 263 | 5 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 265 | 0 | DEV_MCU_SA2_UL0_X2_CLK | CLK_STATE_READY | 333333333 | | |
| | 265 | 1 | DEV_MCU_SA2_UL0_PKA_IN_CLK | CLK_STATE_READY | 400000000 | | |
| | 265 | 2 | DEV_MCU_SA2_UL0_X1_CLK | CLK_STATE_READY | 166666666 | | |
| | 35 | 0 | DEV_MCU_TIMER0_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 35 | 1 | DEV_MCU_TIMER0_TIMER_TCLK_CLK | CLK_STATE_READY | 62500000 | | |
| | 35 | 2 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 35 | 3 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 35 | 4 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 35 | 5 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 35 | 6 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 35 | 7 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 35 | 8 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 35 | 9 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 35 | 11 | DEV_MCU_TIMER0_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 71 | 0 | DEV_MCU_TIMER1_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 71 | 1 | DEV_MCU_TIMER1_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 71 | 2 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1 | CLK_STATE_READY | 19200000 | | |
| | 71 | 3 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 308 | 0 | DEV_MCU_TIMER1_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 308 | 1 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 308 | 2 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 308 | 3 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 308 | 4 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 308 | 5 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 308 | 6 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 308 | 7 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 308 | 8 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 72 | 0 | DEV_MCU_TIMER2_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 72 | 1 | DEV_MCU_TIMER2_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 72 | 2 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 72 | 3 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 72 | 4 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 72 | 5 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 72 | 6 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 72 | 7 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 72 | 8 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 72 | 9 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 72 | 11 | DEV_MCU_TIMER2_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 73 | 0 | DEV_MCU_TIMER3_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 73 | 1 | DEV_MCU_TIMER3_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 73 | 2 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3 | CLK_STATE_READY | 19200000 | | |
| | 73 | 3 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 309 | 0 | DEV_MCU_TIMER3_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 309 | 1 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 309 | 2 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 309 | 3 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 309 | 4 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 309 | 5 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 309 | 6 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 309 | 7 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 309 | 8 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 74 | 0 | DEV_MCU_TIMER4_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 74 | 1 | DEV_MCU_TIMER4_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 74 | 2 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 74 | 3 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 74 | 4 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 74 | 5 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 74 | 6 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 74 | 7 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 74 | 8 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 74 | 9 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 74 | 11 | DEV_MCU_TIMER4_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 75 | 0 | DEV_MCU_TIMER5_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 75 | 1 | DEV_MCU_TIMER5_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 75 | 2 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5 | CLK_STATE_READY | 19200000 | | |
| | 75 | 3 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 310 | 0 | DEV_MCU_TIMER5_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 310 | 1 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 310 | 2 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 310 | 3 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 310 | 4 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 310 | 5 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 310 | 6 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 310 | 7 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 310 | 8 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 76 | 0 | DEV_MCU_TIMER6_TIMER_HCLK_CLK | CLK_STATE_READY | 333333333 | | |
| | 76 | 1 | DEV_MCU_TIMER6_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 76 | 2 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 76 | 3 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 76 | 4 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 76 | 5 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 76 | 6 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 76 | 7 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 76 | 8 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 76 | 9 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 76 | 11 | DEV_MCU_TIMER6_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 77 | 0 | DEV_MCU_TIMER7_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 77 | 1 | DEV_MCU_TIMER7_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 77 | 2 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7 | CLK_STATE_READY | 19200000 | | |
| | 77 | 3 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 311 | 0 | DEV_MCU_TIMER7_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 311 | 1 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 311 | 2 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 311 | 3 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 311 | 4 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 311 | 5 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 311 | 6 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 311 | 7 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 311 | 8 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 78 | 0 | DEV_MCU_TIMER8_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 78 | 1 | DEV_MCU_TIMER8_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 78 | 2 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 78 | 3 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 78 | 4 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 78 | 5 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 78 | 6 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 78 | 7 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 78 | 8 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 78 | 9 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 78 | 11 | DEV_MCU_TIMER8_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 79 | 0 | DEV_MCU_TIMER9_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | |
| | 79 | 1 | DEV_MCU_TIMER9_TIMER_TCLK_CLK | CLK_STATE_READY | 62500000 | | |
| | 79 | 2 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9 | CLK_STATE_READY | 62500000 | | |
| | 79 | 3 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 312 | 0 | DEV_MCU_TIMER9_CLKSEL_VD_CLK | CLK_STATE_READY | 62500000 | | |
| | 312 | 1 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 312 | 2 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK16 | CLK_STATE_READY | 62500000 | | |
| | 312 | 3 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 312 | 4 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 312 | 5 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 312 | 6 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 312 | 7 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | |
| | 312 | 8 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 149 | 2 | DEV_MCU_UART0_FCLK_CLK | CLK_STATE_READY | 96000000 | | |
| | 149 | 3 | DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK | CLK_STATE_READY | 96000000 | | |
| | 149 | 4 | DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_1_HSDIVOUT5_CLK | CLK_STATE_READY | 192000000 | | |
| | 149 | 5 | DEV_MCU_UART0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | |
| | 91 | 0 | DEV_MMCSD0_EMMCSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | |
| | 91 | 3 | DEV_MMCSD0_EMMCSS_XIN_CLK | CLK_STATE_READY | 200000000 | | |
| | 91 | 4 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 91 | 5 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | |
| | 91 | 6 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 91 | 7 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0 | CLK_STATE_READY | 200000000 | | |
| | 92 | 0 | DEV_MMCSD1_EMMCSDSS_IO_CLK_I | CLK_STATE_READY | 0 | | |
| | 92 | 1 | DEV_MMCSD1_EMMCSDSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | |
| | 92 | 2 | DEV_MMCSD1_EMMCSDSS_XIN_CLK | CLK_STATE_READY | 200000000 | | |
| | 92 | 3 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 92 | 4 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | |
| | 92 | 5 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | |
| | 92 | 6 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK_DUP0 | CLK_STATE_READY | 200000000 | | |
| | 92 | 7 | DEV_MMCSD1_EMMCSDSS_IO_CLK_O | CLK_STATE_READY | 0 | | |
| | 199 | 0 | DEV_NAVSS0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 199 | 1 | DEV_NAVSS0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 199 | 2 | DEV_NAVSS0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 201 | 0 | DEV_NAVSS0_CPTS_0_VBUSP_GCLK | CLK_STATE_READY | 500000000 | | |
| | 201 | 1 | DEV_NAVSS0_CPTS_0_RCLK | CLK_STATE_READY | 200000000 | | |
| | 201 | 2 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 201 | 3 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 201 | 4 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 201 | 5 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 201 | 6 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 201 | 7 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 201 | 8 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 201 | 9 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 201 | 10 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 201 | 11 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 201 | 16 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 201 | 17 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 201 | 20 | DEV_NAVSS0_CPTS_0_TS_GENF0 | CLK_STATE_READY | 0 | | |
| | 201 | 21 | DEV_NAVSS0_CPTS_0_TS_GENF1 | CLK_STATE_READY | 0 | | |
| | 206 | 0 | DEV_NAVSS0_DTI_0_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 213 | 0 | DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK | CLK_STATE_READY | 500000000 | | |
| | 214 | 0 | DEV_NAVSS0_MAILBOX_0_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 215 | 0 | DEV_NAVSS0_MAILBOX_1_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 224 | 0 | DEV_NAVSS0_MAILBOX_10_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 225 | 0 | DEV_NAVSS0_MAILBOX_11_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 216 | 0 | DEV_NAVSS0_MAILBOX_2_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 217 | 0 | DEV_NAVSS0_MAILBOX_3_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 218 | 0 | DEV_NAVSS0_MAILBOX_4_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 219 | 0 | DEV_NAVSS0_MAILBOX_5_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 220 | 0 | DEV_NAVSS0_MAILBOX_6_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 221 | 0 | DEV_NAVSS0_MAILBOX_7_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 222 | 0 | DEV_NAVSS0_MAILBOX_8_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 223 | 0 | DEV_NAVSS0_MAILBOX_9_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 227 | 0 | DEV_NAVSS0_MCRC_0_CLK | CLK_STATE_READY | 500000000 | | |
| | 299 | 0 | DEV_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 500000000 | | |
| | 207 | 0 | DEV_NAVSS0_MODSS_INTA_0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 208 | 0 | DEV_NAVSS0_MODSS_INTA_1_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 210 | 0 | DEV_NAVSS0_PROXY_0_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 211 | 0 | DEV_NAVSS0_RINGACC_0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 226 | 0 | DEV_NAVSS0_SPINLOCK_0_CLK | CLK_STATE_READY | 500000000 | | |
| | 228 | 0 | DEV_NAVSS0_TBU_0_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 230 | 0 | DEV_NAVSS0_TIMERMGR_0_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 230 | 1 | DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT | CLK_STATE_READY | 0 | | |
| | 231 | 0 | DEV_NAVSS0_TIMERMGR_1_VCLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 231 | 1 | DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT | CLK_STATE_READY | 0 | | |
| | 212 | 0 | DEV_NAVSS0_UDMAP_0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 300 | 0 | DEV_NAVSS0_UDMASS_VD2CLK | CLK_STATE_READY | 500000000 | | |
| | 209 | 0 | DEV_NAVSS0_UDMASS_INTA_0_SYS_CLK | CLK_STATE_READY | 500000000 | | |
| | 301 | 0 | DEV_NAVSS0_VIRTSS_VD2CLK | CLK_STATE_READY | 500000000 | | |
| | 139 | 1 | DEV_PBIST0_CLK7_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 2 | DEV_PBIST0_CLK3_CLK | CLK_STATE_READY | 250000000 | | |
| | 139 | 3 | DEV_PBIST0_CLK5_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 4 | DEV_PBIST0_CLK1_CLK | CLK_STATE_READY | 500000000 | | |
| | 139 | 5 | DEV_PBIST0_CLK8_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 6 | DEV_PBIST0_CLK6_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 8 | DEV_PBIST0_CLK4_CLK | CLK_STATE_READY | 125000000 | | |
| | 139 | 9 | DEV_PBIST0_CLK2_CLK | CLK_STATE_READY | 250000000 | | |
| | 140 | 1 | DEV_PBIST1_CLK7_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 2 | DEV_PBIST1_CLK3_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 3 | DEV_PBIST1_CLK5_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 4 | DEV_PBIST1_CLK1_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 5 | DEV_PBIST1_CLK8_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 6 | DEV_PBIST1_CLK6_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 8 | DEV_PBIST1_CLK4_CLK | CLK_STATE_READY | 125000000 | | |
| | 140 | 9 | DEV_PBIST1_CLK2_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 1 | DEV_PBIST2_CLK7_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 2 | DEV_PBIST2_CLK3_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 3 | DEV_PBIST2_CLK5_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 4 | DEV_PBIST2_CLK1_CLK | CLK_STATE_READY | 1000000000 | | |
| | 141 | 5 | DEV_PBIST2_CLK8_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 6 | DEV_PBIST2_CLK6_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 8 | DEV_PBIST2_CLK4_CLK | CLK_STATE_READY | 125000000 | | |
| | 141 | 9 | DEV_PBIST2_CLK2_CLK | CLK_STATE_READY | 125000000 | | |
| | 240 | 0 | DEV_PCIE1_PCIE_LANE0_TXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 1 | DEV_PCIE1_PCIE_LANE1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 2 | DEV_PCIE1_PCIE_LANE0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 3 | DEV_PCIE1_PCIE_LANE0_TXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 4 | DEV_PCIE1_PCIE_PM_CLK | CLK_STATE_READY | 12500000 | | |
| | 240 | 5 | DEV_PCIE1_PCIE_LANE3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 6 | DEV_PCIE1_PCIE_CBA_CLK | CLK_STATE_READY | 250000000 | | |
| | 240 | 7 | DEV_PCIE1_PCIE_LANE1_REFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 8 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK | CLK_STATE_READY | 200000000 | | |
| | 240 | 9 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 240 | 10 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 | | |
| | 240 | 11 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 240 | 12 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 240 | 13 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 240 | 14 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 240 | 15 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 16 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 17 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 18 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 23 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | |
| | 240 | 24 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | |
| | 240 | 25 | DEV_PCIE1_PCIE_LANE1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 27 | DEV_PCIE1_PCIE_LANE2_RXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 28 | DEV_PCIE1_PCIE_LANE2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 240 | 29 | DEV_PCIE1_PCIE_LANE1_TXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 30 | DEV_PCIE1_PCIE_LANE3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 31 | DEV_PCIE1_PCIE_LANE2_TXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 32 | DEV_PCIE1_PCIE_LANE1_RXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 33 | DEV_PCIE1_PCIE_LANE2_TXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 34 | DEV_PCIE1_PCIE_LANE1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 35 | DEV_PCIE1_PCIE_LANE0_REFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 36 | DEV_PCIE1_PCIE_LANE3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 37 | DEV_PCIE1_PCIE_LANE2_RXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 38 | DEV_PCIE1_PCIE_LANE3_RXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 39 | DEV_PCIE1_PCIE_LANE3_REFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 40 | DEV_PCIE1_PCIE_LANE2_REFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 41 | DEV_PCIE1_PCIE_LANE0_RXFCLK | CLK_STATE_READY | 0 | | |
| | 240 | 42 | DEV_PCIE1_PCIE_LANE3_TXCLK | CLK_STATE_READY | 0 | | |
| | 240 | 43 | DEV_PCIE1_PCIE_LANE0_RXCLK | CLK_STATE_READY | 0 | | |
| | 133 | 0 | DEV_PSC0_SLOW_CLK | CLK_STATE_READY | 20833333 | | |
| | 133 | 1 | DEV_PSC0_CLK | CLK_STATE_READY | 125000000 | | |
| | 245 | 0 | DEV_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | |
| | 245 | 1 | DEV_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | |
| | 245 | 2 | DEV_R5FSS0_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 1000000000 | | |
| | 246 | 0 | DEV_R5FSS0_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | |
| | 246 | 1 | DEV_R5FSS0_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | |
| | 246 | 2 | DEV_R5FSS0_CORE1_INTERFACE_PHASE | CLK_STATE_READY | 1000000000 | | |
| | 252 | 0 | DEV_RTI0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 252 | 1 | DEV_RTI0_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 252 | 2 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 252 | 3 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 252 | 4 | DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 252 | 5 | DEV_RTI0_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 252 | 6 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 252 | 7 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | |
| | 252 | 8 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | |
| | 252 | 9 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | |
| | 253 | 0 | DEV_RTI1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 253 | 1 | DEV_RTI1_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 253 | 2 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 253 | 3 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 253 | 4 | DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 253 | 5 | DEV_RTI1_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 253 | 6 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 253 | 7 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | |
| | 253 | 8 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | |
| | 253 | 9 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | |
| | 258 | 0 | DEV_RTI28_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 258 | 1 | DEV_RTI28_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 258 | 2 | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 258 | 3 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 258 | 4 | DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 258 | 5 | DEV_RTI28_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 258 | 6 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 258 | 7 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | |
| | 258 | 8 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | |
| | 258 | 9 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | |
| | 259 | 0 | DEV_RTI29_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 259 | 1 | DEV_RTI29_RTI_CLK | CLK_STATE_READY | 19200000 | | |
| | 259 | 2 | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 259 | 3 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 259 | 4 | DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 259 | 5 | DEV_RTI29_RTI_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32550 | | |
| | 259 | 6 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 259 | 7 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | |
| | 259 | 8 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | |
| | 259 | 9 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | |
| | 292 | 1 | DEV_SERDES_10G1_IP3_LN1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 3 | DEV_SERDES_10G1_IP2_LN2_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 4 | DEV_SERDES_10G1_IP1_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 6 | DEV_SERDES_10G1_IP3_LN3_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 9 | DEV_SERDES_10G1_IP2_LN2_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 10 | DEV_SERDES_10G1_IP1_LN0_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 11 | DEV_SERDES_10G1_CLK | CLK_STATE_READY | 125000000 | | |
| | 292 | 13 | DEV_SERDES_10G1_IP1_LN3_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 14 | DEV_SERDES_10G1_IP1_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 15 | DEV_SERDES_10G1_IP2_LN0_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 16 | DEV_SERDES_10G1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 19 | DEV_SERDES_10G1_IP3_LN1_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 21 | DEV_SERDES_10G1_IP2_LN3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 22 | DEV_SERDES_10G1_IP1_LN2_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 24 | DEV_SERDES_10G1_IP2_LN1_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 25 | DEV_SERDES_10G1_IP2_LN1_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 29 | DEV_SERDES_10G1_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 32 | DEV_SERDES_10G1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 33 | DEV_SERDES_10G1_IP2_LN1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 34 | DEV_SERDES_10G1_IP1_LN1_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 38 | DEV_SERDES_10G1_IP1_LN2_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 40 | DEV_SERDES_10G1_IP2_LN1_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 41 | DEV_SERDES_10G1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 42 | DEV_SERDES_10G1_IP2_LN3_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 43 | DEV_SERDES_10G1_IP2_LN2_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 44 | DEV_SERDES_10G1_IP2_LN2_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 45 | DEV_SERDES_10G1_IP1_LN1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 49 | DEV_SERDES_10G1_IP1_LN0_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 52 | DEV_SERDES_10G1_IP1_LN1_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 55 | DEV_SERDES_10G1_IP1_LN0_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 56 | DEV_SERDES_10G1_IP3_LN3_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 59 | DEV_SERDES_10G1_IP2_LN3_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 61 | DEV_SERDES_10G1_IP2_LN0_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 62 | DEV_SERDES_10G1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 63 | DEV_SERDES_10G1_IP1_LN1_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 65 | DEV_SERDES_10G1_IP1_LN3_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 66 | DEV_SERDES_10G1_IP3_LN1_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 67 | DEV_SERDES_10G1_IP2_LN2_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 73 | DEV_SERDES_10G1_IP3_LN1_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 74 | DEV_SERDES_10G1_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 75 | DEV_SERDES_10G1_IP1_LN3_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 77 | DEV_SERDES_10G1_IP1_LN0_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 80 | DEV_SERDES_10G1_IP1_LN2_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 81 | DEV_SERDES_10G1_IP2_LN0_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 82 | DEV_SERDES_10G1_IP2_LN0_RXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 85 | DEV_SERDES_10G1_CORE_REF_CLK | CLK_STATE_READY | 100000000 | | |
| | 292 | 86 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 292 | 87 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 292 | 88 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 125000000 | | |
| | 292 | 89 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | |
| | 292 | 92 | DEV_SERDES_10G1_IP1_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 292 | 95 | DEV_SERDES_10G1_IP2_LN3_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 96 | DEV_SERDES_10G1_IP3_LN3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 98 | DEV_SERDES_10G1_IP3_LN3_REFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 100 | DEV_SERDES_10G1_IP2_LN1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 102 | DEV_SERDES_10G1_IP3_LN1_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 104 | DEV_SERDES_10G1_IP1_LN1_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 107 | DEV_SERDES_10G1_IP3_LN3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 108 | DEV_SERDES_10G1_IP1_LN3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 109 | DEV_SERDES_10G1_IP2_LN3_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 111 | DEV_SERDES_10G1_IP1_LN0_TXCLK | CLK_STATE_READY | 0 | | |
| | 292 | 112 | DEV_SERDES_10G1_IP2_LN0_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 113 | DEV_SERDES_10G1_IP1_LN2_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 118 | DEV_SERDES_10G1_IP1_LN2_TXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 124 | DEV_SERDES_10G1_IP1_LN3_RXFCLK | CLK_STATE_READY | 0 | | |
| | 292 | 126 | DEV_SERDES_10G1_IP3_LN3_TXMCLK | CLK_STATE_READY | 0 | | |
| | 29 | 0 | DEV_STM0_CORE_CLK | CLK_STATE_READY | 250000000 | | |
| | 29 | 1 | DEV_STM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | |
| | 29 | 2 | DEV_STM0_ATB_CLK | CLK_STATE_READY | 250000000 | | |
| | 49 | 0 | DEV_TIMER0_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 49 | 1 | DEV_TIMER0_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 49 | 2 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 49 | 3 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 4 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 49 | 5 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 49 | 6 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 49 | 7 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 8 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 9 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 10 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 49 | 11 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 49 | 12 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 49 | 13 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 49 | 14 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 49 | 15 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 49 | 16 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 49 | 17 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 49 | 26 | DEV_TIMER0_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 50 | 0 | DEV_TIMER1_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 50 | 1 | DEV_TIMER1_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 50 | 2 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1 | CLK_STATE_READY | 19200000 | | |
| | 50 | 3 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 60 | 0 | DEV_TIMER10_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 60 | 1 | DEV_TIMER10_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 60 | 2 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 60 | 3 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 4 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 60 | 5 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 60 | 6 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 60 | 7 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 8 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 9 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 10 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 60 | 11 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 60 | 12 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 60 | 13 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 60 | 14 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 60 | 15 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 60 | 16 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 60 | 17 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 60 | 26 | DEV_TIMER10_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 62 | 0 | DEV_TIMER11_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 62 | 1 | DEV_TIMER11_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 62 | 2 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11 | CLK_STATE_READY | 19200000 | | |
| | 62 | 3 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 318 | 0 | DEV_TIMER11_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 318 | 1 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 318 | 2 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 3 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 318 | 4 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 318 | 5 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 318 | 6 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 7 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 8 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 9 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 318 | 10 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 318 | 11 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 318 | 12 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 318 | 13 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 318 | 14 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 318 | 15 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 318 | 16 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 63 | 0 | DEV_TIMER12_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 63 | 1 | DEV_TIMER12_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 63 | 2 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 63 | 3 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 4 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 63 | 5 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 63 | 6 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 63 | 7 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 8 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 9 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 10 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 63 | 11 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 63 | 12 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 63 | 13 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 63 | 14 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 63 | 15 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 63 | 16 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 63 | 17 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 63 | 26 | DEV_TIMER12_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 64 | 0 | DEV_TIMER13_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 64 | 1 | DEV_TIMER13_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 64 | 2 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13 | CLK_STATE_READY | 19200000 | | |
| | 64 | 3 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 319 | 0 | DEV_TIMER13_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 319 | 1 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 319 | 2 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 3 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 319 | 4 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 319 | 5 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 319 | 6 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 7 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 8 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 9 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 319 | 10 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 319 | 11 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 319 | 12 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 319 | 13 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 319 | 14 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 319 | 15 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 319 | 16 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 65 | 0 | DEV_TIMER14_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 65 | 1 | DEV_TIMER14_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 65 | 2 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 65 | 3 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 4 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 65 | 5 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 65 | 6 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 65 | 7 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 8 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 9 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 10 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 65 | 11 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 65 | 12 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 65 | 13 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 65 | 14 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 65 | 15 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 65 | 16 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 65 | 17 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 65 | 26 | DEV_TIMER14_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 66 | 0 | DEV_TIMER15_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 66 | 1 | DEV_TIMER15_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 66 | 2 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15 | CLK_STATE_READY | 19200000 | | |
| | 66 | 3 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 320 | 0 | DEV_TIMER15_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 320 | 1 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 320 | 2 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 3 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 320 | 4 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 320 | 5 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 320 | 6 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 7 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 8 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 9 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 320 | 10 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 320 | 11 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 320 | 12 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 320 | 13 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 320 | 14 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 320 | 15 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 320 | 16 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 67 | 0 | DEV_TIMER16_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 67 | 1 | DEV_TIMER16_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 67 | 2 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 67 | 3 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 4 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 67 | 5 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 67 | 6 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 67 | 7 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 8 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 9 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 10 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 67 | 11 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 67 | 12 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 67 | 13 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 67 | 14 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 67 | 15 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 67 | 16 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 67 | 17 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 67 | 26 | DEV_TIMER16_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 68 | 0 | DEV_TIMER17_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 68 | 1 | DEV_TIMER17_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 68 | 2 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17 | CLK_STATE_READY | 19200000 | | |
| | 68 | 3 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 321 | 0 | DEV_TIMER17_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 321 | 1 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 321 | 2 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 3 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 321 | 4 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 321 | 5 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 321 | 6 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 7 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 8 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 9 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 321 | 10 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 321 | 11 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 321 | 12 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 321 | 13 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 321 | 14 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 321 | 15 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 321 | 16 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 69 | 0 | DEV_TIMER18_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 69 | 1 | DEV_TIMER18_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 69 | 2 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 69 | 3 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 4 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 69 | 5 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 69 | 6 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 69 | 7 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 8 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 9 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 10 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 69 | 11 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 69 | 12 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 69 | 13 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 69 | 14 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 69 | 15 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 69 | 16 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 69 | 17 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 69 | 26 | DEV_TIMER18_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 70 | 0 | DEV_TIMER19_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 70 | 1 | DEV_TIMER19_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 70 | 2 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19 | CLK_STATE_READY | 19200000 | | |
| | 70 | 3 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | |
| | 322 | 0 | DEV_TIMER19_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 322 | 1 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 322 | 2 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 3 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 322 | 4 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 322 | 5 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 322 | 6 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 7 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 8 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 9 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 322 | 10 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 322 | 11 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 322 | 12 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 322 | 13 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 322 | 14 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 322 | 15 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 322 | 16 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 313 | 0 | DEV_TIMER1_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 313 | 1 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 313 | 2 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 3 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 313 | 4 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 313 | 5 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 313 | 6 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 7 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 8 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 9 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 313 | 10 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 313 | 11 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 313 | 12 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 313 | 13 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 313 | 14 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 313 | 15 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 313 | 16 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 51 | 0 | DEV_TIMER2_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 51 | 1 | DEV_TIMER2_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 51 | 2 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 51 | 3 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 4 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 51 | 5 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 51 | 6 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 51 | 7 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 8 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 9 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 10 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 51 | 11 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 51 | 12 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 51 | 13 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 51 | 14 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 51 | 15 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 51 | 16 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 51 | 17 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 51 | 26 | DEV_TIMER2_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 52 | 0 | DEV_TIMER3_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 52 | 1 | DEV_TIMER3_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 52 | 2 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3 | CLK_STATE_READY | 19200000 | | |
| | 52 | 3 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 314 | 0 | DEV_TIMER3_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 314 | 1 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 314 | 2 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 3 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 314 | 4 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 314 | 5 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 314 | 6 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 7 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 8 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 9 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 314 | 10 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 314 | 11 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 314 | 12 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 314 | 13 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 314 | 14 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 314 | 15 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 314 | 16 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 53 | 0 | DEV_TIMER4_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 53 | 1 | DEV_TIMER4_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 53 | 2 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 53 | 3 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 4 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 53 | 5 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 53 | 6 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 53 | 7 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 8 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 9 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 10 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 53 | 11 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 53 | 12 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 53 | 13 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 53 | 14 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 53 | 15 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 53 | 16 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 53 | 17 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 53 | 26 | DEV_TIMER4_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 54 | 0 | DEV_TIMER5_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 54 | 1 | DEV_TIMER5_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 54 | 2 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5 | CLK_STATE_READY | 19200000 | | |
| | 54 | 3 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 315 | 0 | DEV_TIMER5_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 315 | 1 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 315 | 2 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 3 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 315 | 4 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 315 | 5 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 315 | 6 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 7 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 8 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 9 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 315 | 10 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 315 | 11 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 315 | 12 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 315 | 13 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 315 | 14 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 315 | 15 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 315 | 16 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 55 | 0 | DEV_TIMER6_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 55 | 1 | DEV_TIMER6_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 55 | 2 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 55 | 3 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 4 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 55 | 5 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 55 | 6 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 55 | 7 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 8 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 9 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 10 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 55 | 11 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 55 | 12 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 55 | 13 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 55 | 14 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | |
| | 55 | 15 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | |
| | 55 | 16 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_5XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_NOT_READY | 0 | | |
| | 55 | 17 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS256VCL_MAIN_0_CPTS0_GENF4 | CLK_STATE_READY | 0 | | |
| | 55 | 26 | DEV_TIMER6_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 57 | 0 | DEV_TIMER7_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | |
| | 57 | 1 | DEV_TIMER7_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | |
| | 57 | 2 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7 | CLK_STATE_READY | 19200000 | | |
| | 57 | 3 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM | CLK_STATE_READY | 0 | | |
| | 316 | 0 | DEV_TIMER7_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | |
| | 316 | 1 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | |
| | 316 | 2 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 3 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | |
| | 316 | 4 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_J7VC_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | |
| | 316 | 5 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 200000000 | | |
| | 316 | 6 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 7 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 8 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_WKUP_LF_CLKIN_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 9 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | |
| | 316 | 10 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | |
| | 316 | 11 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 450000000 | | |
| | 316 | 12 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | |
| | 316 | 13 | DEV_TIMER7_CLKSEL |
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