chipyard_digital_top.sv

chipyard_digital_top.sv

module DigitalTop(	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063044:10
  input         clock, reset, auto_domain_resetCtrl_async_reset_sink_in_reset,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_cbus_0_clock,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_cbus_0_reset,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_mbus_0_clock,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_mbus_0_reset,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_fbus_0_clock,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_fbus_0_reset,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_pbus_0_clock,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_pbus_0_reset,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_1_clock,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_1_reset,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_0_clock,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_0_reset,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_implicit_clock_clock,
  input         auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_implicit_clock_reset,
  input         auto_subsystem_mbus_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_clock,
  input         auto_subsystem_mbus_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_reset,
  input         auto_subsystem_cbus_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock,
  input         auto_subsystem_cbus_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset,
  input         auto_subsystem_fbus_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock,
  input         auto_subsystem_fbus_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset,
  input         auto_subsystem_pbus_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock,
  input         auto_subsystem_pbus_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset,
  input         auto_subsystem_sbus_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_clock,
  input         auto_subsystem_sbus_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_reset,
  input         auto_subsystem_sbus_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock,
  input         auto_subsystem_sbus_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset,
  input         mem_axi4_0_aw_ready, mem_axi4_0_w_ready, mem_axi4_0_b_valid,
  input  [3:0]  mem_axi4_0_b_bits_id,
  input  [1:0]  mem_axi4_0_b_bits_resp,
  input         mem_axi4_0_ar_ready, mem_axi4_0_r_valid,
  input  [3:0]  mem_axi4_0_r_bits_id,
  input  [63:0] mem_axi4_0_r_bits_data,
  input  [1:0]  mem_axi4_0_r_bits_resp,
  input         mem_axi4_0_r_bits_last, custom_boot, serial_tl_bits_in_valid,
  input  [3:0]  serial_tl_bits_in_bits,
  input         serial_tl_bits_out_ready, resetctrl_hartIsInReset_0,
  input         resetctrl_hartIsInReset_1, resetctrl_hartIsInReset_2,
  input         resetctrl_hartIsInReset_3, resetctrl_hartIsInReset_4,
  input         resetctrl_hartIsInReset_5, debug_clock, debug_reset,
  input         debug_systemjtag_jtag_TCK, debug_systemjtag_jtag_TMS,
  input         debug_systemjtag_jtag_TDI, debug_systemjtag_reset, debug_dmactiveAck,
  input         uart_0_rxd,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_clock,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_reset,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_clock,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_reset,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_clock,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_reset,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_clock,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_reset,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_clock,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_reset,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_clock,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_reset,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_clock,
  output        auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_reset,
  output        auto_subsystem_mbus_fixedClockNode_out_clock,
  output        auto_subsystem_mbus_fixedClockNode_out_reset,
  output        auto_subsystem_cbus_fixedClockNode_out_clock,
  output        auto_subsystem_cbus_fixedClockNode_out_reset, mem_axi4_0_aw_valid,
  output [3:0]  mem_axi4_0_aw_bits_id,
  output [31:0] mem_axi4_0_aw_bits_addr,
  output [7:0]  mem_axi4_0_aw_bits_len,
  output [2:0]  mem_axi4_0_aw_bits_size,
  output [1:0]  mem_axi4_0_aw_bits_burst,
  output        mem_axi4_0_aw_bits_lock,
  output [3:0]  mem_axi4_0_aw_bits_cache,
  output [2:0]  mem_axi4_0_aw_bits_prot,
  output [3:0]  mem_axi4_0_aw_bits_qos,
  output        mem_axi4_0_w_valid,
  output [63:0] mem_axi4_0_w_bits_data,
  output [7:0]  mem_axi4_0_w_bits_strb,
  output        mem_axi4_0_w_bits_last, mem_axi4_0_b_ready, mem_axi4_0_ar_valid,
  output [3:0]  mem_axi4_0_ar_bits_id,
  output [31:0] mem_axi4_0_ar_bits_addr,
  output [7:0]  mem_axi4_0_ar_bits_len,
  output [2:0]  mem_axi4_0_ar_bits_size,
  output [1:0]  mem_axi4_0_ar_bits_burst,
  output        mem_axi4_0_ar_bits_lock,
  output [3:0]  mem_axi4_0_ar_bits_cache,
  output [2:0]  mem_axi4_0_ar_bits_prot,
  output [3:0]  mem_axi4_0_ar_bits_qos,
  output        mem_axi4_0_r_ready, serial_tl_clock, serial_tl_bits_in_ready,
  output        serial_tl_bits_out_valid,
  output [3:0]  serial_tl_bits_out_bits,
  output        debug_systemjtag_jtag_TDO_data, debug_systemjtag_jtag_TDO_driven,
  output        debug_ndreset, debug_dmactive, uart_0_txd);

  wire        dtm_io_dmi_req_valid;	// Periphery.scala:161:21
  wire [6:0]  dtm_io_dmi_req_bits_addr;	// Periphery.scala:161:21
  wire [31:0] dtm_io_dmi_req_bits_data;	// Periphery.scala:161:21
  wire [1:0]  dtm_io_dmi_req_bits_op;	// Periphery.scala:161:21
  wire        dtm_io_dmi_resp_ready;	// Periphery.scala:161:21
  wire        domain_1_auto_resetCtrl_in_a_ready;	// TileResetCtrl.scala:23:34
  wire        domain_1_auto_resetCtrl_in_d_valid;	// TileResetCtrl.scala:23:34
  wire [2:0]  domain_1_auto_resetCtrl_in_d_bits_opcode;	// TileResetCtrl.scala:23:34
  wire [1:0]  domain_1_auto_resetCtrl_in_d_bits_size;	// TileResetCtrl.scala:23:34
  wire [11:0] domain_1_auto_resetCtrl_in_d_bits_source;	// TileResetCtrl.scala:23:34
  wire [63:0] domain_1_auto_resetCtrl_in_d_bits_data;	// TileResetCtrl.scala:23:34
  wire        domain_1_clock;	// TileResetCtrl.scala:23:34
  wire        domain_1_reset;	// TileResetCtrl.scala:23:34
  wire        intsink_24_auto_out_0;	// Crossing.scala:94:29
  wire        uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0;	// UART.scala:242:44
  wire        uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready;	// UART.scala:242:44
  wire        uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid;	// UART.scala:242:44
  wire [2:0]  uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode;	// UART.scala:242:44
  wire [1:0]  uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size;	// UART.scala:242:44
  wire [11:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source;	// UART.scala:242:44
  wire [63:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data;	// UART.scala:242:44
  wire        uartClockDomainWrapper_clock;	// UART.scala:242:44
  wire        uartClockDomainWrapper_reset;	// UART.scala:242:44
  wire        domain_auto_serdesser_client_out_a_valid;	// SerialAdapter.scala:373:28
  wire [2:0]  domain_auto_serdesser_client_out_a_bits_opcode;	// SerialAdapter.scala:373:28
  wire [2:0]  domain_auto_serdesser_client_out_a_bits_param;	// SerialAdapter.scala:373:28
  wire [3:0]  domain_auto_serdesser_client_out_a_bits_size;	// SerialAdapter.scala:373:28
  wire        domain_auto_serdesser_client_out_a_bits_source;	// SerialAdapter.scala:373:28
  wire [31:0] domain_auto_serdesser_client_out_a_bits_address;	// SerialAdapter.scala:373:28
  wire [7:0]  domain_auto_serdesser_client_out_a_bits_mask;	// SerialAdapter.scala:373:28
  wire [63:0] domain_auto_serdesser_client_out_a_bits_data;	// SerialAdapter.scala:373:28
  wire        domain_auto_serdesser_client_out_a_bits_corrupt;	// SerialAdapter.scala:373:28
  wire        domain_auto_serdesser_client_out_d_ready;	// SerialAdapter.scala:373:28
  wire        domain_auto_tlserial_manager_crossing_in_a_ready;	// SerialAdapter.scala:373:28
  wire        domain_auto_tlserial_manager_crossing_in_d_valid;	// SerialAdapter.scala:373:28
  wire [2:0]  domain_auto_tlserial_manager_crossing_in_d_bits_opcode;	// SerialAdapter.scala:373:28
  wire [1:0]  domain_auto_tlserial_manager_crossing_in_d_bits_param;	// SerialAdapter.scala:373:28
  wire [2:0]  domain_auto_tlserial_manager_crossing_in_d_bits_size;	// SerialAdapter.scala:373:28
  wire [3:0]  domain_auto_tlserial_manager_crossing_in_d_bits_source;	// SerialAdapter.scala:373:28
  wire        domain_auto_tlserial_manager_crossing_in_d_bits_sink;	// SerialAdapter.scala:373:28
  wire        domain_auto_tlserial_manager_crossing_in_d_bits_denied;	// SerialAdapter.scala:373:28
  wire [63:0] domain_auto_tlserial_manager_crossing_in_d_bits_data;	// SerialAdapter.scala:373:28
  wire        domain_auto_tlserial_manager_crossing_in_d_bits_corrupt;	// SerialAdapter.scala:373:28
  wire        domain_reset;	// SerialAdapter.scala:373:28
  wire        bootROMDomainWrapper_auto_bootrom_in_a_ready;	// BootROM.scala:70:42
  wire        bootROMDomainWrapper_auto_bootrom_in_d_valid;	// BootROM.scala:70:42
  wire [1:0]  bootROMDomainWrapper_auto_bootrom_in_d_bits_size;	// BootROM.scala:70:42
  wire [11:0] bootROMDomainWrapper_auto_bootrom_in_d_bits_source;	// BootROM.scala:70:42
  wire [63:0] bootROMDomainWrapper_auto_bootrom_in_d_bits_data;	// BootROM.scala:70:42
  wire        bootROMDomainWrapper_clock;	// BootROM.scala:70:42
  wire        bootROMDomainWrapper_reset;	// BootROM.scala:70:42
  wire        intsink_23_auto_out_0;	// Crossing.scala:94:29
  wire        intsink_22_auto_out_0;	// Crossing.scala:94:29
  wire        intsink_21_auto_out_0;	// Crossing.scala:94:29
  wire        intsource_16_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_15_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_14_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_14_auto_out_sync_1;	// Crossing.scala:26:31
  wire        intsink_19_auto_out_0;	// Crossing.scala:94:29
  wire        intsink_18_auto_out_0;	// Crossing.scala:94:29
  wire        intsink_17_auto_out_0;	// Crossing.scala:94:29
  wire        intsource_13_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_12_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_11_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_11_auto_out_sync_1;	// Crossing.scala:26:31
  wire        intsink_15_auto_out_0;	// Crossing.scala:94:29
  wire        intsink_14_auto_out_0;	// Crossing.scala:94:29
  wire        intsink_13_auto_out_0;	// Crossing.scala:94:29
  wire        intsource_10_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_9_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_8_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_8_auto_out_sync_1;	// Crossing.scala:26:31
  wire        intsink_11_auto_out_0;	// Crossing.scala:94:29
  wire        intsink_10_auto_out_0;	// Crossing.scala:94:29
  wire        intsink_9_auto_out_0;	// Crossing.scala:94:29
  wire        intsource_7_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_6_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_6_auto_out_sync_1;	// Crossing.scala:26:31
  wire        intsink_7_auto_out_0;	// Crossing.scala:94:29
  wire        intsink_6_auto_out_0;	// Crossing.scala:94:29
  wire        intsink_5_auto_out_0;	// Crossing.scala:94:29
  wire        intsource_5_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_4_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_3_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_3_auto_out_sync_1;	// Crossing.scala:26:31
  wire        intsink_3_auto_out_0;	// Crossing.scala:94:29
  wire        intsink_2_auto_out_0;	// Crossing.scala:94:29
  wire        intsink_1_auto_out_0;	// Crossing.scala:94:29
  wire        intsource_2_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_1_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_auto_out_sync_0;	// Crossing.scala:26:31
  wire        intsource_auto_out_sync_1;	// Crossing.scala:26:31
  wire        xbar_2_auto_int_out_0;	// Xbar.scala:30:26
  wire        xbar_2_auto_int_out_1;	// Xbar.scala:30:26
  wire        xbar_2_auto_int_out_2;	// Xbar.scala:30:26
  wire        xbar_2_auto_int_out_3;	// Xbar.scala:30:26
  wire        xbar_2_auto_int_out_4;	// Xbar.scala:30:26
  wire        xbar_2_auto_int_out_5;	// Xbar.scala:30:26
  wire        xbar_1_auto_int_out_0;	// Xbar.scala:30:26
  wire        xbar_1_auto_int_out_1;	// Xbar.scala:30:26
  wire        xbar_1_auto_int_out_2;	// Xbar.scala:30:26
  wire        xbar_1_auto_int_out_3;	// Xbar.scala:30:26
  wire        xbar_1_auto_int_out_4;	// Xbar.scala:30:26
  wire        xbar_1_auto_int_out_5;	// Xbar.scala:30:26
  wire        xbar_auto_int_out_0;	// Xbar.scala:30:26
  wire        xbar_auto_int_out_1;	// Xbar.scala:30:26
  wire        xbar_auto_int_out_2;	// Xbar.scala:30:26
  wire        xbar_auto_int_out_3;	// Xbar.scala:30:26
  wire        xbar_auto_int_out_4;	// Xbar.scala:30:26
  wire        xbar_auto_int_out_5;	// Xbar.scala:30:26
  wire        debug_1_auto_dmInner_dmInner_tl_in_a_ready;	// Periphery.scala:84:27
  wire        debug_1_auto_dmInner_dmInner_tl_in_d_valid;	// Periphery.scala:84:27
  wire [2:0]  debug_1_auto_dmInner_dmInner_tl_in_d_bits_opcode;	// Periphery.scala:84:27
  wire [1:0]  debug_1_auto_dmInner_dmInner_tl_in_d_bits_size;	// Periphery.scala:84:27
  wire [11:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_source;	// Periphery.scala:84:27
  wire [63:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_data;	// Periphery.scala:84:27
  wire        debug_1_auto_dmOuter_intsource_out_5_sync_0;	// Periphery.scala:84:27
  wire        debug_1_auto_dmOuter_intsource_out_4_sync_0;	// Periphery.scala:84:27
  wire        debug_1_auto_dmOuter_intsource_out_3_sync_0;	// Periphery.scala:84:27
  wire        debug_1_auto_dmOuter_intsource_out_2_sync_0;	// Periphery.scala:84:27
  wire        debug_1_auto_dmOuter_intsource_out_1_sync_0;	// Periphery.scala:84:27
  wire        debug_1_auto_dmOuter_intsource_out_0_sync_0;	// Periphery.scala:84:27
  wire        debug_1_io_dmi_dmi_req_ready;	// Periphery.scala:84:27
  wire        debug_1_io_dmi_dmi_resp_valid;	// Periphery.scala:84:27
  wire [31:0] debug_1_io_dmi_dmi_resp_bits_data;	// Periphery.scala:84:27
  wire [1:0]  debug_1_io_dmi_dmi_resp_bits_resp;	// Periphery.scala:84:27
  wire        clint_auto_int_out_5_0;	// CLINT.scala:109:27
  wire        clint_auto_int_out_5_1;	// CLINT.scala:109:27
  wire        clint_auto_int_out_4_0;	// CLINT.scala:109:27
  wire        clint_auto_int_out_4_1;	// CLINT.scala:109:27
  wire        clint_auto_int_out_3_0;	// CLINT.scala:109:27
  wire        clint_auto_int_out_3_1;	// CLINT.scala:109:27
  wire        clint_auto_int_out_2_0;	// CLINT.scala:109:27
  wire        clint_auto_int_out_2_1;	// CLINT.scala:109:27
  wire        clint_auto_int_out_1_0;	// CLINT.scala:109:27
  wire        clint_auto_int_out_1_1;	// CLINT.scala:109:27
  wire        clint_auto_int_out_0_0;	// CLINT.scala:109:27
  wire        clint_auto_int_out_0_1;	// CLINT.scala:109:27
  wire        clint_auto_in_a_ready;	// CLINT.scala:109:27
  wire        clint_auto_in_d_valid;	// CLINT.scala:109:27
  wire [2:0]  clint_auto_in_d_bits_opcode;	// CLINT.scala:109:27
  wire [1:0]  clint_auto_in_d_bits_size;	// CLINT.scala:109:27
  wire [11:0] clint_auto_in_d_bits_source;	// CLINT.scala:109:27
  wire [63:0] clint_auto_in_d_bits_data;	// CLINT.scala:109:27
  wire        plicDomainWrapper_auto_plic_int_out_10_0;	// Plic.scala:359:39
  wire        plicDomainWrapper_auto_plic_int_out_9_0;	// Plic.scala:359:39
  wire        plicDomainWrapper_auto_plic_int_out_8_0;	// Plic.scala:359:39
  wire        plicDomainWrapper_auto_plic_int_out_7_0;	// Plic.scala:359:39
  wire        plicDomainWrapper_auto_plic_int_out_6_0;	// Plic.scala:359:39
  wire        plicDomainWrapper_auto_plic_int_out_5_0;	// Plic.scala:359:39
  wire        plicDomainWrapper_auto_plic_int_out_4_0;	// Plic.scala:359:39
  wire        plicDomainWrapper_auto_plic_int_out_3_0;	// Plic.scala:359:39
  wire        plicDomainWrapper_auto_plic_int_out_2_0;	// Plic.scala:359:39
  wire        plicDomainWrapper_auto_plic_int_out_1_0;	// Plic.scala:359:39
  wire        plicDomainWrapper_auto_plic_int_out_0_0;	// Plic.scala:359:39
  wire        plicDomainWrapper_auto_plic_in_a_ready;	// Plic.scala:359:39
  wire        plicDomainWrapper_auto_plic_in_d_valid;	// Plic.scala:359:39
  wire [2:0]  plicDomainWrapper_auto_plic_in_d_bits_opcode;	// Plic.scala:359:39
  wire [1:0]  plicDomainWrapper_auto_plic_in_d_bits_size;	// Plic.scala:359:39
  wire [11:0] plicDomainWrapper_auto_plic_in_d_bits_source;	// Plic.scala:359:39
  wire [63:0] plicDomainWrapper_auto_plic_in_d_bits_data;	// Plic.scala:359:39
  wire        plicDomainWrapper_clock;	// Plic.scala:359:39
  wire        plicDomainWrapper_reset;	// Plic.scala:359:39
  wire        tile_prci_domain_5_auto_int_out_clock_xing_out_2_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_5_auto_int_out_clock_xing_out_1_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_5_auto_int_out_clock_xing_out_0_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_5_auto_tl_master_clock_xing_out_a_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_opcode;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_param;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_size;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_source;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_address;	// HasTiles.scala:252:38
  wire [7:0]  tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_mask;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_data;	// HasTiles.scala:252:38
  wire        tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_corrupt;	// HasTiles.scala:252:38
  wire        tile_prci_domain_5_auto_tl_master_clock_xing_out_b_ready;	// HasTiles.scala:252:38
  wire        tile_prci_domain_5_auto_tl_master_clock_xing_out_c_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_opcode;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_param;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_size;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_source;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_address;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_data;	// HasTiles.scala:252:38
  wire        tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_corrupt;	// HasTiles.scala:252:38
  wire        tile_prci_domain_5_auto_tl_master_clock_xing_out_d_ready;	// HasTiles.scala:252:38
  wire        tile_prci_domain_5_auto_tl_master_clock_xing_out_e_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_5_auto_tl_master_clock_xing_out_e_bits_sink;	// HasTiles.scala:252:38
  wire        tile_prci_domain_5_clock;	// HasTiles.scala:252:38
  wire        tile_prci_domain_5_reset;	// HasTiles.scala:252:38
  wire        tile_prci_domain_4_auto_int_out_clock_xing_out_2_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_4_auto_int_out_clock_xing_out_1_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_4_auto_int_out_clock_xing_out_0_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_4_auto_tl_master_clock_xing_out_a_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_opcode;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_param;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_size;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_source;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_address;	// HasTiles.scala:252:38
  wire [7:0]  tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_mask;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_data;	// HasTiles.scala:252:38
  wire        tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_corrupt;	// HasTiles.scala:252:38
  wire        tile_prci_domain_4_auto_tl_master_clock_xing_out_b_ready;	// HasTiles.scala:252:38
  wire        tile_prci_domain_4_auto_tl_master_clock_xing_out_c_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_opcode;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_param;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_size;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_source;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_address;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_data;	// HasTiles.scala:252:38
  wire        tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_corrupt;	// HasTiles.scala:252:38
  wire        tile_prci_domain_4_auto_tl_master_clock_xing_out_d_ready;	// HasTiles.scala:252:38
  wire        tile_prci_domain_4_auto_tl_master_clock_xing_out_e_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_4_auto_tl_master_clock_xing_out_e_bits_sink;	// HasTiles.scala:252:38
  wire        tile_prci_domain_4_clock;	// HasTiles.scala:252:38
  wire        tile_prci_domain_4_reset;	// HasTiles.scala:252:38
  wire        tile_prci_domain_3_auto_int_out_clock_xing_out_2_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_3_auto_int_out_clock_xing_out_1_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_3_auto_int_out_clock_xing_out_0_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_3_auto_tl_master_clock_xing_out_a_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_opcode;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_param;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_size;	// HasTiles.scala:252:38
  wire [4:0]  tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_source;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_address;	// HasTiles.scala:252:38
  wire [7:0]  tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_mask;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_data;	// HasTiles.scala:252:38
  wire        tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_corrupt;	// HasTiles.scala:252:38
  wire        tile_prci_domain_3_auto_tl_master_clock_xing_out_b_ready;	// HasTiles.scala:252:38
  wire        tile_prci_domain_3_auto_tl_master_clock_xing_out_c_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_opcode;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_param;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_size;	// HasTiles.scala:252:38
  wire [4:0]  tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_source;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_address;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_data;	// HasTiles.scala:252:38
  wire        tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_corrupt;	// HasTiles.scala:252:38
  wire        tile_prci_domain_3_auto_tl_master_clock_xing_out_d_ready;	// HasTiles.scala:252:38
  wire        tile_prci_domain_3_auto_tl_master_clock_xing_out_e_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_3_auto_tl_master_clock_xing_out_e_bits_sink;	// HasTiles.scala:252:38
  wire        tile_prci_domain_3_clock;	// HasTiles.scala:252:38
  wire        tile_prci_domain_3_reset;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_valid;	// HasTiles.scala:252:38
  wire [33:0] tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_iaddr;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_insn;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_priv;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_exception;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_interrupt;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_cause;	// HasTiles.scala:252:38
  wire [33:0] tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_tval;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_int_out_clock_xing_out_2_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_int_out_clock_xing_out_1_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_int_out_clock_xing_out_0_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_tl_master_clock_xing_out_a_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_opcode;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_param;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_size;	// HasTiles.scala:252:38
  wire [1:0]  tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_source;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_address;	// HasTiles.scala:252:38
  wire [7:0]  tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_mask;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_data;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_corrupt;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_tl_master_clock_xing_out_b_ready;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_tl_master_clock_xing_out_c_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_opcode;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_param;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_size;	// HasTiles.scala:252:38
  wire [1:0]  tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_source;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_address;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_data;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_corrupt;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_tl_master_clock_xing_out_d_ready;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_auto_tl_master_clock_xing_out_e_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_2_auto_tl_master_clock_xing_out_e_bits_sink;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_clock;	// HasTiles.scala:252:38
  wire        tile_prci_domain_2_reset;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_valid;	// HasTiles.scala:252:38
  wire [39:0] tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_iaddr;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_insn;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_priv;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_exception;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_interrupt;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_cause;	// HasTiles.scala:252:38
  wire [39:0] tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_tval;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_int_out_clock_xing_out_2_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_int_out_clock_xing_out_1_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_int_out_clock_xing_out_0_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_tl_master_clock_xing_out_a_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_opcode;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_param;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_size;	// HasTiles.scala:252:38
  wire [1:0]  tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_source;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_address;	// HasTiles.scala:252:38
  wire [7:0]  tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_mask;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_data;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_corrupt;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_tl_master_clock_xing_out_b_ready;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_tl_master_clock_xing_out_c_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_opcode;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_param;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_size;	// HasTiles.scala:252:38
  wire [1:0]  tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_source;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_address;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_data;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_corrupt;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_tl_master_clock_xing_out_d_ready;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_auto_tl_master_clock_xing_out_e_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_1_auto_tl_master_clock_xing_out_e_bits_sink;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_clock;	// HasTiles.scala:252:38
  wire        tile_prci_domain_1_reset;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_valid;	// HasTiles.scala:252:38
  wire [39:0] tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_iaddr;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_insn;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_priv;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_exception;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_interrupt;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_cause;	// HasTiles.scala:252:38
  wire [39:0] tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_tval;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_int_out_clock_xing_out_2_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_int_out_clock_xing_out_1_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_int_out_clock_xing_out_0_sync_0;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_tl_master_clock_xing_out_a_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size;	// HasTiles.scala:252:38
  wire [1:0]  tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address;	// HasTiles.scala:252:38
  wire [7:0]  tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_tl_master_clock_xing_out_b_ready;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_tl_master_clock_xing_out_c_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param;	// HasTiles.scala:252:38
  wire [3:0]  tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size;	// HasTiles.scala:252:38
  wire [1:0]  tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source;	// HasTiles.scala:252:38
  wire [31:0] tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address;	// HasTiles.scala:252:38
  wire [63:0] tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_tl_master_clock_xing_out_d_ready;	// HasTiles.scala:252:38
  wire        tile_prci_domain_auto_tl_master_clock_xing_out_e_valid;	// HasTiles.scala:252:38
  wire [2:0]  tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink;	// HasTiles.scala:252:38
  wire        tile_prci_domain_clock;	// HasTiles.scala:252:38
  wire        tile_prci_domain_reset;	// HasTiles.scala:252:38
  wire        subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_valid;	// BankedL2Params.scala:47:31
  wire [2:0]  subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_opcode;	// BankedL2Params.scala:47:31
  wire [2:0]  subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_param;	// BankedL2Params.scala:47:31
  wire [2:0]  subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_size;	// BankedL2Params.scala:47:31
  wire [3:0]  subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_source;	// BankedL2Params.scala:47:31
  wire [31:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_address;	// BankedL2Params.scala:47:31
  wire [7:0]  subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_mask;	// BankedL2Params.scala:47:31
  wire [63:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_data;	// BankedL2Params.scala:47:31
  wire        subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_corrupt;	// BankedL2Params.scala:47:31
  wire        subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_ready;	// BankedL2Params.scala:47:31
  wire        subsystem_l2_wrapper_auto_coherent_jbar_in_a_ready;	// BankedL2Params.scala:47:31
  wire        subsystem_l2_wrapper_auto_coherent_jbar_in_b_valid;	// BankedL2Params.scala:47:31
  wire [1:0]  subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_param;	// BankedL2Params.scala:47:31
  wire [6:0]  subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_source;	// BankedL2Params.scala:47:31
  wire [31:0] subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_address;	// BankedL2Params.scala:47:31
  wire        subsystem_l2_wrapper_auto_coherent_jbar_in_c_ready;	// BankedL2Params.scala:47:31
  wire        subsystem_l2_wrapper_auto_coherent_jbar_in_d_valid;	// BankedL2Params.scala:47:31
  wire [2:0]  subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_opcode;	// BankedL2Params.scala:47:31
  wire [1:0]  subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_param;	// BankedL2Params.scala:47:31
  wire [2:0]  subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_size;	// BankedL2Params.scala:47:31
  wire [6:0]  subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_source;	// BankedL2Params.scala:47:31
  wire [2:0]  subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_sink;	// BankedL2Params.scala:47:31
  wire        subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_denied;	// BankedL2Params.scala:47:31
  wire [63:0] subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_data;	// BankedL2Params.scala:47:31
  wire        subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_corrupt;	// BankedL2Params.scala:47:31
  wire        subsystem_l2_wrapper_auto_l2_ctl_in_a_ready;	// BankedL2Params.scala:47:31
  wire        subsystem_l2_wrapper_auto_l2_ctl_in_d_valid;	// BankedL2Params.scala:47:31
  wire [2:0]  subsystem_l2_wrapper_auto_l2_ctl_in_d_bits_opcode;	// BankedL2Params.scala:47:31
  wire [1:0]  subsystem_l2_wrapper_auto_l2_ctl_in_d_bits_size;	// BankedL2Params.scala:47:31
  wire [11:0] subsystem_l2_wrapper_auto_l2_ctl_in_d_bits_source;	// BankedL2Params.scala:47:31
  wire [63:0] subsystem_l2_wrapper_auto_l2_ctl_in_d_bits_data;	// BankedL2Params.scala:47:31
  wire        subsystem_l2_wrapper_clock;	// BankedL2Params.scala:47:31
  wire        subsystem_l2_wrapper_reset;	// BankedL2Params.scala:47:31
  wire        subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_valid;	// MemoryBus.scala:25:26
  wire [2:0]  subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_opcode;	// MemoryBus.scala:25:26
  wire [2:0]  subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_param;	// MemoryBus.scala:25:26
  wire [2:0]  subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_size;	// MemoryBus.scala:25:26
  wire [3:0]  subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_source;	// MemoryBus.scala:25:26
  wire [28:0] subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_address;	// MemoryBus.scala:25:26
  wire [7:0]  subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_mask;	// MemoryBus.scala:25:26
  wire [63:0] subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_data;	// MemoryBus.scala:25:26
  wire        subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_corrupt;	// MemoryBus.scala:25:26
  wire        subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_ready;	// MemoryBus.scala:25:26
  wire        subsystem_mbus_auto_bus_xing_in_a_ready;	// MemoryBus.scala:25:26
  wire        subsystem_mbus_auto_bus_xing_in_d_valid;	// MemoryBus.scala:25:26
  wire [2:0]  subsystem_mbus_auto_bus_xing_in_d_bits_opcode;	// MemoryBus.scala:25:26
  wire [1:0]  subsystem_mbus_auto_bus_xing_in_d_bits_param;	// MemoryBus.scala:25:26
  wire [2:0]  subsystem_mbus_auto_bus_xing_in_d_bits_size;	// MemoryBus.scala:25:26
  wire [3:0]  subsystem_mbus_auto_bus_xing_in_d_bits_source;	// MemoryBus.scala:25:26
  wire        subsystem_mbus_auto_bus_xing_in_d_bits_sink;	// MemoryBus.scala:25:26
  wire        subsystem_mbus_auto_bus_xing_in_d_bits_denied;	// MemoryBus.scala:25:26
  wire [63:0] subsystem_mbus_auto_bus_xing_in_d_bits_data;	// MemoryBus.scala:25:26
  wire        subsystem_mbus_auto_bus_xing_in_d_bits_corrupt;	// MemoryBus.scala:25:26
  wire        subsystem_mbus_clock;	// MemoryBus.scala:25:26
  wire        subsystem_mbus_reset;	// MemoryBus.scala:25:26
  wire        subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_valid;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_param;	// PeripheryBus.scala:31:26
  wire [1:0]  subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_size;	// PeripheryBus.scala:31:26
  wire [11:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_source;	// PeripheryBus.scala:31:26
  wire [16:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_address;	// PeripheryBus.scala:31:26
  wire [7:0]  subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_mask;	// PeripheryBus.scala:31:26
  wire [63:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_data;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_ready;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_valid;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_opcode;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_param;	// PeripheryBus.scala:31:26
  wire [1:0]  subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_size;	// PeripheryBus.scala:31:26
  wire [11:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_source;	// PeripheryBus.scala:31:26
  wire [11:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_address;	// PeripheryBus.scala:31:26
  wire [7:0]  subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_mask;	// PeripheryBus.scala:31:26
  wire [63:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_data;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_corrupt;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_ready;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_valid;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_opcode;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_param;	// PeripheryBus.scala:31:26
  wire [1:0]  subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_size;	// PeripheryBus.scala:31:26
  wire [11:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_source;	// PeripheryBus.scala:31:26
  wire [25:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_address;	// PeripheryBus.scala:31:26
  wire [7:0]  subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_mask;	// PeripheryBus.scala:31:26
  wire [63:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_data;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_corrupt;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_ready;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_valid;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_opcode;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_param;	// PeripheryBus.scala:31:26
  wire [1:0]  subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_size;	// PeripheryBus.scala:31:26
  wire [11:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_source;	// PeripheryBus.scala:31:26
  wire [27:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_address;	// PeripheryBus.scala:31:26
  wire [7:0]  subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_mask;	// PeripheryBus.scala:31:26
  wire [63:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_data;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_corrupt;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_ready;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size;	// PeripheryBus.scala:31:26
  wire [7:0]  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source;	// PeripheryBus.scala:31:26
  wire [30:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address;	// PeripheryBus.scala:31:26
  wire [7:0]  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask;	// PeripheryBus.scala:31:26
  wire [63:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param;	// PeripheryBus.scala:31:26
  wire [1:0]  subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size;	// PeripheryBus.scala:31:26
  wire [11:0] subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source;	// PeripheryBus.scala:31:26
  wire [25:0] subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address;	// PeripheryBus.scala:31:26
  wire [7:0]  subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask;	// PeripheryBus.scala:31:26
  wire [63:0] subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_fixedClockNode_out_2_clock;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_fixedClockNode_out_2_reset;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_fixedClockNode_out_1_clock;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_fixedClockNode_out_1_reset;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_fixedClockNode_out_0_clock;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_fixedClockNode_out_0_reset;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_bus_xing_in_a_ready;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_bus_xing_in_d_valid;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_cbus_auto_bus_xing_in_d_bits_opcode;	// PeripheryBus.scala:31:26
  wire [1:0]  subsystem_cbus_auto_bus_xing_in_d_bits_param;	// PeripheryBus.scala:31:26
  wire [3:0]  subsystem_cbus_auto_bus_xing_in_d_bits_size;	// PeripheryBus.scala:31:26
  wire [6:0]  subsystem_cbus_auto_bus_xing_in_d_bits_source;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_bus_xing_in_d_bits_sink;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_bus_xing_in_d_bits_denied;	// PeripheryBus.scala:31:26
  wire [63:0] subsystem_cbus_auto_bus_xing_in_d_bits_data;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_auto_bus_xing_in_d_bits_corrupt;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_clock;	// PeripheryBus.scala:31:26
  wire        subsystem_cbus_reset;	// PeripheryBus.scala:31:26
  wire        subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_ready;	// FrontBus.scala:22:26
  wire        subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_valid;	// FrontBus.scala:22:26
  wire [2:0]  subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_opcode;	// FrontBus.scala:22:26
  wire [1:0]  subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_param;	// FrontBus.scala:22:26
  wire [3:0]  subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_size;	// FrontBus.scala:22:26
  wire        subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_source;	// FrontBus.scala:22:26
  wire [2:0]  subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_sink;	// FrontBus.scala:22:26
  wire        subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_denied;	// FrontBus.scala:22:26
  wire [63:0] subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_data;	// FrontBus.scala:22:26
  wire        subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_corrupt;	// FrontBus.scala:22:26
  wire        subsystem_fbus_auto_fixedClockNode_out_clock;	// FrontBus.scala:22:26
  wire        subsystem_fbus_auto_fixedClockNode_out_reset;	// FrontBus.scala:22:26
  wire        subsystem_fbus_auto_bus_xing_out_a_valid;	// FrontBus.scala:22:26
  wire [2:0]  subsystem_fbus_auto_bus_xing_out_a_bits_opcode;	// FrontBus.scala:22:26
  wire [2:0]  subsystem_fbus_auto_bus_xing_out_a_bits_param;	// FrontBus.scala:22:26
  wire [3:0]  subsystem_fbus_auto_bus_xing_out_a_bits_size;	// FrontBus.scala:22:26
  wire        subsystem_fbus_auto_bus_xing_out_a_bits_source;	// FrontBus.scala:22:26
  wire [31:0] subsystem_fbus_auto_bus_xing_out_a_bits_address;	// FrontBus.scala:22:26
  wire [7:0]  subsystem_fbus_auto_bus_xing_out_a_bits_mask;	// FrontBus.scala:22:26
  wire [63:0] subsystem_fbus_auto_bus_xing_out_a_bits_data;	// FrontBus.scala:22:26
  wire        subsystem_fbus_auto_bus_xing_out_a_bits_corrupt;	// FrontBus.scala:22:26
  wire        subsystem_fbus_auto_bus_xing_out_d_ready;	// FrontBus.scala:22:26
  wire        subsystem_fbus_clock;	// FrontBus.scala:22:26
  wire        subsystem_fbus_reset;	// FrontBus.scala:22:26
  wire        subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_valid;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_opcode;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_param;	// PeripheryBus.scala:31:26
  wire [1:0]  subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_size;	// PeripheryBus.scala:31:26
  wire [11:0] subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_source;	// PeripheryBus.scala:31:26
  wire [20:0] subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_address;	// PeripheryBus.scala:31:26
  wire [7:0]  subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_mask;	// PeripheryBus.scala:31:26
  wire [63:0] subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_data;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_corrupt;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_d_ready;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param;	// PeripheryBus.scala:31:26
  wire [1:0]  subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size;	// PeripheryBus.scala:31:26
  wire [11:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source;	// PeripheryBus.scala:31:26
  wire [30:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address;	// PeripheryBus.scala:31:26
  wire [7:0]  subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask;	// PeripheryBus.scala:31:26
  wire [63:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_fixedClockNode_out_1_clock;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_fixedClockNode_out_1_reset;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_fixedClockNode_out_0_clock;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_fixedClockNode_out_0_reset;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_bus_xing_in_a_ready;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_bus_xing_in_d_valid;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_pbus_auto_bus_xing_in_d_bits_opcode;	// PeripheryBus.scala:31:26
  wire [1:0]  subsystem_pbus_auto_bus_xing_in_d_bits_param;	// PeripheryBus.scala:31:26
  wire [2:0]  subsystem_pbus_auto_bus_xing_in_d_bits_size;	// PeripheryBus.scala:31:26
  wire [7:0]  subsystem_pbus_auto_bus_xing_in_d_bits_source;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_bus_xing_in_d_bits_sink;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_bus_xing_in_d_bits_denied;	// PeripheryBus.scala:31:26
  wire [63:0] subsystem_pbus_auto_bus_xing_in_d_bits_data;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_auto_bus_xing_in_d_bits_corrupt;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_clock;	// PeripheryBus.scala:31:26
  wire        subsystem_pbus_reset;	// PeripheryBus.scala:31:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_valid;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_bits_param;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_bits_source;	// SystemBus.scala:24:26
  wire [31:0] subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_bits_address;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_c_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_valid;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_opcode;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_param;	// SystemBus.scala:24:26
  wire [3:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_size;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_source;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_sink;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_denied;	// SystemBus.scala:24:26
  wire [63:0] subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_data;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_corrupt;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_e_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_valid;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_bits_param;	// SystemBus.scala:24:26
  wire [3:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_bits_source;	// SystemBus.scala:24:26
  wire [31:0] subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_bits_address;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_c_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_valid;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_opcode;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_param;	// SystemBus.scala:24:26
  wire [3:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_size;	// SystemBus.scala:24:26
  wire [3:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_source;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_sink;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_denied;	// SystemBus.scala:24:26
  wire [63:0] subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_data;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_corrupt;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_e_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_valid;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_bits_param;	// SystemBus.scala:24:26
  wire [4:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_bits_source;	// SystemBus.scala:24:26
  wire [31:0] subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_bits_address;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_c_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_valid;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_opcode;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_param;	// SystemBus.scala:24:26
  wire [3:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_size;	// SystemBus.scala:24:26
  wire [4:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_source;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_sink;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_denied;	// SystemBus.scala:24:26
  wire [63:0] subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_data;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_corrupt;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_e_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_a_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_b_valid;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_b_bits_param;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_b_bits_source;	// SystemBus.scala:24:26
  wire [31:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_b_bits_address;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_c_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_valid;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_opcode;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_param;	// SystemBus.scala:24:26
  wire [3:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_size;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_source;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_sink;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_denied;	// SystemBus.scala:24:26
  wire [63:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_data;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_corrupt;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_e_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_a_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_b_valid;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_b_bits_param;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_b_bits_source;	// SystemBus.scala:24:26
  wire [31:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_b_bits_address;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_c_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_valid;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_opcode;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_param;	// SystemBus.scala:24:26
  wire [3:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_size;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_source;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_sink;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_denied;	// SystemBus.scala:24:26
  wire [63:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_data;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_corrupt;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_e_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_a_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_b_valid;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_b_bits_param;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_b_bits_source;	// SystemBus.scala:24:26
  wire [31:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_b_bits_address;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_c_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_valid;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_opcode;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_param;	// SystemBus.scala:24:26
  wire [3:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_size;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_source;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_sink;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_denied;	// SystemBus.scala:24:26
  wire [63:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_data;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_corrupt;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_e_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_valid;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_opcode;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_param;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_size;	// SystemBus.scala:24:26
  wire [6:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_source;	// SystemBus.scala:24:26
  wire [31:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_address;	// SystemBus.scala:24:26
  wire [7:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_mask;	// SystemBus.scala:24:26
  wire [63:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_data;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_corrupt;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_valid;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_opcode;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_param;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_size;	// SystemBus.scala:24:26
  wire [6:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_source;	// SystemBus.scala:24:26
  wire [31:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_address;	// SystemBus.scala:24:26
  wire [63:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_data;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_corrupt;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_e_valid;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_e_bits_sink;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_valid;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_opcode;	// SystemBus.scala:24:26
  wire [1:0]  subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_param;	// SystemBus.scala:24:26
  wire [3:0]  subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_size;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_sink;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_denied;	// SystemBus.scala:24:26
  wire [63:0] subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_data;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_corrupt;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode;	// SystemBus.scala:24:26
  wire [2:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param;	// SystemBus.scala:24:26
  wire [3:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size;	// SystemBus.scala:24:26
  wire [6:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source;	// SystemBus.scala:24:26
  wire [30:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address;	// SystemBus.scala:24:26
  wire [7:0]  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask;	// SystemBus.scala:24:26
  wire [63:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_6_clock;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_6_reset;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_5_clock;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_5_reset;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_4_clock;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_4_reset;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_3_clock;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_3_reset;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_2_clock;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_2_reset;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_1_clock;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_1_reset;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_0_clock;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_fixedClockNode_out_0_reset;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_subsystem_sbus_clock_groups_out_member_subsystem_l2_0_clock;	// SystemBus.scala:24:26
  wire        subsystem_sbus_auto_subsystem_sbus_clock_groups_out_member_subsystem_l2_0_reset;	// SystemBus.scala:24:26
  wire        subsystem_sbus_clock;	// SystemBus.scala:24:26
  wire        subsystem_sbus_reset;	// SystemBus.scala:24:26
  wire        ibus_auto_int_bus_int_out_0;	// BaseSubsystem.scala:50:24
  wire        ibus_clock;	// BaseSubsystem.scala:50:24
  wire        ibus_reset;	// BaseSubsystem.scala:50:24
  wire        _GEN;	// Counter.scala:60:40
  reg  [6:0]  int_rtc_tick_value;	// Counter.scala:60:40

  `ifndef SYNTHESIS	// Counter.scala:60:40
    `ifdef RANDOMIZE_REG_INIT	// Counter.scala:60:40
      reg [31:0] _RANDOM;	// Counter.scala:60:40

    `endif
    initial begin	// Counter.scala:60:40
      `INIT_RANDOM_PROLOG_	// Counter.scala:60:40
      `ifdef RANDOMIZE_REG_INIT	// Counter.scala:60:40
        _RANDOM = `RANDOM;	// Counter.scala:60:40
        int_rtc_tick_value = _RANDOM[6:0];	// Counter.scala:60:40
      `endif
    end // initial
  `endif
      wire int_rtc_tick_wrap_wrap = int_rtc_tick_value == 7'h63;	// Counter.scala:72:24
  assign _GEN = subsystem_pbus_clock;	// Counter.scala:60:40, PeripheryBus.scala:31:26
  always @(posedge _GEN) begin	// Counter.scala:60:40
    if (subsystem_pbus_reset)	// Counter.scala:60:40, PeripheryBus.scala:31:26
      int_rtc_tick_value <= 7'h0;	// Counter.scala:60:40
    else	// Counter.scala:60:40, PeripheryBus.scala:31:26
      int_rtc_tick_value <= int_rtc_tick_wrap_wrap ? 7'h0 : int_rtc_tick_value + 7'h1;	// Counter.scala:60:40, :72:24, :76:24, :86:28
  end // always @(posedge)
  InterruptBusWrapper ibus (	// BaseSubsystem.scala:50:24
    .auto_int_bus_int_in_0  (intsink_24_auto_out_0),	// Crossing.scala:94:29
    .auto_clock_in_clock    (subsystem_sbus_auto_fixedClockNode_out_0_clock),	// SystemBus.scala:24:26
    .auto_clock_in_reset    (subsystem_sbus_auto_fixedClockNode_out_0_reset),	// SystemBus.scala:24:26
    .auto_int_bus_int_out_0 (ibus_auto_int_bus_int_out_0),
    .clock                  (ibus_clock),
    .reset                  (ibus_reset)
  );
  SystemBus subsystem_sbus (	// SystemBus.scala:24:26
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_valid         (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_bits_opcode   (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_opcode),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_bits_param    (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_param),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_bits_size     (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_size),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_bits_source   (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_source),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_bits_address  (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_address),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_bits_mask     (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_mask),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_bits_data     (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_data),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_bits_corrupt  (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_corrupt),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_ready         (tile_prci_domain_5_auto_tl_master_clock_xing_out_b_ready),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_c_valid         (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_c_bits_opcode   (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_opcode),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_c_bits_param    (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_param),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_c_bits_size     (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_size),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_c_bits_source   (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_source),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_c_bits_address  (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_address),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_c_bits_data     (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_data),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_c_bits_corrupt  (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_corrupt),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_ready         (tile_prci_domain_5_auto_tl_master_clock_xing_out_d_ready),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_e_valid         (tile_prci_domain_5_auto_tl_master_clock_xing_out_e_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_e_bits_sink     (tile_prci_domain_5_auto_tl_master_clock_xing_out_e_bits_sink),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_valid         (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_bits_opcode   (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_opcode),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_bits_param    (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_param),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_bits_size     (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_size),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_bits_source   (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_source),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_bits_address  (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_address),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_bits_mask     (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_mask),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_bits_data     (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_data),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_bits_corrupt  (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_corrupt),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_ready         (tile_prci_domain_4_auto_tl_master_clock_xing_out_b_ready),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_c_valid         (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_c_bits_opcode   (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_opcode),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_c_bits_param    (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_param),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_c_bits_size     (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_size),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_c_bits_source   (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_source),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_c_bits_address  (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_address),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_c_bits_data     (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_data),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_c_bits_corrupt  (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_corrupt),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_ready         (tile_prci_domain_4_auto_tl_master_clock_xing_out_d_ready),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_e_valid         (tile_prci_domain_4_auto_tl_master_clock_xing_out_e_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_e_bits_sink     (tile_prci_domain_4_auto_tl_master_clock_xing_out_e_bits_sink),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_valid         (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_bits_opcode   (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_opcode),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_bits_param    (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_param),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_bits_size     (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_size),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_bits_source   (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_source),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_bits_address  (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_address),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_bits_mask     (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_mask),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_bits_data     (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_data),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_bits_corrupt  (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_corrupt),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_ready         (tile_prci_domain_3_auto_tl_master_clock_xing_out_b_ready),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_c_valid         (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_c_bits_opcode   (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_opcode),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_c_bits_param    (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_param),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_c_bits_size     (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_size),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_c_bits_source   (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_source),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_c_bits_address  (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_address),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_c_bits_data     (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_data),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_c_bits_corrupt  (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_corrupt),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_ready         (tile_prci_domain_3_auto_tl_master_clock_xing_out_d_ready),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_e_valid         (tile_prci_domain_3_auto_tl_master_clock_xing_out_e_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_e_bits_sink     (tile_prci_domain_3_auto_tl_master_clock_xing_out_e_bits_sink),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_a_valid              (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_a_bits_opcode        (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_opcode),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_a_bits_param         (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_param),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_a_bits_size          (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_size),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_a_bits_source        (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_source),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_a_bits_address       (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_address),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_a_bits_mask          (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_mask),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_a_bits_data          (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_data),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_a_bits_corrupt       (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_corrupt),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_b_ready              (tile_prci_domain_2_auto_tl_master_clock_xing_out_b_ready),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_c_valid              (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_c_bits_opcode        (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_opcode),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_c_bits_param         (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_param),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_c_bits_size          (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_size),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_c_bits_source        (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_source),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_c_bits_address       (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_address),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_c_bits_data          (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_data),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_c_bits_corrupt       (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_corrupt),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_d_ready              (tile_prci_domain_2_auto_tl_master_clock_xing_out_d_ready),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_e_valid              (tile_prci_domain_2_auto_tl_master_clock_xing_out_e_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_e_bits_sink          (tile_prci_domain_2_auto_tl_master_clock_xing_out_e_bits_sink),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_a_valid              (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_a_bits_opcode        (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_opcode),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_a_bits_param         (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_param),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_a_bits_size          (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_size),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_a_bits_source        (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_source),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_a_bits_address       (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_address),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_a_bits_mask          (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_mask),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_a_bits_data          (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_data),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_a_bits_corrupt       (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_corrupt),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_b_ready              (tile_prci_domain_1_auto_tl_master_clock_xing_out_b_ready),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_c_valid              (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_c_bits_opcode        (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_opcode),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_c_bits_param         (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_param),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_c_bits_size          (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_size),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_c_bits_source        (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_source),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_c_bits_address       (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_address),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_c_bits_data          (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_data),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_c_bits_corrupt       (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_corrupt),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_d_ready              (tile_prci_domain_1_auto_tl_master_clock_xing_out_d_ready),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_e_valid              (tile_prci_domain_1_auto_tl_master_clock_xing_out_e_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_e_bits_sink          (tile_prci_domain_1_auto_tl_master_clock_xing_out_e_bits_sink),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_a_valid              (tile_prci_domain_auto_tl_master_clock_xing_out_a_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_a_bits_opcode        (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_a_bits_param         (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_a_bits_size          (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_a_bits_source        (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_a_bits_address       (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_a_bits_mask          (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_a_bits_data          (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_a_bits_corrupt       (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_b_ready              (tile_prci_domain_auto_tl_master_clock_xing_out_b_ready),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_c_valid              (tile_prci_domain_auto_tl_master_clock_xing_out_c_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_c_bits_opcode        (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_c_bits_param         (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_c_bits_size          (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_c_bits_source        (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_c_bits_address       (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_c_bits_data          (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_c_bits_corrupt       (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_d_ready              (tile_prci_domain_auto_tl_master_clock_xing_out_d_ready),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_e_valid              (tile_prci_domain_auto_tl_master_clock_xing_out_e_valid),	// HasTiles.scala:252:38
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_e_bits_sink          (tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink),	// HasTiles.scala:252:38
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_ready             (subsystem_l2_wrapper_auto_coherent_jbar_in_a_ready),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_b_valid             (subsystem_l2_wrapper_auto_coherent_jbar_in_b_valid),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_param        (subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_param),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_source       (subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_source),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_address      (subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_address),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_ready             (subsystem_l2_wrapper_auto_coherent_jbar_in_c_ready),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_valid             (subsystem_l2_wrapper_auto_coherent_jbar_in_d_valid),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_opcode       (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_opcode),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_param        (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_param),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_size         (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_size),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_source       (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_source),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_sink         (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_sink),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_denied       (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_denied),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_data         (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_data),	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_corrupt      (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_corrupt),	// BankedL2Params.scala:47:31
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_valid        (subsystem_fbus_auto_bus_xing_out_a_valid),	// FrontBus.scala:22:26
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_opcode  (subsystem_fbus_auto_bus_xing_out_a_bits_opcode),	// FrontBus.scala:22:26
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_param   (subsystem_fbus_auto_bus_xing_out_a_bits_param),	// FrontBus.scala:22:26
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_size    (subsystem_fbus_auto_bus_xing_out_a_bits_size),	// FrontBus.scala:22:26
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_source  (subsystem_fbus_auto_bus_xing_out_a_bits_source),	// FrontBus.scala:22:26
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_address (subsystem_fbus_auto_bus_xing_out_a_bits_address),	// FrontBus.scala:22:26
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_mask    (subsystem_fbus_auto_bus_xing_out_a_bits_mask),	// FrontBus.scala:22:26
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_data    (subsystem_fbus_auto_bus_xing_out_a_bits_data),	// FrontBus.scala:22:26
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_corrupt (subsystem_fbus_auto_bus_xing_out_a_bits_corrupt),	// FrontBus.scala:22:26
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_ready        (subsystem_fbus_auto_bus_xing_out_d_ready),	// FrontBus.scala:22:26
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready         (subsystem_cbus_auto_bus_xing_in_a_ready),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid         (subsystem_cbus_auto_bus_xing_in_d_valid),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode   (subsystem_cbus_auto_bus_xing_in_d_bits_opcode),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param    (subsystem_cbus_auto_bus_xing_in_d_bits_param),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size     (subsystem_cbus_auto_bus_xing_in_d_bits_size),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source   (subsystem_cbus_auto_bus_xing_in_d_bits_source),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink     (subsystem_cbus_auto_bus_xing_in_d_bits_sink),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied   (subsystem_cbus_auto_bus_xing_in_d_bits_denied),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data     (subsystem_cbus_auto_bus_xing_in_d_bits_data),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt  (subsystem_cbus_auto_bus_xing_in_d_bits_corrupt),	// PeripheryBus.scala:31:26
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_clock     (auto_subsystem_sbus_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_clock),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_reset     (auto_subsystem_sbus_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_reset),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock     (auto_subsystem_sbus_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset     (auto_subsystem_sbus_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_ready         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_ready),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_valid         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_valid),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_bits_param    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_bits_param),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_bits_source   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_bits_source),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_bits_address  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_bits_address),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_c_ready         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_c_ready),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_valid         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_valid),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_opcode   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_opcode),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_param    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_param),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_size     (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_size),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_source   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_source),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_sink     (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_sink),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_denied   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_denied),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_data     (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_data),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_corrupt  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_corrupt),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_e_ready         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_e_ready),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_ready         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_ready),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_valid         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_valid),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_bits_param    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_bits_param),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_bits_source   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_bits_source),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_bits_address  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_bits_address),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_c_ready         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_c_ready),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_valid         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_valid),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_opcode   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_opcode),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_param    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_param),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_size     (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_size),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_source   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_source),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_sink     (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_sink),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_denied   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_denied),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_data     (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_data),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_corrupt  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_corrupt),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_e_ready         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_e_ready),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_ready         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_ready),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_valid         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_valid),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_bits_param    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_bits_param),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_bits_source   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_bits_source),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_bits_address  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_bits_address),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_c_ready         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_c_ready),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_valid         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_valid),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_opcode   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_opcode),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_param    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_param),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_size     (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_size),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_source   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_source),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_sink     (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_sink),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_denied   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_denied),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_data     (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_data),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_corrupt  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_corrupt),
    .auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_e_ready         (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_e_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_a_ready              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_a_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_b_valid              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_b_valid),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_b_bits_param         (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_b_bits_param),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_b_bits_source        (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_b_bits_source),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_b_bits_address       (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_b_bits_address),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_c_ready              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_c_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_d_valid              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_valid),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_opcode        (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_opcode),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_param         (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_param),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_size          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_size),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_source        (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_source),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_sink          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_sink),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_denied        (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_denied),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_data          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_data),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_corrupt       (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_corrupt),
    .auto_coupler_from_tile_tl_master_clock_xing_in_2_e_ready              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_e_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_a_ready              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_a_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_b_valid              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_b_valid),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_b_bits_param         (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_b_bits_param),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_b_bits_source        (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_b_bits_source),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_b_bits_address       (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_b_bits_address),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_c_ready              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_c_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_d_valid              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_valid),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_opcode        (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_opcode),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_param         (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_param),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_size          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_size),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_source        (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_source),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_sink          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_sink),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_denied        (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_denied),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_data          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_data),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_corrupt       (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_corrupt),
    .auto_coupler_from_tile_tl_master_clock_xing_in_1_e_ready              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_e_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_a_ready              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_a_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_b_valid              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_b_valid),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_b_bits_param         (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_b_bits_param),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_b_bits_source        (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_b_bits_source),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_b_bits_address       (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_b_bits_address),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_c_ready              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_c_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_d_valid              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_valid),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_opcode        (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_opcode),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_param         (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_param),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_size          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_size),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_source        (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_source),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_sink          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_sink),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_denied        (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_denied),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_data          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_data),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_corrupt       (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_corrupt),
    .auto_coupler_from_tile_tl_master_clock_xing_in_0_e_ready              (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_e_ready),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_valid             (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_valid),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_opcode       (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_param        (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_param),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_size         (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_size),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_source       (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_source),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_address      (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_address),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_mask         (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_mask),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_data         (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_data),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_corrupt      (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_corrupt),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_b_ready             (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_ready),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_valid             (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_valid),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_opcode       (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_param        (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_param),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_size         (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_size),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_source       (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_source),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_address      (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_address),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_data         (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_data),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_corrupt      (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_corrupt),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_ready             (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_ready),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_e_valid             (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_e_valid),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_e_bits_sink         (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_e_bits_sink),
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_ready        (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_ready),
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_valid        (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_valid),
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_opcode  (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_opcode),
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_param   (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_param),
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_size    (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_size),
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_sink    (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_sink),
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_denied  (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_denied),
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_data    (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_data),
    .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_corrupt (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_corrupt),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid         (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode   (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param    (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size     (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source   (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address  (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask     (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data     (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt  (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready         (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready),
    .auto_fixedClockNode_out_6_clock                                       (subsystem_sbus_auto_fixedClockNode_out_6_clock),
    .auto_fixedClockNode_out_6_reset                                       (subsystem_sbus_auto_fixedClockNode_out_6_reset),
    .auto_fixedClockNode_out_5_clock                                       (subsystem_sbus_auto_fixedClockNode_out_5_clock),
    .auto_fixedClockNode_out_5_reset                                       (subsystem_sbus_auto_fixedClockNode_out_5_reset),
    .auto_fixedClockNode_out_4_clock                                       (subsystem_sbus_auto_fixedClockNode_out_4_clock),
    .auto_fixedClockNode_out_4_reset                                       (subsystem_sbus_auto_fixedClockNode_out_4_reset),
    .auto_fixedClockNode_out_3_clock                                       (subsystem_sbus_auto_fixedClockNode_out_3_clock),
    .auto_fixedClockNode_out_3_reset                                       (subsystem_sbus_auto_fixedClockNode_out_3_reset),
    .auto_fixedClockNode_out_2_clock                                       (subsystem_sbus_auto_fixedClockNode_out_2_clock),
    .auto_fixedClockNode_out_2_reset                                       (subsystem_sbus_auto_fixedClockNode_out_2_reset),
    .auto_fixedClockNode_out_1_clock                                       (subsystem_sbus_auto_fixedClockNode_out_1_clock),
    .auto_fixedClockNode_out_1_reset                                       (subsystem_sbus_auto_fixedClockNode_out_1_reset),
    .auto_fixedClockNode_out_0_clock                                       (subsystem_sbus_auto_fixedClockNode_out_0_clock),
    .auto_fixedClockNode_out_0_reset                                       (subsystem_sbus_auto_fixedClockNode_out_0_reset),
    .auto_subsystem_sbus_clock_groups_out_member_subsystem_l2_0_clock      (subsystem_sbus_auto_subsystem_sbus_clock_groups_out_member_subsystem_l2_0_clock),
    .auto_subsystem_sbus_clock_groups_out_member_subsystem_l2_0_reset      (subsystem_sbus_auto_subsystem_sbus_clock_groups_out_member_subsystem_l2_0_reset),
    .clock                                                                 (subsystem_sbus_clock),
    .reset                                                                 (subsystem_sbus_reset)
  );
  PeripheryBus subsystem_pbus (	// PeripheryBus.scala:31:26
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_ready        (domain_1_auto_resetCtrl_in_a_ready),	// TileResetCtrl.scala:23:34
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_d_valid        (domain_1_auto_resetCtrl_in_d_valid),	// TileResetCtrl.scala:23:34
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_d_bits_opcode  (domain_1_auto_resetCtrl_in_d_bits_opcode),	// TileResetCtrl.scala:23:34
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_d_bits_size    (domain_1_auto_resetCtrl_in_d_bits_size),	// TileResetCtrl.scala:23:34
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_d_bits_source  (domain_1_auto_resetCtrl_in_d_bits_source),	// TileResetCtrl.scala:23:34
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_d_bits_data    (domain_1_auto_resetCtrl_in_d_bits_data),	// TileResetCtrl.scala:23:34
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_ready        (uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready),	// UART.scala:242:44
    .auto_coupler_to_device_named_uart_0_control_xing_out_d_valid        (uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid),	// UART.scala:242:44
    .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode  (uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode),	// UART.scala:242:44
    .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size    (uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size),	// UART.scala:242:44
    .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source  (uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source),	// UART.scala:242:44
    .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data    (uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data),	// UART.scala:242:44
    .auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock   (auto_subsystem_pbus_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock),
    .auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset   (auto_subsystem_pbus_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset),
    .auto_bus_xing_in_a_valid                                            (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid),	// PeripheryBus.scala:31:26
    .auto_bus_xing_in_a_bits_opcode                                      (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode),	// PeripheryBus.scala:31:26
    .auto_bus_xing_in_a_bits_param                                       (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param),	// PeripheryBus.scala:31:26
    .auto_bus_xing_in_a_bits_size                                        (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size),	// PeripheryBus.scala:31:26
    .auto_bus_xing_in_a_bits_source                                      (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source),	// PeripheryBus.scala:31:26
    .auto_bus_xing_in_a_bits_address                                     (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address),	// PeripheryBus.scala:31:26
    .auto_bus_xing_in_a_bits_mask                                        (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask),	// PeripheryBus.scala:31:26
    .auto_bus_xing_in_a_bits_data                                        (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data),	// PeripheryBus.scala:31:26
    .auto_bus_xing_in_a_bits_corrupt                                     (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt),	// PeripheryBus.scala:31:26
    .auto_bus_xing_in_d_ready                                            (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready),	// PeripheryBus.scala:31:26
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_valid        (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_valid),
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_opcode  (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_opcode),
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_param   (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_param),
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_size    (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_size),
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_source  (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_source),
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_address (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_address),
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_mask    (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_mask),
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_data    (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_data),
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_corrupt (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_corrupt),
    .auto_coupler_to_slave_named_tileresetctrl_buffer_out_d_ready        (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_d_ready),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_valid        (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode  (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param   (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size    (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source  (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask    (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data    (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_uart_0_control_xing_out_d_ready        (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready),
    .auto_fixedClockNode_out_1_clock                                     (subsystem_pbus_auto_fixedClockNode_out_1_clock),
    .auto_fixedClockNode_out_1_reset                                     (subsystem_pbus_auto_fixedClockNode_out_1_reset),
    .auto_fixedClockNode_out_0_clock                                     (subsystem_pbus_auto_fixedClockNode_out_0_clock),
    .auto_fixedClockNode_out_0_reset                                     (subsystem_pbus_auto_fixedClockNode_out_0_reset),
    .auto_bus_xing_in_a_ready                                            (subsystem_pbus_auto_bus_xing_in_a_ready),
    .auto_bus_xing_in_d_valid                                            (subsystem_pbus_auto_bus_xing_in_d_valid),
    .auto_bus_xing_in_d_bits_opcode                                      (subsystem_pbus_auto_bus_xing_in_d_bits_opcode),
    .auto_bus_xing_in_d_bits_param                                       (subsystem_pbus_auto_bus_xing_in_d_bits_param),
    .auto_bus_xing_in_d_bits_size                                        (subsystem_pbus_auto_bus_xing_in_d_bits_size),
    .auto_bus_xing_in_d_bits_source                                      (subsystem_pbus_auto_bus_xing_in_d_bits_source),
    .auto_bus_xing_in_d_bits_sink                                        (subsystem_pbus_auto_bus_xing_in_d_bits_sink),
    .auto_bus_xing_in_d_bits_denied                                      (subsystem_pbus_auto_bus_xing_in_d_bits_denied),
    .auto_bus_xing_in_d_bits_data                                        (subsystem_pbus_auto_bus_xing_in_d_bits_data),
    .auto_bus_xing_in_d_bits_corrupt                                     (subsystem_pbus_auto_bus_xing_in_d_bits_corrupt),
    .clock                                                               (subsystem_pbus_clock),
    .reset                                                               (subsystem_pbus_reset)
  );
  FrontBus subsystem_fbus (	// FrontBus.scala:22:26
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_valid        (domain_auto_serdesser_client_out_a_valid),	// SerialAdapter.scala:373:28
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_opcode  (domain_auto_serdesser_client_out_a_bits_opcode),	// SerialAdapter.scala:373:28
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_param   (domain_auto_serdesser_client_out_a_bits_param),	// SerialAdapter.scala:373:28
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_size    (domain_auto_serdesser_client_out_a_bits_size),	// SerialAdapter.scala:373:28
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_source  (domain_auto_serdesser_client_out_a_bits_source),	// SerialAdapter.scala:373:28
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_address (domain_auto_serdesser_client_out_a_bits_address),	// SerialAdapter.scala:373:28
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_mask    (domain_auto_serdesser_client_out_a_bits_mask),	// SerialAdapter.scala:373:28
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_data    (domain_auto_serdesser_client_out_a_bits_data),	// SerialAdapter.scala:373:28
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_corrupt (domain_auto_serdesser_client_out_a_bits_corrupt),	// SerialAdapter.scala:373:28
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_ready        (domain_auto_serdesser_client_out_d_ready),	// SerialAdapter.scala:373:28
    .auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock    (auto_subsystem_fbus_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock),
    .auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset    (auto_subsystem_fbus_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset),
    .auto_bus_xing_out_a_ready                                            (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_ready),	// SystemBus.scala:24:26
    .auto_bus_xing_out_d_valid                                            (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_valid),	// SystemBus.scala:24:26
    .auto_bus_xing_out_d_bits_opcode                                      (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_opcode),	// SystemBus.scala:24:26
    .auto_bus_xing_out_d_bits_param                                       (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_param),	// SystemBus.scala:24:26
    .auto_bus_xing_out_d_bits_size                                        (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_size),	// SystemBus.scala:24:26
    .auto_bus_xing_out_d_bits_sink                                        (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_sink),	// SystemBus.scala:24:26
    .auto_bus_xing_out_d_bits_denied                                      (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_denied),	// SystemBus.scala:24:26
    .auto_bus_xing_out_d_bits_data                                        (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_data),	// SystemBus.scala:24:26
    .auto_bus_xing_out_d_bits_corrupt                                     (subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_corrupt),	// SystemBus.scala:24:26
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_ready        (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_ready),
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_valid        (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_valid),
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_opcode  (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_opcode),
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_param   (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_param),
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_size    (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_size),
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_source  (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_source),
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_sink    (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_sink),
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_denied  (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_denied),
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_data    (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_data),
    .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_corrupt (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_corrupt),
    .auto_fixedClockNode_out_clock                                        (subsystem_fbus_auto_fixedClockNode_out_clock),
    .auto_fixedClockNode_out_reset                                        (subsystem_fbus_auto_fixedClockNode_out_reset),
    .auto_bus_xing_out_a_valid                                            (subsystem_fbus_auto_bus_xing_out_a_valid),
    .auto_bus_xing_out_a_bits_opcode                                      (subsystem_fbus_auto_bus_xing_out_a_bits_opcode),
    .auto_bus_xing_out_a_bits_param                                       (subsystem_fbus_auto_bus_xing_out_a_bits_param),
    .auto_bus_xing_out_a_bits_size                                        (subsystem_fbus_auto_bus_xing_out_a_bits_size),
    .auto_bus_xing_out_a_bits_source                                      (subsystem_fbus_auto_bus_xing_out_a_bits_source),
    .auto_bus_xing_out_a_bits_address                                     (subsystem_fbus_auto_bus_xing_out_a_bits_address),
    .auto_bus_xing_out_a_bits_mask                                        (subsystem_fbus_auto_bus_xing_out_a_bits_mask),
    .auto_bus_xing_out_a_bits_data                                        (subsystem_fbus_auto_bus_xing_out_a_bits_data),
    .auto_bus_xing_out_a_bits_corrupt                                     (subsystem_fbus_auto_bus_xing_out_a_bits_corrupt),
    .auto_bus_xing_out_d_ready                                            (subsystem_fbus_auto_bus_xing_out_d_ready),
    .clock                                                                (subsystem_fbus_clock),
    .reset                                                                (subsystem_fbus_reset)
  );
  PeripheryBus_1 subsystem_cbus (	// PeripheryBus.scala:31:26
    .auto_coupler_to_bootrom_fragmenter_out_a_ready                       (bootROMDomainWrapper_auto_bootrom_in_a_ready),	// BootROM.scala:70:42
    .auto_coupler_to_bootrom_fragmenter_out_d_valid                       (bootROMDomainWrapper_auto_bootrom_in_d_valid),	// BootROM.scala:70:42
    .auto_coupler_to_bootrom_fragmenter_out_d_bits_size                   (bootROMDomainWrapper_auto_bootrom_in_d_bits_size),	// BootROM.scala:70:42
    .auto_coupler_to_bootrom_fragmenter_out_d_bits_source                 (bootROMDomainWrapper_auto_bootrom_in_d_bits_source),	// BootROM.scala:70:42
    .auto_coupler_to_bootrom_fragmenter_out_d_bits_data                   (bootROMDomainWrapper_auto_bootrom_in_d_bits_data),	// BootROM.scala:70:42
    .auto_coupler_to_debug_fragmenter_out_a_ready                         (debug_1_auto_dmInner_dmInner_tl_in_a_ready),	// Periphery.scala:84:27
    .auto_coupler_to_debug_fragmenter_out_d_valid                         (debug_1_auto_dmInner_dmInner_tl_in_d_valid),	// Periphery.scala:84:27
    .auto_coupler_to_debug_fragmenter_out_d_bits_opcode                   (debug_1_auto_dmInner_dmInner_tl_in_d_bits_opcode),	// Periphery.scala:84:27
    .auto_coupler_to_debug_fragmenter_out_d_bits_size                     (debug_1_auto_dmInner_dmInner_tl_in_d_bits_size),	// Periphery.scala:84:27
    .auto_coupler_to_debug_fragmenter_out_d_bits_source                   (debug_1_auto_dmInner_dmInner_tl_in_d_bits_source),	// Periphery.scala:84:27
    .auto_coupler_to_debug_fragmenter_out_d_bits_data                     (debug_1_auto_dmInner_dmInner_tl_in_d_bits_data),	// Periphery.scala:84:27
    .auto_coupler_to_clint_fragmenter_out_a_ready                         (clint_auto_in_a_ready),	// CLINT.scala:109:27
    .auto_coupler_to_clint_fragmenter_out_d_valid                         (clint_auto_in_d_valid),	// CLINT.scala:109:27
    .auto_coupler_to_clint_fragmenter_out_d_bits_opcode                   (clint_auto_in_d_bits_opcode),	// CLINT.scala:109:27
    .auto_coupler_to_clint_fragmenter_out_d_bits_size                     (clint_auto_in_d_bits_size),	// CLINT.scala:109:27
    .auto_coupler_to_clint_fragmenter_out_d_bits_source                   (clint_auto_in_d_bits_source),	// CLINT.scala:109:27
    .auto_coupler_to_clint_fragmenter_out_d_bits_data                     (clint_auto_in_d_bits_data),	// CLINT.scala:109:27
    .auto_coupler_to_plic_fragmenter_out_a_ready                          (plicDomainWrapper_auto_plic_in_a_ready),	// Plic.scala:359:39
    .auto_coupler_to_plic_fragmenter_out_d_valid                          (plicDomainWrapper_auto_plic_in_d_valid),	// Plic.scala:359:39
    .auto_coupler_to_plic_fragmenter_out_d_bits_opcode                    (plicDomainWrapper_auto_plic_in_d_bits_opcode),	// Plic.scala:359:39
    .auto_coupler_to_plic_fragmenter_out_d_bits_size                      (plicDomainWrapper_auto_plic_in_d_bits_size),	// Plic.scala:359:39
    .auto_coupler_to_plic_fragmenter_out_d_bits_source                    (plicDomainWrapper_auto_plic_in_d_bits_source),	// Plic.scala:359:39
    .auto_coupler_to_plic_fragmenter_out_d_bits_data                      (plicDomainWrapper_auto_plic_in_d_bits_data),	// Plic.scala:359:39
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready        (subsystem_pbus_auto_bus_xing_in_a_ready),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid        (subsystem_pbus_auto_bus_xing_in_d_valid),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode  (subsystem_pbus_auto_bus_xing_in_d_bits_opcode),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param   (subsystem_pbus_auto_bus_xing_in_d_bits_param),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size    (subsystem_pbus_auto_bus_xing_in_d_bits_size),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source  (subsystem_pbus_auto_bus_xing_in_d_bits_source),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink    (subsystem_pbus_auto_bus_xing_in_d_bits_sink),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied  (subsystem_pbus_auto_bus_xing_in_d_bits_denied),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data    (subsystem_pbus_auto_bus_xing_in_d_bits_data),	// PeripheryBus.scala:31:26
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt (subsystem_pbus_auto_bus_xing_in_d_bits_corrupt),	// PeripheryBus.scala:31:26
    .auto_coupler_to_l2_ctrl_buffer_out_a_ready                           (subsystem_l2_wrapper_auto_l2_ctl_in_a_ready),	// BankedL2Params.scala:47:31
    .auto_coupler_to_l2_ctrl_buffer_out_d_valid                           (subsystem_l2_wrapper_auto_l2_ctl_in_d_valid),	// BankedL2Params.scala:47:31
    .auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode                     (subsystem_l2_wrapper_auto_l2_ctl_in_d_bits_opcode),	// BankedL2Params.scala:47:31
    .auto_coupler_to_l2_ctrl_buffer_out_d_bits_size                       (subsystem_l2_wrapper_auto_l2_ctl_in_d_bits_size),	// BankedL2Params.scala:47:31
    .auto_coupler_to_l2_ctrl_buffer_out_d_bits_source                     (subsystem_l2_wrapper_auto_l2_ctl_in_d_bits_source),	// BankedL2Params.scala:47:31
    .auto_coupler_to_l2_ctrl_buffer_out_d_bits_data                       (subsystem_l2_wrapper_auto_l2_ctl_in_d_bits_data),	// BankedL2Params.scala:47:31
    .auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock    (auto_subsystem_cbus_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock),
    .auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset    (auto_subsystem_cbus_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset),
    .auto_bus_xing_in_a_valid                                             (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid),	// SystemBus.scala:24:26
    .auto_bus_xing_in_a_bits_opcode                                       (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode),	// SystemBus.scala:24:26
    .auto_bus_xing_in_a_bits_param                                        (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param),	// SystemBus.scala:24:26
    .auto_bus_xing_in_a_bits_size                                         (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size),	// SystemBus.scala:24:26
    .auto_bus_xing_in_a_bits_source                                       (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source),	// SystemBus.scala:24:26
    .auto_bus_xing_in_a_bits_address                                      (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address),	// SystemBus.scala:24:26
    .auto_bus_xing_in_a_bits_mask                                         (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask),	// SystemBus.scala:24:26
    .auto_bus_xing_in_a_bits_data                                         (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data),	// SystemBus.scala:24:26
    .auto_bus_xing_in_a_bits_corrupt                                      (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt),	// SystemBus.scala:24:26
    .auto_bus_xing_in_d_ready                                             (subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready),	// SystemBus.scala:24:26
    .custom_boot                                                          (custom_boot),
    .auto_coupler_to_bootrom_fragmenter_out_a_valid                       (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_valid),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode                 (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_param                  (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_param),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_size                   (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_size),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_source                 (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_source),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_address                (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_address),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_mask                   (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_mask),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_data                   (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_data),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt                (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt),
    .auto_coupler_to_bootrom_fragmenter_out_d_ready                       (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_ready),
    .auto_coupler_to_debug_fragmenter_out_a_valid                         (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_valid),
    .auto_coupler_to_debug_fragmenter_out_a_bits_opcode                   (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_opcode),
    .auto_coupler_to_debug_fragmenter_out_a_bits_param                    (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_param),
    .auto_coupler_to_debug_fragmenter_out_a_bits_size                     (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_size),
    .auto_coupler_to_debug_fragmenter_out_a_bits_source                   (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_source),
    .auto_coupler_to_debug_fragmenter_out_a_bits_address                  (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_address),
    .auto_coupler_to_debug_fragmenter_out_a_bits_mask                     (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_mask),
    .auto_coupler_to_debug_fragmenter_out_a_bits_data                     (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_data),
    .auto_coupler_to_debug_fragmenter_out_a_bits_corrupt                  (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_corrupt),
    .auto_coupler_to_debug_fragmenter_out_d_ready                         (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_ready),
    .auto_coupler_to_clint_fragmenter_out_a_valid                         (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_valid),
    .auto_coupler_to_clint_fragmenter_out_a_bits_opcode                   (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_opcode),
    .auto_coupler_to_clint_fragmenter_out_a_bits_param                    (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_param),
    .auto_coupler_to_clint_fragmenter_out_a_bits_size                     (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_size),
    .auto_coupler_to_clint_fragmenter_out_a_bits_source                   (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_source),
    .auto_coupler_to_clint_fragmenter_out_a_bits_address                  (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_address),
    .auto_coupler_to_clint_fragmenter_out_a_bits_mask                     (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_mask),
    .auto_coupler_to_clint_fragmenter_out_a_bits_data                     (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_data),
    .auto_coupler_to_clint_fragmenter_out_a_bits_corrupt                  (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_corrupt),
    .auto_coupler_to_clint_fragmenter_out_d_ready                         (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_ready),
    .auto_coupler_to_plic_fragmenter_out_a_valid                          (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_valid),
    .auto_coupler_to_plic_fragmenter_out_a_bits_opcode                    (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_opcode),
    .auto_coupler_to_plic_fragmenter_out_a_bits_param                     (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_param),
    .auto_coupler_to_plic_fragmenter_out_a_bits_size                      (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_size),
    .auto_coupler_to_plic_fragmenter_out_a_bits_source                    (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_source),
    .auto_coupler_to_plic_fragmenter_out_a_bits_address                   (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_address),
    .auto_coupler_to_plic_fragmenter_out_a_bits_mask                      (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_mask),
    .auto_coupler_to_plic_fragmenter_out_a_bits_data                      (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_data),
    .auto_coupler_to_plic_fragmenter_out_a_bits_corrupt                   (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_corrupt),
    .auto_coupler_to_plic_fragmenter_out_d_ready                          (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_ready),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid        (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode  (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param   (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size    (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source  (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask    (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data    (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready        (subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready),
    .auto_coupler_to_l2_ctrl_buffer_out_a_valid                           (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid),
    .auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode                     (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode),
    .auto_coupler_to_l2_ctrl_buffer_out_a_bits_param                      (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param),
    .auto_coupler_to_l2_ctrl_buffer_out_a_bits_size                       (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size),
    .auto_coupler_to_l2_ctrl_buffer_out_a_bits_source                     (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source),
    .auto_coupler_to_l2_ctrl_buffer_out_a_bits_address                    (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address),
    .auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask                       (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask),
    .auto_coupler_to_l2_ctrl_buffer_out_a_bits_data                       (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data),
    .auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt                    (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt),
    .auto_coupler_to_l2_ctrl_buffer_out_d_ready                           (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready),
    .auto_fixedClockNode_out_3_clock                                      (auto_subsystem_cbus_fixedClockNode_out_clock),
    .auto_fixedClockNode_out_3_reset                                      (auto_subsystem_cbus_fixedClockNode_out_reset),
    .auto_fixedClockNode_out_2_clock                                      (subsystem_cbus_auto_fixedClockNode_out_2_clock),
    .auto_fixedClockNode_out_2_reset                                      (subsystem_cbus_auto_fixedClockNode_out_2_reset),
    .auto_fixedClockNode_out_1_clock                                      (subsystem_cbus_auto_fixedClockNode_out_1_clock),
    .auto_fixedClockNode_out_1_reset                                      (subsystem_cbus_auto_fixedClockNode_out_1_reset),
    .auto_fixedClockNode_out_0_clock                                      (subsystem_cbus_auto_fixedClockNode_out_0_clock),
    .auto_fixedClockNode_out_0_reset                                      (subsystem_cbus_auto_fixedClockNode_out_0_reset),
    .auto_bus_xing_in_a_ready                                             (subsystem_cbus_auto_bus_xing_in_a_ready),
    .auto_bus_xing_in_d_valid                                             (subsystem_cbus_auto_bus_xing_in_d_valid),
    .auto_bus_xing_in_d_bits_opcode                                       (subsystem_cbus_auto_bus_xing_in_d_bits_opcode),
    .auto_bus_xing_in_d_bits_param                                        (subsystem_cbus_auto_bus_xing_in_d_bits_param),
    .auto_bus_xing_in_d_bits_size                                         (subsystem_cbus_auto_bus_xing_in_d_bits_size),
    .auto_bus_xing_in_d_bits_source                                       (subsystem_cbus_auto_bus_xing_in_d_bits_source),
    .auto_bus_xing_in_d_bits_sink                                         (subsystem_cbus_auto_bus_xing_in_d_bits_sink),
    .auto_bus_xing_in_d_bits_denied                                       (subsystem_cbus_auto_bus_xing_in_d_bits_denied),
    .auto_bus_xing_in_d_bits_data                                         (subsystem_cbus_auto_bus_xing_in_d_bits_data),
    .auto_bus_xing_in_d_bits_corrupt                                      (subsystem_cbus_auto_bus_xing_in_d_bits_corrupt),
    .clock                                                                (subsystem_cbus_clock),
    .reset                                                                (subsystem_cbus_reset)
  );
  MemoryBus subsystem_mbus (	// MemoryBus.scala:25:26
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_ready        (domain_auto_tlserial_manager_crossing_in_a_ready),	// SerialAdapter.scala:373:28
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_valid        (domain_auto_tlserial_manager_crossing_in_d_valid),	// SerialAdapter.scala:373:28
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_opcode  (domain_auto_tlserial_manager_crossing_in_d_bits_opcode),	// SerialAdapter.scala:373:28
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_param   (domain_auto_tlserial_manager_crossing_in_d_bits_param),	// SerialAdapter.scala:373:28
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_size    (domain_auto_tlserial_manager_crossing_in_d_bits_size),	// SerialAdapter.scala:373:28
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_source  (domain_auto_tlserial_manager_crossing_in_d_bits_source),	// SerialAdapter.scala:373:28
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_sink    (domain_auto_tlserial_manager_crossing_in_d_bits_sink),	// SerialAdapter.scala:373:28
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_denied  (domain_auto_tlserial_manager_crossing_in_d_bits_denied),	// SerialAdapter.scala:373:28
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_data    (domain_auto_tlserial_manager_crossing_in_d_bits_data),	// SerialAdapter.scala:373:28
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_corrupt (domain_auto_tlserial_manager_crossing_in_d_bits_corrupt),	// SerialAdapter.scala:373:28
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready               (mem_axi4_0_aw_ready),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready                (mem_axi4_0_w_ready),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid                (mem_axi4_0_b_valid),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id              (mem_axi4_0_b_bits_id),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp            (mem_axi4_0_b_bits_resp),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready               (mem_axi4_0_ar_ready),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid                (mem_axi4_0_r_valid),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id              (mem_axi4_0_r_bits_id),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data            (mem_axi4_0_r_bits_data),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp            (mem_axi4_0_r_bits_resp),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last            (mem_axi4_0_r_bits_last),
    .auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_clock                     (auto_subsystem_mbus_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_clock),
    .auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_reset                     (auto_subsystem_mbus_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_reset),
    .auto_bus_xing_in_a_valid                                                              (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_valid),	// BankedL2Params.scala:47:31
    .auto_bus_xing_in_a_bits_opcode                                                        (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_opcode),	// BankedL2Params.scala:47:31
    .auto_bus_xing_in_a_bits_param                                                         (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_param),	// BankedL2Params.scala:47:31
    .auto_bus_xing_in_a_bits_size                                                          (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_size),	// BankedL2Params.scala:47:31
    .auto_bus_xing_in_a_bits_source                                                        (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_source),	// BankedL2Params.scala:47:31
    .auto_bus_xing_in_a_bits_address                                                       (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_address),	// BankedL2Params.scala:47:31
    .auto_bus_xing_in_a_bits_mask                                                          (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_mask),	// BankedL2Params.scala:47:31
    .auto_bus_xing_in_a_bits_data                                                          (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_data),	// BankedL2Params.scala:47:31
    .auto_bus_xing_in_a_bits_corrupt                                                       (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_corrupt),	// BankedL2Params.scala:47:31
    .auto_bus_xing_in_d_ready                                                              (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_ready),	// BankedL2Params.scala:47:31
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_valid        (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_valid),
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_opcode  (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_opcode),
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_param   (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_param),
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_size    (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_size),
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_source  (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_source),
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_address (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_address),
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_mask    (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_mask),
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_data    (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_data),
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_corrupt (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_corrupt),
    .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_ready        (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_ready),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid               (mem_axi4_0_aw_valid),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id             (mem_axi4_0_aw_bits_id),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr           (mem_axi4_0_aw_bits_addr),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len            (mem_axi4_0_aw_bits_len),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size           (mem_axi4_0_aw_bits_size),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst          (mem_axi4_0_aw_bits_burst),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock           (mem_axi4_0_aw_bits_lock),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache          (mem_axi4_0_aw_bits_cache),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot           (mem_axi4_0_aw_bits_prot),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos            (mem_axi4_0_aw_bits_qos),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid                (mem_axi4_0_w_valid),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data            (mem_axi4_0_w_bits_data),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb            (mem_axi4_0_w_bits_strb),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last            (mem_axi4_0_w_bits_last),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready                (mem_axi4_0_b_ready),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid               (mem_axi4_0_ar_valid),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id             (mem_axi4_0_ar_bits_id),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr           (mem_axi4_0_ar_bits_addr),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len            (mem_axi4_0_ar_bits_len),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size           (mem_axi4_0_ar_bits_size),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst          (mem_axi4_0_ar_bits_burst),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock           (mem_axi4_0_ar_bits_lock),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache          (mem_axi4_0_ar_bits_cache),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot           (mem_axi4_0_ar_bits_prot),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos            (mem_axi4_0_ar_bits_qos),
    .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready                (mem_axi4_0_r_ready),
    .auto_fixedClockNode_out_clock                                                         (auto_subsystem_mbus_fixedClockNode_out_clock),
    .auto_fixedClockNode_out_reset                                                         (auto_subsystem_mbus_fixedClockNode_out_reset),
    .auto_bus_xing_in_a_ready                                                              (subsystem_mbus_auto_bus_xing_in_a_ready),
    .auto_bus_xing_in_d_valid                                                              (subsystem_mbus_auto_bus_xing_in_d_valid),
    .auto_bus_xing_in_d_bits_opcode                                                        (subsystem_mbus_auto_bus_xing_in_d_bits_opcode),
    .auto_bus_xing_in_d_bits_param                                                         (subsystem_mbus_auto_bus_xing_in_d_bits_param),
    .auto_bus_xing_in_d_bits_size                                                          (subsystem_mbus_auto_bus_xing_in_d_bits_size),
    .auto_bus_xing_in_d_bits_source                                                        (subsystem_mbus_auto_bus_xing_in_d_bits_source),
    .auto_bus_xing_in_d_bits_sink                                                          (subsystem_mbus_auto_bus_xing_in_d_bits_sink),
    .auto_bus_xing_in_d_bits_denied                                                        (subsystem_mbus_auto_bus_xing_in_d_bits_denied),
    .auto_bus_xing_in_d_bits_data                                                          (subsystem_mbus_auto_bus_xing_in_d_bits_data),
    .auto_bus_xing_in_d_bits_corrupt                                                       (subsystem_mbus_auto_bus_xing_in_d_bits_corrupt),
    .clock                                                                                 (subsystem_mbus_clock),
    .reset                                                                                 (subsystem_mbus_reset)
  );
  CoherenceManagerWrapper subsystem_l2_wrapper (	// BankedL2Params.scala:47:31
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_ready        (subsystem_mbus_auto_bus_xing_in_a_ready),	// MemoryBus.scala:25:26
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_valid        (subsystem_mbus_auto_bus_xing_in_d_valid),	// MemoryBus.scala:25:26
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_opcode  (subsystem_mbus_auto_bus_xing_in_d_bits_opcode),	// MemoryBus.scala:25:26
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_param   (subsystem_mbus_auto_bus_xing_in_d_bits_param),	// MemoryBus.scala:25:26
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_size    (subsystem_mbus_auto_bus_xing_in_d_bits_size),	// MemoryBus.scala:25:26
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_source  (subsystem_mbus_auto_bus_xing_in_d_bits_source),	// MemoryBus.scala:25:26
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_sink    (subsystem_mbus_auto_bus_xing_in_d_bits_sink),	// MemoryBus.scala:25:26
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_denied  (subsystem_mbus_auto_bus_xing_in_d_bits_denied),	// MemoryBus.scala:25:26
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_data    (subsystem_mbus_auto_bus_xing_in_d_bits_data),	// MemoryBus.scala:25:26
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_corrupt (subsystem_mbus_auto_bus_xing_in_d_bits_corrupt),	// MemoryBus.scala:25:26
    .auto_coherent_jbar_in_a_valid                                        (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_valid),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_a_bits_opcode                                  (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_opcode),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_a_bits_param                                   (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_param),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_a_bits_size                                    (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_size),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_a_bits_source                                  (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_source),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_a_bits_address                                 (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_address),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_a_bits_mask                                    (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_mask),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_a_bits_data                                    (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_data),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_a_bits_corrupt                                 (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_corrupt),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_b_ready                                        (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_ready),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_c_valid                                        (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_valid),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_c_bits_opcode                                  (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_opcode),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_c_bits_param                                   (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_param),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_c_bits_size                                    (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_size),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_c_bits_source                                  (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_source),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_c_bits_address                                 (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_address),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_c_bits_data                                    (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_data),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_c_bits_corrupt                                 (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_corrupt),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_d_ready                                        (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_ready),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_e_valid                                        (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_e_valid),	// SystemBus.scala:24:26
    .auto_coherent_jbar_in_e_bits_sink                                    (subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_e_bits_sink),	// SystemBus.scala:24:26
    .auto_l2_ctl_in_a_valid                                               (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid),	// PeripheryBus.scala:31:26
    .auto_l2_ctl_in_a_bits_opcode                                         (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode),	// PeripheryBus.scala:31:26
    .auto_l2_ctl_in_a_bits_param                                          (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param),	// PeripheryBus.scala:31:26
    .auto_l2_ctl_in_a_bits_size                                           (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size),	// PeripheryBus.scala:31:26
    .auto_l2_ctl_in_a_bits_source                                         (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source),	// PeripheryBus.scala:31:26
    .auto_l2_ctl_in_a_bits_address                                        (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address),	// PeripheryBus.scala:31:26
    .auto_l2_ctl_in_a_bits_mask                                           (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask),	// PeripheryBus.scala:31:26
    .auto_l2_ctl_in_a_bits_data                                           (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data),	// PeripheryBus.scala:31:26
    .auto_l2_ctl_in_a_bits_corrupt                                        (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt),	// PeripheryBus.scala:31:26
    .auto_l2_ctl_in_d_ready                                               (subsystem_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready),	// PeripheryBus.scala:31:26
    .auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_clock        (subsystem_sbus_auto_subsystem_sbus_clock_groups_out_member_subsystem_l2_0_clock),	// SystemBus.scala:24:26
    .auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_reset        (subsystem_sbus_auto_subsystem_sbus_clock_groups_out_member_subsystem_l2_0_reset),	// SystemBus.scala:24:26
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_valid        (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_valid),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_opcode  (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_param   (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_param),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_size    (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_size),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_source  (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_source),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_address (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_address),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_mask    (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_mask),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_data    (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_data),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_corrupt (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_corrupt),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_ready        (subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_ready),
    .auto_coherent_jbar_in_a_ready                                        (subsystem_l2_wrapper_auto_coherent_jbar_in_a_ready),
    .auto_coherent_jbar_in_b_valid                                        (subsystem_l2_wrapper_auto_coherent_jbar_in_b_valid),
    .auto_coherent_jbar_in_b_bits_param                                   (subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_param),
    .auto_coherent_jbar_in_b_bits_source                                  (subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_source),
    .auto_coherent_jbar_in_b_bits_address                                 (subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_address),
    .auto_coherent_jbar_in_c_ready                                        (subsystem_l2_wrapper_auto_coherent_jbar_in_c_ready),
    .auto_coherent_jbar_in_d_valid                                        (subsystem_l2_wrapper_auto_coherent_jbar_in_d_valid),
    .auto_coherent_jbar_in_d_bits_opcode                                  (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_opcode),
    .auto_coherent_jbar_in_d_bits_param                                   (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_param),
    .auto_coherent_jbar_in_d_bits_size                                    (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_size),
    .auto_coherent_jbar_in_d_bits_source                                  (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_source),
    .auto_coherent_jbar_in_d_bits_sink                                    (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_sink),
    .auto_coherent_jbar_in_d_bits_denied                                  (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_denied),
    .auto_coherent_jbar_in_d_bits_data                                    (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_data),
    .auto_coherent_jbar_in_d_bits_corrupt                                 (subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_corrupt),
    .auto_l2_ctl_in_a_ready                                               (subsystem_l2_wrapper_auto_l2_ctl_in_a_ready),
    .auto_l2_ctl_in_d_valid                                               (subsystem_l2_wrapper_auto_l2_ctl_in_d_valid),
    .auto_l2_ctl_in_d_bits_opcode                                         (subsystem_l2_wrapper_auto_l2_ctl_in_d_bits_opcode),
    .auto_l2_ctl_in_d_bits_size                                           (subsystem_l2_wrapper_auto_l2_ctl_in_d_bits_size),
    .auto_l2_ctl_in_d_bits_source                                         (subsystem_l2_wrapper_auto_l2_ctl_in_d_bits_source),
    .auto_l2_ctl_in_d_bits_data                                           (subsystem_l2_wrapper_auto_l2_ctl_in_d_bits_data),
    .clock                                                                (subsystem_l2_wrapper_clock),
    .reset                                                                (subsystem_l2_wrapper_reset)
  );
  TilePRCIDomain tile_prci_domain (	// HasTiles.scala:252:38
    .auto_intsink_in_sync_0                                (debug_1_auto_dmOuter_intsource_out_0_sync_0),	// Periphery.scala:84:27
    .auto_int_in_clock_xing_in_2_sync_0                    (intsource_2_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_1_sync_0                    (intsource_1_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_0_sync_0                    (intsource_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_0_sync_1                    (intsource_auto_out_sync_1),	// Crossing.scala:26:31
    .auto_tl_master_clock_xing_out_a_ready                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_a_ready),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_valid                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_b_valid),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_param            (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_b_bits_param),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_source           (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_b_bits_source),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_address          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_b_bits_address),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_c_ready                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_c_ready),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_valid                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_valid),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_opcode           (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_opcode),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_param            (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_param),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_size             (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_size),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_source           (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_source),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_sink             (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_sink),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_denied           (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_denied),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_data             (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_data),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_corrupt          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_d_bits_corrupt),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_e_ready                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_0_e_ready),	// SystemBus.scala:24:26
    .auto_tap_clock_in_clock                               (subsystem_sbus_auto_fixedClockNode_out_1_clock),	// SystemBus.scala:24:26
    .auto_tap_clock_in_reset                               (subsystem_sbus_auto_fixedClockNode_out_1_reset),	// SystemBus.scala:24:26
    .auto_tile_reset_domain_tile_broadcast_out_0_valid     (tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_valid),
    .auto_tile_reset_domain_tile_broadcast_out_0_iaddr     (tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_iaddr),
    .auto_tile_reset_domain_tile_broadcast_out_0_insn      (tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_insn),
    .auto_tile_reset_domain_tile_broadcast_out_0_priv      (tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_priv),
    .auto_tile_reset_domain_tile_broadcast_out_0_exception (tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_exception),
    .auto_tile_reset_domain_tile_broadcast_out_0_interrupt (tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_interrupt),
    .auto_tile_reset_domain_tile_broadcast_out_0_cause     (tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_cause),
    .auto_tile_reset_domain_tile_broadcast_out_0_tval      (tile_prci_domain_auto_tile_reset_domain_tile_broadcast_out_0_tval),
    .auto_int_out_clock_xing_out_2_sync_0                  (tile_prci_domain_auto_int_out_clock_xing_out_2_sync_0),
    .auto_int_out_clock_xing_out_1_sync_0                  (tile_prci_domain_auto_int_out_clock_xing_out_1_sync_0),
    .auto_int_out_clock_xing_out_0_sync_0                  (tile_prci_domain_auto_int_out_clock_xing_out_0_sync_0),
    .auto_tl_master_clock_xing_out_a_valid                 (tile_prci_domain_auto_tl_master_clock_xing_out_a_valid),
    .auto_tl_master_clock_xing_out_a_bits_opcode           (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode),
    .auto_tl_master_clock_xing_out_a_bits_param            (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param),
    .auto_tl_master_clock_xing_out_a_bits_size             (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size),
    .auto_tl_master_clock_xing_out_a_bits_source           (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source),
    .auto_tl_master_clock_xing_out_a_bits_address          (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address),
    .auto_tl_master_clock_xing_out_a_bits_mask             (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask),
    .auto_tl_master_clock_xing_out_a_bits_data             (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data),
    .auto_tl_master_clock_xing_out_a_bits_corrupt          (tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt),
    .auto_tl_master_clock_xing_out_b_ready                 (tile_prci_domain_auto_tl_master_clock_xing_out_b_ready),
    .auto_tl_master_clock_xing_out_c_valid                 (tile_prci_domain_auto_tl_master_clock_xing_out_c_valid),
    .auto_tl_master_clock_xing_out_c_bits_opcode           (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode),
    .auto_tl_master_clock_xing_out_c_bits_param            (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param),
    .auto_tl_master_clock_xing_out_c_bits_size             (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size),
    .auto_tl_master_clock_xing_out_c_bits_source           (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source),
    .auto_tl_master_clock_xing_out_c_bits_address          (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address),
    .auto_tl_master_clock_xing_out_c_bits_data             (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data),
    .auto_tl_master_clock_xing_out_c_bits_corrupt          (tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt),
    .auto_tl_master_clock_xing_out_d_ready                 (tile_prci_domain_auto_tl_master_clock_xing_out_d_ready),
    .auto_tl_master_clock_xing_out_e_valid                 (tile_prci_domain_auto_tl_master_clock_xing_out_e_valid),
    .auto_tl_master_clock_xing_out_e_bits_sink             (tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink),
    .clock                                                 (tile_prci_domain_clock),
    .reset                                                 (tile_prci_domain_reset)
  );
  TilePRCIDomain_1 tile_prci_domain_1 (	// HasTiles.scala:252:38
    .auto_intsink_in_sync_0                                (debug_1_auto_dmOuter_intsource_out_1_sync_0),	// Periphery.scala:84:27
    .auto_int_in_clock_xing_in_2_sync_0                    (intsource_5_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_1_sync_0                    (intsource_4_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_0_sync_0                    (intsource_3_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_0_sync_1                    (intsource_3_auto_out_sync_1),	// Crossing.scala:26:31
    .auto_tl_master_clock_xing_out_a_ready                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_a_ready),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_valid                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_b_valid),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_param            (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_b_bits_param),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_source           (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_b_bits_source),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_address          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_b_bits_address),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_c_ready                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_c_ready),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_valid                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_valid),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_opcode           (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_opcode),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_param            (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_param),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_size             (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_size),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_source           (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_source),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_sink             (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_sink),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_denied           (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_denied),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_data             (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_data),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_corrupt          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_d_bits_corrupt),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_e_ready                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_1_e_ready),	// SystemBus.scala:24:26
    .auto_tap_clock_in_clock                               (subsystem_sbus_auto_fixedClockNode_out_2_clock),	// SystemBus.scala:24:26
    .auto_tap_clock_in_reset                               (subsystem_sbus_auto_fixedClockNode_out_2_reset),	// SystemBus.scala:24:26
    .auto_tile_reset_domain_tile_broadcast_out_0_valid     (tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_valid),
    .auto_tile_reset_domain_tile_broadcast_out_0_iaddr     (tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_iaddr),
    .auto_tile_reset_domain_tile_broadcast_out_0_insn      (tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_insn),
    .auto_tile_reset_domain_tile_broadcast_out_0_priv      (tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_priv),
    .auto_tile_reset_domain_tile_broadcast_out_0_exception (tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_exception),
    .auto_tile_reset_domain_tile_broadcast_out_0_interrupt (tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_interrupt),
    .auto_tile_reset_domain_tile_broadcast_out_0_cause     (tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_cause),
    .auto_tile_reset_domain_tile_broadcast_out_0_tval      (tile_prci_domain_1_auto_tile_reset_domain_tile_broadcast_out_0_tval),
    .auto_int_out_clock_xing_out_2_sync_0                  (tile_prci_domain_1_auto_int_out_clock_xing_out_2_sync_0),
    .auto_int_out_clock_xing_out_1_sync_0                  (tile_prci_domain_1_auto_int_out_clock_xing_out_1_sync_0),
    .auto_int_out_clock_xing_out_0_sync_0                  (tile_prci_domain_1_auto_int_out_clock_xing_out_0_sync_0),
    .auto_tl_master_clock_xing_out_a_valid                 (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_valid),
    .auto_tl_master_clock_xing_out_a_bits_opcode           (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_opcode),
    .auto_tl_master_clock_xing_out_a_bits_param            (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_param),
    .auto_tl_master_clock_xing_out_a_bits_size             (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_size),
    .auto_tl_master_clock_xing_out_a_bits_source           (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_source),
    .auto_tl_master_clock_xing_out_a_bits_address          (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_address),
    .auto_tl_master_clock_xing_out_a_bits_mask             (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_mask),
    .auto_tl_master_clock_xing_out_a_bits_data             (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_data),
    .auto_tl_master_clock_xing_out_a_bits_corrupt          (tile_prci_domain_1_auto_tl_master_clock_xing_out_a_bits_corrupt),
    .auto_tl_master_clock_xing_out_b_ready                 (tile_prci_domain_1_auto_tl_master_clock_xing_out_b_ready),
    .auto_tl_master_clock_xing_out_c_valid                 (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_valid),
    .auto_tl_master_clock_xing_out_c_bits_opcode           (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_opcode),
    .auto_tl_master_clock_xing_out_c_bits_param            (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_param),
    .auto_tl_master_clock_xing_out_c_bits_size             (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_size),
    .auto_tl_master_clock_xing_out_c_bits_source           (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_source),
    .auto_tl_master_clock_xing_out_c_bits_address          (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_address),
    .auto_tl_master_clock_xing_out_c_bits_data             (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_data),
    .auto_tl_master_clock_xing_out_c_bits_corrupt          (tile_prci_domain_1_auto_tl_master_clock_xing_out_c_bits_corrupt),
    .auto_tl_master_clock_xing_out_d_ready                 (tile_prci_domain_1_auto_tl_master_clock_xing_out_d_ready),
    .auto_tl_master_clock_xing_out_e_valid                 (tile_prci_domain_1_auto_tl_master_clock_xing_out_e_valid),
    .auto_tl_master_clock_xing_out_e_bits_sink             (tile_prci_domain_1_auto_tl_master_clock_xing_out_e_bits_sink),
    .clock                                                 (tile_prci_domain_1_clock),
    .reset                                                 (tile_prci_domain_1_reset)
  );
  TilePRCIDomain_2 tile_prci_domain_2 (	// HasTiles.scala:252:38
    .auto_intsink_in_sync_0                                (debug_1_auto_dmOuter_intsource_out_2_sync_0),	// Periphery.scala:84:27
    .auto_int_in_clock_xing_in_1_sync_0                    (intsource_7_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_0_sync_0                    (intsource_6_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_0_sync_1                    (intsource_6_auto_out_sync_1),	// Crossing.scala:26:31
    .auto_tl_master_clock_xing_out_a_ready                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_a_ready),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_valid                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_b_valid),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_param            (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_b_bits_param),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_source           (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_b_bits_source),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_address          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_b_bits_address),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_c_ready                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_c_ready),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_valid                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_valid),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_opcode           (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_opcode),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_param            (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_param),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_size             (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_size),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_source           (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_source),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_sink             (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_sink),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_denied           (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_denied),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_data             (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_data),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_corrupt          (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_d_bits_corrupt),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_e_ready                 (subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_2_e_ready),	// SystemBus.scala:24:26
    .auto_tap_clock_in_clock                               (subsystem_sbus_auto_fixedClockNode_out_3_clock),	// SystemBus.scala:24:26
    .auto_tap_clock_in_reset                               (subsystem_sbus_auto_fixedClockNode_out_3_reset),	// SystemBus.scala:24:26
    .auto_tile_reset_domain_tile_broadcast_out_0_valid     (tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_valid),
    .auto_tile_reset_domain_tile_broadcast_out_0_iaddr     (tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_iaddr),
    .auto_tile_reset_domain_tile_broadcast_out_0_insn      (tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_insn),
    .auto_tile_reset_domain_tile_broadcast_out_0_priv      (tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_priv),
    .auto_tile_reset_domain_tile_broadcast_out_0_exception (tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_exception),
    .auto_tile_reset_domain_tile_broadcast_out_0_interrupt (tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_interrupt),
    .auto_tile_reset_domain_tile_broadcast_out_0_cause     (tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_cause),
    .auto_tile_reset_domain_tile_broadcast_out_0_tval      (tile_prci_domain_2_auto_tile_reset_domain_tile_broadcast_out_0_tval),
    .auto_int_out_clock_xing_out_2_sync_0                  (tile_prci_domain_2_auto_int_out_clock_xing_out_2_sync_0),
    .auto_int_out_clock_xing_out_1_sync_0                  (tile_prci_domain_2_auto_int_out_clock_xing_out_1_sync_0),
    .auto_int_out_clock_xing_out_0_sync_0                  (tile_prci_domain_2_auto_int_out_clock_xing_out_0_sync_0),
    .auto_tl_master_clock_xing_out_a_valid                 (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_valid),
    .auto_tl_master_clock_xing_out_a_bits_opcode           (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_opcode),
    .auto_tl_master_clock_xing_out_a_bits_param            (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_param),
    .auto_tl_master_clock_xing_out_a_bits_size             (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_size),
    .auto_tl_master_clock_xing_out_a_bits_source           (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_source),
    .auto_tl_master_clock_xing_out_a_bits_address          (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_address),
    .auto_tl_master_clock_xing_out_a_bits_mask             (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_mask),
    .auto_tl_master_clock_xing_out_a_bits_data             (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_data),
    .auto_tl_master_clock_xing_out_a_bits_corrupt          (tile_prci_domain_2_auto_tl_master_clock_xing_out_a_bits_corrupt),
    .auto_tl_master_clock_xing_out_b_ready                 (tile_prci_domain_2_auto_tl_master_clock_xing_out_b_ready),
    .auto_tl_master_clock_xing_out_c_valid                 (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_valid),
    .auto_tl_master_clock_xing_out_c_bits_opcode           (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_opcode),
    .auto_tl_master_clock_xing_out_c_bits_param            (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_param),
    .auto_tl_master_clock_xing_out_c_bits_size             (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_size),
    .auto_tl_master_clock_xing_out_c_bits_source           (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_source),
    .auto_tl_master_clock_xing_out_c_bits_address          (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_address),
    .auto_tl_master_clock_xing_out_c_bits_data             (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_data),
    .auto_tl_master_clock_xing_out_c_bits_corrupt          (tile_prci_domain_2_auto_tl_master_clock_xing_out_c_bits_corrupt),
    .auto_tl_master_clock_xing_out_d_ready                 (tile_prci_domain_2_auto_tl_master_clock_xing_out_d_ready),
    .auto_tl_master_clock_xing_out_e_valid                 (tile_prci_domain_2_auto_tl_master_clock_xing_out_e_valid),
    .auto_tl_master_clock_xing_out_e_bits_sink             (tile_prci_domain_2_auto_tl_master_clock_xing_out_e_bits_sink),
    .clock                                                 (tile_prci_domain_2_clock),
    .reset                                                 (tile_prci_domain_2_reset)
  );
  TilePRCIDomain_3 tile_prci_domain_3 (	// HasTiles.scala:252:38
    .auto_intsink_in_sync_0                       (debug_1_auto_dmOuter_intsource_out_3_sync_0),	// Periphery.scala:84:27
    .auto_int_in_clock_xing_in_2_sync_0           (intsource_10_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_1_sync_0           (intsource_9_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_0_sync_0           (intsource_8_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_0_sync_1           (intsource_8_auto_out_sync_1),	// Crossing.scala:26:31
    .auto_tl_master_clock_xing_out_a_ready        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_a_ready),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_valid        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_valid),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_param   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_bits_param),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_source  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_bits_source),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_address (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_b_bits_address),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_c_ready        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_c_ready),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_valid        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_valid),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_opcode  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_opcode),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_param   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_param),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_size    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_size),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_source  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_source),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_sink    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_sink),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_denied  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_denied),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_data    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_data),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_corrupt (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_d_bits_corrupt),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_e_ready        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_0_e_ready),	// SystemBus.scala:24:26
    .auto_tap_clock_in_clock                      (subsystem_sbus_auto_fixedClockNode_out_4_clock),	// SystemBus.scala:24:26
    .auto_tap_clock_in_reset                      (subsystem_sbus_auto_fixedClockNode_out_4_reset),	// SystemBus.scala:24:26
    .auto_int_out_clock_xing_out_2_sync_0         (tile_prci_domain_3_auto_int_out_clock_xing_out_2_sync_0),
    .auto_int_out_clock_xing_out_1_sync_0         (tile_prci_domain_3_auto_int_out_clock_xing_out_1_sync_0),
    .auto_int_out_clock_xing_out_0_sync_0         (tile_prci_domain_3_auto_int_out_clock_xing_out_0_sync_0),
    .auto_tl_master_clock_xing_out_a_valid        (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_valid),
    .auto_tl_master_clock_xing_out_a_bits_opcode  (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_opcode),
    .auto_tl_master_clock_xing_out_a_bits_param   (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_param),
    .auto_tl_master_clock_xing_out_a_bits_size    (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_size),
    .auto_tl_master_clock_xing_out_a_bits_source  (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_source),
    .auto_tl_master_clock_xing_out_a_bits_address (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_address),
    .auto_tl_master_clock_xing_out_a_bits_mask    (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_mask),
    .auto_tl_master_clock_xing_out_a_bits_data    (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_data),
    .auto_tl_master_clock_xing_out_a_bits_corrupt (tile_prci_domain_3_auto_tl_master_clock_xing_out_a_bits_corrupt),
    .auto_tl_master_clock_xing_out_b_ready        (tile_prci_domain_3_auto_tl_master_clock_xing_out_b_ready),
    .auto_tl_master_clock_xing_out_c_valid        (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_valid),
    .auto_tl_master_clock_xing_out_c_bits_opcode  (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_opcode),
    .auto_tl_master_clock_xing_out_c_bits_param   (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_param),
    .auto_tl_master_clock_xing_out_c_bits_size    (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_size),
    .auto_tl_master_clock_xing_out_c_bits_source  (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_source),
    .auto_tl_master_clock_xing_out_c_bits_address (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_address),
    .auto_tl_master_clock_xing_out_c_bits_data    (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_data),
    .auto_tl_master_clock_xing_out_c_bits_corrupt (tile_prci_domain_3_auto_tl_master_clock_xing_out_c_bits_corrupt),
    .auto_tl_master_clock_xing_out_d_ready        (tile_prci_domain_3_auto_tl_master_clock_xing_out_d_ready),
    .auto_tl_master_clock_xing_out_e_valid        (tile_prci_domain_3_auto_tl_master_clock_xing_out_e_valid),
    .auto_tl_master_clock_xing_out_e_bits_sink    (tile_prci_domain_3_auto_tl_master_clock_xing_out_e_bits_sink),
    .clock                                        (tile_prci_domain_3_clock),
    .reset                                        (tile_prci_domain_3_reset)
  );
  TilePRCIDomain_4 tile_prci_domain_4 (	// HasTiles.scala:252:38
    .auto_intsink_in_sync_0                       (debug_1_auto_dmOuter_intsource_out_4_sync_0),	// Periphery.scala:84:27
    .auto_int_in_clock_xing_in_2_sync_0           (intsource_13_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_1_sync_0           (intsource_12_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_0_sync_0           (intsource_11_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_0_sync_1           (intsource_11_auto_out_sync_1),	// Crossing.scala:26:31
    .auto_tl_master_clock_xing_out_a_ready        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_a_ready),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_valid        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_valid),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_param   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_bits_param),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_source  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_bits_source),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_address (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_b_bits_address),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_c_ready        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_c_ready),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_valid        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_valid),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_opcode  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_opcode),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_param   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_param),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_size    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_size),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_source  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_source),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_sink    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_sink),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_denied  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_denied),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_data    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_data),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_corrupt (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_d_bits_corrupt),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_e_ready        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_1_e_ready),	// SystemBus.scala:24:26
    .auto_tap_clock_in_clock                      (subsystem_sbus_auto_fixedClockNode_out_5_clock),	// SystemBus.scala:24:26
    .auto_tap_clock_in_reset                      (subsystem_sbus_auto_fixedClockNode_out_5_reset),	// SystemBus.scala:24:26
    .auto_int_out_clock_xing_out_2_sync_0         (tile_prci_domain_4_auto_int_out_clock_xing_out_2_sync_0),
    .auto_int_out_clock_xing_out_1_sync_0         (tile_prci_domain_4_auto_int_out_clock_xing_out_1_sync_0),
    .auto_int_out_clock_xing_out_0_sync_0         (tile_prci_domain_4_auto_int_out_clock_xing_out_0_sync_0),
    .auto_tl_master_clock_xing_out_a_valid        (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_valid),
    .auto_tl_master_clock_xing_out_a_bits_opcode  (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_opcode),
    .auto_tl_master_clock_xing_out_a_bits_param   (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_param),
    .auto_tl_master_clock_xing_out_a_bits_size    (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_size),
    .auto_tl_master_clock_xing_out_a_bits_source  (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_source),
    .auto_tl_master_clock_xing_out_a_bits_address (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_address),
    .auto_tl_master_clock_xing_out_a_bits_mask    (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_mask),
    .auto_tl_master_clock_xing_out_a_bits_data    (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_data),
    .auto_tl_master_clock_xing_out_a_bits_corrupt (tile_prci_domain_4_auto_tl_master_clock_xing_out_a_bits_corrupt),
    .auto_tl_master_clock_xing_out_b_ready        (tile_prci_domain_4_auto_tl_master_clock_xing_out_b_ready),
    .auto_tl_master_clock_xing_out_c_valid        (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_valid),
    .auto_tl_master_clock_xing_out_c_bits_opcode  (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_opcode),
    .auto_tl_master_clock_xing_out_c_bits_param   (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_param),
    .auto_tl_master_clock_xing_out_c_bits_size    (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_size),
    .auto_tl_master_clock_xing_out_c_bits_source  (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_source),
    .auto_tl_master_clock_xing_out_c_bits_address (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_address),
    .auto_tl_master_clock_xing_out_c_bits_data    (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_data),
    .auto_tl_master_clock_xing_out_c_bits_corrupt (tile_prci_domain_4_auto_tl_master_clock_xing_out_c_bits_corrupt),
    .auto_tl_master_clock_xing_out_d_ready        (tile_prci_domain_4_auto_tl_master_clock_xing_out_d_ready),
    .auto_tl_master_clock_xing_out_e_valid        (tile_prci_domain_4_auto_tl_master_clock_xing_out_e_valid),
    .auto_tl_master_clock_xing_out_e_bits_sink    (tile_prci_domain_4_auto_tl_master_clock_xing_out_e_bits_sink),
    .clock                                        (tile_prci_domain_4_clock),
    .reset                                        (tile_prci_domain_4_reset)
  );
  TilePRCIDomain_5 tile_prci_domain_5 (	// HasTiles.scala:252:38
    .auto_intsink_in_sync_0                       (debug_1_auto_dmOuter_intsource_out_5_sync_0),	// Periphery.scala:84:27
    .auto_int_in_clock_xing_in_2_sync_0           (intsource_16_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_1_sync_0           (intsource_15_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_0_sync_0           (intsource_14_auto_out_sync_0),	// Crossing.scala:26:31
    .auto_int_in_clock_xing_in_0_sync_1           (intsource_14_auto_out_sync_1),	// Crossing.scala:26:31
    .auto_tl_master_clock_xing_out_a_ready        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_a_ready),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_valid        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_valid),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_param   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_bits_param),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_source  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_bits_source),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_b_bits_address (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_b_bits_address),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_c_ready        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_c_ready),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_valid        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_valid),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_opcode  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_opcode),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_param   (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_param),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_size    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_size),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_source  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_source),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_sink    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_sink),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_denied  (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_denied),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_data    (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_data),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_d_bits_corrupt (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_d_bits_corrupt),	// SystemBus.scala:24:26
    .auto_tl_master_clock_xing_out_e_ready        (subsystem_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_2_e_ready),	// SystemBus.scala:24:26
    .auto_tap_clock_in_clock                      (subsystem_sbus_auto_fixedClockNode_out_6_clock),	// SystemBus.scala:24:26
    .auto_tap_clock_in_reset                      (subsystem_sbus_auto_fixedClockNode_out_6_reset),	// SystemBus.scala:24:26
    .auto_int_out_clock_xing_out_2_sync_0         (tile_prci_domain_5_auto_int_out_clock_xing_out_2_sync_0),
    .auto_int_out_clock_xing_out_1_sync_0         (tile_prci_domain_5_auto_int_out_clock_xing_out_1_sync_0),
    .auto_int_out_clock_xing_out_0_sync_0         (tile_prci_domain_5_auto_int_out_clock_xing_out_0_sync_0),
    .auto_tl_master_clock_xing_out_a_valid        (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_valid),
    .auto_tl_master_clock_xing_out_a_bits_opcode  (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_opcode),
    .auto_tl_master_clock_xing_out_a_bits_param   (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_param),
    .auto_tl_master_clock_xing_out_a_bits_size    (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_size),
    .auto_tl_master_clock_xing_out_a_bits_source  (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_source),
    .auto_tl_master_clock_xing_out_a_bits_address (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_address),
    .auto_tl_master_clock_xing_out_a_bits_mask    (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_mask),
    .auto_tl_master_clock_xing_out_a_bits_data    (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_data),
    .auto_tl_master_clock_xing_out_a_bits_corrupt (tile_prci_domain_5_auto_tl_master_clock_xing_out_a_bits_corrupt),
    .auto_tl_master_clock_xing_out_b_ready        (tile_prci_domain_5_auto_tl_master_clock_xing_out_b_ready),
    .auto_tl_master_clock_xing_out_c_valid        (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_valid),
    .auto_tl_master_clock_xing_out_c_bits_opcode  (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_opcode),
    .auto_tl_master_clock_xing_out_c_bits_param   (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_param),
    .auto_tl_master_clock_xing_out_c_bits_size    (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_size),
    .auto_tl_master_clock_xing_out_c_bits_source  (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_source),
    .auto_tl_master_clock_xing_out_c_bits_address (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_address),
    .auto_tl_master_clock_xing_out_c_bits_data    (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_data),
    .auto_tl_master_clock_xing_out_c_bits_corrupt (tile_prci_domain_5_auto_tl_master_clock_xing_out_c_bits_corrupt),
    .auto_tl_master_clock_xing_out_d_ready        (tile_prci_domain_5_auto_tl_master_clock_xing_out_d_ready),
    .auto_tl_master_clock_xing_out_e_valid        (tile_prci_domain_5_auto_tl_master_clock_xing_out_e_valid),
    .auto_tl_master_clock_xing_out_e_bits_sink    (tile_prci_domain_5_auto_tl_master_clock_xing_out_e_bits_sink),
    .clock                                        (tile_prci_domain_5_clock),
    .reset                                        (tile_prci_domain_5_reset)
  );
  ClockSinkDomain plicDomainWrapper (	// Plic.scala:359:39
    .auto_plic_int_in_0          (ibus_auto_int_bus_int_out_0),	// BaseSubsystem.scala:50:24
    .auto_plic_in_a_valid        (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_valid),	// PeripheryBus.scala:31:26
    .auto_plic_in_a_bits_opcode  (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_opcode),	// PeripheryBus.scala:31:26
    .auto_plic_in_a_bits_param   (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_param),	// PeripheryBus.scala:31:26
    .auto_plic_in_a_bits_size    (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_size),	// PeripheryBus.scala:31:26
    .auto_plic_in_a_bits_source  (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_source),	// PeripheryBus.scala:31:26
    .auto_plic_in_a_bits_address (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_address),	// PeripheryBus.scala:31:26
    .auto_plic_in_a_bits_mask    (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_mask),	// PeripheryBus.scala:31:26
    .auto_plic_in_a_bits_data    (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_data),	// PeripheryBus.scala:31:26
    .auto_plic_in_a_bits_corrupt (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_corrupt),	// PeripheryBus.scala:31:26
    .auto_plic_in_d_ready        (subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_ready),	// PeripheryBus.scala:31:26
    .auto_clock_in_clock         (subsystem_cbus_auto_fixedClockNode_out_0_clock),	// PeripheryBus.scala:31:26
    .auto_clock_in_reset         (subsystem_cbus_auto_fixedClockNode_out_0_reset),	// PeripheryBus.scala:31:26
    .auto_plic_int_out_10_0      (plicDomainWrapper_auto_plic_int_out_10_0),
    .auto_plic_int_out_9_0       (plicDomainWrapper_auto_plic_int_out_9_0),
    .auto_plic_int_out_8_0       (plicDomainWrapper_auto_plic_int_out_8_0),
    .auto_plic_int_out_7_0       (plicDomainWrapper_auto_plic_int_out_7_0),
    .auto_plic_int_out_6_0       (plicDomainWrapper_auto_plic_int_out_6_0),
    .auto_plic_int_out_5_0       (plicDomainWrapper_auto_plic_int_out_5_0),
    .auto_plic_int_out_4_0       (plicDomainWrapper_auto_plic_int_out_4_0),
    .auto_plic_int_out_3_0       (plicDomainWrapper_auto_plic_int_out_3_0),
    .auto_plic_int_out_2_0       (plicDomainWrapper_auto_plic_int_out_2_0),
    .auto_plic_int_out_1_0       (plicDomainWrapper_auto_plic_int_out_1_0),
    .auto_plic_int_out_0_0       (plicDomainWrapper_auto_plic_int_out_0_0),
    .auto_plic_in_a_ready        (plicDomainWrapper_auto_plic_in_a_ready),
    .auto_plic_in_d_valid        (plicDomainWrapper_auto_plic_in_d_valid),
    .auto_plic_in_d_bits_opcode  (plicDomainWrapper_auto_plic_in_d_bits_opcode),
    .auto_plic_in_d_bits_size    (plicDomainWrapper_auto_plic_in_d_bits_size),
    .auto_plic_in_d_bits_source  (plicDomainWrapper_auto_plic_in_d_bits_source),
    .auto_plic_in_d_bits_data    (plicDomainWrapper_auto_plic_in_d_bits_data),
    .clock                       (plicDomainWrapper_clock),
    .reset                       (plicDomainWrapper_reset)
  );
  CLINT clint (	// CLINT.scala:109:27
    .clock                  (subsystem_cbus_clock),	// PeripheryBus.scala:31:26
    .reset                  (subsystem_cbus_reset),	// PeripheryBus.scala:31:26
    .auto_in_a_valid        (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_valid),	// PeripheryBus.scala:31:26
    .auto_in_a_bits_opcode  (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_opcode),	// PeripheryBus.scala:31:26
    .auto_in_a_bits_param   (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_param),	// PeripheryBus.scala:31:26
    .auto_in_a_bits_size    (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_size),	// PeripheryBus.scala:31:26
    .auto_in_a_bits_source  (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_source),	// PeripheryBus.scala:31:26
    .auto_in_a_bits_address (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_address),	// PeripheryBus.scala:31:26
    .auto_in_a_bits_mask    (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_mask),	// PeripheryBus.scala:31:26
    .auto_in_a_bits_data    (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_data),	// PeripheryBus.scala:31:26
    .auto_in_a_bits_corrupt (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_corrupt),	// PeripheryBus.scala:31:26
    .auto_in_d_ready        (subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_ready),	// PeripheryBus.scala:31:26
    .io_rtcTick             (int_rtc_tick_wrap_wrap),
    .auto_int_out_5_0       (clint_auto_int_out_5_0),
    .auto_int_out_5_1       (clint_auto_int_out_5_1),
    .auto_int_out_4_0       (clint_auto_int_out_4_0),
    .auto_int_out_4_1       (clint_auto_int_out_4_1),
    .auto_int_out_3_0       (clint_auto_int_out_3_0),
    .auto_int_out_3_1       (clint_auto_int_out_3_1),
    .auto_int_out_2_0       (clint_auto_int_out_2_0),
    .auto_int_out_2_1       (clint_auto_int_out_2_1),
    .auto_int_out_1_0       (clint_auto_int_out_1_0),
    .auto_int_out_1_1       (clint_auto_int_out_1_1),
    .auto_int_out_0_0       (clint_auto_int_out_0_0),
    .auto_int_out_0_1       (clint_auto_int_out_0_1),
    .auto_in_a_ready        (clint_auto_in_a_ready),
    .auto_in_d_valid        (clint_auto_in_d_valid),
    .auto_in_d_bits_opcode  (clint_auto_in_d_bits_opcode),
    .auto_in_d_bits_size    (clint_auto_in_d_bits_size),
    .auto_in_d_bits_source  (clint_auto_in_d_bits_source),
    .auto_in_d_bits_data    (clint_auto_in_d_bits_data)
  );
  DebugCustomXbar debugCustomXbarOpt ();	// Periphery.scala:76:70
  TLDebugModule debug_1 (	// Periphery.scala:84:27
    .auto_dmInner_dmInner_tl_in_a_valid        (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_valid),	// PeripheryBus.scala:31:26
    .auto_dmInner_dmInner_tl_in_a_bits_opcode  (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_opcode),	// PeripheryBus.scala:31:26
    .auto_dmInner_dmInner_tl_in_a_bits_param   (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_param),	// PeripheryBus.scala:31:26
    .auto_dmInner_dmInner_tl_in_a_bits_size    (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_size),	// PeripheryBus.scala:31:26
    .auto_dmInner_dmInner_tl_in_a_bits_source  (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_source),	// PeripheryBus.scala:31:26
    .auto_dmInner_dmInner_tl_in_a_bits_address (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_address),	// PeripheryBus.scala:31:26
    .auto_dmInner_dmInner_tl_in_a_bits_mask    (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_mask),	// PeripheryBus.scala:31:26
    .auto_dmInner_dmInner_tl_in_a_bits_data    (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_data),	// PeripheryBus.scala:31:26
    .auto_dmInner_dmInner_tl_in_a_bits_corrupt (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_corrupt),	// PeripheryBus.scala:31:26
    .auto_dmInner_dmInner_tl_in_d_ready        (subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_ready),	// PeripheryBus.scala:31:26
    .io_debug_clock                            (debug_clock),
    .io_debug_reset                            (debug_reset),
    .io_tl_clock                               (subsystem_cbus_auto_fixedClockNode_out_1_clock),	// PeripheryBus.scala:31:26
    .io_tl_reset                               (subsystem_cbus_auto_fixedClockNode_out_1_reset),	// PeripheryBus.scala:31:26
    .io_ctrl_dmactiveAck                       (debug_dmactiveAck),
    .io_dmi_dmi_req_valid                      (dtm_io_dmi_req_valid),	// Periphery.scala:161:21
    .io_dmi_dmi_req_bits_addr                  (dtm_io_dmi_req_bits_addr),	// Periphery.scala:161:21
    .io_dmi_dmi_req_bits_data                  (dtm_io_dmi_req_bits_data),	// Periphery.scala:161:21
    .io_dmi_dmi_req_bits_op                    (dtm_io_dmi_req_bits_op),	// Periphery.scala:161:21
    .io_dmi_dmi_resp_ready                     (dtm_io_dmi_resp_ready),	// Periphery.scala:161:21
    .io_dmi_dmiClock                           (debug_systemjtag_jtag_TCK),
    .io_dmi_dmiReset                           (debug_systemjtag_reset),
    .io_hartIsInReset_0                        (resetctrl_hartIsInReset_0),
    .io_hartIsInReset_1                        (resetctrl_hartIsInReset_1),
    .io_hartIsInReset_2                        (resetctrl_hartIsInReset_2),
    .io_hartIsInReset_3                        (resetctrl_hartIsInReset_3),
    .io_hartIsInReset_4                        (resetctrl_hartIsInReset_4),
    .io_hartIsInReset_5                        (resetctrl_hartIsInReset_5),
    .auto_dmInner_dmInner_tl_in_a_ready        (debug_1_auto_dmInner_dmInner_tl_in_a_ready),
    .auto_dmInner_dmInner_tl_in_d_valid        (debug_1_auto_dmInner_dmInner_tl_in_d_valid),
    .auto_dmInner_dmInner_tl_in_d_bits_opcode  (debug_1_auto_dmInner_dmInner_tl_in_d_bits_opcode),
    .auto_dmInner_dmInner_tl_in_d_bits_size    (debug_1_auto_dmInner_dmInner_tl_in_d_bits_size),
    .auto_dmInner_dmInner_tl_in_d_bits_source  (debug_1_auto_dmInner_dmInner_tl_in_d_bits_source),
    .auto_dmInner_dmInner_tl_in_d_bits_data    (debug_1_auto_dmInner_dmInner_tl_in_d_bits_data),
    .auto_dmOuter_intsource_out_5_sync_0       (debug_1_auto_dmOuter_intsource_out_5_sync_0),
    .auto_dmOuter_intsource_out_4_sync_0       (debug_1_auto_dmOuter_intsource_out_4_sync_0),
    .auto_dmOuter_intsource_out_3_sync_0       (debug_1_auto_dmOuter_intsource_out_3_sync_0),
    .auto_dmOuter_intsource_out_2_sync_0       (debug_1_auto_dmOuter_intsource_out_2_sync_0),
    .auto_dmOuter_intsource_out_1_sync_0       (debug_1_auto_dmOuter_intsource_out_1_sync_0),
    .auto_dmOuter_intsource_out_0_sync_0       (debug_1_auto_dmOuter_intsource_out_0_sync_0),
    .io_ctrl_ndreset                           (debug_ndreset),
    .io_ctrl_dmactive                          (debug_dmactive),
    .io_dmi_dmi_req_ready                      (debug_1_io_dmi_dmi_req_ready),
    .io_dmi_dmi_resp_valid                     (debug_1_io_dmi_dmi_resp_valid),
    .io_dmi_dmi_resp_bits_data                 (debug_1_io_dmi_dmi_resp_bits_data),
    .io_dmi_dmi_resp_bits_resp                 (debug_1_io_dmi_dmi_resp_bits_resp)
  );
  IntXbar_7 xbar (	// Xbar.scala:30:26
    .auto_int_in_5_0 (intsink_21_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_4_0 (intsink_17_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_3_0 (intsink_13_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_2_0 (intsink_9_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_1_0 (intsink_5_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_0_0 (intsink_1_auto_out_0),	// Crossing.scala:94:29
    .auto_int_out_0  (xbar_auto_int_out_0),
    .auto_int_out_1  (xbar_auto_int_out_1),
    .auto_int_out_2  (xbar_auto_int_out_2),
    .auto_int_out_3  (xbar_auto_int_out_3),
    .auto_int_out_4  (xbar_auto_int_out_4),
    .auto_int_out_5  (xbar_auto_int_out_5)
  );
  IntXbar_7 xbar_1 (	// Xbar.scala:30:26
    .auto_int_in_5_0 (intsink_22_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_4_0 (intsink_18_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_3_0 (intsink_14_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_2_0 (intsink_10_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_1_0 (intsink_6_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_0_0 (intsink_2_auto_out_0),	// Crossing.scala:94:29
    .auto_int_out_0  (xbar_1_auto_int_out_0),
    .auto_int_out_1  (xbar_1_auto_int_out_1),
    .auto_int_out_2  (xbar_1_auto_int_out_2),
    .auto_int_out_3  (xbar_1_auto_int_out_3),
    .auto_int_out_4  (xbar_1_auto_int_out_4),
    .auto_int_out_5  (xbar_1_auto_int_out_5)
  );
  IntXbar_7 xbar_2 (	// Xbar.scala:30:26
    .auto_int_in_5_0 (intsink_23_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_4_0 (intsink_19_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_3_0 (intsink_15_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_2_0 (intsink_11_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_1_0 (intsink_7_auto_out_0),	// Crossing.scala:94:29
    .auto_int_in_0_0 (intsink_3_auto_out_0),	// Crossing.scala:94:29
    .auto_int_out_0  (xbar_2_auto_int_out_0),
    .auto_int_out_1  (xbar_2_auto_int_out_1),
    .auto_int_out_2  (xbar_2_auto_int_out_2),
    .auto_int_out_3  (xbar_2_auto_int_out_3),
    .auto_int_out_4  (xbar_2_auto_int_out_4),
    .auto_int_out_5  (xbar_2_auto_int_out_5)
  );
  BundleBridgeNexus_63 tileHartIdNexusNode ();	// HasTiles.scala:159:39
  BundleBridgeNexus_64 broadcast ();	// BundleBridge.scala:196:31
  IntSyncCrossingSource_25 intsource (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (clint_auto_int_out_0_0),	// CLINT.scala:109:27
    .auto_in_1       (clint_auto_int_out_0_1),	// CLINT.scala:109:27
    .auto_out_sync_0 (intsource_auto_out_sync_0),
    .auto_out_sync_1 (intsource_auto_out_sync_1)
  );
  IntSyncCrossingSource_1 intsource_1 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (plicDomainWrapper_auto_plic_int_out_0_0),	// Plic.scala:359:39
    .auto_out_sync_0 (intsource_1_auto_out_sync_0)
  );
  IntSyncCrossingSource_1 intsource_2 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (plicDomainWrapper_auto_plic_int_out_1_0),	// Plic.scala:359:39
    .auto_out_sync_0 (intsource_2_auto_out_sync_0)
  );
  BundleBridgeNexus intsink ();	// Crossing.scala:94:29
  IntSyncSyncCrossingSink_1 intsink_1 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_auto_int_out_clock_xing_out_0_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_1_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_2 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_auto_int_out_clock_xing_out_1_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_2_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_3 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_auto_int_out_clock_xing_out_2_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_3_auto_out_0)
  );
  IntSyncCrossingSource_25 intsource_3 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (clint_auto_int_out_1_0),	// CLINT.scala:109:27
    .auto_in_1       (clint_auto_int_out_1_1),	// CLINT.scala:109:27
    .auto_out_sync_0 (intsource_3_auto_out_sync_0),
    .auto_out_sync_1 (intsource_3_auto_out_sync_1)
  );
  IntSyncCrossingSource_1 intsource_4 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (plicDomainWrapper_auto_plic_int_out_2_0),	// Plic.scala:359:39
    .auto_out_sync_0 (intsource_4_auto_out_sync_0)
  );
  IntSyncCrossingSource_1 intsource_5 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (plicDomainWrapper_auto_plic_int_out_3_0),	// Plic.scala:359:39
    .auto_out_sync_0 (intsource_5_auto_out_sync_0)
  );
  BundleBridgeNexus intsink_4 ();	// Crossing.scala:94:29
  IntSyncSyncCrossingSink_1 intsink_5 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_1_auto_int_out_clock_xing_out_0_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_5_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_6 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_1_auto_int_out_clock_xing_out_1_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_6_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_7 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_1_auto_int_out_clock_xing_out_2_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_7_auto_out_0)
  );
  IntSyncCrossingSource_25 intsource_6 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (clint_auto_int_out_2_0),	// CLINT.scala:109:27
    .auto_in_1       (clint_auto_int_out_2_1),	// CLINT.scala:109:27
    .auto_out_sync_0 (intsource_6_auto_out_sync_0),
    .auto_out_sync_1 (intsource_6_auto_out_sync_1)
  );
  IntSyncCrossingSource_1 intsource_7 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (plicDomainWrapper_auto_plic_int_out_4_0),	// Plic.scala:359:39
    .auto_out_sync_0 (intsource_7_auto_out_sync_0)
  );
  BundleBridgeNexus intsink_8 ();	// Crossing.scala:94:29
  IntSyncSyncCrossingSink_1 intsink_9 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_2_auto_int_out_clock_xing_out_0_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_9_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_10 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_2_auto_int_out_clock_xing_out_1_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_10_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_11 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_2_auto_int_out_clock_xing_out_2_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_11_auto_out_0)
  );
  IntSyncCrossingSource_25 intsource_8 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (clint_auto_int_out_3_0),	// CLINT.scala:109:27
    .auto_in_1       (clint_auto_int_out_3_1),	// CLINT.scala:109:27
    .auto_out_sync_0 (intsource_8_auto_out_sync_0),
    .auto_out_sync_1 (intsource_8_auto_out_sync_1)
  );
  IntSyncCrossingSource_1 intsource_9 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (plicDomainWrapper_auto_plic_int_out_5_0),	// Plic.scala:359:39
    .auto_out_sync_0 (intsource_9_auto_out_sync_0)
  );
  IntSyncCrossingSource_1 intsource_10 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (plicDomainWrapper_auto_plic_int_out_6_0),	// Plic.scala:359:39
    .auto_out_sync_0 (intsource_10_auto_out_sync_0)
  );
  BundleBridgeNexus intsink_12 ();	// Crossing.scala:94:29
  IntSyncSyncCrossingSink_1 intsink_13 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_3_auto_int_out_clock_xing_out_0_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_13_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_14 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_3_auto_int_out_clock_xing_out_1_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_14_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_15 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_3_auto_int_out_clock_xing_out_2_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_15_auto_out_0)
  );
  IntSyncCrossingSource_25 intsource_11 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (clint_auto_int_out_4_0),	// CLINT.scala:109:27
    .auto_in_1       (clint_auto_int_out_4_1),	// CLINT.scala:109:27
    .auto_out_sync_0 (intsource_11_auto_out_sync_0),
    .auto_out_sync_1 (intsource_11_auto_out_sync_1)
  );
  IntSyncCrossingSource_1 intsource_12 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (plicDomainWrapper_auto_plic_int_out_7_0),	// Plic.scala:359:39
    .auto_out_sync_0 (intsource_12_auto_out_sync_0)
  );
  IntSyncCrossingSource_1 intsource_13 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (plicDomainWrapper_auto_plic_int_out_8_0),	// Plic.scala:359:39
    .auto_out_sync_0 (intsource_13_auto_out_sync_0)
  );
  BundleBridgeNexus intsink_16 ();	// Crossing.scala:94:29
  IntSyncSyncCrossingSink_1 intsink_17 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_4_auto_int_out_clock_xing_out_0_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_17_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_18 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_4_auto_int_out_clock_xing_out_1_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_18_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_19 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_4_auto_int_out_clock_xing_out_2_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_19_auto_out_0)
  );
  IntSyncCrossingSource_25 intsource_14 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (clint_auto_int_out_5_0),	// CLINT.scala:109:27
    .auto_in_1       (clint_auto_int_out_5_1),	// CLINT.scala:109:27
    .auto_out_sync_0 (intsource_14_auto_out_sync_0),
    .auto_out_sync_1 (intsource_14_auto_out_sync_1)
  );
  IntSyncCrossingSource_1 intsource_15 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (plicDomainWrapper_auto_plic_int_out_9_0),	// Plic.scala:359:39
    .auto_out_sync_0 (intsource_15_auto_out_sync_0)
  );
  IntSyncCrossingSource_1 intsource_16 (	// Crossing.scala:26:31
    .clock           (clock),
    .reset           (reset),
    .auto_in_0       (plicDomainWrapper_auto_plic_int_out_10_0),	// Plic.scala:359:39
    .auto_out_sync_0 (intsource_16_auto_out_sync_0)
  );
  BundleBridgeNexus intsink_20 ();	// Crossing.scala:94:29
  IntSyncSyncCrossingSink_1 intsink_21 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_5_auto_int_out_clock_xing_out_0_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_21_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_22 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_5_auto_int_out_clock_xing_out_1_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_22_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_23 (	// Crossing.scala:94:29
    .auto_in_sync_0 (tile_prci_domain_5_auto_int_out_clock_xing_out_2_sync_0),	// HasTiles.scala:252:38
    .auto_out_0     (intsink_23_auto_out_0)
  );
  ClockSinkDomain_1 bootROMDomainWrapper (	// BootROM.scala:70:42
    .auto_bootrom_in_a_valid        (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_valid),	// PeripheryBus.scala:31:26
    .auto_bootrom_in_a_bits_opcode  (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode),	// PeripheryBus.scala:31:26
    .auto_bootrom_in_a_bits_param   (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_param),	// PeripheryBus.scala:31:26
    .auto_bootrom_in_a_bits_size    (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_size),	// PeripheryBus.scala:31:26
    .auto_bootrom_in_a_bits_source  (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_source),	// PeripheryBus.scala:31:26
    .auto_bootrom_in_a_bits_address (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_address),	// PeripheryBus.scala:31:26
    .auto_bootrom_in_a_bits_mask    (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_mask),	// PeripheryBus.scala:31:26
    .auto_bootrom_in_a_bits_data    (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_data),	// PeripheryBus.scala:31:26
    .auto_bootrom_in_a_bits_corrupt (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt),	// PeripheryBus.scala:31:26
    .auto_bootrom_in_d_ready        (subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_ready),	// PeripheryBus.scala:31:26
    .auto_clock_in_clock            (subsystem_cbus_auto_fixedClockNode_out_2_clock),	// PeripheryBus.scala:31:26
    .auto_clock_in_reset            (subsystem_cbus_auto_fixedClockNode_out_2_reset),	// PeripheryBus.scala:31:26
    .auto_bootrom_in_a_ready        (bootROMDomainWrapper_auto_bootrom_in_a_ready),
    .auto_bootrom_in_d_valid        (bootROMDomainWrapper_auto_bootrom_in_d_valid),
    .auto_bootrom_in_d_bits_size    (bootROMDomainWrapper_auto_bootrom_in_d_bits_size),
    .auto_bootrom_in_d_bits_source  (bootROMDomainWrapper_auto_bootrom_in_d_bits_source),
    .auto_bootrom_in_d_bits_data    (bootROMDomainWrapper_auto_bootrom_in_d_bits_data),
    .clock                          (bootROMDomainWrapper_clock),
    .reset                          (bootROMDomainWrapper_reset)
  );
  ClockSinkDomain_2 domain (	// SerialAdapter.scala:373:28
    .auto_serdesser_client_out_a_ready                (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_ready),	// FrontBus.scala:22:26
    .auto_serdesser_client_out_d_valid                (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_valid),	// FrontBus.scala:22:26
    .auto_serdesser_client_out_d_bits_opcode          (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_opcode),	// FrontBus.scala:22:26
    .auto_serdesser_client_out_d_bits_param           (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_param),	// FrontBus.scala:22:26
    .auto_serdesser_client_out_d_bits_size            (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_size),	// FrontBus.scala:22:26
    .auto_serdesser_client_out_d_bits_source          (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_source),	// FrontBus.scala:22:26
    .auto_serdesser_client_out_d_bits_sink            (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_sink),	// FrontBus.scala:22:26
    .auto_serdesser_client_out_d_bits_denied          (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_denied),	// FrontBus.scala:22:26
    .auto_serdesser_client_out_d_bits_data            (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_data),	// FrontBus.scala:22:26
    .auto_serdesser_client_out_d_bits_corrupt         (subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_corrupt),	// FrontBus.scala:22:26
    .auto_tlserial_manager_crossing_in_a_valid        (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_valid),	// MemoryBus.scala:25:26
    .auto_tlserial_manager_crossing_in_a_bits_opcode  (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_opcode),	// MemoryBus.scala:25:26
    .auto_tlserial_manager_crossing_in_a_bits_param   (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_param),	// MemoryBus.scala:25:26
    .auto_tlserial_manager_crossing_in_a_bits_size    (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_size),	// MemoryBus.scala:25:26
    .auto_tlserial_manager_crossing_in_a_bits_source  (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_source),	// MemoryBus.scala:25:26
    .auto_tlserial_manager_crossing_in_a_bits_address (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_address),	// MemoryBus.scala:25:26
    .auto_tlserial_manager_crossing_in_a_bits_mask    (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_mask),	// MemoryBus.scala:25:26
    .auto_tlserial_manager_crossing_in_a_bits_data    (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_data),	// MemoryBus.scala:25:26
    .auto_tlserial_manager_crossing_in_a_bits_corrupt (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_corrupt),	// MemoryBus.scala:25:26
    .auto_tlserial_manager_crossing_in_d_ready        (subsystem_mbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_ready),	// MemoryBus.scala:25:26
    .auto_clock_in_clock                              (subsystem_fbus_auto_fixedClockNode_out_clock),	// FrontBus.scala:22:26
    .auto_clock_in_reset                              (subsystem_fbus_auto_fixedClockNode_out_reset),	// FrontBus.scala:22:26
    .serial_tl_in_valid                               (serial_tl_bits_in_valid),
    .serial_tl_in_bits                                (serial_tl_bits_in_bits),
    .serial_tl_out_ready                              (serial_tl_bits_out_ready),
    .auto_serdesser_client_out_a_valid                (domain_auto_serdesser_client_out_a_valid),
    .auto_serdesser_client_out_a_bits_opcode          (domain_auto_serdesser_client_out_a_bits_opcode),
    .auto_serdesser_client_out_a_bits_param           (domain_auto_serdesser_client_out_a_bits_param),
    .auto_serdesser_client_out_a_bits_size            (domain_auto_serdesser_client_out_a_bits_size),
    .auto_serdesser_client_out_a_bits_source          (domain_auto_serdesser_client_out_a_bits_source),
    .auto_serdesser_client_out_a_bits_address         (domain_auto_serdesser_client_out_a_bits_address),
    .auto_serdesser_client_out_a_bits_mask            (domain_auto_serdesser_client_out_a_bits_mask),
    .auto_serdesser_client_out_a_bits_data            (domain_auto_serdesser_client_out_a_bits_data),
    .auto_serdesser_client_out_a_bits_corrupt         (domain_auto_serdesser_client_out_a_bits_corrupt),
    .auto_serdesser_client_out_d_ready                (domain_auto_serdesser_client_out_d_ready),
    .auto_tlserial_manager_crossing_in_a_ready        (domain_auto_tlserial_manager_crossing_in_a_ready),
    .auto_tlserial_manager_crossing_in_d_valid        (domain_auto_tlserial_manager_crossing_in_d_valid),
    .auto_tlserial_manager_crossing_in_d_bits_opcode  (domain_auto_tlserial_manager_crossing_in_d_bits_opcode),
    .auto_tlserial_manager_crossing_in_d_bits_param   (domain_auto_tlserial_manager_crossing_in_d_bits_param),
    .auto_tlserial_manager_crossing_in_d_bits_size    (domain_auto_tlserial_manager_crossing_in_d_bits_size),
    .auto_tlserial_manager_crossing_in_d_bits_source  (domain_auto_tlserial_manager_crossing_in_d_bits_source),
    .auto_tlserial_manager_crossing_in_d_bits_sink    (domain_auto_tlserial_manager_crossing_in_d_bits_sink),
    .auto_tlserial_manager_crossing_in_d_bits_denied  (domain_auto_tlserial_manager_crossing_in_d_bits_denied),
    .auto_tlserial_manager_crossing_in_d_bits_data    (domain_auto_tlserial_manager_crossing_in_d_bits_data),
    .auto_tlserial_manager_crossing_in_d_bits_corrupt (domain_auto_tlserial_manager_crossing_in_d_bits_corrupt),
    .serial_tl_in_ready                               (serial_tl_bits_in_ready),
    .serial_tl_out_valid                              (serial_tl_bits_out_valid),
    .serial_tl_out_bits                               (serial_tl_bits_out_bits),
    .clock                                            (serial_tl_clock),
    .reset                                            (domain_reset)
  );
  ClockSinkDomain_3 uartClockDomainWrapper (	// UART.scala:242:44
    .auto_uart_0_control_xing_in_a_valid        (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid),	// PeripheryBus.scala:31:26
    .auto_uart_0_control_xing_in_a_bits_opcode  (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode),	// PeripheryBus.scala:31:26
    .auto_uart_0_control_xing_in_a_bits_param   (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param),	// PeripheryBus.scala:31:26
    .auto_uart_0_control_xing_in_a_bits_size    (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size),	// PeripheryBus.scala:31:26
    .auto_uart_0_control_xing_in_a_bits_source  (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source),	// PeripheryBus.scala:31:26
    .auto_uart_0_control_xing_in_a_bits_address (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address),	// PeripheryBus.scala:31:26
    .auto_uart_0_control_xing_in_a_bits_mask    (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask),	// PeripheryBus.scala:31:26
    .auto_uart_0_control_xing_in_a_bits_data    (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data),	// PeripheryBus.scala:31:26
    .auto_uart_0_control_xing_in_a_bits_corrupt (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt),	// PeripheryBus.scala:31:26
    .auto_uart_0_control_xing_in_d_ready        (subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready),	// PeripheryBus.scala:31:26
    .auto_uart_0_io_out_rxd                     (uart_0_rxd),
    .auto_clock_in_clock                        (subsystem_pbus_auto_fixedClockNode_out_0_clock),	// PeripheryBus.scala:31:26
    .auto_clock_in_reset                        (subsystem_pbus_auto_fixedClockNode_out_0_reset),	// PeripheryBus.scala:31:26
    .auto_uart_0_int_xing_out_sync_0            (uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0),
    .auto_uart_0_control_xing_in_a_ready        (uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready),
    .auto_uart_0_control_xing_in_d_valid        (uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid),
    .auto_uart_0_control_xing_in_d_bits_opcode  (uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode),
    .auto_uart_0_control_xing_in_d_bits_size    (uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size),
    .auto_uart_0_control_xing_in_d_bits_source  (uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source),
    .auto_uart_0_control_xing_in_d_bits_data    (uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data),
    .auto_uart_0_io_out_txd                     (uart_0_txd),
    .clock                                      (uartClockDomainWrapper_clock),
    .reset                                      (uartClockDomainWrapper_reset)
  );
  IntSyncSyncCrossingSink_1 intsink_24 (	// Crossing.scala:94:29
    .auto_in_sync_0 (uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0),	// UART.scala:242:44
    .auto_out_0     (intsink_24_auto_out_0)
  );
  ClockSinkDomain_4 domain_1 (	// TileResetCtrl.scala:23:34
    .auto_resetCtrl_async_reset_sink_in_reset                                       (auto_domain_resetCtrl_async_reset_sink_in_reset),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_cbus_0_clock  (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_cbus_0_clock),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_cbus_0_reset  (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_cbus_0_reset),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_mbus_0_clock  (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_mbus_0_clock),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_mbus_0_reset  (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_mbus_0_reset),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_fbus_0_clock  (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_fbus_0_clock),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_fbus_0_reset  (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_fbus_0_reset),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_pbus_0_clock  (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_pbus_0_clock),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_pbus_0_reset  (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_pbus_0_reset),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_1_clock  (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_1_clock),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_1_reset  (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_1_reset),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_0_clock  (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_0_clock),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_0_reset  (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_0_reset),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_implicit_clock_clock    (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_implicit_clock_clock),
    .auto_resetCtrl_tile_reset_provider_in_member_allClocks_implicit_clock_reset    (auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_implicit_clock_reset),
    .auto_resetCtrl_in_a_valid                                                      (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_valid),	// PeripheryBus.scala:31:26
    .auto_resetCtrl_in_a_bits_opcode                                                (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_opcode),	// PeripheryBus.scala:31:26
    .auto_resetCtrl_in_a_bits_param                                                 (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_param),	// PeripheryBus.scala:31:26
    .auto_resetCtrl_in_a_bits_size                                                  (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_size),	// PeripheryBus.scala:31:26
    .auto_resetCtrl_in_a_bits_source                                                (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_source),	// PeripheryBus.scala:31:26
    .auto_resetCtrl_in_a_bits_address                                               (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_address),	// PeripheryBus.scala:31:26
    .auto_resetCtrl_in_a_bits_mask                                                  (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_mask),	// PeripheryBus.scala:31:26
    .auto_resetCtrl_in_a_bits_data                                                  (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_data),	// PeripheryBus.scala:31:26
    .auto_resetCtrl_in_a_bits_corrupt                                               (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_a_bits_corrupt),	// PeripheryBus.scala:31:26
    .auto_resetCtrl_in_d_ready                                                      (subsystem_pbus_auto_coupler_to_slave_named_tileresetctrl_buffer_out_d_ready),	// PeripheryBus.scala:31:26
    .auto_clock_in_clock                                                            (subsystem_pbus_auto_fixedClockNode_out_1_clock),	// PeripheryBus.scala:31:26
    .auto_clock_in_reset                                                            (subsystem_pbus_auto_fixedClockNode_out_1_reset),	// PeripheryBus.scala:31:26
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_clock (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_clock),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_reset (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_reset),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_clock (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_clock),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_reset (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_reset),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_clock (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_clock),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_reset (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_reset),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_clock (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_clock),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_reset (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_reset),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_clock (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_clock),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_reset (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_reset),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_clock (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_clock),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_reset (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_reset),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_clock   (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_clock),
    .auto_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_reset   (auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_reset),
    .auto_resetCtrl_in_a_ready                                                      (domain_1_auto_resetCtrl_in_a_ready),
    .auto_resetCtrl_in_d_valid                                                      (domain_1_auto_resetCtrl_in_d_valid),
    .auto_resetCtrl_in_d_bits_opcode                                                (domain_1_auto_resetCtrl_in_d_bits_opcode),
    .auto_resetCtrl_in_d_bits_size                                                  (domain_1_auto_resetCtrl_in_d_bits_size),
    .auto_resetCtrl_in_d_bits_source                                                (domain_1_auto_resetCtrl_in_d_bits_source),
    .auto_resetCtrl_in_d_bits_data                                                  (domain_1_auto_resetCtrl_in_d_bits_data),
    .clock                                                                          (domain_1_clock),
    .reset                                                                          (domain_1_reset)
  );
  DebugTransportModuleJTAG dtm (	// Periphery.scala:161:21
    .io_jtag_clock         (debug_systemjtag_jtag_TCK),
    .io_jtag_reset         (debug_systemjtag_reset),
    .io_dmi_req_ready      (debug_1_io_dmi_dmi_req_ready),	// Periphery.scala:84:27
    .io_dmi_resp_valid     (debug_1_io_dmi_dmi_resp_valid),	// Periphery.scala:84:27
    .io_dmi_resp_bits_data (debug_1_io_dmi_dmi_resp_bits_data),	// Periphery.scala:84:27
    .io_dmi_resp_bits_resp (debug_1_io_dmi_dmi_resp_bits_resp),	// Periphery.scala:84:27
    .io_jtag_TCK           (debug_systemjtag_jtag_TCK),
    .io_jtag_TMS           (debug_systemjtag_jtag_TMS),
    .io_jtag_TDI           (debug_systemjtag_jtag_TDI),
    .io_dmi_req_valid      (dtm_io_dmi_req_valid),
    .io_dmi_req_bits_addr  (dtm_io_dmi_req_bits_addr),
    .io_dmi_req_bits_data  (dtm_io_dmi_req_bits_data),
    .io_dmi_req_bits_op    (dtm_io_dmi_req_bits_op),
    .io_dmi_resp_ready     (dtm_io_dmi_resp_ready),
    .io_jtag_TDO_data      (debug_systemjtag_jtag_TDO_data),
    .io_jtag_TDO_driven    (debug_systemjtag_jtag_TDO_driven)
  );
endmodule

module ClockGroupAggregator_6(	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  input  auto_in_member_allClocks_subsystem_cbus_0_clock,
  input  auto_in_member_allClocks_subsystem_cbus_0_reset,
  input  auto_in_member_allClocks_subsystem_mbus_0_clock,
  input  auto_in_member_allClocks_subsystem_mbus_0_reset,
  input  auto_in_member_allClocks_subsystem_fbus_0_clock,
  input  auto_in_member_allClocks_subsystem_fbus_0_reset,
  input  auto_in_member_allClocks_subsystem_pbus_0_clock,
  input  auto_in_member_allClocks_subsystem_pbus_0_reset,
  input  auto_in_member_allClocks_subsystem_sbus_1_clock,
  input  auto_in_member_allClocks_subsystem_sbus_1_reset,
  input  auto_in_member_allClocks_subsystem_sbus_0_clock,
  input  auto_in_member_allClocks_subsystem_sbus_0_reset,
  input  auto_in_member_allClocks_implicit_clock_clock,
  input  auto_in_member_allClocks_implicit_clock_reset,
  output auto_out_5_member_subsystem_cbus_subsystem_cbus_0_clock,
  output auto_out_5_member_subsystem_cbus_subsystem_cbus_0_reset,
  output auto_out_4_member_subsystem_mbus_subsystem_mbus_0_clock,
  output auto_out_4_member_subsystem_mbus_subsystem_mbus_0_reset,
  output auto_out_3_member_subsystem_fbus_subsystem_fbus_0_clock,
  output auto_out_3_member_subsystem_fbus_subsystem_fbus_0_reset,
  output auto_out_2_member_subsystem_pbus_subsystem_pbus_0_clock,
  output auto_out_2_member_subsystem_pbus_subsystem_pbus_0_reset,
  output auto_out_1_member_subsystem_sbus_subsystem_sbus_1_clock,
  output auto_out_1_member_subsystem_sbus_subsystem_sbus_1_reset,
  output auto_out_1_member_subsystem_sbus_subsystem_sbus_0_clock,
  output auto_out_1_member_subsystem_sbus_subsystem_sbus_0_reset,
  output auto_out_0_member_dividerOnlyClockGenerator_implicit_clock_clock,
  output auto_out_0_member_dividerOnlyClockGenerator_implicit_clock_reset);

  assign auto_out_5_member_subsystem_cbus_subsystem_cbus_0_clock = auto_in_member_allClocks_subsystem_cbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_5_member_subsystem_cbus_subsystem_cbus_0_reset = auto_in_member_allClocks_subsystem_cbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_4_member_subsystem_mbus_subsystem_mbus_0_clock = auto_in_member_allClocks_subsystem_mbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_4_member_subsystem_mbus_subsystem_mbus_0_reset = auto_in_member_allClocks_subsystem_mbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_3_member_subsystem_fbus_subsystem_fbus_0_clock = auto_in_member_allClocks_subsystem_fbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_3_member_subsystem_fbus_subsystem_fbus_0_reset = auto_in_member_allClocks_subsystem_fbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_2_member_subsystem_pbus_subsystem_pbus_0_clock = auto_in_member_allClocks_subsystem_pbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_2_member_subsystem_pbus_subsystem_pbus_0_reset = auto_in_member_allClocks_subsystem_pbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_1_member_subsystem_sbus_subsystem_sbus_1_clock = auto_in_member_allClocks_subsystem_sbus_1_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_1_member_subsystem_sbus_subsystem_sbus_1_reset = auto_in_member_allClocks_subsystem_sbus_1_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_1_member_subsystem_sbus_subsystem_sbus_0_clock = auto_in_member_allClocks_subsystem_sbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_1_member_subsystem_sbus_subsystem_sbus_0_reset = auto_in_member_allClocks_subsystem_sbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_0_member_dividerOnlyClockGenerator_implicit_clock_clock = auto_in_member_allClocks_implicit_clock_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
  assign auto_out_0_member_dividerOnlyClockGenerator_implicit_clock_reset = auto_in_member_allClocks_implicit_clock_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063916:10
endmodule

module ClockGroup_6(	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063963:10
  input  auto_in_member_dividerOnlyClockGenerator_implicit_clock_clock,
  input  auto_in_member_dividerOnlyClockGenerator_implicit_clock_reset,
  output auto_out_clock, auto_out_reset);

  assign auto_out_clock = auto_in_member_dividerOnlyClockGenerator_implicit_clock_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063963:10
  assign auto_out_reset = auto_in_member_dividerOnlyClockGenerator_implicit_clock_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063963:10
endmodule

module ClockGroupParameterModifier(	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
  input  auto_divider_only_clock_generator_in_4_member_subsystem_cbus_subsystem_cbus_0_clock,
  input  auto_divider_only_clock_generator_in_4_member_subsystem_cbus_subsystem_cbus_0_reset,
  input  auto_divider_only_clock_generator_in_3_member_subsystem_mbus_subsystem_mbus_0_clock,
  input  auto_divider_only_clock_generator_in_3_member_subsystem_mbus_subsystem_mbus_0_reset,
  input  auto_divider_only_clock_generator_in_2_member_subsystem_fbus_subsystem_fbus_0_clock,
  input  auto_divider_only_clock_generator_in_2_member_subsystem_fbus_subsystem_fbus_0_reset,
  input  auto_divider_only_clock_generator_in_1_member_subsystem_pbus_subsystem_pbus_0_clock,
  input  auto_divider_only_clock_generator_in_1_member_subsystem_pbus_subsystem_pbus_0_reset,
  input  auto_divider_only_clock_generator_in_0_member_subsystem_sbus_subsystem_sbus_1_clock,
  input  auto_divider_only_clock_generator_in_0_member_subsystem_sbus_subsystem_sbus_1_reset,
  input  auto_divider_only_clock_generator_in_0_member_subsystem_sbus_subsystem_sbus_0_clock,
  input  auto_divider_only_clock_generator_in_0_member_subsystem_sbus_subsystem_sbus_0_reset,
  output auto_divider_only_clock_generator_out_4_member_subsystem_cbus_0_clock,
  output auto_divider_only_clock_generator_out_4_member_subsystem_cbus_0_reset,
  output auto_divider_only_clock_generator_out_3_member_subsystem_mbus_0_clock,
  output auto_divider_only_clock_generator_out_3_member_subsystem_mbus_0_reset,
  output auto_divider_only_clock_generator_out_2_member_subsystem_fbus_0_clock,
  output auto_divider_only_clock_generator_out_2_member_subsystem_fbus_0_reset,
  output auto_divider_only_clock_generator_out_1_member_subsystem_pbus_0_clock,
  output auto_divider_only_clock_generator_out_1_member_subsystem_pbus_0_reset,
  output auto_divider_only_clock_generator_out_0_member_subsystem_sbus_1_clock,
  output auto_divider_only_clock_generator_out_0_member_subsystem_sbus_1_reset,
  output auto_divider_only_clock_generator_out_0_member_subsystem_sbus_0_clock,
  output auto_divider_only_clock_generator_out_0_member_subsystem_sbus_0_reset);

  assign auto_divider_only_clock_generator_out_4_member_subsystem_cbus_0_clock = auto_divider_only_clock_generator_in_4_member_subsystem_cbus_subsystem_cbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
  assign auto_divider_only_clock_generator_out_4_member_subsystem_cbus_0_reset = auto_divider_only_clock_generator_in_4_member_subsystem_cbus_subsystem_cbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
  assign auto_divider_only_clock_generator_out_3_member_subsystem_mbus_0_clock = auto_divider_only_clock_generator_in_3_member_subsystem_mbus_subsystem_mbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
  assign auto_divider_only_clock_generator_out_3_member_subsystem_mbus_0_reset = auto_divider_only_clock_generator_in_3_member_subsystem_mbus_subsystem_mbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
  assign auto_divider_only_clock_generator_out_2_member_subsystem_fbus_0_clock = auto_divider_only_clock_generator_in_2_member_subsystem_fbus_subsystem_fbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
  assign auto_divider_only_clock_generator_out_2_member_subsystem_fbus_0_reset = auto_divider_only_clock_generator_in_2_member_subsystem_fbus_subsystem_fbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
  assign auto_divider_only_clock_generator_out_1_member_subsystem_pbus_0_clock = auto_divider_only_clock_generator_in_1_member_subsystem_pbus_subsystem_pbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
  assign auto_divider_only_clock_generator_out_1_member_subsystem_pbus_0_reset = auto_divider_only_clock_generator_in_1_member_subsystem_pbus_subsystem_pbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
  assign auto_divider_only_clock_generator_out_0_member_subsystem_sbus_1_clock = auto_divider_only_clock_generator_in_0_member_subsystem_sbus_subsystem_sbus_1_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
  assign auto_divider_only_clock_generator_out_0_member_subsystem_sbus_1_reset = auto_divider_only_clock_generator_in_0_member_subsystem_sbus_subsystem_sbus_1_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
  assign auto_divider_only_clock_generator_out_0_member_subsystem_sbus_0_clock = auto_divider_only_clock_generator_in_0_member_subsystem_sbus_subsystem_sbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
  assign auto_divider_only_clock_generator_out_0_member_subsystem_sbus_0_reset = auto_divider_only_clock_generator_in_0_member_subsystem_sbus_subsystem_sbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1063983:10
endmodule

// external module ClockDividerN

module DividerOnlyClockGenerator(	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10
  input  auto_divider_only_clk_generator_in_clock,
  input  auto_divider_only_clk_generator_in_reset,
  output auto_divider_only_clk_generator_out_member_allClocks_subsystem_cbus_0_clock,
  output auto_divider_only_clk_generator_out_member_allClocks_subsystem_cbus_0_reset,
  output auto_divider_only_clk_generator_out_member_allClocks_subsystem_mbus_0_clock,
  output auto_divider_only_clk_generator_out_member_allClocks_subsystem_mbus_0_reset,
  output auto_divider_only_clk_generator_out_member_allClocks_subsystem_fbus_0_clock,
  output auto_divider_only_clk_generator_out_member_allClocks_subsystem_fbus_0_reset,
  output auto_divider_only_clk_generator_out_member_allClocks_subsystem_pbus_0_clock,
  output auto_divider_only_clk_generator_out_member_allClocks_subsystem_pbus_0_reset,
  output auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_1_clock,
  output auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_1_reset,
  output auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_0_clock,
  output auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_0_reset,
  output auto_divider_only_clk_generator_out_member_allClocks_implicit_clock_clock,
  output auto_divider_only_clk_generator_out_member_allClocks_implicit_clock_reset);

  wire bundleOut_0_member_allClocks_implicit_clock_clock_ClockDivideBy1_clk_out;	// DividerOnlyClockGenerator.scala:133:27

  ClockDividerN #(
    .DIV(1)
  ) bundleOut_0_member_allClocks_implicit_clock_clock_ClockDivideBy1 (	// DividerOnlyClockGenerator.scala:133:27
    .clk_in  (auto_divider_only_clk_generator_in_clock),
    .clk_out (bundleOut_0_member_allClocks_implicit_clock_clock_ClockDivideBy1_clk_out)
  );
  assign auto_divider_only_clk_generator_out_member_allClocks_subsystem_cbus_0_clock = bundleOut_0_member_allClocks_implicit_clock_clock_ClockDivideBy1_clk_out;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10, DividerOnlyClockGenerator.scala:133:27
  assign auto_divider_only_clk_generator_out_member_allClocks_subsystem_cbus_0_reset = auto_divider_only_clk_generator_in_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10
  assign auto_divider_only_clk_generator_out_member_allClocks_subsystem_mbus_0_clock = bundleOut_0_member_allClocks_implicit_clock_clock_ClockDivideBy1_clk_out;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10, DividerOnlyClockGenerator.scala:133:27
  assign auto_divider_only_clk_generator_out_member_allClocks_subsystem_mbus_0_reset = auto_divider_only_clk_generator_in_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10
  assign auto_divider_only_clk_generator_out_member_allClocks_subsystem_fbus_0_clock = bundleOut_0_member_allClocks_implicit_clock_clock_ClockDivideBy1_clk_out;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10, DividerOnlyClockGenerator.scala:133:27
  assign auto_divider_only_clk_generator_out_member_allClocks_subsystem_fbus_0_reset = auto_divider_only_clk_generator_in_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10
  assign auto_divider_only_clk_generator_out_member_allClocks_subsystem_pbus_0_clock = bundleOut_0_member_allClocks_implicit_clock_clock_ClockDivideBy1_clk_out;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10, DividerOnlyClockGenerator.scala:133:27
  assign auto_divider_only_clk_generator_out_member_allClocks_subsystem_pbus_0_reset = auto_divider_only_clk_generator_in_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10
  assign auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_1_clock = bundleOut_0_member_allClocks_implicit_clock_clock_ClockDivideBy1_clk_out;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10, DividerOnlyClockGenerator.scala:133:27
  assign auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_1_reset = auto_divider_only_clk_generator_in_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10
  assign auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_0_clock = bundleOut_0_member_allClocks_implicit_clock_clock_ClockDivideBy1_clk_out;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10, DividerOnlyClockGenerator.scala:133:27
  assign auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_0_reset = auto_divider_only_clk_generator_in_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10
  assign auto_divider_only_clk_generator_out_member_allClocks_implicit_clock_clock = bundleOut_0_member_allClocks_implicit_clock_clock_ClockDivideBy1_clk_out;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10, DividerOnlyClockGenerator.scala:133:27
  assign auto_divider_only_clk_generator_out_member_allClocks_implicit_clock_reset = auto_divider_only_clk_generator_in_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064043:10
endmodule

module ClockGroupParameterModifier_1(	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  input  auto_divider_only_clock_generator_in_member_allClocks_subsystem_cbus_0_clock,
  input  auto_divider_only_clock_generator_in_member_allClocks_subsystem_cbus_0_reset,
  input  auto_divider_only_clock_generator_in_member_allClocks_subsystem_mbus_0_clock,
  input  auto_divider_only_clock_generator_in_member_allClocks_subsystem_mbus_0_reset,
  input  auto_divider_only_clock_generator_in_member_allClocks_subsystem_fbus_0_clock,
  input  auto_divider_only_clock_generator_in_member_allClocks_subsystem_fbus_0_reset,
  input  auto_divider_only_clock_generator_in_member_allClocks_subsystem_pbus_0_clock,
  input  auto_divider_only_clock_generator_in_member_allClocks_subsystem_pbus_0_reset,
  input  auto_divider_only_clock_generator_in_member_allClocks_subsystem_sbus_1_clock,
  input  auto_divider_only_clock_generator_in_member_allClocks_subsystem_sbus_1_reset,
  input  auto_divider_only_clock_generator_in_member_allClocks_subsystem_sbus_0_clock,
  input  auto_divider_only_clock_generator_in_member_allClocks_subsystem_sbus_0_reset,
  input  auto_divider_only_clock_generator_in_member_allClocks_implicit_clock_clock,
  input  auto_divider_only_clock_generator_in_member_allClocks_implicit_clock_reset,
  output auto_divider_only_clock_generator_out_member_allClocks_subsystem_cbus_0_clock,
  output auto_divider_only_clock_generator_out_member_allClocks_subsystem_cbus_0_reset,
  output auto_divider_only_clock_generator_out_member_allClocks_subsystem_mbus_0_clock,
  output auto_divider_only_clock_generator_out_member_allClocks_subsystem_mbus_0_reset,
  output auto_divider_only_clock_generator_out_member_allClocks_subsystem_fbus_0_clock,
  output auto_divider_only_clock_generator_out_member_allClocks_subsystem_fbus_0_reset,
  output auto_divider_only_clock_generator_out_member_allClocks_subsystem_pbus_0_clock,
  output auto_divider_only_clock_generator_out_member_allClocks_subsystem_pbus_0_reset,
  output auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_1_clock,
  output auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_1_reset,
  output auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_0_clock,
  output auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_0_reset,
  output auto_divider_only_clock_generator_out_member_allClocks_implicit_clock_clock,
  output auto_divider_only_clock_generator_out_member_allClocks_implicit_clock_reset);

  assign auto_divider_only_clock_generator_out_member_allClocks_subsystem_cbus_0_clock = auto_divider_only_clock_generator_in_member_allClocks_subsystem_cbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_subsystem_cbus_0_reset = auto_divider_only_clock_generator_in_member_allClocks_subsystem_cbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_subsystem_mbus_0_clock = auto_divider_only_clock_generator_in_member_allClocks_subsystem_mbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_subsystem_mbus_0_reset = auto_divider_only_clock_generator_in_member_allClocks_subsystem_mbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_subsystem_fbus_0_clock = auto_divider_only_clock_generator_in_member_allClocks_subsystem_fbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_subsystem_fbus_0_reset = auto_divider_only_clock_generator_in_member_allClocks_subsystem_fbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_subsystem_pbus_0_clock = auto_divider_only_clock_generator_in_member_allClocks_subsystem_pbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_subsystem_pbus_0_reset = auto_divider_only_clock_generator_in_member_allClocks_subsystem_pbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_1_clock = auto_divider_only_clock_generator_in_member_allClocks_subsystem_sbus_1_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_1_reset = auto_divider_only_clock_generator_in_member_allClocks_subsystem_sbus_1_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_0_clock = auto_divider_only_clock_generator_in_member_allClocks_subsystem_sbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_0_reset = auto_divider_only_clock_generator_in_member_allClocks_subsystem_sbus_0_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_implicit_clock_clock = auto_divider_only_clock_generator_in_member_allClocks_implicit_clock_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
  assign auto_divider_only_clock_generator_out_member_allClocks_implicit_clock_reset = auto_divider_only_clock_generator_in_member_allClocks_implicit_clock_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064079:10
endmodule

module ResetCatchAndSync_d3(	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064111:10
  input  clock, reset,
  output io_sync_reset);

  wire io_sync_reset_chain_io_q;	// ShiftReg.scala:45:23

  AsyncResetSynchronizerShiftReg_w1_d3_i0 io_sync_reset_chain (	// ShiftReg.scala:45:23
    .clock (clock),
    .reset (reset),
    .io_d  (1'h1),	// ShiftReg.scala:47:16
    .io_q  (io_sync_reset_chain_io_q)
  );
  assign io_sync_reset = ~io_sync_reset_chain_io_q;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064111:10, ResetCatchAndSync.scala:29:7, ShiftReg.scala:45:23
endmodule

module ClockGroupResetSynchronizer(	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064130:10
  input  auto_in_member_allClocks_subsystem_cbus_0_clock,
  input  auto_in_member_allClocks_subsystem_cbus_0_reset,
  input  auto_in_member_allClocks_subsystem_mbus_0_clock,
  input  auto_in_member_allClocks_subsystem_mbus_0_reset,
  input  auto_in_member_allClocks_subsystem_fbus_0_clock,
  input  auto_in_member_allClocks_subsystem_fbus_0_reset,
  input  auto_in_member_allClocks_subsystem_pbus_0_clock,
  input  auto_in_member_allClocks_subsystem_pbus_0_reset,
  input  auto_in_member_allClocks_subsystem_sbus_1_clock,
  input  auto_in_member_allClocks_subsystem_sbus_1_reset,
  input  auto_in_member_allClocks_subsystem_sbus_0_clock,
  input  auto_in_member_allClocks_subsystem_sbus_0_reset,
  input  auto_in_member_allClocks_implicit_clock_clock,
  input  auto_in_member_allClocks_implicit_clock_reset,
  output auto_out_member_allClocks_subsystem_cbus_0_clock,
  output auto_out_member_allClocks_subsystem_cbus_0_reset,
  output auto_out_member_allClocks_subsystem_mbus_0_clock,
  output auto_out_member_allClocks_subsystem_mbus_0_reset,
  output auto_out_member_allClocks_subsystem_fbus_0_clock,
  output auto_out_member_allClocks_subsystem_fbus_0_reset,
  output auto_out_member_allClocks_subsystem_pbus_0_clock,
  output auto_out_member_allClocks_subsystem_pbus_0_reset,
  output auto_out_member_allClocks_subsystem_sbus_1_clock,
  output auto_out_member_allClocks_subsystem_sbus_1_reset,
  output auto_out_member_allClocks_subsystem_sbus_0_clock,
  output auto_out_member_allClocks_subsystem_sbus_0_reset,
  output auto_out_member_allClocks_implicit_clock_clock,
  output auto_out_member_allClocks_implicit_clock_reset);

  ResetCatchAndSync_d3 bundleOut_0_member_allClocks_implicit_clock_reset_catcher (	// ResetCatchAndSync.scala:39:28
    .clock         (auto_in_member_allClocks_implicit_clock_clock),
    .reset         (auto_in_member_allClocks_implicit_clock_reset),
    .io_sync_reset (auto_out_member_allClocks_implicit_clock_reset)
  );
  ResetCatchAndSync_d3 bundleOut_0_member_allClocks_subsystem_sbus_0_reset_catcher (	// ResetCatchAndSync.scala:39:28
    .clock         (auto_in_member_allClocks_subsystem_sbus_0_clock),
    .reset         (auto_in_member_allClocks_subsystem_sbus_0_reset),
    .io_sync_reset (auto_out_member_allClocks_subsystem_sbus_0_reset)
  );
  ResetCatchAndSync_d3 bundleOut_0_member_allClocks_subsystem_sbus_1_reset_catcher (	// ResetCatchAndSync.scala:39:28
    .clock         (auto_in_member_allClocks_subsystem_sbus_1_clock),
    .reset         (auto_in_member_allClocks_subsystem_sbus_1_reset),
    .io_sync_reset (auto_out_member_allClocks_subsystem_sbus_1_reset)
  );
  ResetCatchAndSync_d3 bundleOut_0_member_allClocks_subsystem_pbus_0_reset_catcher (	// ResetCatchAndSync.scala:39:28
    .clock         (auto_in_member_allClocks_subsystem_pbus_0_clock),
    .reset         (auto_in_member_allClocks_subsystem_pbus_0_reset),
    .io_sync_reset (auto_out_member_allClocks_subsystem_pbus_0_reset)
  );
  ResetCatchAndSync_d3 bundleOut_0_member_allClocks_subsystem_fbus_0_reset_catcher (	// ResetCatchAndSync.scala:39:28
    .clock         (auto_in_member_allClocks_subsystem_fbus_0_clock),
    .reset         (auto_in_member_allClocks_subsystem_fbus_0_reset),
    .io_sync_reset (auto_out_member_allClocks_subsystem_fbus_0_reset)
  );
  ResetCatchAndSync_d3 bundleOut_0_member_allClocks_subsystem_mbus_0_reset_catcher (	// ResetCatchAndSync.scala:39:28
    .clock         (auto_in_member_allClocks_subsystem_mbus_0_clock),
    .reset         (auto_in_member_allClocks_subsystem_mbus_0_reset),
    .io_sync_reset (auto_out_member_allClocks_subsystem_mbus_0_reset)
  );
  ResetCatchAndSync_d3 bundleOut_0_member_allClocks_subsystem_cbus_0_reset_catcher (	// ResetCatchAndSync.scala:39:28
    .clock         (auto_in_member_allClocks_subsystem_cbus_0_clock),
    .reset         (auto_in_member_allClocks_subsystem_cbus_0_reset),
    .io_sync_reset (auto_out_member_allClocks_subsystem_cbus_0_reset)
  );
  assign auto_out_member_allClocks_subsystem_cbus_0_clock = auto_in_member_allClocks_subsystem_cbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064130:10
  assign auto_out_member_allClocks_subsystem_mbus_0_clock = auto_in_member_allClocks_subsystem_mbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064130:10
  assign auto_out_member_allClocks_subsystem_fbus_0_clock = auto_in_member_allClocks_subsystem_fbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064130:10
  assign auto_out_member_allClocks_subsystem_pbus_0_clock = auto_in_member_allClocks_subsystem_pbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064130:10
  assign auto_out_member_allClocks_subsystem_sbus_1_clock = auto_in_member_allClocks_subsystem_sbus_1_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064130:10
  assign auto_out_member_allClocks_subsystem_sbus_0_clock = auto_in_member_allClocks_subsystem_sbus_0_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064130:10
  assign auto_out_member_allClocks_implicit_clock_clock = auto_in_member_allClocks_implicit_clock_clock;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064130:10
endmodule

module FixedClockBroadcast_12(	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064246:10
  input  auto_in_reset,
  output auto_out_clock, auto_out_reset);

  assign auto_out_clock = 1'h0;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064246:10
  assign auto_out_reset = auto_in_reset;	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064246:10
endmodule

module ResetSynchronizerShiftReg_w1_d3_i0(	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064266:10
  input  clock, reset, io_d,
  output io_q);

  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain (	// ShiftReg.scala:45:23
    .clock (clock),
    .reset (reset),
    .io_d  (io_d),
    .io_q  (io_q)
  );
endmodule

// external module EICG_wrapper

// external module GenericDigitalOutIOCell

// external module GenericDigitalInIOCell

module ChipTop(	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064299:10
  input         jtag_TCK, jtag_TMS, jtag_TDI, serial_tl_bits_in_valid,
  input  [3:0]  serial_tl_bits_in_bits,
  input         serial_tl_bits_out_ready, custom_boot, axi4_mem_0_bits_aw_ready,
  input         axi4_mem_0_bits_w_ready, axi4_mem_0_bits_b_valid,
  input  [3:0]  axi4_mem_0_bits_b_bits_id,
  input  [1:0]  axi4_mem_0_bits_b_bits_resp,
  input         axi4_mem_0_bits_ar_ready, axi4_mem_0_bits_r_valid,
  input  [3:0]  axi4_mem_0_bits_r_bits_id,
  input  [63:0] axi4_mem_0_bits_r_bits_data,
  input  [1:0]  axi4_mem_0_bits_r_bits_resp,
  input         axi4_mem_0_bits_r_bits_last, uart_0_rxd, reset_wire_reset, clock,
  output        jtag_TDO, serial_tl_clock, serial_tl_bits_in_ready,
  output        serial_tl_bits_out_valid,
  output [3:0]  serial_tl_bits_out_bits,
  output        axi4_mem_0_clock, axi4_mem_0_reset, axi4_mem_0_bits_aw_valid,
  output [3:0]  axi4_mem_0_bits_aw_bits_id,
  output [31:0] axi4_mem_0_bits_aw_bits_addr,
  output [7:0]  axi4_mem_0_bits_aw_bits_len,
  output [2:0]  axi4_mem_0_bits_aw_bits_size,
  output [1:0]  axi4_mem_0_bits_aw_bits_burst,
  output        axi4_mem_0_bits_aw_bits_lock,
  output [3:0]  axi4_mem_0_bits_aw_bits_cache,
  output [2:0]  axi4_mem_0_bits_aw_bits_prot,
  output [3:0]  axi4_mem_0_bits_aw_bits_qos,
  output        axi4_mem_0_bits_w_valid,
  output [63:0] axi4_mem_0_bits_w_bits_data,
  output [7:0]  axi4_mem_0_bits_w_bits_strb,
  output        axi4_mem_0_bits_w_bits_last, axi4_mem_0_bits_b_ready,
  output        axi4_mem_0_bits_ar_valid,
  output [3:0]  axi4_mem_0_bits_ar_bits_id,
  output [31:0] axi4_mem_0_bits_ar_bits_addr,
  output [7:0]  axi4_mem_0_bits_ar_bits_len,
  output [2:0]  axi4_mem_0_bits_ar_bits_size,
  output [1:0]  axi4_mem_0_bits_ar_bits_burst,
  output        axi4_mem_0_bits_ar_bits_lock,
  output [3:0]  axi4_mem_0_bits_ar_bits_cache,
  output [2:0]  axi4_mem_0_bits_ar_bits_prot,
  output [3:0]  axi4_mem_0_bits_ar_bits_qos,
  output        axi4_mem_0_bits_r_ready, uart_0_txd);

  wire       iocell_clock_i;	// IOCell.scala:111:23
  wire       reset_wire_iocell_reset_i;	// IOCell.scala:111:23
  wire       iocell_uart_0_rxd_i;	// IOCell.scala:111:23
  wire       iocell_custom_boot_i;	// IOCell.scala:111:23
  wire       iocell_serial_tl_bits_in_valid_i;	// IOCell.scala:111:23
  wire       iocell_serial_tl_bits_in_bits_3_i;	// IOCell.scala:111:23
  wire       iocell_serial_tl_bits_in_bits_2_i;	// IOCell.scala:111:23
  wire       iocell_serial_tl_bits_in_bits_1_i;	// IOCell.scala:111:23
  wire       iocell_serial_tl_bits_in_bits_i;	// IOCell.scala:111:23
  wire       iocell_serial_tl_bits_out_ready_i;	// IOCell.scala:111:23
  wire       iocell_serial_tl_bits_out_bits_3_pad;	// IOCell.scala:112:24
  wire       iocell_serial_tl_bits_out_bits_2_pad;	// IOCell.scala:112:24
  wire       iocell_serial_tl_bits_out_bits_1_pad;	// IOCell.scala:112:24
  wire       iocell_serial_tl_bits_out_bits_pad;	// IOCell.scala:112:24
  wire       iocell_jtag_TCK_i;	// IOCell.scala:111:23
  wire       iocell_jtag_TMS_i;	// IOCell.scala:111:23
  wire       iocell_jtag_TDI_i;	// IOCell.scala:111:23
  wire       gated_clock_debug_clock_gate_out;	// ClockGate.scala:24:20
  wire       dmactiveAck_dmactiveAck_io_q;	// ShiftReg.scala:45:23
  wire       debug_reset_syncd_debug_reset_sync_io_q;	// ShiftReg.scala:45:23
  wire       system_debug_systemjtag_reset_catcher_io_sync_reset;	// ResetCatchAndSync.scala:39:28
  wire       asyncResetBroadcast_auto_out_clock;	// ClockGroup.scala:106:107
  wire       asyncResetBroadcast_auto_out_reset;	// ClockGroup.scala:106:107
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_cbus_0_clock;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_cbus_0_reset;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_mbus_0_clock;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_mbus_0_reset;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_fbus_0_clock;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_fbus_0_reset;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_pbus_0_clock;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_pbus_0_reset;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_sbus_1_clock;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_sbus_1_reset;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_sbus_0_clock;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_sbus_0_reset;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_implicit_clock_clock;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_3_auto_out_member_allClocks_implicit_clock_reset;	// ResetSynchronizer.scala:42:69
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_cbus_0_clock;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_cbus_0_reset;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_mbus_0_clock;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_mbus_0_reset;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_fbus_0_clock;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_fbus_0_reset;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_pbus_0_clock;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_pbus_0_reset;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_1_clock;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_1_reset;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_0_clock;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_0_reset;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_implicit_clock_clock;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_implicit_clock_reset;	// ClockGroupNamePrefixer.scala:68:15
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_cbus_0_clock;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_cbus_0_reset;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_mbus_0_clock;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_mbus_0_reset;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_fbus_0_clock;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_fbus_0_reset;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_pbus_0_clock;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_pbus_0_reset;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_1_clock;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_1_reset;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_0_clock;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_0_reset;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_implicit_clock_clock;	// Clocks.scala:90:45
  wire       dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_implicit_clock_reset;	// Clocks.scala:90:45
  wire       dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_4_member_subsystem_cbus_0_clock;	// ClockGroupNamePrefixer.scala:32:15
  wire       dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_4_member_subsystem_cbus_0_reset;	// ClockGroupNamePrefixer.scala:32:15
  wire       dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_3_member_subsystem_mbus_0_clock;	// ClockGroupNamePrefixer.scala:32:15
  wire       dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_3_member_subsystem_mbus_0_reset;	// ClockGroupNamePrefixer.scala:32:15
  wire       dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_2_member_subsystem_fbus_0_clock;	// ClockGroupNamePrefixer.scala:32:15
  wire       dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_2_member_subsystem_fbus_0_reset;	// ClockGroupNamePrefixer.scala:32:15
  wire       dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_1_member_subsystem_pbus_0_clock;	// ClockGroupNamePrefixer.scala:32:15
  wire       dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_1_member_subsystem_pbus_0_reset;	// ClockGroupNamePrefixer.scala:32:15
  wire       dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_0_member_subsystem_sbus_1_clock;	// ClockGroupNamePrefixer.scala:32:15
  wire       dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_0_member_subsystem_sbus_1_reset;	// ClockGroupNamePrefixer.scala:32:15
  wire       dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_0_member_subsystem_sbus_0_clock;	// ClockGroupNamePrefixer.scala:32:15
  wire       dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_0_member_subsystem_sbus_0_reset;	// ClockGroupNamePrefixer.scala:32:15
  wire       dividerOnlyClockGenerator_auto_out_clock;	// ClockGroup.scala:32:69
  wire       dividerOnlyClockGenerator_auto_out_reset;	// ClockGroup.scala:32:69
  wire       aggregator_auto_out_5_member_subsystem_cbus_subsystem_cbus_0_clock;	// Clocks.scala:79:32
  wire       aggregator_auto_out_5_member_subsystem_cbus_subsystem_cbus_0_reset;	// Clocks.scala:79:32
  wire       aggregator_auto_out_4_member_subsystem_mbus_subsystem_mbus_0_clock;	// Clocks.scala:79:32
  wire       aggregator_auto_out_4_member_subsystem_mbus_subsystem_mbus_0_reset;	// Clocks.scala:79:32
  wire       aggregator_auto_out_3_member_subsystem_fbus_subsystem_fbus_0_clock;	// Clocks.scala:79:32
  wire       aggregator_auto_out_3_member_subsystem_fbus_subsystem_fbus_0_reset;	// Clocks.scala:79:32
  wire       aggregator_auto_out_2_member_subsystem_pbus_subsystem_pbus_0_clock;	// Clocks.scala:79:32
  wire       aggregator_auto_out_2_member_subsystem_pbus_subsystem_pbus_0_reset;	// Clocks.scala:79:32
  wire       aggregator_auto_out_1_member_subsystem_sbus_subsystem_sbus_1_clock;	// Clocks.scala:79:32
  wire       aggregator_auto_out_1_member_subsystem_sbus_subsystem_sbus_1_reset;	// Clocks.scala:79:32
  wire       aggregator_auto_out_1_member_subsystem_sbus_subsystem_sbus_0_clock;	// Clocks.scala:79:32
  wire       aggregator_auto_out_1_member_subsystem_sbus_subsystem_sbus_0_reset;	// Clocks.scala:79:32
  wire       aggregator_auto_out_0_member_dividerOnlyClockGenerator_implicit_clock_clock;	// Clocks.scala:79:32
  wire       aggregator_auto_out_0_member_dividerOnlyClockGenerator_implicit_clock_reset;	// Clocks.scala:79:32
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_clock;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_reset;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_clock;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_reset;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_clock;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_reset;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_clock;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_reset;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_clock;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_reset;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_clock;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_reset;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_clock;	// ChipTop.scala:32:35
  wire       system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_reset;	// ChipTop.scala:32:35
  wire       system_auto_subsystem_cbus_fixedClockNode_out_clock;	// ChipTop.scala:32:35
  wire       system_auto_subsystem_cbus_fixedClockNode_out_reset;	// ChipTop.scala:32:35
  wire       system_serial_tl_clock;	// ChipTop.scala:32:35
  wire       system_serial_tl_bits_in_ready;	// ChipTop.scala:32:35
  wire       system_serial_tl_bits_out_valid;	// ChipTop.scala:32:35
  wire [3:0] system_serial_tl_bits_out_bits;	// ChipTop.scala:32:35
  wire       system_debug_systemjtag_jtag_TDO_data;	// ChipTop.scala:32:35
  wire       system_debug_systemjtag_jtag_TDO_driven;	// ChipTop.scala:32:35
  wire       system_debug_ndreset;	// ChipTop.scala:32:35
  wire       system_debug_dmactive;	// ChipTop.scala:32:35
  wire       system_uart_0_txd;	// ChipTop.scala:32:35
  wire       _GEN;	// Periphery.scala:299:29
  wire       _GEN_0;	// Periphery.scala:299:29
  reg        clock_en;	// Periphery.scala:299:29

  `ifndef SYNTHESIS	// Periphery.scala:299:29
    `ifdef RANDOMIZE_REG_INIT	// Periphery.scala:299:29
      reg [31:0] _RANDOM;	// Periphery.scala:299:29

    `endif
    initial begin	// Periphery.scala:299:29
      `INIT_RANDOM_PROLOG_	// Periphery.scala:299:29
      `ifdef RANDOMIZE_REG_INIT	// Periphery.scala:299:29
        _RANDOM = `RANDOM;	// Periphery.scala:299:29
        clock_en = _RANDOM[0];	// Periphery.scala:299:29
      `endif
    end // initial
  `endif
  assign _GEN_0 = system_auto_subsystem_cbus_fixedClockNode_out_clock;	// ChipTop.scala:32:35, Periphery.scala:299:29
  assign _GEN = ~debug_reset_syncd_debug_reset_sync_io_q;	// Periphery.scala:291:40, :299:29, ShiftReg.scala:45:23
  always @(posedge _GEN_0 or posedge _GEN) begin	// Periphery.scala:299:29
    if (~debug_reset_syncd_debug_reset_sync_io_q)	// Periphery.scala:291:40, :299:29, ShiftReg.scala:45:23
      clock_en <= 1'h1;	// Periphery.scala:299:29, ShiftReg.scala:47:16
    else	// Periphery.scala:291:40, :299:29, ShiftReg.scala:45:23
      clock_en <= dmactiveAck_dmactiveAck_io_q;	// Periphery.scala:299:29, ShiftReg.scala:45:23
  end // always @(posedge, posedge)
  DigitalTop system (	// ChipTop.scala:32:35
    .clock                                                                                 (dividerOnlyClockGenerator_auto_out_clock),	// ClockGroup.scala:32:69
    .reset                                                                                 (dividerOnlyClockGenerator_auto_out_reset),	// ClockGroup.scala:32:69
    .auto_domain_resetCtrl_async_reset_sink_in_reset                                       (asyncResetBroadcast_auto_out_reset),	// ClockGroup.scala:106:107
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_cbus_0_clock  (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_cbus_0_clock),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_cbus_0_reset  (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_cbus_0_reset),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_mbus_0_clock  (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_mbus_0_clock),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_mbus_0_reset  (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_mbus_0_reset),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_fbus_0_clock  (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_fbus_0_clock),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_fbus_0_reset  (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_fbus_0_reset),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_pbus_0_clock  (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_pbus_0_clock),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_pbus_0_reset  (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_pbus_0_reset),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_1_clock  (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_1_clock),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_1_reset  (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_1_reset),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_0_clock  (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_0_clock),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_subsystem_sbus_0_reset  (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_0_reset),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_implicit_clock_clock    (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_implicit_clock_clock),	// Clocks.scala:90:45
    .auto_domain_resetCtrl_tile_reset_provider_in_member_allClocks_implicit_clock_reset    (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_implicit_clock_reset),	// Clocks.scala:90:45
    .auto_subsystem_mbus_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_clock      (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_3_member_subsystem_mbus_0_clock),	// ClockGroupNamePrefixer.scala:32:15
    .auto_subsystem_mbus_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_reset      (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_3_member_subsystem_mbus_0_reset),	// ClockGroupNamePrefixer.scala:32:15
    .auto_subsystem_cbus_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock      (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_4_member_subsystem_cbus_0_clock),	// ClockGroupNamePrefixer.scala:32:15
    .auto_subsystem_cbus_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset      (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_4_member_subsystem_cbus_0_reset),	// ClockGroupNamePrefixer.scala:32:15
    .auto_subsystem_fbus_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock      (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_2_member_subsystem_fbus_0_clock),	// ClockGroupNamePrefixer.scala:32:15
    .auto_subsystem_fbus_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset      (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_2_member_subsystem_fbus_0_reset),	// ClockGroupNamePrefixer.scala:32:15
    .auto_subsystem_pbus_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock      (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_1_member_subsystem_pbus_0_clock),	// ClockGroupNamePrefixer.scala:32:15
    .auto_subsystem_pbus_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset      (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_1_member_subsystem_pbus_0_reset),	// ClockGroupNamePrefixer.scala:32:15
    .auto_subsystem_sbus_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_clock      (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_0_member_subsystem_sbus_1_clock),	// ClockGroupNamePrefixer.scala:32:15
    .auto_subsystem_sbus_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_reset      (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_0_member_subsystem_sbus_1_reset),	// ClockGroupNamePrefixer.scala:32:15
    .auto_subsystem_sbus_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock      (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_0_member_subsystem_sbus_0_clock),	// ClockGroupNamePrefixer.scala:32:15
    .auto_subsystem_sbus_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset      (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_0_member_subsystem_sbus_0_reset),	// ClockGroupNamePrefixer.scala:32:15
    .mem_axi4_0_aw_ready                                                                   (axi4_mem_0_bits_aw_ready),
    .mem_axi4_0_w_ready                                                                    (axi4_mem_0_bits_w_ready),
    .mem_axi4_0_b_valid                                                                    (axi4_mem_0_bits_b_valid),
    .mem_axi4_0_b_bits_id                                                                  (axi4_mem_0_bits_b_bits_id),
    .mem_axi4_0_b_bits_resp                                                                (axi4_mem_0_bits_b_bits_resp),
    .mem_axi4_0_ar_ready                                                                   (axi4_mem_0_bits_ar_ready),
    .mem_axi4_0_r_valid                                                                    (axi4_mem_0_bits_r_valid),
    .mem_axi4_0_r_bits_id                                                                  (axi4_mem_0_bits_r_bits_id),
    .mem_axi4_0_r_bits_data                                                                (axi4_mem_0_bits_r_bits_data),
    .mem_axi4_0_r_bits_resp                                                                (axi4_mem_0_bits_r_bits_resp),
    .mem_axi4_0_r_bits_last                                                                (axi4_mem_0_bits_r_bits_last),
    .custom_boot                                                                           (iocell_custom_boot_i),	// IOCell.scala:111:23
    .serial_tl_bits_in_valid                                                               (iocell_serial_tl_bits_in_valid_i),	// IOCell.scala:111:23
    .serial_tl_bits_in_bits                                                                ({iocell_serial_tl_bits_in_bits_3_i, iocell_serial_tl_bits_in_bits_2_i,
                iocell_serial_tl_bits_in_bits_1_i, iocell_serial_tl_bits_in_bits_i}),	// Cat.scala:30:58, IOCell.scala:111:23
    .serial_tl_bits_out_ready                                                              (iocell_serial_tl_bits_out_ready_i),	// IOCell.scala:111:23
    .resetctrl_hartIsInReset_0                                                             (system_auto_subsystem_cbus_fixedClockNode_out_reset),	// ChipTop.scala:32:35
    .resetctrl_hartIsInReset_1                                                             (system_auto_subsystem_cbus_fixedClockNode_out_reset),	// ChipTop.scala:32:35
    .resetctrl_hartIsInReset_2                                                             (system_auto_subsystem_cbus_fixedClockNode_out_reset),	// ChipTop.scala:32:35
    .resetctrl_hartIsInReset_3                                                             (system_auto_subsystem_cbus_fixedClockNode_out_reset),	// ChipTop.scala:32:35
    .resetctrl_hartIsInReset_4                                                             (system_auto_subsystem_cbus_fixedClockNode_out_reset),	// ChipTop.scala:32:35
    .resetctrl_hartIsInReset_5                                                             (system_auto_subsystem_cbus_fixedClockNode_out_reset),	// ChipTop.scala:32:35
    .debug_clock                                                                           (gated_clock_debug_clock_gate_out),	// ClockGate.scala:24:20
    .debug_reset                                                                           (~debug_reset_syncd_debug_reset_sync_io_q),	// Periphery.scala:291:40, ShiftReg.scala:45:23
    .debug_systemjtag_jtag_TCK                                                             (iocell_jtag_TCK_i),	// IOCell.scala:111:23
    .debug_systemjtag_jtag_TMS                                                             (iocell_jtag_TMS_i),	// IOCell.scala:111:23
    .debug_systemjtag_jtag_TDI                                                             (iocell_jtag_TDI_i),	// IOCell.scala:111:23
    .debug_systemjtag_reset                                                                (system_debug_systemjtag_reset_catcher_io_sync_reset),	// ResetCatchAndSync.scala:39:28
    .debug_dmactiveAck                                                                     (dmactiveAck_dmactiveAck_io_q),	// ShiftReg.scala:45:23
    .uart_0_rxd                                                                            (iocell_uart_0_rxd_i),	// IOCell.scala:111:23
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_clock (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_clock),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_reset (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_reset),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_clock (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_clock),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_reset (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_reset),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_clock (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_clock),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_reset (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_reset),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_clock (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_clock),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_reset (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_reset),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_clock (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_clock),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_reset (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_reset),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_clock (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_clock),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_reset (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_reset),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_clock   (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_clock),
    .auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_reset   (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_reset),
    .auto_subsystem_mbus_fixedClockNode_out_clock                                          (axi4_mem_0_clock),
    .auto_subsystem_mbus_fixedClockNode_out_reset                                          (axi4_mem_0_reset),
    .auto_subsystem_cbus_fixedClockNode_out_clock                                          (system_auto_subsystem_cbus_fixedClockNode_out_clock),
    .auto_subsystem_cbus_fixedClockNode_out_reset                                          (system_auto_subsystem_cbus_fixedClockNode_out_reset),
    .mem_axi4_0_aw_valid                                                                   (axi4_mem_0_bits_aw_valid),
    .mem_axi4_0_aw_bits_id                                                                 (axi4_mem_0_bits_aw_bits_id),
    .mem_axi4_0_aw_bits_addr                                                               (axi4_mem_0_bits_aw_bits_addr),
    .mem_axi4_0_aw_bits_len                                                                (axi4_mem_0_bits_aw_bits_len),
    .mem_axi4_0_aw_bits_size                                                               (axi4_mem_0_bits_aw_bits_size),
    .mem_axi4_0_aw_bits_burst                                                              (axi4_mem_0_bits_aw_bits_burst),
    .mem_axi4_0_aw_bits_lock                                                               (axi4_mem_0_bits_aw_bits_lock),
    .mem_axi4_0_aw_bits_cache                                                              (axi4_mem_0_bits_aw_bits_cache),
    .mem_axi4_0_aw_bits_prot                                                               (axi4_mem_0_bits_aw_bits_prot),
    .mem_axi4_0_aw_bits_qos                                                                (axi4_mem_0_bits_aw_bits_qos),
    .mem_axi4_0_w_valid                                                                    (axi4_mem_0_bits_w_valid),
    .mem_axi4_0_w_bits_data                                                                (axi4_mem_0_bits_w_bits_data),
    .mem_axi4_0_w_bits_strb                                                                (axi4_mem_0_bits_w_bits_strb),
    .mem_axi4_0_w_bits_last                                                                (axi4_mem_0_bits_w_bits_last),
    .mem_axi4_0_b_ready                                                                    (axi4_mem_0_bits_b_ready),
    .mem_axi4_0_ar_valid                                                                   (axi4_mem_0_bits_ar_valid),
    .mem_axi4_0_ar_bits_id                                                                 (axi4_mem_0_bits_ar_bits_id),
    .mem_axi4_0_ar_bits_addr                                                               (axi4_mem_0_bits_ar_bits_addr),
    .mem_axi4_0_ar_bits_len                                                                (axi4_mem_0_bits_ar_bits_len),
    .mem_axi4_0_ar_bits_size                                                               (axi4_mem_0_bits_ar_bits_size),
    .mem_axi4_0_ar_bits_burst                                                              (axi4_mem_0_bits_ar_bits_burst),
    .mem_axi4_0_ar_bits_lock                                                               (axi4_mem_0_bits_ar_bits_lock),
    .mem_axi4_0_ar_bits_cache                                                              (axi4_mem_0_bits_ar_bits_cache),
    .mem_axi4_0_ar_bits_prot                                                               (axi4_mem_0_bits_ar_bits_prot),
    .mem_axi4_0_ar_bits_qos                                                                (axi4_mem_0_bits_ar_bits_qos),
    .mem_axi4_0_r_ready                                                                    (axi4_mem_0_bits_r_ready),
    .serial_tl_clock                                                                       (system_serial_tl_clock),
    .serial_tl_bits_in_ready                                                               (system_serial_tl_bits_in_ready),
    .serial_tl_bits_out_valid                                                              (system_serial_tl_bits_out_valid),
    .serial_tl_bits_out_bits                                                               (system_serial_tl_bits_out_bits),
    .debug_systemjtag_jtag_TDO_data                                                        (system_debug_systemjtag_jtag_TDO_data),
    .debug_systemjtag_jtag_TDO_driven                                                      (system_debug_systemjtag_jtag_TDO_driven),
    .debug_ndreset                                                                         (system_debug_ndreset),
    .debug_dmactive                                                                        (system_debug_dmactive),
    .uart_0_txd                                                                            (system_uart_0_txd)
  );
  ClockGroupAggregator_6 aggregator (	// Clocks.scala:79:32
    .auto_in_member_allClocks_subsystem_cbus_0_clock                  (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_cbus_0_clock),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_subsystem_cbus_0_reset                  (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_cbus_0_reset),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_subsystem_mbus_0_clock                  (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_mbus_0_clock),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_subsystem_mbus_0_reset                  (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_mbus_0_reset),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_subsystem_fbus_0_clock                  (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_fbus_0_clock),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_subsystem_fbus_0_reset                  (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_fbus_0_reset),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_subsystem_pbus_0_clock                  (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_pbus_0_clock),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_subsystem_pbus_0_reset                  (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_pbus_0_reset),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_subsystem_sbus_1_clock                  (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_1_clock),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_subsystem_sbus_1_reset                  (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_1_reset),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_subsystem_sbus_0_clock                  (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_0_clock),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_subsystem_sbus_0_reset                  (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_0_reset),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_implicit_clock_clock                    (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_implicit_clock_clock),	// ClockGroupNamePrefixer.scala:68:15
    .auto_in_member_allClocks_implicit_clock_reset                    (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_implicit_clock_reset),	// ClockGroupNamePrefixer.scala:68:15
    .auto_out_5_member_subsystem_cbus_subsystem_cbus_0_clock          (aggregator_auto_out_5_member_subsystem_cbus_subsystem_cbus_0_clock),
    .auto_out_5_member_subsystem_cbus_subsystem_cbus_0_reset          (aggregator_auto_out_5_member_subsystem_cbus_subsystem_cbus_0_reset),
    .auto_out_4_member_subsystem_mbus_subsystem_mbus_0_clock          (aggregator_auto_out_4_member_subsystem_mbus_subsystem_mbus_0_clock),
    .auto_out_4_member_subsystem_mbus_subsystem_mbus_0_reset          (aggregator_auto_out_4_member_subsystem_mbus_subsystem_mbus_0_reset),
    .auto_out_3_member_subsystem_fbus_subsystem_fbus_0_clock          (aggregator_auto_out_3_member_subsystem_fbus_subsystem_fbus_0_clock),
    .auto_out_3_member_subsystem_fbus_subsystem_fbus_0_reset          (aggregator_auto_out_3_member_subsystem_fbus_subsystem_fbus_0_reset),
    .auto_out_2_member_subsystem_pbus_subsystem_pbus_0_clock          (aggregator_auto_out_2_member_subsystem_pbus_subsystem_pbus_0_clock),
    .auto_out_2_member_subsystem_pbus_subsystem_pbus_0_reset          (aggregator_auto_out_2_member_subsystem_pbus_subsystem_pbus_0_reset),
    .auto_out_1_member_subsystem_sbus_subsystem_sbus_1_clock          (aggregator_auto_out_1_member_subsystem_sbus_subsystem_sbus_1_clock),
    .auto_out_1_member_subsystem_sbus_subsystem_sbus_1_reset          (aggregator_auto_out_1_member_subsystem_sbus_subsystem_sbus_1_reset),
    .auto_out_1_member_subsystem_sbus_subsystem_sbus_0_clock          (aggregator_auto_out_1_member_subsystem_sbus_subsystem_sbus_0_clock),
    .auto_out_1_member_subsystem_sbus_subsystem_sbus_0_reset          (aggregator_auto_out_1_member_subsystem_sbus_subsystem_sbus_0_reset),
    .auto_out_0_member_dividerOnlyClockGenerator_implicit_clock_clock (aggregator_auto_out_0_member_dividerOnlyClockGenerator_implicit_clock_clock),
    .auto_out_0_member_dividerOnlyClockGenerator_implicit_clock_reset (aggregator_auto_out_0_member_dividerOnlyClockGenerator_implicit_clock_reset)
  );
  ClockGroup_6 dividerOnlyClockGenerator (	// ClockGroup.scala:32:69
    .auto_in_member_dividerOnlyClockGenerator_implicit_clock_clock (aggregator_auto_out_0_member_dividerOnlyClockGenerator_implicit_clock_clock),	// Clocks.scala:79:32
    .auto_in_member_dividerOnlyClockGenerator_implicit_clock_reset (aggregator_auto_out_0_member_dividerOnlyClockGenerator_implicit_clock_reset),	// Clocks.scala:79:32
    .auto_out_clock                                                (dividerOnlyClockGenerator_auto_out_clock),
    .auto_out_reset                                                (dividerOnlyClockGenerator_auto_out_reset)
  );
  ClockGroupParameterModifier dividerOnlyClockGenerator_1 (	// ClockGroupNamePrefixer.scala:32:15
    .auto_divider_only_clock_generator_in_4_member_subsystem_cbus_subsystem_cbus_0_clock (aggregator_auto_out_5_member_subsystem_cbus_subsystem_cbus_0_clock),	// Clocks.scala:79:32
    .auto_divider_only_clock_generator_in_4_member_subsystem_cbus_subsystem_cbus_0_reset (aggregator_auto_out_5_member_subsystem_cbus_subsystem_cbus_0_reset),	// Clocks.scala:79:32
    .auto_divider_only_clock_generator_in_3_member_subsystem_mbus_subsystem_mbus_0_clock (aggregator_auto_out_4_member_subsystem_mbus_subsystem_mbus_0_clock),	// Clocks.scala:79:32
    .auto_divider_only_clock_generator_in_3_member_subsystem_mbus_subsystem_mbus_0_reset (aggregator_auto_out_4_member_subsystem_mbus_subsystem_mbus_0_reset),	// Clocks.scala:79:32
    .auto_divider_only_clock_generator_in_2_member_subsystem_fbus_subsystem_fbus_0_clock (aggregator_auto_out_3_member_subsystem_fbus_subsystem_fbus_0_clock),	// Clocks.scala:79:32
    .auto_divider_only_clock_generator_in_2_member_subsystem_fbus_subsystem_fbus_0_reset (aggregator_auto_out_3_member_subsystem_fbus_subsystem_fbus_0_reset),	// Clocks.scala:79:32
    .auto_divider_only_clock_generator_in_1_member_subsystem_pbus_subsystem_pbus_0_clock (aggregator_auto_out_2_member_subsystem_pbus_subsystem_pbus_0_clock),	// Clocks.scala:79:32
    .auto_divider_only_clock_generator_in_1_member_subsystem_pbus_subsystem_pbus_0_reset (aggregator_auto_out_2_member_subsystem_pbus_subsystem_pbus_0_reset),	// Clocks.scala:79:32
    .auto_divider_only_clock_generator_in_0_member_subsystem_sbus_subsystem_sbus_1_clock (aggregator_auto_out_1_member_subsystem_sbus_subsystem_sbus_1_clock),	// Clocks.scala:79:32
    .auto_divider_only_clock_generator_in_0_member_subsystem_sbus_subsystem_sbus_1_reset (aggregator_auto_out_1_member_subsystem_sbus_subsystem_sbus_1_reset),	// Clocks.scala:79:32
    .auto_divider_only_clock_generator_in_0_member_subsystem_sbus_subsystem_sbus_0_clock (aggregator_auto_out_1_member_subsystem_sbus_subsystem_sbus_0_clock),	// Clocks.scala:79:32
    .auto_divider_only_clock_generator_in_0_member_subsystem_sbus_subsystem_sbus_0_reset (aggregator_auto_out_1_member_subsystem_sbus_subsystem_sbus_0_reset),	// Clocks.scala:79:32
    .auto_divider_only_clock_generator_out_4_member_subsystem_cbus_0_clock               (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_4_member_subsystem_cbus_0_clock),
    .auto_divider_only_clock_generator_out_4_member_subsystem_cbus_0_reset               (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_4_member_subsystem_cbus_0_reset),
    .auto_divider_only_clock_generator_out_3_member_subsystem_mbus_0_clock               (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_3_member_subsystem_mbus_0_clock),
    .auto_divider_only_clock_generator_out_3_member_subsystem_mbus_0_reset               (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_3_member_subsystem_mbus_0_reset),
    .auto_divider_only_clock_generator_out_2_member_subsystem_fbus_0_clock               (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_2_member_subsystem_fbus_0_clock),
    .auto_divider_only_clock_generator_out_2_member_subsystem_fbus_0_reset               (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_2_member_subsystem_fbus_0_reset),
    .auto_divider_only_clock_generator_out_1_member_subsystem_pbus_0_clock               (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_1_member_subsystem_pbus_0_clock),
    .auto_divider_only_clock_generator_out_1_member_subsystem_pbus_0_reset               (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_1_member_subsystem_pbus_0_reset),
    .auto_divider_only_clock_generator_out_0_member_subsystem_sbus_1_clock               (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_0_member_subsystem_sbus_1_clock),
    .auto_divider_only_clock_generator_out_0_member_subsystem_sbus_1_reset               (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_0_member_subsystem_sbus_1_reset),
    .auto_divider_only_clock_generator_out_0_member_subsystem_sbus_0_clock               (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_0_member_subsystem_sbus_0_clock),
    .auto_divider_only_clock_generator_out_0_member_subsystem_sbus_0_reset               (dividerOnlyClockGenerator_1_auto_divider_only_clock_generator_out_0_member_subsystem_sbus_0_reset)
  );
  DividerOnlyClockGenerator dividerOnlyClkGenerator (	// Clocks.scala:90:45
    .auto_divider_only_clk_generator_in_clock                                    (iocell_clock_i),	// IOCell.scala:111:23
    .auto_divider_only_clk_generator_in_reset                                    (reset_wire_iocell_reset_i),	// IOCell.scala:111:23
    .auto_divider_only_clk_generator_out_member_allClocks_subsystem_cbus_0_clock (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_cbus_0_clock),
    .auto_divider_only_clk_generator_out_member_allClocks_subsystem_cbus_0_reset (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_cbus_0_reset),
    .auto_divider_only_clk_generator_out_member_allClocks_subsystem_mbus_0_clock (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_mbus_0_clock),
    .auto_divider_only_clk_generator_out_member_allClocks_subsystem_mbus_0_reset (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_mbus_0_reset),
    .auto_divider_only_clk_generator_out_member_allClocks_subsystem_fbus_0_clock (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_fbus_0_clock),
    .auto_divider_only_clk_generator_out_member_allClocks_subsystem_fbus_0_reset (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_fbus_0_reset),
    .auto_divider_only_clk_generator_out_member_allClocks_subsystem_pbus_0_clock (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_pbus_0_clock),
    .auto_divider_only_clk_generator_out_member_allClocks_subsystem_pbus_0_reset (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_pbus_0_reset),
    .auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_1_clock (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_1_clock),
    .auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_1_reset (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_1_reset),
    .auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_0_clock (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_0_clock),
    .auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_0_reset (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_subsystem_sbus_0_reset),
    .auto_divider_only_clk_generator_out_member_allClocks_implicit_clock_clock   (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_implicit_clock_clock),
    .auto_divider_only_clk_generator_out_member_allClocks_implicit_clock_reset   (dividerOnlyClkGenerator_auto_divider_only_clk_generator_out_member_allClocks_implicit_clock_reset)
  );
  ClockGroupParameterModifier_1 dividerOnlyClockGenerator_2 (	// ClockGroupNamePrefixer.scala:68:15
    .auto_divider_only_clock_generator_in_member_allClocks_subsystem_cbus_0_clock  (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_cbus_0_clock),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_subsystem_cbus_0_reset  (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_cbus_0_reset),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_subsystem_mbus_0_clock  (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_mbus_0_clock),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_subsystem_mbus_0_reset  (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_mbus_0_reset),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_subsystem_fbus_0_clock  (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_fbus_0_clock),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_subsystem_fbus_0_reset  (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_fbus_0_reset),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_subsystem_pbus_0_clock  (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_pbus_0_clock),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_subsystem_pbus_0_reset  (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_pbus_0_reset),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_subsystem_sbus_1_clock  (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_sbus_1_clock),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_subsystem_sbus_1_reset  (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_sbus_1_reset),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_subsystem_sbus_0_clock  (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_sbus_0_clock),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_subsystem_sbus_0_reset  (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_sbus_0_reset),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_implicit_clock_clock    (dividerOnlyClockGenerator_3_auto_out_member_allClocks_implicit_clock_clock),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_in_member_allClocks_implicit_clock_reset    (dividerOnlyClockGenerator_3_auto_out_member_allClocks_implicit_clock_reset),	// ResetSynchronizer.scala:42:69
    .auto_divider_only_clock_generator_out_member_allClocks_subsystem_cbus_0_clock (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_cbus_0_clock),
    .auto_divider_only_clock_generator_out_member_allClocks_subsystem_cbus_0_reset (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_cbus_0_reset),
    .auto_divider_only_clock_generator_out_member_allClocks_subsystem_mbus_0_clock (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_mbus_0_clock),
    .auto_divider_only_clock_generator_out_member_allClocks_subsystem_mbus_0_reset (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_mbus_0_reset),
    .auto_divider_only_clock_generator_out_member_allClocks_subsystem_fbus_0_clock (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_fbus_0_clock),
    .auto_divider_only_clock_generator_out_member_allClocks_subsystem_fbus_0_reset (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_fbus_0_reset),
    .auto_divider_only_clock_generator_out_member_allClocks_subsystem_pbus_0_clock (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_pbus_0_clock),
    .auto_divider_only_clock_generator_out_member_allClocks_subsystem_pbus_0_reset (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_pbus_0_reset),
    .auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_1_clock (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_1_clock),
    .auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_1_reset (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_1_reset),
    .auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_0_clock (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_0_clock),
    .auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_0_reset (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_subsystem_sbus_0_reset),
    .auto_divider_only_clock_generator_out_member_allClocks_implicit_clock_clock   (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_implicit_clock_clock),
    .auto_divider_only_clock_generator_out_member_allClocks_implicit_clock_reset   (dividerOnlyClockGenerator_2_auto_divider_only_clock_generator_out_member_allClocks_implicit_clock_reset)
  );
  ClockGroupResetSynchronizer dividerOnlyClockGenerator_3 (	// ResetSynchronizer.scala:42:69
    .auto_in_member_allClocks_subsystem_cbus_0_clock  (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_clock),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_subsystem_cbus_0_reset  (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_cbus_0_reset),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_subsystem_mbus_0_clock  (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_clock),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_subsystem_mbus_0_reset  (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_mbus_0_reset),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_subsystem_fbus_0_clock  (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_clock),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_subsystem_fbus_0_reset  (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_fbus_0_reset),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_subsystem_pbus_0_clock  (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_clock),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_subsystem_pbus_0_reset  (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_pbus_0_reset),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_subsystem_sbus_1_clock  (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_clock),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_subsystem_sbus_1_reset  (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_1_reset),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_subsystem_sbus_0_clock  (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_clock),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_subsystem_sbus_0_reset  (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_subsystem_sbus_0_reset),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_implicit_clock_clock    (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_clock),	// ChipTop.scala:32:35
    .auto_in_member_allClocks_implicit_clock_reset    (system_auto_domain_resetCtrl_tile_reset_provider_out_member_allClocks_implicit_clock_reset),	// ChipTop.scala:32:35
    .auto_out_member_allClocks_subsystem_cbus_0_clock (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_cbus_0_clock),
    .auto_out_member_allClocks_subsystem_cbus_0_reset (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_cbus_0_reset),
    .auto_out_member_allClocks_subsystem_mbus_0_clock (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_mbus_0_clock),
    .auto_out_member_allClocks_subsystem_mbus_0_reset (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_mbus_0_reset),
    .auto_out_member_allClocks_subsystem_fbus_0_clock (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_fbus_0_clock),
    .auto_out_member_allClocks_subsystem_fbus_0_reset (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_fbus_0_reset),
    .auto_out_member_allClocks_subsystem_pbus_0_clock (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_pbus_0_clock),
    .auto_out_member_allClocks_subsystem_pbus_0_reset (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_pbus_0_reset),
    .auto_out_member_allClocks_subsystem_sbus_1_clock (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_sbus_1_clock),
    .auto_out_member_allClocks_subsystem_sbus_1_reset (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_sbus_1_reset),
    .auto_out_member_allClocks_subsystem_sbus_0_clock (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_sbus_0_clock),
    .auto_out_member_allClocks_subsystem_sbus_0_reset (dividerOnlyClockGenerator_3_auto_out_member_allClocks_subsystem_sbus_0_reset),
    .auto_out_member_allClocks_implicit_clock_clock   (dividerOnlyClockGenerator_3_auto_out_member_allClocks_implicit_clock_clock),
    .auto_out_member_allClocks_implicit_clock_reset   (dividerOnlyClockGenerator_3_auto_out_member_allClocks_implicit_clock_reset)
  );
  FixedClockBroadcast_12 asyncResetBroadcast (	// ClockGroup.scala:106:107
    .auto_in_reset  (reset_wire_iocell_reset_i),	// IOCell.scala:111:23
    .auto_out_clock (asyncResetBroadcast_auto_out_clock),
    .auto_out_reset (asyncResetBroadcast_auto_out_reset)
  );
  ResetCatchAndSync_d3 system_debug_systemjtag_reset_catcher (	// ResetCatchAndSync.scala:39:28
    .clock         (iocell_jtag_TCK_i),	// IOCell.scala:111:23
    .reset         (system_auto_subsystem_cbus_fixedClockNode_out_reset),	// ChipTop.scala:32:35
    .io_sync_reset (system_debug_systemjtag_reset_catcher_io_sync_reset)
  );
  AsyncResetSynchronizerShiftReg_w1_d3_i0 debug_reset_syncd_debug_reset_sync (	// ShiftReg.scala:45:23
    .clock (system_auto_subsystem_cbus_fixedClockNode_out_clock),	// ChipTop.scala:32:35
    .reset (system_debug_systemjtag_reset_catcher_io_sync_reset),	// ResetCatchAndSync.scala:39:28
    .io_d  (1'h1),	// ShiftReg.scala:47:16
    .io_q  (debug_reset_syncd_debug_reset_sync_io_q)
  );
  ResetSynchronizerShiftReg_w1_d3_i0 dmactiveAck_dmactiveAck (	// ShiftReg.scala:45:23
    .clock (system_auto_subsystem_cbus_fixedClockNode_out_clock),	// ChipTop.scala:32:35
    .reset (~debug_reset_syncd_debug_reset_sync_io_q),	// Periphery.scala:291:40, ShiftReg.scala:45:23
    .io_d  (system_debug_dmactive),	// ChipTop.scala:32:35
    .io_q  (dmactiveAck_dmactiveAck_io_q)
  );
  EICG_wrapper gated_clock_debug_clock_gate (	// ClockGate.scala:24:20
    .in      (system_auto_subsystem_cbus_fixedClockNode_out_clock),	// ChipTop.scala:32:35
    .test_en (1'h0),	// ClockGroup.scala:106:107
    .en      (clock_en),	// ClockGate.scala:28:14
    .out     (gated_clock_debug_clock_gate_out)
  );
  GenericDigitalOutIOCell iocell_jtag_TDO (	// IOCell.scala:112:24
    .o   (system_debug_systemjtag_jtag_TDO_data),	// ChipTop.scala:32:35
    .oe  (1'h1),	// ShiftReg.scala:47:16
    .pad (jtag_TDO)
  );
  GenericDigitalInIOCell iocell_jtag_TDI (	// IOCell.scala:111:23
    .pad (jtag_TDI),
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (iocell_jtag_TDI_i)
  );
  GenericDigitalInIOCell iocell_jtag_TMS (	// IOCell.scala:111:23
    .pad (jtag_TMS),
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (iocell_jtag_TMS_i)
  );
  GenericDigitalInIOCell iocell_jtag_TCK (	// IOCell.scala:111:23
    .pad (jtag_TCK),
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (iocell_jtag_TCK_i)
  );
  GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits (	// IOCell.scala:112:24
    .o   (system_serial_tl_bits_out_bits[0]),	// ChipTop.scala:32:35, IOCell.scala:228:40
    .oe  (1'h1),	// ShiftReg.scala:47:16
    .pad (iocell_serial_tl_bits_out_bits_pad)
  );
  GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_1 (	// IOCell.scala:112:24
    .o   (system_serial_tl_bits_out_bits[1]),	// ChipTop.scala:32:35, IOCell.scala:228:40
    .oe  (1'h1),	// ShiftReg.scala:47:16
    .pad (iocell_serial_tl_bits_out_bits_1_pad)
  );
  GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_2 (	// IOCell.scala:112:24
    .o   (system_serial_tl_bits_out_bits[2]),	// ChipTop.scala:32:35, IOCell.scala:228:40
    .oe  (1'h1),	// ShiftReg.scala:47:16
    .pad (iocell_serial_tl_bits_out_bits_2_pad)
  );
  GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_3 (	// IOCell.scala:112:24
    .o   (system_serial_tl_bits_out_bits[3]),	// ChipTop.scala:32:35, IOCell.scala:228:40
    .oe  (1'h1),	// ShiftReg.scala:47:16
    .pad (iocell_serial_tl_bits_out_bits_3_pad)
  );
  GenericDigitalOutIOCell iocell_serial_tl_bits_out_valid (	// IOCell.scala:112:24
    .o   (system_serial_tl_bits_out_valid),	// ChipTop.scala:32:35
    .oe  (1'h1),	// ShiftReg.scala:47:16
    .pad (serial_tl_bits_out_valid)
  );
  GenericDigitalInIOCell iocell_serial_tl_bits_out_ready (	// IOCell.scala:111:23
    .pad (serial_tl_bits_out_ready),
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (iocell_serial_tl_bits_out_ready_i)
  );
  GenericDigitalInIOCell iocell_serial_tl_bits_in_bits (	// IOCell.scala:111:23
    .pad (serial_tl_bits_in_bits[0]),	// IOCell.scala:213:39
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (iocell_serial_tl_bits_in_bits_i)
  );
  GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_1 (	// IOCell.scala:111:23
    .pad (serial_tl_bits_in_bits[1]),	// IOCell.scala:213:39
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (iocell_serial_tl_bits_in_bits_1_i)
  );
  GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_2 (	// IOCell.scala:111:23
    .pad (serial_tl_bits_in_bits[2]),	// IOCell.scala:213:39
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (iocell_serial_tl_bits_in_bits_2_i)
  );
  GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_3 (	// IOCell.scala:111:23
    .pad (serial_tl_bits_in_bits[3]),	// IOCell.scala:213:39
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (iocell_serial_tl_bits_in_bits_3_i)
  );
  GenericDigitalInIOCell iocell_serial_tl_bits_in_valid (	// IOCell.scala:111:23
    .pad (serial_tl_bits_in_valid),
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (iocell_serial_tl_bits_in_valid_i)
  );
  GenericDigitalOutIOCell iocell_serial_tl_bits_in_ready (	// IOCell.scala:112:24
    .o   (system_serial_tl_bits_in_ready),	// ChipTop.scala:32:35
    .oe  (1'h1),	// ShiftReg.scala:47:16
    .pad (serial_tl_bits_in_ready)
  );
  GenericDigitalOutIOCell iocell_serial_tl_clock (	// IOCell.scala:112:24
    .o   (system_serial_tl_clock),	// ChipTop.scala:32:35
    .oe  (1'h1),	// ShiftReg.scala:47:16
    .pad (serial_tl_clock)
  );
  GenericDigitalInIOCell iocell_custom_boot (	// IOCell.scala:111:23
    .pad (custom_boot),
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (iocell_custom_boot_i)
  );
  GenericDigitalInIOCell iocell_uart_0_rxd (	// IOCell.scala:111:23
    .pad (uart_0_rxd),
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (iocell_uart_0_rxd_i)
  );
  GenericDigitalOutIOCell iocell_uart_0_txd (	// IOCell.scala:112:24
    .o   (system_uart_0_txd),	// ChipTop.scala:32:35
    .oe  (1'h1),	// ShiftReg.scala:47:16
    .pad (uart_0_txd)
  );
  GenericDigitalInIOCell reset_wire_iocell_reset (	// IOCell.scala:111:23
    .pad (reset_wire_reset),
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (reset_wire_iocell_reset_i)
  );
  GenericDigitalInIOCell iocell_clock (	// IOCell.scala:111:23
    .pad (clock),
    .ie  (1'h1),	// ShiftReg.scala:47:16
    .i   (iocell_clock_i)
  );
  assign serial_tl_bits_out_bits = {iocell_serial_tl_bits_out_bits_3_pad, iocell_serial_tl_bits_out_bits_2_pad,
                iocell_serial_tl_bits_out_bits_1_pad, iocell_serial_tl_bits_out_bits_pad};	// ../perf/regress/chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.hi.fir:1064299:10, Cat.scala:30:58, IOCell.scala:112:24
endmodule