reduce.mlir

reduced.mlir

module attributes {circt.loweringOptions = "disallowLocalVariables"} {
  sv.verbatim "// Standard header to adapt well known macros to our needs." {symbols = []}
  sv.ifdef "RANDOMIZE_REG_INIT" {
    sv.verbatim "`define RANDOMIZE" {symbols = []}
  }
  sv.verbatim "\0A// RANDOM may be set to an expression that produces a 32-bit random unsigned value." {symbols = []}
  sv.ifdef "RANDOM" {
  } else {
    sv.verbatim "`define RANDOM {$random}" {symbols = []}
  }
  sv.verbatim "\0A// Users can define 'PRINTF_COND' to add an extra gate to prints." {symbols = []}
  sv.ifdef "PRINTF_COND" {
    sv.verbatim "`define PRINTF_COND_ (`PRINTF_COND)" {symbols = []}
  } else {
    sv.verbatim "`define PRINTF_COND_ 1" {symbols = []}
  }
  sv.verbatim "\0A// Users can define 'STOP_COND' to add an extra gate to stop conditions." {symbols = []}
  sv.ifdef "STOP_COND" {
    sv.verbatim "`define STOP_COND_ (`STOP_COND)" {symbols = []}
  } else {
    sv.verbatim "`define STOP_COND_ 1" {symbols = []}
  }
  sv.verbatim "\0A// Users can define INIT_RANDOM as general code that gets injected into the\0A// initializer block for modules with registers." {symbols = []}
  sv.ifdef "INIT_RANDOM" {
  } else {
    sv.verbatim "`define INIT_RANDOM" {symbols = []}
  }
  sv.verbatim "\0A// If using random initialization, you can also define RANDOMIZE_DELAY to\0A// customize the delay used, otherwise 0.002 is used." {symbols = []}
  sv.ifdef "RANDOMIZE_DELAY" {
  } else {
    sv.verbatim "`define RANDOMIZE_DELAY 0.002" {symbols = []}
  }
  sv.verbatim "\0A// Define INIT_RANDOM_PROLOG_ for use in our modules below." {symbols = []}
  sv.ifdef "RANDOMIZE" {
    sv.ifdef "VERILATOR" {
      sv.verbatim "`define INIT_RANDOM_PROLOG_ `INIT_RANDOM" {symbols = []}
    } else {
      sv.verbatim "`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end" {symbols = []}
    }
  } else {
    sv.verbatim "`define INIT_RANDOM_PROLOG_" {symbols = []}
  }
  sv.verbatim "" {symbols = []}
  hw.module.extern @IssueSlot_32(%clock: i1, %reset: i1, %io_grant: i1, %io_brupdate_b1_resolve_mask: i20, %io_brupdate_b1_mispredict_mask: i20, %io_kill: i1, %io_clear: i1, %io_ldspec_miss: i1, %io_wakeup_ports_0_valid: i1, %io_wakeup_ports_0_bits_pdst: i7, %io_wakeup_ports_1_valid: i1, %io_wakeup_ports_1_bits_pdst: i7, %io_wakeup_ports_2_valid: i1, %io_wakeup_ports_2_bits_pdst: i7, %io_wakeup_ports_3_valid: i1, %io_wakeup_ports_3_bits_pdst: i7, %io_wakeup_ports_4_valid: i1, %io_wakeup_ports_4_bits_pdst: i7, %io_wakeup_ports_5_valid: i1, %io_wakeup_ports_5_bits_pdst: i7, %io_wakeup_ports_6_valid: i1, %io_wakeup_ports_6_bits_pdst: i7, %io_wakeup_ports_7_valid: i1, %io_wakeup_ports_7_bits_pdst: i7, %io_wakeup_ports_8_valid: i1, %io_wakeup_ports_8_bits_pdst: i7, %io_wakeup_ports_9_valid: i1, %io_wakeup_ports_9_bits_pdst: i7, %io_spec_ld_wakeup_0_valid: i1, %io_spec_ld_wakeup_0_bits: i7, %io_spec_ld_wakeup_1_valid: i1, %io_spec_ld_wakeup_1_bits: i7, %io_in_uop_valid: i1, %io_in_uop_bits_uopc: i7, %io_in_uop_bits_is_rvc: i1, %io_in_uop_bits_fu_code: i10, %io_in_uop_bits_iw_state: i2, %io_in_uop_bits_iw_p1_poisoned: i1, %io_in_uop_bits_iw_p2_poisoned: i1, %io_in_uop_bits_is_br: i1, %io_in_uop_bits_is_jalr: i1, %io_in_uop_bits_is_jal: i1, %io_in_uop_bits_is_sfb: i1, %io_in_uop_bits_br_mask: i20, %io_in_uop_bits_br_tag: i5, %io_in_uop_bits_ftq_idx: i6, %io_in_uop_bits_edge_inst: i1, %io_in_uop_bits_pc_lob: i6, %io_in_uop_bits_taken: i1, %io_in_uop_bits_imm_packed: i20, %io_in_uop_bits_rob_idx: i7, %io_in_uop_bits_ldq_idx: i5, %io_in_uop_bits_stq_idx: i5, %io_in_uop_bits_pdst: i7, %io_in_uop_bits_prs1: i7, %io_in_uop_bits_prs2: i7, %io_in_uop_bits_prs3: i7, %io_in_uop_bits_prs1_busy: i1, %io_in_uop_bits_prs2_busy: i1, %io_in_uop_bits_prs3_busy: i1, %io_in_uop_bits_ppred_busy: i1, %io_in_uop_bits_bypassable: i1, %io_in_uop_bits_mem_cmd: i5, %io_in_uop_bits_mem_size: i2, %io_in_uop_bits_mem_signed: i1, %io_in_uop_bits_is_fence: i1, %io_in_uop_bits_is_amo: i1, %io_in_uop_bits_uses_ldq: i1, %io_in_uop_bits_uses_stq: i1, %io_in_uop_bits_ldst_val: i1, %io_in_uop_bits_dst_rtype: i2, %io_in_uop_bits_lrs1_rtype: i2, %io_in_uop_bits_lrs2_rtype: i2, %io_in_uop_bits_fp_val: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
  hw.module @IssueUnitCollapsing_2(%clock: i1, %reset: i1, %io_dis_uops_0_valid: i1, %io_dis_uops_0_bits_uopc: i7, %io_dis_uops_0_bits_is_rvc: i1, %io_dis_uops_0_bits_fu_code: i10, %io_dis_uops_0_bits_is_br: i1, %io_dis_uops_0_bits_is_jalr: i1, %io_dis_uops_0_bits_is_jal: i1, %io_dis_uops_0_bits_is_sfb: i1, %io_dis_uops_0_bits_br_mask: i20, %io_dis_uops_0_bits_br_tag: i5, %io_dis_uops_0_bits_ftq_idx: i6, %io_dis_uops_0_bits_edge_inst: i1, %io_dis_uops_0_bits_pc_lob: i6, %io_dis_uops_0_bits_taken: i1, %io_dis_uops_0_bits_imm_packed: i20, %io_dis_uops_0_bits_rob_idx: i7, %io_dis_uops_0_bits_ldq_idx: i5, %io_dis_uops_0_bits_stq_idx: i5, %io_dis_uops_0_bits_pdst: i7, %io_dis_uops_0_bits_prs1: i7, %io_dis_uops_0_bits_prs2: i7, %io_dis_uops_0_bits_prs3: i7, %io_dis_uops_0_bits_prs1_busy: i1, %io_dis_uops_0_bits_prs2_busy: i1, %io_dis_uops_0_bits_exception: i1, %io_dis_uops_0_bits_bypassable: i1, %io_dis_uops_0_bits_mem_cmd: i5, %io_dis_uops_0_bits_mem_size: i2, %io_dis_uops_0_bits_mem_signed: i1, %io_dis_uops_0_bits_is_fence: i1, %io_dis_uops_0_bits_is_fencei: i1, %io_dis_uops_0_bits_is_amo: i1, %io_dis_uops_0_bits_uses_ldq: i1, %io_dis_uops_0_bits_uses_stq: i1, %io_dis_uops_0_bits_ldst_val: i1, %io_dis_uops_0_bits_dst_rtype: i2, %io_dis_uops_0_bits_lrs1_rtype: i2, %io_dis_uops_0_bits_lrs2_rtype: i2, %io_dis_uops_0_bits_fp_val: i1, %io_dis_uops_1_valid: i1, %io_dis_uops_1_bits_uopc: i7, %io_dis_uops_1_bits_is_rvc: i1, %io_dis_uops_1_bits_fu_code: i10, %io_dis_uops_1_bits_is_br: i1, %io_dis_uops_1_bits_is_jalr: i1, %io_dis_uops_1_bits_is_jal: i1, %io_dis_uops_1_bits_is_sfb: i1, %io_dis_uops_1_bits_br_mask: i20, %io_dis_uops_1_bits_br_tag: i5, %io_dis_uops_1_bits_ftq_idx: i6, %io_dis_uops_1_bits_edge_inst: i1, %io_dis_uops_1_bits_pc_lob: i6, %io_dis_uops_1_bits_taken: i1, %io_dis_uops_1_bits_imm_packed: i20, %io_dis_uops_1_bits_rob_idx: i7, %io_dis_uops_1_bits_ldq_idx: i5, %io_dis_uops_1_bits_stq_idx: i5, %io_dis_uops_1_bits_pdst: i7, %io_dis_uops_1_bits_prs1: i7, %io_dis_uops_1_bits_prs2: i7, %io_dis_uops_1_bits_prs3: i7, %io_dis_uops_1_bits_prs1_busy: i1, %io_dis_uops_1_bits_prs2_busy: i1, %io_dis_uops_1_bits_exception: i1, %io_dis_uops_1_bits_bypassable: i1, %io_dis_uops_1_bits_mem_cmd: i5, %io_dis_uops_1_bits_mem_size: i2, %io_dis_uops_1_bits_mem_signed: i1, %io_dis_uops_1_bits_is_fence: i1, %io_dis_uops_1_bits_is_fencei: i1, %io_dis_uops_1_bits_is_amo: i1, %io_dis_uops_1_bits_uses_ldq: i1, %io_dis_uops_1_bits_uses_stq: i1, %io_dis_uops_1_bits_ldst_val: i1, %io_dis_uops_1_bits_dst_rtype: i2, %io_dis_uops_1_bits_lrs1_rtype: i2, %io_dis_uops_1_bits_lrs2_rtype: i2, %io_dis_uops_1_bits_fp_val: i1, %io_dis_uops_2_valid: i1, %io_dis_uops_2_bits_uopc: i7, %io_dis_uops_2_bits_is_rvc: i1, %io_dis_uops_2_bits_fu_code: i10, %io_dis_uops_2_bits_is_br: i1, %io_dis_uops_2_bits_is_jalr: i1, %io_dis_uops_2_bits_is_jal: i1, %io_dis_uops_2_bits_is_sfb: i1, %io_dis_uops_2_bits_br_mask: i20, %io_dis_uops_2_bits_br_tag: i5, %io_dis_uops_2_bits_ftq_idx: i6, %io_dis_uops_2_bits_edge_inst: i1, %io_dis_uops_2_bits_pc_lob: i6, %io_dis_uops_2_bits_taken: i1, %io_dis_uops_2_bits_imm_packed: i20, %io_dis_uops_2_bits_rob_idx: i7, %io_dis_uops_2_bits_ldq_idx: i5, %io_dis_uops_2_bits_stq_idx: i5, %io_dis_uops_2_bits_pdst: i7, %io_dis_uops_2_bits_prs1: i7, %io_dis_uops_2_bits_prs2: i7, %io_dis_uops_2_bits_prs3: i7, %io_dis_uops_2_bits_prs1_busy: i1, %io_dis_uops_2_bits_prs2_busy: i1, %io_dis_uops_2_bits_exception: i1, %io_dis_uops_2_bits_bypassable: i1, %io_dis_uops_2_bits_mem_cmd: i5, %io_dis_uops_2_bits_mem_size: i2, %io_dis_uops_2_bits_mem_signed: i1, %io_dis_uops_2_bits_is_fence: i1, %io_dis_uops_2_bits_is_fencei: i1, %io_dis_uops_2_bits_is_amo: i1, %io_dis_uops_2_bits_uses_ldq: i1, %io_dis_uops_2_bits_uses_stq: i1, %io_dis_uops_2_bits_ldst_val: i1, %io_dis_uops_2_bits_dst_rtype: i2, %io_dis_uops_2_bits_lrs1_rtype: i2, %io_dis_uops_2_bits_lrs2_rtype: i2, %io_dis_uops_2_bits_fp_val: i1, %io_dis_uops_3_valid: i1, %io_dis_uops_3_bits_uopc: i7, %io_dis_uops_3_bits_is_rvc: i1, %io_dis_uops_3_bits_fu_code: i10, %io_dis_uops_3_bits_is_br: i1, %io_dis_uops_3_bits_is_jalr: i1, %io_dis_uops_3_bits_is_jal: i1, %io_dis_uops_3_bits_is_sfb: i1, %io_dis_uops_3_bits_br_mask: i20, %io_dis_uops_3_bits_br_tag: i5, %io_dis_uops_3_bits_ftq_idx: i6, %io_dis_uops_3_bits_edge_inst: i1, %io_dis_uops_3_bits_pc_lob: i6, %io_dis_uops_3_bits_taken: i1, %io_dis_uops_3_bits_imm_packed: i20, %io_dis_uops_3_bits_rob_idx: i7, %io_dis_uops_3_bits_ldq_idx: i5, %io_dis_uops_3_bits_stq_idx: i5, %io_dis_uops_3_bits_pdst: i7, %io_dis_uops_3_bits_prs1: i7, %io_dis_uops_3_bits_prs2: i7, %io_dis_uops_3_bits_prs3: i7, %io_dis_uops_3_bits_prs1_busy: i1, %io_dis_uops_3_bits_prs2_busy: i1, %io_dis_uops_3_bits_exception: i1, %io_dis_uops_3_bits_bypassable: i1, %io_dis_uops_3_bits_mem_cmd: i5, %io_dis_uops_3_bits_mem_size: i2, %io_dis_uops_3_bits_mem_signed: i1, %io_dis_uops_3_bits_is_fence: i1, %io_dis_uops_3_bits_is_fencei: i1, %io_dis_uops_3_bits_is_amo: i1, %io_dis_uops_3_bits_uses_ldq: i1, %io_dis_uops_3_bits_uses_stq: i1, %io_dis_uops_3_bits_ldst_val: i1, %io_dis_uops_3_bits_dst_rtype: i2, %io_dis_uops_3_bits_lrs1_rtype: i2, %io_dis_uops_3_bits_lrs2_rtype: i2, %io_dis_uops_3_bits_fp_val: i1, %io_wakeup_ports_0_valid: i1, %io_wakeup_ports_0_bits_pdst: i7, %io_wakeup_ports_1_valid: i1, %io_wakeup_ports_1_bits_pdst: i7, %io_wakeup_ports_2_valid: i1, %io_wakeup_ports_2_bits_pdst: i7, %io_wakeup_ports_3_valid: i1, %io_wakeup_ports_3_bits_pdst: i7, %io_wakeup_ports_4_valid: i1, %io_wakeup_ports_4_bits_pdst: i7, %io_wakeup_ports_5_valid: i1, %io_wakeup_ports_5_bits_pdst: i7, %io_wakeup_ports_6_valid: i1, %io_wakeup_ports_6_bits_pdst: i7, %io_wakeup_ports_7_valid: i1, %io_wakeup_ports_7_bits_pdst: i7, %io_wakeup_ports_8_valid: i1, %io_wakeup_ports_8_bits_pdst: i7, %io_wakeup_ports_9_valid: i1, %io_wakeup_ports_9_bits_pdst: i7, %io_spec_ld_wakeup_0_valid: i1, %io_spec_ld_wakeup_0_bits: i7, %io_spec_ld_wakeup_1_valid: i1, %io_spec_ld_wakeup_1_bits: i7, %io_fu_types_0: i10, %io_fu_types_2: i10, %io_fu_types_3: i10, %io_brupdate_b1_resolve_mask: i20, %io_brupdate_b1_mispredict_mask: i20, %io_flush_pipeline: i1, %io_ld_miss: i1) -> (io_dis_uops_0_ready: i1, io_dis_uops_1_ready: i1, io_dis_uops_2_ready: i1, io_dis_uops_3_ready: i1, io_iss_valids_0: i1, io_iss_valids_1: i1, io_iss_valids_2: i1, io_iss_valids_3: i1, io_iss_uops_0_uopc: i7, io_iss_uops_0_is_rvc: i1, io_iss_uops_0_fu_code: i10, io_iss_uops_0_iw_p1_poisoned: i1, io_iss_uops_0_iw_p2_poisoned: i1, io_iss_uops_0_is_br: i1, io_iss_uops_0_is_jalr: i1, io_iss_uops_0_is_jal: i1, io_iss_uops_0_is_sfb: i1, io_iss_uops_0_br_mask: i20, io_iss_uops_0_br_tag: i5, io_iss_uops_0_ftq_idx: i6, io_iss_uops_0_edge_inst: i1, io_iss_uops_0_pc_lob: i6, io_iss_uops_0_taken: i1, io_iss_uops_0_imm_packed: i20, io_iss_uops_0_rob_idx: i7, io_iss_uops_0_ldq_idx: i5, io_iss_uops_0_stq_idx: i5, io_iss_uops_0_pdst: i7, io_iss_uops_0_prs1: i7, io_iss_uops_0_prs2: i7, io_iss_uops_0_bypassable: i1, io_iss_uops_0_mem_cmd: i5, io_iss_uops_0_is_amo: i1, io_iss_uops_0_uses_stq: i1, io_iss_uops_0_ldst_val: i1, io_iss_uops_0_dst_rtype: i2, io_iss_uops_0_lrs1_rtype: i2, io_iss_uops_0_lrs2_rtype: i2, io_iss_uops_0_fp_val: i1, io_iss_uops_1_uopc: i7, io_iss_uops_1_is_rvc: i1, io_iss_uops_1_fu_code: i10, io_iss_uops_1_iw_p1_poisoned: i1, io_iss_uops_1_iw_p2_poisoned: i1, io_iss_uops_1_is_br: i1, io_iss_uops_1_is_jalr: i1, io_iss_uops_1_is_jal: i1, io_iss_uops_1_is_sfb: i1, io_iss_uops_1_br_mask: i20, io_iss_uops_1_br_tag: i5, io_iss_uops_1_ftq_idx: i6, io_iss_uops_1_edge_inst: i1, io_iss_uops_1_pc_lob: i6, io_iss_uops_1_taken: i1, io_iss_uops_1_imm_packed: i20, io_iss_uops_1_rob_idx: i7, io_iss_uops_1_ldq_idx: i5, io_iss_uops_1_stq_idx: i5, io_iss_uops_1_pdst: i7, io_iss_uops_1_prs1: i7, io_iss_uops_1_prs2: i7, io_iss_uops_1_bypassable: i1, io_iss_uops_1_mem_cmd: i5, io_iss_uops_1_is_amo: i1, io_iss_uops_1_uses_stq: i1, io_iss_uops_1_ldst_val: i1, io_iss_uops_1_dst_rtype: i2, io_iss_uops_1_lrs1_rtype: i2, io_iss_uops_1_lrs2_rtype: i2, io_iss_uops_2_uopc: i7, io_iss_uops_2_is_rvc: i1, io_iss_uops_2_fu_code: i10, io_iss_uops_2_iw_p1_poisoned: i1, io_iss_uops_2_iw_p2_poisoned: i1, io_iss_uops_2_is_br: i1, io_iss_uops_2_is_jalr: i1, io_iss_uops_2_is_jal: i1, io_iss_uops_2_is_sfb: i1, io_iss_uops_2_br_mask: i20, io_iss_uops_2_br_tag: i5, io_iss_uops_2_ftq_idx: i6, io_iss_uops_2_edge_inst: i1, io_iss_uops_2_pc_lob: i6, io_iss_uops_2_taken: i1, io_iss_uops_2_imm_packed: i20, io_iss_uops_2_rob_idx: i7, io_iss_uops_2_ldq_idx: i5, io_iss_uops_2_stq_idx: i5, io_iss_uops_2_pdst: i7, io_iss_uops_2_prs1: i7, io_iss_uops_2_prs2: i7, io_iss_uops_2_bypassable: i1, io_iss_uops_2_mem_cmd: i5, io_iss_uops_2_is_amo: i1, io_iss_uops_2_uses_stq: i1, io_iss_uops_2_ldst_val: i1, io_iss_uops_2_dst_rtype: i2, io_iss_uops_2_lrs1_rtype: i2, io_iss_uops_2_lrs2_rtype: i2, io_iss_uops_3_uopc: i7, io_iss_uops_3_is_rvc: i1, io_iss_uops_3_fu_code: i10, io_iss_uops_3_iw_p1_poisoned: i1, io_iss_uops_3_iw_p2_poisoned: i1, io_iss_uops_3_is_br: i1, io_iss_uops_3_is_jalr: i1, io_iss_uops_3_is_jal: i1, io_iss_uops_3_is_sfb: i1, io_iss_uops_3_br_mask: i20, io_iss_uops_3_br_tag: i5, io_iss_uops_3_ftq_idx: i6, io_iss_uops_3_edge_inst: i1, io_iss_uops_3_pc_lob: i6, io_iss_uops_3_taken: i1, io_iss_uops_3_imm_packed: i20, io_iss_uops_3_rob_idx: i7, io_iss_uops_3_ldq_idx: i5, io_iss_uops_3_stq_idx: i5, io_iss_uops_3_pdst: i7, io_iss_uops_3_prs1: i7, io_iss_uops_3_prs2: i7, io_iss_uops_3_bypassable: i1, io_iss_uops_3_mem_cmd: i5, io_iss_uops_3_is_amo: i1, io_iss_uops_3_uses_stq: i1, io_iss_uops_3_ldst_val: i1, io_iss_uops_3_dst_rtype: i2, io_iss_uops_3_lrs1_rtype: i2, io_iss_uops_3_lrs2_rtype: i2) {
    %false = hw.constant false
    %true = hw.constant true
    %c0_i4 = hw.constant 0 : i4
    %c0_i5 = hw.constant 0 : i5
    %c0_i2 = hw.constant 0 : i2
    %c1_i4 = hw.constant 1 : i4
    %c1_i2 = hw.constant 1 : i2
    %c-2_i2 = hw.constant -2 : i2
    %c0_i3 = hw.constant 0 : i3
    %c5_i6 = hw.constant 5 : i6
    %c2_i7 = hw.constant 2 : i7
    %c-61_i7 = hw.constant -61 : i7
    %c0_i10 = hw.constant 0 : i10
    %c2_i4 = hw.constant 2 : i4
    %c4_i4 = hw.constant 4 : i4
    %c-8_i4 = hw.constant -8 : i4
    %c0_i7 = hw.constant 0 : i7
    %c0_i20 = hw.constant 0 : i20
    %c0_i6 = hw.constant 0 : i6
    %c2_i6 = hw.constant 2 : i6
    %slots_0.io_valid, %slots_0.io_will_be_valid, %slots_0.io_request, %slots_0.io_out_uop_uopc, %slots_0.io_out_uop_is_rvc, %slots_0.io_out_uop_fu_code, %slots_0.io_out_uop_iw_state, %slots_0.io_out_uop_iw_p1_poisoned, %slots_0.io_out_uop_iw_p2_poisoned, %slots_0.io_out_uop_is_br, %slots_0.io_out_uop_is_jalr, %slots_0.io_out_uop_is_jal, %slots_0.io_out_uop_is_sfb, %slots_0.io_out_uop_br_mask, %slots_0.io_out_uop_br_tag, %slots_0.io_out_uop_ftq_idx, %slots_0.io_out_uop_edge_inst, %slots_0.io_out_uop_pc_lob, %slots_0.io_out_uop_taken, %slots_0.io_out_uop_imm_packed, %slots_0.io_out_uop_rob_idx, %slots_0.io_out_uop_ldq_idx, %slots_0.io_out_uop_stq_idx, %slots_0.io_out_uop_pdst, %slots_0.io_out_uop_prs1, %slots_0.io_out_uop_prs2, %slots_0.io_out_uop_prs3, %slots_0.io_out_uop_prs1_busy, %slots_0.io_out_uop_prs2_busy, %slots_0.io_out_uop_prs3_busy, %slots_0.io_out_uop_ppred_busy, %slots_0.io_out_uop_bypassable, %slots_0.io_out_uop_mem_cmd, %slots_0.io_out_uop_mem_size, %slots_0.io_out_uop_mem_signed, %slots_0.io_out_uop_is_fence, %slots_0.io_out_uop_is_amo, %slots_0.io_out_uop_uses_ldq, %slots_0.io_out_uop_uses_stq, %slots_0.io_out_uop_ldst_val, %slots_0.io_out_uop_dst_rtype, %slots_0.io_out_uop_lrs1_rtype, %slots_0.io_out_uop_lrs2_rtype, %slots_0.io_out_uop_fp_val, %slots_0.io_uop_uopc, %slots_0.io_uop_is_rvc, %slots_0.io_uop_fu_code, %slots_0.io_uop_iw_p1_poisoned, %slots_0.io_uop_iw_p2_poisoned, %slots_0.io_uop_is_br, %slots_0.io_uop_is_jalr, %slots_0.io_uop_is_jal, %slots_0.io_uop_is_sfb, %slots_0.io_uop_br_mask, %slots_0.io_uop_br_tag, %slots_0.io_uop_ftq_idx, %slots_0.io_uop_edge_inst, %slots_0.io_uop_pc_lob, %slots_0.io_uop_taken, %slots_0.io_uop_imm_packed, %slots_0.io_uop_rob_idx, %slots_0.io_uop_ldq_idx, %slots_0.io_uop_stq_idx, %slots_0.io_uop_pdst, %slots_0.io_uop_prs1, %slots_0.io_uop_prs2, %slots_0.io_uop_bypassable, %slots_0.io_uop_mem_cmd, %slots_0.io_uop_mem_size, %slots_0.io_uop_mem_signed, %slots_0.io_uop_is_fence, %slots_0.io_uop_is_amo, %slots_0.io_uop_uses_ldq, %slots_0.io_uop_uses_stq, %slots_0.io_uop_ldst_val, %slots_0.io_uop_dst_rtype, %slots_0.io_uop_lrs1_rtype, %slots_0.io_uop_lrs2_rtype, %slots_0.io_uop_fp_val = hw.instance "slots_0" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %178: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %false: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %2081: i1, io_in_uop_bits_uopc: %10732: i7, io_in_uop_bits_is_rvc: %10733: i1, io_in_uop_bits_fu_code: %10734: i10, io_in_uop_bits_iw_state: %10735: i2, io_in_uop_bits_iw_p1_poisoned: %10736: i1, io_in_uop_bits_iw_p2_poisoned: %10737: i1, io_in_uop_bits_is_br: %10738: i1, io_in_uop_bits_is_jalr: %10739: i1, io_in_uop_bits_is_jal: %10740: i1, io_in_uop_bits_is_sfb: %10741: i1, io_in_uop_bits_br_mask: %10742: i20, io_in_uop_bits_br_tag: %10743: i5, io_in_uop_bits_ftq_idx: %10744: i6, io_in_uop_bits_edge_inst: %10745: i1, io_in_uop_bits_pc_lob: %10746: i6, io_in_uop_bits_taken: %10747: i1, io_in_uop_bits_imm_packed: %10748: i20, io_in_uop_bits_rob_idx: %10749: i7, io_in_uop_bits_ldq_idx: %10750: i5, io_in_uop_bits_stq_idx: %10751: i5, io_in_uop_bits_pdst: %10752: i7, io_in_uop_bits_prs1: %10753: i7, io_in_uop_bits_prs2: %10754: i7, io_in_uop_bits_prs3: %10755: i7, io_in_uop_bits_prs1_busy: %10756: i1, io_in_uop_bits_prs2_busy: %10757: i1, io_in_uop_bits_prs3_busy: %10758: i1, io_in_uop_bits_ppred_busy: %10759: i1, io_in_uop_bits_bypassable: %10760: i1, io_in_uop_bits_mem_cmd: %10761: i5, io_in_uop_bits_mem_size: %10762: i2, io_in_uop_bits_mem_signed: %10763: i1, io_in_uop_bits_is_fence: %10764: i1, io_in_uop_bits_is_amo: %10765: i1, io_in_uop_bits_uses_ldq: %10766: i1, io_in_uop_bits_uses_stq: %10767: i1, io_in_uop_bits_ldst_val: %10768: i1, io_in_uop_bits_dst_rtype: %10769: i2, io_in_uop_bits_lrs1_rtype: %10770: i2, io_in_uop_bits_lrs2_rtype: %10771: i2, io_in_uop_bits_fp_val: %10772: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_1.io_valid, %slots_1.io_will_be_valid, %slots_1.io_request, %slots_1.io_out_uop_uopc, %slots_1.io_out_uop_is_rvc, %slots_1.io_out_uop_fu_code, %slots_1.io_out_uop_iw_state, %slots_1.io_out_uop_iw_p1_poisoned, %slots_1.io_out_uop_iw_p2_poisoned, %slots_1.io_out_uop_is_br, %slots_1.io_out_uop_is_jalr, %slots_1.io_out_uop_is_jal, %slots_1.io_out_uop_is_sfb, %slots_1.io_out_uop_br_mask, %slots_1.io_out_uop_br_tag, %slots_1.io_out_uop_ftq_idx, %slots_1.io_out_uop_edge_inst, %slots_1.io_out_uop_pc_lob, %slots_1.io_out_uop_taken, %slots_1.io_out_uop_imm_packed, %slots_1.io_out_uop_rob_idx, %slots_1.io_out_uop_ldq_idx, %slots_1.io_out_uop_stq_idx, %slots_1.io_out_uop_pdst, %slots_1.io_out_uop_prs1, %slots_1.io_out_uop_prs2, %slots_1.io_out_uop_prs3, %slots_1.io_out_uop_prs1_busy, %slots_1.io_out_uop_prs2_busy, %slots_1.io_out_uop_prs3_busy, %slots_1.io_out_uop_ppred_busy, %slots_1.io_out_uop_bypassable, %slots_1.io_out_uop_mem_cmd, %slots_1.io_out_uop_mem_size, %slots_1.io_out_uop_mem_signed, %slots_1.io_out_uop_is_fence, %slots_1.io_out_uop_is_amo, %slots_1.io_out_uop_uses_ldq, %slots_1.io_out_uop_uses_stq, %slots_1.io_out_uop_ldst_val, %slots_1.io_out_uop_dst_rtype, %slots_1.io_out_uop_lrs1_rtype, %slots_1.io_out_uop_lrs2_rtype, %slots_1.io_out_uop_fp_val, %slots_1.io_uop_uopc, %slots_1.io_uop_is_rvc, %slots_1.io_uop_fu_code, %slots_1.io_uop_iw_p1_poisoned, %slots_1.io_uop_iw_p2_poisoned, %slots_1.io_uop_is_br, %slots_1.io_uop_is_jalr, %slots_1.io_uop_is_jal, %slots_1.io_uop_is_sfb, %slots_1.io_uop_br_mask, %slots_1.io_uop_br_tag, %slots_1.io_uop_ftq_idx, %slots_1.io_uop_edge_inst, %slots_1.io_uop_pc_lob, %slots_1.io_uop_taken, %slots_1.io_uop_imm_packed, %slots_1.io_uop_rob_idx, %slots_1.io_uop_ldq_idx, %slots_1.io_uop_stq_idx, %slots_1.io_uop_pdst, %slots_1.io_uop_prs1, %slots_1.io_uop_prs2, %slots_1.io_uop_bypassable, %slots_1.io_uop_mem_cmd, %slots_1.io_uop_mem_size, %slots_1.io_uop_mem_signed, %slots_1.io_uop_is_fence, %slots_1.io_uop_is_amo, %slots_1.io_uop_uses_ldq, %slots_1.io_uop_uses_stq, %slots_1.io_uop_ldst_val, %slots_1.io_uop_dst_rtype, %slots_1.io_uop_lrs1_rtype, %slots_1.io_uop_lrs2_rtype, %slots_1.io_uop_fp_val = hw.instance "slots_1" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %207: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %1600: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %2172: i1, io_in_uop_bits_uopc: %10773: i7, io_in_uop_bits_is_rvc: %10774: i1, io_in_uop_bits_fu_code: %10775: i10, io_in_uop_bits_iw_state: %10776: i2, io_in_uop_bits_iw_p1_poisoned: %10777: i1, io_in_uop_bits_iw_p2_poisoned: %10778: i1, io_in_uop_bits_is_br: %10779: i1, io_in_uop_bits_is_jalr: %10780: i1, io_in_uop_bits_is_jal: %10781: i1, io_in_uop_bits_is_sfb: %10782: i1, io_in_uop_bits_br_mask: %10783: i20, io_in_uop_bits_br_tag: %10784: i5, io_in_uop_bits_ftq_idx: %10785: i6, io_in_uop_bits_edge_inst: %10786: i1, io_in_uop_bits_pc_lob: %10787: i6, io_in_uop_bits_taken: %10788: i1, io_in_uop_bits_imm_packed: %10789: i20, io_in_uop_bits_rob_idx: %10790: i7, io_in_uop_bits_ldq_idx: %10791: i5, io_in_uop_bits_stq_idx: %10792: i5, io_in_uop_bits_pdst: %10793: i7, io_in_uop_bits_prs1: %10794: i7, io_in_uop_bits_prs2: %10795: i7, io_in_uop_bits_prs3: %10796: i7, io_in_uop_bits_prs1_busy: %10797: i1, io_in_uop_bits_prs2_busy: %10798: i1, io_in_uop_bits_prs3_busy: %10799: i1, io_in_uop_bits_ppred_busy: %10800: i1, io_in_uop_bits_bypassable: %10801: i1, io_in_uop_bits_mem_cmd: %10802: i5, io_in_uop_bits_mem_size: %10803: i2, io_in_uop_bits_mem_signed: %10804: i1, io_in_uop_bits_is_fence: %10805: i1, io_in_uop_bits_is_amo: %10806: i1, io_in_uop_bits_uses_ldq: %10807: i1, io_in_uop_bits_uses_stq: %10808: i1, io_in_uop_bits_ldst_val: %10809: i1, io_in_uop_bits_dst_rtype: %10810: i2, io_in_uop_bits_lrs1_rtype: %10811: i2, io_in_uop_bits_lrs2_rtype: %10812: i2, io_in_uop_bits_fp_val: %10813: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_2.io_valid, %slots_2.io_will_be_valid, %slots_2.io_request, %slots_2.io_out_uop_uopc, %slots_2.io_out_uop_is_rvc, %slots_2.io_out_uop_fu_code, %slots_2.io_out_uop_iw_state, %slots_2.io_out_uop_iw_p1_poisoned, %slots_2.io_out_uop_iw_p2_poisoned, %slots_2.io_out_uop_is_br, %slots_2.io_out_uop_is_jalr, %slots_2.io_out_uop_is_jal, %slots_2.io_out_uop_is_sfb, %slots_2.io_out_uop_br_mask, %slots_2.io_out_uop_br_tag, %slots_2.io_out_uop_ftq_idx, %slots_2.io_out_uop_edge_inst, %slots_2.io_out_uop_pc_lob, %slots_2.io_out_uop_taken, %slots_2.io_out_uop_imm_packed, %slots_2.io_out_uop_rob_idx, %slots_2.io_out_uop_ldq_idx, %slots_2.io_out_uop_stq_idx, %slots_2.io_out_uop_pdst, %slots_2.io_out_uop_prs1, %slots_2.io_out_uop_prs2, %slots_2.io_out_uop_prs3, %slots_2.io_out_uop_prs1_busy, %slots_2.io_out_uop_prs2_busy, %slots_2.io_out_uop_prs3_busy, %slots_2.io_out_uop_ppred_busy, %slots_2.io_out_uop_bypassable, %slots_2.io_out_uop_mem_cmd, %slots_2.io_out_uop_mem_size, %slots_2.io_out_uop_mem_signed, %slots_2.io_out_uop_is_fence, %slots_2.io_out_uop_is_amo, %slots_2.io_out_uop_uses_ldq, %slots_2.io_out_uop_uses_stq, %slots_2.io_out_uop_ldst_val, %slots_2.io_out_uop_dst_rtype, %slots_2.io_out_uop_lrs1_rtype, %slots_2.io_out_uop_lrs2_rtype, %slots_2.io_out_uop_fp_val, %slots_2.io_uop_uopc, %slots_2.io_uop_is_rvc, %slots_2.io_uop_fu_code, %slots_2.io_uop_iw_p1_poisoned, %slots_2.io_uop_iw_p2_poisoned, %slots_2.io_uop_is_br, %slots_2.io_uop_is_jalr, %slots_2.io_uop_is_jal, %slots_2.io_uop_is_sfb, %slots_2.io_uop_br_mask, %slots_2.io_uop_br_tag, %slots_2.io_uop_ftq_idx, %slots_2.io_uop_edge_inst, %slots_2.io_uop_pc_lob, %slots_2.io_uop_taken, %slots_2.io_uop_imm_packed, %slots_2.io_uop_rob_idx, %slots_2.io_uop_ldq_idx, %slots_2.io_uop_stq_idx, %slots_2.io_uop_pdst, %slots_2.io_uop_prs1, %slots_2.io_uop_prs2, %slots_2.io_uop_bypassable, %slots_2.io_uop_mem_cmd, %slots_2.io_uop_mem_size, %slots_2.io_uop_mem_signed, %slots_2.io_uop_is_fence, %slots_2.io_uop_is_amo, %slots_2.io_uop_uses_ldq, %slots_2.io_uop_uses_stq, %slots_2.io_uop_ldst_val, %slots_2.io_uop_dst_rtype, %slots_2.io_uop_lrs1_rtype, %slots_2.io_uop_lrs2_rtype, %slots_2.io_uop_fp_val = hw.instance "slots_2" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %314: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %2264: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %2262: i1, io_in_uop_bits_uopc: %10814: i7, io_in_uop_bits_is_rvc: %10815: i1, io_in_uop_bits_fu_code: %10816: i10, io_in_uop_bits_iw_state: %10817: i2, io_in_uop_bits_iw_p1_poisoned: %10818: i1, io_in_uop_bits_iw_p2_poisoned: %10819: i1, io_in_uop_bits_is_br: %10820: i1, io_in_uop_bits_is_jalr: %10821: i1, io_in_uop_bits_is_jal: %10822: i1, io_in_uop_bits_is_sfb: %10823: i1, io_in_uop_bits_br_mask: %10824: i20, io_in_uop_bits_br_tag: %10825: i5, io_in_uop_bits_ftq_idx: %10826: i6, io_in_uop_bits_edge_inst: %10827: i1, io_in_uop_bits_pc_lob: %10828: i6, io_in_uop_bits_taken: %10829: i1, io_in_uop_bits_imm_packed: %10830: i20, io_in_uop_bits_rob_idx: %10831: i7, io_in_uop_bits_ldq_idx: %10832: i5, io_in_uop_bits_stq_idx: %10833: i5, io_in_uop_bits_pdst: %10834: i7, io_in_uop_bits_prs1: %10835: i7, io_in_uop_bits_prs2: %10836: i7, io_in_uop_bits_prs3: %10837: i7, io_in_uop_bits_prs1_busy: %10838: i1, io_in_uop_bits_prs2_busy: %10839: i1, io_in_uop_bits_prs3_busy: %10840: i1, io_in_uop_bits_ppred_busy: %10841: i1, io_in_uop_bits_bypassable: %10842: i1, io_in_uop_bits_mem_cmd: %10843: i5, io_in_uop_bits_mem_size: %10844: i2, io_in_uop_bits_mem_signed: %10845: i1, io_in_uop_bits_is_fence: %10846: i1, io_in_uop_bits_is_amo: %10847: i1, io_in_uop_bits_uses_ldq: %10848: i1, io_in_uop_bits_uses_stq: %10849: i1, io_in_uop_bits_ldst_val: %10850: i1, io_in_uop_bits_dst_rtype: %10851: i2, io_in_uop_bits_lrs1_rtype: %10852: i2, io_in_uop_bits_lrs2_rtype: %10853: i2, io_in_uop_bits_fp_val: %10854: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_3.io_valid, %slots_3.io_will_be_valid, %slots_3.io_request, %slots_3.io_out_uop_uopc, %slots_3.io_out_uop_is_rvc, %slots_3.io_out_uop_fu_code, %slots_3.io_out_uop_iw_state, %slots_3.io_out_uop_iw_p1_poisoned, %slots_3.io_out_uop_iw_p2_poisoned, %slots_3.io_out_uop_is_br, %slots_3.io_out_uop_is_jalr, %slots_3.io_out_uop_is_jal, %slots_3.io_out_uop_is_sfb, %slots_3.io_out_uop_br_mask, %slots_3.io_out_uop_br_tag, %slots_3.io_out_uop_ftq_idx, %slots_3.io_out_uop_edge_inst, %slots_3.io_out_uop_pc_lob, %slots_3.io_out_uop_taken, %slots_3.io_out_uop_imm_packed, %slots_3.io_out_uop_rob_idx, %slots_3.io_out_uop_ldq_idx, %slots_3.io_out_uop_stq_idx, %slots_3.io_out_uop_pdst, %slots_3.io_out_uop_prs1, %slots_3.io_out_uop_prs2, %slots_3.io_out_uop_prs3, %slots_3.io_out_uop_prs1_busy, %slots_3.io_out_uop_prs2_busy, %slots_3.io_out_uop_prs3_busy, %slots_3.io_out_uop_ppred_busy, %slots_3.io_out_uop_bypassable, %slots_3.io_out_uop_mem_cmd, %slots_3.io_out_uop_mem_size, %slots_3.io_out_uop_mem_signed, %slots_3.io_out_uop_is_fence, %slots_3.io_out_uop_is_amo, %slots_3.io_out_uop_uses_ldq, %slots_3.io_out_uop_uses_stq, %slots_3.io_out_uop_ldst_val, %slots_3.io_out_uop_dst_rtype, %slots_3.io_out_uop_lrs1_rtype, %slots_3.io_out_uop_lrs2_rtype, %slots_3.io_out_uop_fp_val, %slots_3.io_uop_uopc, %slots_3.io_uop_is_rvc, %slots_3.io_uop_fu_code, %slots_3.io_uop_iw_p1_poisoned, %slots_3.io_uop_iw_p2_poisoned, %slots_3.io_uop_is_br, %slots_3.io_uop_is_jalr, %slots_3.io_uop_is_jal, %slots_3.io_uop_is_sfb, %slots_3.io_uop_br_mask, %slots_3.io_uop_br_tag, %slots_3.io_uop_ftq_idx, %slots_3.io_uop_edge_inst, %slots_3.io_uop_pc_lob, %slots_3.io_uop_taken, %slots_3.io_uop_imm_packed, %slots_3.io_uop_rob_idx, %slots_3.io_uop_ldq_idx, %slots_3.io_uop_stq_idx, %slots_3.io_uop_pdst, %slots_3.io_uop_prs1, %slots_3.io_uop_prs2, %slots_3.io_uop_bypassable, %slots_3.io_uop_mem_cmd, %slots_3.io_uop_mem_size, %slots_3.io_uop_mem_signed, %slots_3.io_uop_is_fence, %slots_3.io_uop_is_amo, %slots_3.io_uop_uses_ldq, %slots_3.io_uop_uses_stq, %slots_3.io_uop_ldst_val, %slots_3.io_uop_dst_rtype, %slots_3.io_uop_lrs1_rtype, %slots_3.io_uop_lrs2_rtype, %slots_3.io_uop_fp_val = hw.instance "slots_3" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %273: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %2355: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %2354: i1, io_in_uop_bits_uopc: %10855: i7, io_in_uop_bits_is_rvc: %10856: i1, io_in_uop_bits_fu_code: %10857: i10, io_in_uop_bits_iw_state: %10858: i2, io_in_uop_bits_iw_p1_poisoned: %10859: i1, io_in_uop_bits_iw_p2_poisoned: %10860: i1, io_in_uop_bits_is_br: %10861: i1, io_in_uop_bits_is_jalr: %10862: i1, io_in_uop_bits_is_jal: %10863: i1, io_in_uop_bits_is_sfb: %10864: i1, io_in_uop_bits_br_mask: %10865: i20, io_in_uop_bits_br_tag: %10866: i5, io_in_uop_bits_ftq_idx: %10867: i6, io_in_uop_bits_edge_inst: %10868: i1, io_in_uop_bits_pc_lob: %10869: i6, io_in_uop_bits_taken: %10870: i1, io_in_uop_bits_imm_packed: %10871: i20, io_in_uop_bits_rob_idx: %10872: i7, io_in_uop_bits_ldq_idx: %10873: i5, io_in_uop_bits_stq_idx: %10874: i5, io_in_uop_bits_pdst: %10875: i7, io_in_uop_bits_prs1: %10876: i7, io_in_uop_bits_prs2: %10877: i7, io_in_uop_bits_prs3: %10878: i7, io_in_uop_bits_prs1_busy: %10879: i1, io_in_uop_bits_prs2_busy: %10880: i1, io_in_uop_bits_prs3_busy: %10881: i1, io_in_uop_bits_ppred_busy: %10882: i1, io_in_uop_bits_bypassable: %10883: i1, io_in_uop_bits_mem_cmd: %10884: i5, io_in_uop_bits_mem_size: %10885: i2, io_in_uop_bits_mem_signed: %10886: i1, io_in_uop_bits_is_fence: %10887: i1, io_in_uop_bits_is_amo: %10888: i1, io_in_uop_bits_uses_ldq: %10889: i1, io_in_uop_bits_uses_stq: %10890: i1, io_in_uop_bits_ldst_val: %10891: i1, io_in_uop_bits_dst_rtype: %10892: i2, io_in_uop_bits_lrs1_rtype: %10893: i2, io_in_uop_bits_lrs2_rtype: %10894: i2, io_in_uop_bits_fp_val: %10895: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_4.io_valid, %slots_4.io_will_be_valid, %slots_4.io_request, %slots_4.io_out_uop_uopc, %slots_4.io_out_uop_is_rvc, %slots_4.io_out_uop_fu_code, %slots_4.io_out_uop_iw_state, %slots_4.io_out_uop_iw_p1_poisoned, %slots_4.io_out_uop_iw_p2_poisoned, %slots_4.io_out_uop_is_br, %slots_4.io_out_uop_is_jalr, %slots_4.io_out_uop_is_jal, %slots_4.io_out_uop_is_sfb, %slots_4.io_out_uop_br_mask, %slots_4.io_out_uop_br_tag, %slots_4.io_out_uop_ftq_idx, %slots_4.io_out_uop_edge_inst, %slots_4.io_out_uop_pc_lob, %slots_4.io_out_uop_taken, %slots_4.io_out_uop_imm_packed, %slots_4.io_out_uop_rob_idx, %slots_4.io_out_uop_ldq_idx, %slots_4.io_out_uop_stq_idx, %slots_4.io_out_uop_pdst, %slots_4.io_out_uop_prs1, %slots_4.io_out_uop_prs2, %slots_4.io_out_uop_prs3, %slots_4.io_out_uop_prs1_busy, %slots_4.io_out_uop_prs2_busy, %slots_4.io_out_uop_prs3_busy, %slots_4.io_out_uop_ppred_busy, %slots_4.io_out_uop_bypassable, %slots_4.io_out_uop_mem_cmd, %slots_4.io_out_uop_mem_size, %slots_4.io_out_uop_mem_signed, %slots_4.io_out_uop_is_fence, %slots_4.io_out_uop_is_amo, %slots_4.io_out_uop_uses_ldq, %slots_4.io_out_uop_uses_stq, %slots_4.io_out_uop_ldst_val, %slots_4.io_out_uop_dst_rtype, %slots_4.io_out_uop_lrs1_rtype, %slots_4.io_out_uop_lrs2_rtype, %slots_4.io_out_uop_fp_val, %slots_4.io_uop_uopc, %slots_4.io_uop_is_rvc, %slots_4.io_uop_fu_code, %slots_4.io_uop_iw_p1_poisoned, %slots_4.io_uop_iw_p2_poisoned, %slots_4.io_uop_is_br, %slots_4.io_uop_is_jalr, %slots_4.io_uop_is_jal, %slots_4.io_uop_is_sfb, %slots_4.io_uop_br_mask, %slots_4.io_uop_br_tag, %slots_4.io_uop_ftq_idx, %slots_4.io_uop_edge_inst, %slots_4.io_uop_pc_lob, %slots_4.io_uop_taken, %slots_4.io_uop_imm_packed, %slots_4.io_uop_rob_idx, %slots_4.io_uop_ldq_idx, %slots_4.io_uop_stq_idx, %slots_4.io_uop_pdst, %slots_4.io_uop_prs1, %slots_4.io_uop_prs2, %slots_4.io_uop_bypassable, %slots_4.io_uop_mem_cmd, %slots_4.io_uop_mem_size, %slots_4.io_uop_mem_signed, %slots_4.io_uop_is_fence, %slots_4.io_uop_is_amo, %slots_4.io_uop_uses_ldq, %slots_4.io_uop_uses_stq, %slots_4.io_uop_ldst_val, %slots_4.io_uop_dst_rtype, %slots_4.io_uop_lrs1_rtype, %slots_4.io_uop_lrs2_rtype, %slots_4.io_uop_fp_val = hw.instance "slots_4" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %307: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %2446: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %2445: i1, io_in_uop_bits_uopc: %10896: i7, io_in_uop_bits_is_rvc: %10897: i1, io_in_uop_bits_fu_code: %10898: i10, io_in_uop_bits_iw_state: %10899: i2, io_in_uop_bits_iw_p1_poisoned: %10900: i1, io_in_uop_bits_iw_p2_poisoned: %10901: i1, io_in_uop_bits_is_br: %10902: i1, io_in_uop_bits_is_jalr: %10903: i1, io_in_uop_bits_is_jal: %10904: i1, io_in_uop_bits_is_sfb: %10905: i1, io_in_uop_bits_br_mask: %10906: i20, io_in_uop_bits_br_tag: %10907: i5, io_in_uop_bits_ftq_idx: %10908: i6, io_in_uop_bits_edge_inst: %10909: i1, io_in_uop_bits_pc_lob: %10910: i6, io_in_uop_bits_taken: %10911: i1, io_in_uop_bits_imm_packed: %10912: i20, io_in_uop_bits_rob_idx: %10913: i7, io_in_uop_bits_ldq_idx: %10914: i5, io_in_uop_bits_stq_idx: %10915: i5, io_in_uop_bits_pdst: %10916: i7, io_in_uop_bits_prs1: %10917: i7, io_in_uop_bits_prs2: %10918: i7, io_in_uop_bits_prs3: %10919: i7, io_in_uop_bits_prs1_busy: %10920: i1, io_in_uop_bits_prs2_busy: %10921: i1, io_in_uop_bits_prs3_busy: %10922: i1, io_in_uop_bits_ppred_busy: %10923: i1, io_in_uop_bits_bypassable: %10924: i1, io_in_uop_bits_mem_cmd: %10925: i5, io_in_uop_bits_mem_size: %10926: i2, io_in_uop_bits_mem_signed: %10927: i1, io_in_uop_bits_is_fence: %10928: i1, io_in_uop_bits_is_amo: %10929: i1, io_in_uop_bits_uses_ldq: %10930: i1, io_in_uop_bits_uses_stq: %10931: i1, io_in_uop_bits_ldst_val: %10932: i1, io_in_uop_bits_dst_rtype: %10933: i2, io_in_uop_bits_lrs1_rtype: %10934: i2, io_in_uop_bits_lrs2_rtype: %10935: i2, io_in_uop_bits_fp_val: %10936: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_5.io_valid, %slots_5.io_will_be_valid, %slots_5.io_request, %slots_5.io_out_uop_uopc, %slots_5.io_out_uop_is_rvc, %slots_5.io_out_uop_fu_code, %slots_5.io_out_uop_iw_state, %slots_5.io_out_uop_iw_p1_poisoned, %slots_5.io_out_uop_iw_p2_poisoned, %slots_5.io_out_uop_is_br, %slots_5.io_out_uop_is_jalr, %slots_5.io_out_uop_is_jal, %slots_5.io_out_uop_is_sfb, %slots_5.io_out_uop_br_mask, %slots_5.io_out_uop_br_tag, %slots_5.io_out_uop_ftq_idx, %slots_5.io_out_uop_edge_inst, %slots_5.io_out_uop_pc_lob, %slots_5.io_out_uop_taken, %slots_5.io_out_uop_imm_packed, %slots_5.io_out_uop_rob_idx, %slots_5.io_out_uop_ldq_idx, %slots_5.io_out_uop_stq_idx, %slots_5.io_out_uop_pdst, %slots_5.io_out_uop_prs1, %slots_5.io_out_uop_prs2, %slots_5.io_out_uop_prs3, %slots_5.io_out_uop_prs1_busy, %slots_5.io_out_uop_prs2_busy, %slots_5.io_out_uop_prs3_busy, %slots_5.io_out_uop_ppred_busy, %slots_5.io_out_uop_bypassable, %slots_5.io_out_uop_mem_cmd, %slots_5.io_out_uop_mem_size, %slots_5.io_out_uop_mem_signed, %slots_5.io_out_uop_is_fence, %slots_5.io_out_uop_is_amo, %slots_5.io_out_uop_uses_ldq, %slots_5.io_out_uop_uses_stq, %slots_5.io_out_uop_ldst_val, %slots_5.io_out_uop_dst_rtype, %slots_5.io_out_uop_lrs1_rtype, %slots_5.io_out_uop_lrs2_rtype, %slots_5.io_out_uop_fp_val, %slots_5.io_uop_uopc, %slots_5.io_uop_is_rvc, %slots_5.io_uop_fu_code, %slots_5.io_uop_iw_p1_poisoned, %slots_5.io_uop_iw_p2_poisoned, %slots_5.io_uop_is_br, %slots_5.io_uop_is_jalr, %slots_5.io_uop_is_jal, %slots_5.io_uop_is_sfb, %slots_5.io_uop_br_mask, %slots_5.io_uop_br_tag, %slots_5.io_uop_ftq_idx, %slots_5.io_uop_edge_inst, %slots_5.io_uop_pc_lob, %slots_5.io_uop_taken, %slots_5.io_uop_imm_packed, %slots_5.io_uop_rob_idx, %slots_5.io_uop_ldq_idx, %slots_5.io_uop_stq_idx, %slots_5.io_uop_pdst, %slots_5.io_uop_prs1, %slots_5.io_uop_prs2, %slots_5.io_uop_bypassable, %slots_5.io_uop_mem_cmd, %slots_5.io_uop_mem_size, %slots_5.io_uop_mem_signed, %slots_5.io_uop_is_fence, %slots_5.io_uop_is_amo, %slots_5.io_uop_uses_ldq, %slots_5.io_uop_uses_stq, %slots_5.io_uop_ldst_val, %slots_5.io_uop_dst_rtype, %slots_5.io_uop_lrs1_rtype, %slots_5.io_uop_lrs2_rtype, %slots_5.io_uop_fp_val = hw.instance "slots_5" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %353: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %2537: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %2536: i1, io_in_uop_bits_uopc: %10937: i7, io_in_uop_bits_is_rvc: %10938: i1, io_in_uop_bits_fu_code: %10939: i10, io_in_uop_bits_iw_state: %10940: i2, io_in_uop_bits_iw_p1_poisoned: %10941: i1, io_in_uop_bits_iw_p2_poisoned: %10942: i1, io_in_uop_bits_is_br: %10943: i1, io_in_uop_bits_is_jalr: %10944: i1, io_in_uop_bits_is_jal: %10945: i1, io_in_uop_bits_is_sfb: %10946: i1, io_in_uop_bits_br_mask: %10947: i20, io_in_uop_bits_br_tag: %10948: i5, io_in_uop_bits_ftq_idx: %10949: i6, io_in_uop_bits_edge_inst: %10950: i1, io_in_uop_bits_pc_lob: %10951: i6, io_in_uop_bits_taken: %10952: i1, io_in_uop_bits_imm_packed: %10953: i20, io_in_uop_bits_rob_idx: %10954: i7, io_in_uop_bits_ldq_idx: %10955: i5, io_in_uop_bits_stq_idx: %10956: i5, io_in_uop_bits_pdst: %10957: i7, io_in_uop_bits_prs1: %10958: i7, io_in_uop_bits_prs2: %10959: i7, io_in_uop_bits_prs3: %10960: i7, io_in_uop_bits_prs1_busy: %10961: i1, io_in_uop_bits_prs2_busy: %10962: i1, io_in_uop_bits_prs3_busy: %10963: i1, io_in_uop_bits_ppred_busy: %10964: i1, io_in_uop_bits_bypassable: %10965: i1, io_in_uop_bits_mem_cmd: %10966: i5, io_in_uop_bits_mem_size: %10967: i2, io_in_uop_bits_mem_signed: %10968: i1, io_in_uop_bits_is_fence: %10969: i1, io_in_uop_bits_is_amo: %10970: i1, io_in_uop_bits_uses_ldq: %10971: i1, io_in_uop_bits_uses_stq: %10972: i1, io_in_uop_bits_ldst_val: %10973: i1, io_in_uop_bits_dst_rtype: %10974: i2, io_in_uop_bits_lrs1_rtype: %10975: i2, io_in_uop_bits_lrs2_rtype: %10976: i2, io_in_uop_bits_fp_val: %10977: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_6.io_valid, %slots_6.io_will_be_valid, %slots_6.io_request, %slots_6.io_out_uop_uopc, %slots_6.io_out_uop_is_rvc, %slots_6.io_out_uop_fu_code, %slots_6.io_out_uop_iw_state, %slots_6.io_out_uop_iw_p1_poisoned, %slots_6.io_out_uop_iw_p2_poisoned, %slots_6.io_out_uop_is_br, %slots_6.io_out_uop_is_jalr, %slots_6.io_out_uop_is_jal, %slots_6.io_out_uop_is_sfb, %slots_6.io_out_uop_br_mask, %slots_6.io_out_uop_br_tag, %slots_6.io_out_uop_ftq_idx, %slots_6.io_out_uop_edge_inst, %slots_6.io_out_uop_pc_lob, %slots_6.io_out_uop_taken, %slots_6.io_out_uop_imm_packed, %slots_6.io_out_uop_rob_idx, %slots_6.io_out_uop_ldq_idx, %slots_6.io_out_uop_stq_idx, %slots_6.io_out_uop_pdst, %slots_6.io_out_uop_prs1, %slots_6.io_out_uop_prs2, %slots_6.io_out_uop_prs3, %slots_6.io_out_uop_prs1_busy, %slots_6.io_out_uop_prs2_busy, %slots_6.io_out_uop_prs3_busy, %slots_6.io_out_uop_ppred_busy, %slots_6.io_out_uop_bypassable, %slots_6.io_out_uop_mem_cmd, %slots_6.io_out_uop_mem_size, %slots_6.io_out_uop_mem_signed, %slots_6.io_out_uop_is_fence, %slots_6.io_out_uop_is_amo, %slots_6.io_out_uop_uses_ldq, %slots_6.io_out_uop_uses_stq, %slots_6.io_out_uop_ldst_val, %slots_6.io_out_uop_dst_rtype, %slots_6.io_out_uop_lrs1_rtype, %slots_6.io_out_uop_lrs2_rtype, %slots_6.io_out_uop_fp_val, %slots_6.io_uop_uopc, %slots_6.io_uop_is_rvc, %slots_6.io_uop_fu_code, %slots_6.io_uop_iw_p1_poisoned, %slots_6.io_uop_iw_p2_poisoned, %slots_6.io_uop_is_br, %slots_6.io_uop_is_jalr, %slots_6.io_uop_is_jal, %slots_6.io_uop_is_sfb, %slots_6.io_uop_br_mask, %slots_6.io_uop_br_tag, %slots_6.io_uop_ftq_idx, %slots_6.io_uop_edge_inst, %slots_6.io_uop_pc_lob, %slots_6.io_uop_taken, %slots_6.io_uop_imm_packed, %slots_6.io_uop_rob_idx, %slots_6.io_uop_ldq_idx, %slots_6.io_uop_stq_idx, %slots_6.io_uop_pdst, %slots_6.io_uop_prs1, %slots_6.io_uop_prs2, %slots_6.io_uop_bypassable, %slots_6.io_uop_mem_cmd, %slots_6.io_uop_mem_size, %slots_6.io_uop_mem_signed, %slots_6.io_uop_is_fence, %slots_6.io_uop_is_amo, %slots_6.io_uop_uses_ldq, %slots_6.io_uop_uses_stq, %slots_6.io_uop_ldst_val, %slots_6.io_uop_dst_rtype, %slots_6.io_uop_lrs1_rtype, %slots_6.io_uop_lrs2_rtype, %slots_6.io_uop_fp_val = hw.instance "slots_6" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %387: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %2628: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %2627: i1, io_in_uop_bits_uopc: %10978: i7, io_in_uop_bits_is_rvc: %10979: i1, io_in_uop_bits_fu_code: %10980: i10, io_in_uop_bits_iw_state: %10981: i2, io_in_uop_bits_iw_p1_poisoned: %10982: i1, io_in_uop_bits_iw_p2_poisoned: %10983: i1, io_in_uop_bits_is_br: %10984: i1, io_in_uop_bits_is_jalr: %10985: i1, io_in_uop_bits_is_jal: %10986: i1, io_in_uop_bits_is_sfb: %10987: i1, io_in_uop_bits_br_mask: %10988: i20, io_in_uop_bits_br_tag: %10989: i5, io_in_uop_bits_ftq_idx: %10990: i6, io_in_uop_bits_edge_inst: %10991: i1, io_in_uop_bits_pc_lob: %10992: i6, io_in_uop_bits_taken: %10993: i1, io_in_uop_bits_imm_packed: %10994: i20, io_in_uop_bits_rob_idx: %10995: i7, io_in_uop_bits_ldq_idx: %10996: i5, io_in_uop_bits_stq_idx: %10997: i5, io_in_uop_bits_pdst: %10998: i7, io_in_uop_bits_prs1: %10999: i7, io_in_uop_bits_prs2: %11000: i7, io_in_uop_bits_prs3: %11001: i7, io_in_uop_bits_prs1_busy: %11002: i1, io_in_uop_bits_prs2_busy: %11003: i1, io_in_uop_bits_prs3_busy: %11004: i1, io_in_uop_bits_ppred_busy: %11005: i1, io_in_uop_bits_bypassable: %11006: i1, io_in_uop_bits_mem_cmd: %11007: i5, io_in_uop_bits_mem_size: %11008: i2, io_in_uop_bits_mem_signed: %11009: i1, io_in_uop_bits_is_fence: %11010: i1, io_in_uop_bits_is_amo: %11011: i1, io_in_uop_bits_uses_ldq: %11012: i1, io_in_uop_bits_uses_stq: %11013: i1, io_in_uop_bits_ldst_val: %11014: i1, io_in_uop_bits_dst_rtype: %11015: i2, io_in_uop_bits_lrs1_rtype: %11016: i2, io_in_uop_bits_lrs2_rtype: %11017: i2, io_in_uop_bits_fp_val: %11018: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_7.io_valid, %slots_7.io_will_be_valid, %slots_7.io_request, %slots_7.io_out_uop_uopc, %slots_7.io_out_uop_is_rvc, %slots_7.io_out_uop_fu_code, %slots_7.io_out_uop_iw_state, %slots_7.io_out_uop_iw_p1_poisoned, %slots_7.io_out_uop_iw_p2_poisoned, %slots_7.io_out_uop_is_br, %slots_7.io_out_uop_is_jalr, %slots_7.io_out_uop_is_jal, %slots_7.io_out_uop_is_sfb, %slots_7.io_out_uop_br_mask, %slots_7.io_out_uop_br_tag, %slots_7.io_out_uop_ftq_idx, %slots_7.io_out_uop_edge_inst, %slots_7.io_out_uop_pc_lob, %slots_7.io_out_uop_taken, %slots_7.io_out_uop_imm_packed, %slots_7.io_out_uop_rob_idx, %slots_7.io_out_uop_ldq_idx, %slots_7.io_out_uop_stq_idx, %slots_7.io_out_uop_pdst, %slots_7.io_out_uop_prs1, %slots_7.io_out_uop_prs2, %slots_7.io_out_uop_prs3, %slots_7.io_out_uop_prs1_busy, %slots_7.io_out_uop_prs2_busy, %slots_7.io_out_uop_prs3_busy, %slots_7.io_out_uop_ppred_busy, %slots_7.io_out_uop_bypassable, %slots_7.io_out_uop_mem_cmd, %slots_7.io_out_uop_mem_size, %slots_7.io_out_uop_mem_signed, %slots_7.io_out_uop_is_fence, %slots_7.io_out_uop_is_amo, %slots_7.io_out_uop_uses_ldq, %slots_7.io_out_uop_uses_stq, %slots_7.io_out_uop_ldst_val, %slots_7.io_out_uop_dst_rtype, %slots_7.io_out_uop_lrs1_rtype, %slots_7.io_out_uop_lrs2_rtype, %slots_7.io_out_uop_fp_val, %slots_7.io_uop_uopc, %slots_7.io_uop_is_rvc, %slots_7.io_uop_fu_code, %slots_7.io_uop_iw_p1_poisoned, %slots_7.io_uop_iw_p2_poisoned, %slots_7.io_uop_is_br, %slots_7.io_uop_is_jalr, %slots_7.io_uop_is_jal, %slots_7.io_uop_is_sfb, %slots_7.io_uop_br_mask, %slots_7.io_uop_br_tag, %slots_7.io_uop_ftq_idx, %slots_7.io_uop_edge_inst, %slots_7.io_uop_pc_lob, %slots_7.io_uop_taken, %slots_7.io_uop_imm_packed, %slots_7.io_uop_rob_idx, %slots_7.io_uop_ldq_idx, %slots_7.io_uop_stq_idx, %slots_7.io_uop_pdst, %slots_7.io_uop_prs1, %slots_7.io_uop_prs2, %slots_7.io_uop_bypassable, %slots_7.io_uop_mem_cmd, %slots_7.io_uop_mem_size, %slots_7.io_uop_mem_signed, %slots_7.io_uop_is_fence, %slots_7.io_uop_is_amo, %slots_7.io_uop_uses_ldq, %slots_7.io_uop_uses_stq, %slots_7.io_uop_ldst_val, %slots_7.io_uop_dst_rtype, %slots_7.io_uop_lrs1_rtype, %slots_7.io_uop_lrs2_rtype, %slots_7.io_uop_fp_val = hw.instance "slots_7" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %494: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %2719: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %2718: i1, io_in_uop_bits_uopc: %11019: i7, io_in_uop_bits_is_rvc: %11020: i1, io_in_uop_bits_fu_code: %11021: i10, io_in_uop_bits_iw_state: %11022: i2, io_in_uop_bits_iw_p1_poisoned: %11023: i1, io_in_uop_bits_iw_p2_poisoned: %11024: i1, io_in_uop_bits_is_br: %11025: i1, io_in_uop_bits_is_jalr: %11026: i1, io_in_uop_bits_is_jal: %11027: i1, io_in_uop_bits_is_sfb: %11028: i1, io_in_uop_bits_br_mask: %11029: i20, io_in_uop_bits_br_tag: %11030: i5, io_in_uop_bits_ftq_idx: %11031: i6, io_in_uop_bits_edge_inst: %11032: i1, io_in_uop_bits_pc_lob: %11033: i6, io_in_uop_bits_taken: %11034: i1, io_in_uop_bits_imm_packed: %11035: i20, io_in_uop_bits_rob_idx: %11036: i7, io_in_uop_bits_ldq_idx: %11037: i5, io_in_uop_bits_stq_idx: %11038: i5, io_in_uop_bits_pdst: %11039: i7, io_in_uop_bits_prs1: %11040: i7, io_in_uop_bits_prs2: %11041: i7, io_in_uop_bits_prs3: %11042: i7, io_in_uop_bits_prs1_busy: %11043: i1, io_in_uop_bits_prs2_busy: %11044: i1, io_in_uop_bits_prs3_busy: %11045: i1, io_in_uop_bits_ppred_busy: %11046: i1, io_in_uop_bits_bypassable: %11047: i1, io_in_uop_bits_mem_cmd: %11048: i5, io_in_uop_bits_mem_size: %11049: i2, io_in_uop_bits_mem_signed: %11050: i1, io_in_uop_bits_is_fence: %11051: i1, io_in_uop_bits_is_amo: %11052: i1, io_in_uop_bits_uses_ldq: %11053: i1, io_in_uop_bits_uses_stq: %11054: i1, io_in_uop_bits_ldst_val: %11055: i1, io_in_uop_bits_dst_rtype: %11056: i2, io_in_uop_bits_lrs1_rtype: %11057: i2, io_in_uop_bits_lrs2_rtype: %11058: i2, io_in_uop_bits_fp_val: %11059: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_8.io_valid, %slots_8.io_will_be_valid, %slots_8.io_request, %slots_8.io_out_uop_uopc, %slots_8.io_out_uop_is_rvc, %slots_8.io_out_uop_fu_code, %slots_8.io_out_uop_iw_state, %slots_8.io_out_uop_iw_p1_poisoned, %slots_8.io_out_uop_iw_p2_poisoned, %slots_8.io_out_uop_is_br, %slots_8.io_out_uop_is_jalr, %slots_8.io_out_uop_is_jal, %slots_8.io_out_uop_is_sfb, %slots_8.io_out_uop_br_mask, %slots_8.io_out_uop_br_tag, %slots_8.io_out_uop_ftq_idx, %slots_8.io_out_uop_edge_inst, %slots_8.io_out_uop_pc_lob, %slots_8.io_out_uop_taken, %slots_8.io_out_uop_imm_packed, %slots_8.io_out_uop_rob_idx, %slots_8.io_out_uop_ldq_idx, %slots_8.io_out_uop_stq_idx, %slots_8.io_out_uop_pdst, %slots_8.io_out_uop_prs1, %slots_8.io_out_uop_prs2, %slots_8.io_out_uop_prs3, %slots_8.io_out_uop_prs1_busy, %slots_8.io_out_uop_prs2_busy, %slots_8.io_out_uop_prs3_busy, %slots_8.io_out_uop_ppred_busy, %slots_8.io_out_uop_bypassable, %slots_8.io_out_uop_mem_cmd, %slots_8.io_out_uop_mem_size, %slots_8.io_out_uop_mem_signed, %slots_8.io_out_uop_is_fence, %slots_8.io_out_uop_is_amo, %slots_8.io_out_uop_uses_ldq, %slots_8.io_out_uop_uses_stq, %slots_8.io_out_uop_ldst_val, %slots_8.io_out_uop_dst_rtype, %slots_8.io_out_uop_lrs1_rtype, %slots_8.io_out_uop_lrs2_rtype, %slots_8.io_out_uop_fp_val, %slots_8.io_uop_uopc, %slots_8.io_uop_is_rvc, %slots_8.io_uop_fu_code, %slots_8.io_uop_iw_p1_poisoned, %slots_8.io_uop_iw_p2_poisoned, %slots_8.io_uop_is_br, %slots_8.io_uop_is_jalr, %slots_8.io_uop_is_jal, %slots_8.io_uop_is_sfb, %slots_8.io_uop_br_mask, %slots_8.io_uop_br_tag, %slots_8.io_uop_ftq_idx, %slots_8.io_uop_edge_inst, %slots_8.io_uop_pc_lob, %slots_8.io_uop_taken, %slots_8.io_uop_imm_packed, %slots_8.io_uop_rob_idx, %slots_8.io_uop_ldq_idx, %slots_8.io_uop_stq_idx, %slots_8.io_uop_pdst, %slots_8.io_uop_prs1, %slots_8.io_uop_prs2, %slots_8.io_uop_bypassable, %slots_8.io_uop_mem_cmd, %slots_8.io_uop_mem_size, %slots_8.io_uop_mem_signed, %slots_8.io_uop_is_fence, %slots_8.io_uop_is_amo, %slots_8.io_uop_uses_ldq, %slots_8.io_uop_uses_stq, %slots_8.io_uop_ldst_val, %slots_8.io_uop_dst_rtype, %slots_8.io_uop_lrs1_rtype, %slots_8.io_uop_lrs2_rtype, %slots_8.io_uop_fp_val = hw.instance "slots_8" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %453: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %2810: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %2809: i1, io_in_uop_bits_uopc: %11060: i7, io_in_uop_bits_is_rvc: %11061: i1, io_in_uop_bits_fu_code: %11062: i10, io_in_uop_bits_iw_state: %11063: i2, io_in_uop_bits_iw_p1_poisoned: %11064: i1, io_in_uop_bits_iw_p2_poisoned: %11065: i1, io_in_uop_bits_is_br: %11066: i1, io_in_uop_bits_is_jalr: %11067: i1, io_in_uop_bits_is_jal: %11068: i1, io_in_uop_bits_is_sfb: %11069: i1, io_in_uop_bits_br_mask: %11070: i20, io_in_uop_bits_br_tag: %11071: i5, io_in_uop_bits_ftq_idx: %11072: i6, io_in_uop_bits_edge_inst: %11073: i1, io_in_uop_bits_pc_lob: %11074: i6, io_in_uop_bits_taken: %11075: i1, io_in_uop_bits_imm_packed: %11076: i20, io_in_uop_bits_rob_idx: %11077: i7, io_in_uop_bits_ldq_idx: %11078: i5, io_in_uop_bits_stq_idx: %11079: i5, io_in_uop_bits_pdst: %11080: i7, io_in_uop_bits_prs1: %11081: i7, io_in_uop_bits_prs2: %11082: i7, io_in_uop_bits_prs3: %11083: i7, io_in_uop_bits_prs1_busy: %11084: i1, io_in_uop_bits_prs2_busy: %11085: i1, io_in_uop_bits_prs3_busy: %11086: i1, io_in_uop_bits_ppred_busy: %11087: i1, io_in_uop_bits_bypassable: %11088: i1, io_in_uop_bits_mem_cmd: %11089: i5, io_in_uop_bits_mem_size: %11090: i2, io_in_uop_bits_mem_signed: %11091: i1, io_in_uop_bits_is_fence: %11092: i1, io_in_uop_bits_is_amo: %11093: i1, io_in_uop_bits_uses_ldq: %11094: i1, io_in_uop_bits_uses_stq: %11095: i1, io_in_uop_bits_ldst_val: %11096: i1, io_in_uop_bits_dst_rtype: %11097: i2, io_in_uop_bits_lrs1_rtype: %11098: i2, io_in_uop_bits_lrs2_rtype: %11099: i2, io_in_uop_bits_fp_val: %11100: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_9.io_valid, %slots_9.io_will_be_valid, %slots_9.io_request, %slots_9.io_out_uop_uopc, %slots_9.io_out_uop_is_rvc, %slots_9.io_out_uop_fu_code, %slots_9.io_out_uop_iw_state, %slots_9.io_out_uop_iw_p1_poisoned, %slots_9.io_out_uop_iw_p2_poisoned, %slots_9.io_out_uop_is_br, %slots_9.io_out_uop_is_jalr, %slots_9.io_out_uop_is_jal, %slots_9.io_out_uop_is_sfb, %slots_9.io_out_uop_br_mask, %slots_9.io_out_uop_br_tag, %slots_9.io_out_uop_ftq_idx, %slots_9.io_out_uop_edge_inst, %slots_9.io_out_uop_pc_lob, %slots_9.io_out_uop_taken, %slots_9.io_out_uop_imm_packed, %slots_9.io_out_uop_rob_idx, %slots_9.io_out_uop_ldq_idx, %slots_9.io_out_uop_stq_idx, %slots_9.io_out_uop_pdst, %slots_9.io_out_uop_prs1, %slots_9.io_out_uop_prs2, %slots_9.io_out_uop_prs3, %slots_9.io_out_uop_prs1_busy, %slots_9.io_out_uop_prs2_busy, %slots_9.io_out_uop_prs3_busy, %slots_9.io_out_uop_ppred_busy, %slots_9.io_out_uop_bypassable, %slots_9.io_out_uop_mem_cmd, %slots_9.io_out_uop_mem_size, %slots_9.io_out_uop_mem_signed, %slots_9.io_out_uop_is_fence, %slots_9.io_out_uop_is_amo, %slots_9.io_out_uop_uses_ldq, %slots_9.io_out_uop_uses_stq, %slots_9.io_out_uop_ldst_val, %slots_9.io_out_uop_dst_rtype, %slots_9.io_out_uop_lrs1_rtype, %slots_9.io_out_uop_lrs2_rtype, %slots_9.io_out_uop_fp_val, %slots_9.io_uop_uopc, %slots_9.io_uop_is_rvc, %slots_9.io_uop_fu_code, %slots_9.io_uop_iw_p1_poisoned, %slots_9.io_uop_iw_p2_poisoned, %slots_9.io_uop_is_br, %slots_9.io_uop_is_jalr, %slots_9.io_uop_is_jal, %slots_9.io_uop_is_sfb, %slots_9.io_uop_br_mask, %slots_9.io_uop_br_tag, %slots_9.io_uop_ftq_idx, %slots_9.io_uop_edge_inst, %slots_9.io_uop_pc_lob, %slots_9.io_uop_taken, %slots_9.io_uop_imm_packed, %slots_9.io_uop_rob_idx, %slots_9.io_uop_ldq_idx, %slots_9.io_uop_stq_idx, %slots_9.io_uop_pdst, %slots_9.io_uop_prs1, %slots_9.io_uop_prs2, %slots_9.io_uop_bypassable, %slots_9.io_uop_mem_cmd, %slots_9.io_uop_mem_size, %slots_9.io_uop_mem_signed, %slots_9.io_uop_is_fence, %slots_9.io_uop_is_amo, %slots_9.io_uop_uses_ldq, %slots_9.io_uop_uses_stq, %slots_9.io_uop_ldst_val, %slots_9.io_uop_dst_rtype, %slots_9.io_uop_lrs1_rtype, %slots_9.io_uop_lrs2_rtype, %slots_9.io_uop_fp_val = hw.instance "slots_9" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %487: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %2901: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %2900: i1, io_in_uop_bits_uopc: %11101: i7, io_in_uop_bits_is_rvc: %11102: i1, io_in_uop_bits_fu_code: %11103: i10, io_in_uop_bits_iw_state: %11104: i2, io_in_uop_bits_iw_p1_poisoned: %11105: i1, io_in_uop_bits_iw_p2_poisoned: %11106: i1, io_in_uop_bits_is_br: %11107: i1, io_in_uop_bits_is_jalr: %11108: i1, io_in_uop_bits_is_jal: %11109: i1, io_in_uop_bits_is_sfb: %11110: i1, io_in_uop_bits_br_mask: %11111: i20, io_in_uop_bits_br_tag: %11112: i5, io_in_uop_bits_ftq_idx: %11113: i6, io_in_uop_bits_edge_inst: %11114: i1, io_in_uop_bits_pc_lob: %11115: i6, io_in_uop_bits_taken: %11116: i1, io_in_uop_bits_imm_packed: %11117: i20, io_in_uop_bits_rob_idx: %11118: i7, io_in_uop_bits_ldq_idx: %11119: i5, io_in_uop_bits_stq_idx: %11120: i5, io_in_uop_bits_pdst: %11121: i7, io_in_uop_bits_prs1: %11122: i7, io_in_uop_bits_prs2: %11123: i7, io_in_uop_bits_prs3: %11124: i7, io_in_uop_bits_prs1_busy: %11125: i1, io_in_uop_bits_prs2_busy: %11126: i1, io_in_uop_bits_prs3_busy: %11127: i1, io_in_uop_bits_ppred_busy: %11128: i1, io_in_uop_bits_bypassable: %11129: i1, io_in_uop_bits_mem_cmd: %11130: i5, io_in_uop_bits_mem_size: %11131: i2, io_in_uop_bits_mem_signed: %11132: i1, io_in_uop_bits_is_fence: %11133: i1, io_in_uop_bits_is_amo: %11134: i1, io_in_uop_bits_uses_ldq: %11135: i1, io_in_uop_bits_uses_stq: %11136: i1, io_in_uop_bits_ldst_val: %11137: i1, io_in_uop_bits_dst_rtype: %11138: i2, io_in_uop_bits_lrs1_rtype: %11139: i2, io_in_uop_bits_lrs2_rtype: %11140: i2, io_in_uop_bits_fp_val: %11141: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_10.io_valid, %slots_10.io_will_be_valid, %slots_10.io_request, %slots_10.io_out_uop_uopc, %slots_10.io_out_uop_is_rvc, %slots_10.io_out_uop_fu_code, %slots_10.io_out_uop_iw_state, %slots_10.io_out_uop_iw_p1_poisoned, %slots_10.io_out_uop_iw_p2_poisoned, %slots_10.io_out_uop_is_br, %slots_10.io_out_uop_is_jalr, %slots_10.io_out_uop_is_jal, %slots_10.io_out_uop_is_sfb, %slots_10.io_out_uop_br_mask, %slots_10.io_out_uop_br_tag, %slots_10.io_out_uop_ftq_idx, %slots_10.io_out_uop_edge_inst, %slots_10.io_out_uop_pc_lob, %slots_10.io_out_uop_taken, %slots_10.io_out_uop_imm_packed, %slots_10.io_out_uop_rob_idx, %slots_10.io_out_uop_ldq_idx, %slots_10.io_out_uop_stq_idx, %slots_10.io_out_uop_pdst, %slots_10.io_out_uop_prs1, %slots_10.io_out_uop_prs2, %slots_10.io_out_uop_prs3, %slots_10.io_out_uop_prs1_busy, %slots_10.io_out_uop_prs2_busy, %slots_10.io_out_uop_prs3_busy, %slots_10.io_out_uop_ppred_busy, %slots_10.io_out_uop_bypassable, %slots_10.io_out_uop_mem_cmd, %slots_10.io_out_uop_mem_size, %slots_10.io_out_uop_mem_signed, %slots_10.io_out_uop_is_fence, %slots_10.io_out_uop_is_amo, %slots_10.io_out_uop_uses_ldq, %slots_10.io_out_uop_uses_stq, %slots_10.io_out_uop_ldst_val, %slots_10.io_out_uop_dst_rtype, %slots_10.io_out_uop_lrs1_rtype, %slots_10.io_out_uop_lrs2_rtype, %slots_10.io_out_uop_fp_val, %slots_10.io_uop_uopc, %slots_10.io_uop_is_rvc, %slots_10.io_uop_fu_code, %slots_10.io_uop_iw_p1_poisoned, %slots_10.io_uop_iw_p2_poisoned, %slots_10.io_uop_is_br, %slots_10.io_uop_is_jalr, %slots_10.io_uop_is_jal, %slots_10.io_uop_is_sfb, %slots_10.io_uop_br_mask, %slots_10.io_uop_br_tag, %slots_10.io_uop_ftq_idx, %slots_10.io_uop_edge_inst, %slots_10.io_uop_pc_lob, %slots_10.io_uop_taken, %slots_10.io_uop_imm_packed, %slots_10.io_uop_rob_idx, %slots_10.io_uop_ldq_idx, %slots_10.io_uop_stq_idx, %slots_10.io_uop_pdst, %slots_10.io_uop_prs1, %slots_10.io_uop_prs2, %slots_10.io_uop_bypassable, %slots_10.io_uop_mem_cmd, %slots_10.io_uop_mem_size, %slots_10.io_uop_mem_signed, %slots_10.io_uop_is_fence, %slots_10.io_uop_is_amo, %slots_10.io_uop_uses_ldq, %slots_10.io_uop_uses_stq, %slots_10.io_uop_ldst_val, %slots_10.io_uop_dst_rtype, %slots_10.io_uop_lrs1_rtype, %slots_10.io_uop_lrs2_rtype, %slots_10.io_uop_fp_val = hw.instance "slots_10" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %536: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %2992: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %2991: i1, io_in_uop_bits_uopc: %11142: i7, io_in_uop_bits_is_rvc: %11143: i1, io_in_uop_bits_fu_code: %11144: i10, io_in_uop_bits_iw_state: %11145: i2, io_in_uop_bits_iw_p1_poisoned: %11146: i1, io_in_uop_bits_iw_p2_poisoned: %11147: i1, io_in_uop_bits_is_br: %11148: i1, io_in_uop_bits_is_jalr: %11149: i1, io_in_uop_bits_is_jal: %11150: i1, io_in_uop_bits_is_sfb: %11151: i1, io_in_uop_bits_br_mask: %11152: i20, io_in_uop_bits_br_tag: %11153: i5, io_in_uop_bits_ftq_idx: %11154: i6, io_in_uop_bits_edge_inst: %11155: i1, io_in_uop_bits_pc_lob: %11156: i6, io_in_uop_bits_taken: %11157: i1, io_in_uop_bits_imm_packed: %11158: i20, io_in_uop_bits_rob_idx: %11159: i7, io_in_uop_bits_ldq_idx: %11160: i5, io_in_uop_bits_stq_idx: %11161: i5, io_in_uop_bits_pdst: %11162: i7, io_in_uop_bits_prs1: %11163: i7, io_in_uop_bits_prs2: %11164: i7, io_in_uop_bits_prs3: %11165: i7, io_in_uop_bits_prs1_busy: %11166: i1, io_in_uop_bits_prs2_busy: %11167: i1, io_in_uop_bits_prs3_busy: %11168: i1, io_in_uop_bits_ppred_busy: %11169: i1, io_in_uop_bits_bypassable: %11170: i1, io_in_uop_bits_mem_cmd: %11171: i5, io_in_uop_bits_mem_size: %11172: i2, io_in_uop_bits_mem_signed: %11173: i1, io_in_uop_bits_is_fence: %11174: i1, io_in_uop_bits_is_amo: %11175: i1, io_in_uop_bits_uses_ldq: %11176: i1, io_in_uop_bits_uses_stq: %11177: i1, io_in_uop_bits_ldst_val: %11178: i1, io_in_uop_bits_dst_rtype: %11179: i2, io_in_uop_bits_lrs1_rtype: %11180: i2, io_in_uop_bits_lrs2_rtype: %11181: i2, io_in_uop_bits_fp_val: %11182: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_11.io_valid, %slots_11.io_will_be_valid, %slots_11.io_request, %slots_11.io_out_uop_uopc, %slots_11.io_out_uop_is_rvc, %slots_11.io_out_uop_fu_code, %slots_11.io_out_uop_iw_state, %slots_11.io_out_uop_iw_p1_poisoned, %slots_11.io_out_uop_iw_p2_poisoned, %slots_11.io_out_uop_is_br, %slots_11.io_out_uop_is_jalr, %slots_11.io_out_uop_is_jal, %slots_11.io_out_uop_is_sfb, %slots_11.io_out_uop_br_mask, %slots_11.io_out_uop_br_tag, %slots_11.io_out_uop_ftq_idx, %slots_11.io_out_uop_edge_inst, %slots_11.io_out_uop_pc_lob, %slots_11.io_out_uop_taken, %slots_11.io_out_uop_imm_packed, %slots_11.io_out_uop_rob_idx, %slots_11.io_out_uop_ldq_idx, %slots_11.io_out_uop_stq_idx, %slots_11.io_out_uop_pdst, %slots_11.io_out_uop_prs1, %slots_11.io_out_uop_prs2, %slots_11.io_out_uop_prs3, %slots_11.io_out_uop_prs1_busy, %slots_11.io_out_uop_prs2_busy, %slots_11.io_out_uop_prs3_busy, %slots_11.io_out_uop_ppred_busy, %slots_11.io_out_uop_bypassable, %slots_11.io_out_uop_mem_cmd, %slots_11.io_out_uop_mem_size, %slots_11.io_out_uop_mem_signed, %slots_11.io_out_uop_is_fence, %slots_11.io_out_uop_is_amo, %slots_11.io_out_uop_uses_ldq, %slots_11.io_out_uop_uses_stq, %slots_11.io_out_uop_ldst_val, %slots_11.io_out_uop_dst_rtype, %slots_11.io_out_uop_lrs1_rtype, %slots_11.io_out_uop_lrs2_rtype, %slots_11.io_out_uop_fp_val, %slots_11.io_uop_uopc, %slots_11.io_uop_is_rvc, %slots_11.io_uop_fu_code, %slots_11.io_uop_iw_p1_poisoned, %slots_11.io_uop_iw_p2_poisoned, %slots_11.io_uop_is_br, %slots_11.io_uop_is_jalr, %slots_11.io_uop_is_jal, %slots_11.io_uop_is_sfb, %slots_11.io_uop_br_mask, %slots_11.io_uop_br_tag, %slots_11.io_uop_ftq_idx, %slots_11.io_uop_edge_inst, %slots_11.io_uop_pc_lob, %slots_11.io_uop_taken, %slots_11.io_uop_imm_packed, %slots_11.io_uop_rob_idx, %slots_11.io_uop_ldq_idx, %slots_11.io_uop_stq_idx, %slots_11.io_uop_pdst, %slots_11.io_uop_prs1, %slots_11.io_uop_prs2, %slots_11.io_uop_bypassable, %slots_11.io_uop_mem_cmd, %slots_11.io_uop_mem_size, %slots_11.io_uop_mem_signed, %slots_11.io_uop_is_fence, %slots_11.io_uop_is_amo, %slots_11.io_uop_uses_ldq, %slots_11.io_uop_uses_stq, %slots_11.io_uop_ldst_val, %slots_11.io_uop_dst_rtype, %slots_11.io_uop_lrs1_rtype, %slots_11.io_uop_lrs2_rtype, %slots_11.io_uop_fp_val = hw.instance "slots_11" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %570: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %3083: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %3082: i1, io_in_uop_bits_uopc: %11183: i7, io_in_uop_bits_is_rvc: %11184: i1, io_in_uop_bits_fu_code: %11185: i10, io_in_uop_bits_iw_state: %11186: i2, io_in_uop_bits_iw_p1_poisoned: %11187: i1, io_in_uop_bits_iw_p2_poisoned: %11188: i1, io_in_uop_bits_is_br: %11189: i1, io_in_uop_bits_is_jalr: %11190: i1, io_in_uop_bits_is_jal: %11191: i1, io_in_uop_bits_is_sfb: %11192: i1, io_in_uop_bits_br_mask: %11193: i20, io_in_uop_bits_br_tag: %11194: i5, io_in_uop_bits_ftq_idx: %11195: i6, io_in_uop_bits_edge_inst: %11196: i1, io_in_uop_bits_pc_lob: %11197: i6, io_in_uop_bits_taken: %11198: i1, io_in_uop_bits_imm_packed: %11199: i20, io_in_uop_bits_rob_idx: %11200: i7, io_in_uop_bits_ldq_idx: %11201: i5, io_in_uop_bits_stq_idx: %11202: i5, io_in_uop_bits_pdst: %11203: i7, io_in_uop_bits_prs1: %11204: i7, io_in_uop_bits_prs2: %11205: i7, io_in_uop_bits_prs3: %11206: i7, io_in_uop_bits_prs1_busy: %11207: i1, io_in_uop_bits_prs2_busy: %11208: i1, io_in_uop_bits_prs3_busy: %11209: i1, io_in_uop_bits_ppred_busy: %11210: i1, io_in_uop_bits_bypassable: %11211: i1, io_in_uop_bits_mem_cmd: %11212: i5, io_in_uop_bits_mem_size: %11213: i2, io_in_uop_bits_mem_signed: %11214: i1, io_in_uop_bits_is_fence: %11215: i1, io_in_uop_bits_is_amo: %11216: i1, io_in_uop_bits_uses_ldq: %11217: i1, io_in_uop_bits_uses_stq: %11218: i1, io_in_uop_bits_ldst_val: %11219: i1, io_in_uop_bits_dst_rtype: %11220: i2, io_in_uop_bits_lrs1_rtype: %11221: i2, io_in_uop_bits_lrs2_rtype: %11222: i2, io_in_uop_bits_fp_val: %11223: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_12.io_valid, %slots_12.io_will_be_valid, %slots_12.io_request, %slots_12.io_out_uop_uopc, %slots_12.io_out_uop_is_rvc, %slots_12.io_out_uop_fu_code, %slots_12.io_out_uop_iw_state, %slots_12.io_out_uop_iw_p1_poisoned, %slots_12.io_out_uop_iw_p2_poisoned, %slots_12.io_out_uop_is_br, %slots_12.io_out_uop_is_jalr, %slots_12.io_out_uop_is_jal, %slots_12.io_out_uop_is_sfb, %slots_12.io_out_uop_br_mask, %slots_12.io_out_uop_br_tag, %slots_12.io_out_uop_ftq_idx, %slots_12.io_out_uop_edge_inst, %slots_12.io_out_uop_pc_lob, %slots_12.io_out_uop_taken, %slots_12.io_out_uop_imm_packed, %slots_12.io_out_uop_rob_idx, %slots_12.io_out_uop_ldq_idx, %slots_12.io_out_uop_stq_idx, %slots_12.io_out_uop_pdst, %slots_12.io_out_uop_prs1, %slots_12.io_out_uop_prs2, %slots_12.io_out_uop_prs3, %slots_12.io_out_uop_prs1_busy, %slots_12.io_out_uop_prs2_busy, %slots_12.io_out_uop_prs3_busy, %slots_12.io_out_uop_ppred_busy, %slots_12.io_out_uop_bypassable, %slots_12.io_out_uop_mem_cmd, %slots_12.io_out_uop_mem_size, %slots_12.io_out_uop_mem_signed, %slots_12.io_out_uop_is_fence, %slots_12.io_out_uop_is_amo, %slots_12.io_out_uop_uses_ldq, %slots_12.io_out_uop_uses_stq, %slots_12.io_out_uop_ldst_val, %slots_12.io_out_uop_dst_rtype, %slots_12.io_out_uop_lrs1_rtype, %slots_12.io_out_uop_lrs2_rtype, %slots_12.io_out_uop_fp_val, %slots_12.io_uop_uopc, %slots_12.io_uop_is_rvc, %slots_12.io_uop_fu_code, %slots_12.io_uop_iw_p1_poisoned, %slots_12.io_uop_iw_p2_poisoned, %slots_12.io_uop_is_br, %slots_12.io_uop_is_jalr, %slots_12.io_uop_is_jal, %slots_12.io_uop_is_sfb, %slots_12.io_uop_br_mask, %slots_12.io_uop_br_tag, %slots_12.io_uop_ftq_idx, %slots_12.io_uop_edge_inst, %slots_12.io_uop_pc_lob, %slots_12.io_uop_taken, %slots_12.io_uop_imm_packed, %slots_12.io_uop_rob_idx, %slots_12.io_uop_ldq_idx, %slots_12.io_uop_stq_idx, %slots_12.io_uop_pdst, %slots_12.io_uop_prs1, %slots_12.io_uop_prs2, %slots_12.io_uop_bypassable, %slots_12.io_uop_mem_cmd, %slots_12.io_uop_mem_size, %slots_12.io_uop_mem_signed, %slots_12.io_uop_is_fence, %slots_12.io_uop_is_amo, %slots_12.io_uop_uses_ldq, %slots_12.io_uop_uses_stq, %slots_12.io_uop_ldst_val, %slots_12.io_uop_dst_rtype, %slots_12.io_uop_lrs1_rtype, %slots_12.io_uop_lrs2_rtype, %slots_12.io_uop_fp_val = hw.instance "slots_12" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %677: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %3174: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %3173: i1, io_in_uop_bits_uopc: %11224: i7, io_in_uop_bits_is_rvc: %11225: i1, io_in_uop_bits_fu_code: %11226: i10, io_in_uop_bits_iw_state: %11227: i2, io_in_uop_bits_iw_p1_poisoned: %11228: i1, io_in_uop_bits_iw_p2_poisoned: %11229: i1, io_in_uop_bits_is_br: %11230: i1, io_in_uop_bits_is_jalr: %11231: i1, io_in_uop_bits_is_jal: %11232: i1, io_in_uop_bits_is_sfb: %11233: i1, io_in_uop_bits_br_mask: %11234: i20, io_in_uop_bits_br_tag: %11235: i5, io_in_uop_bits_ftq_idx: %11236: i6, io_in_uop_bits_edge_inst: %11237: i1, io_in_uop_bits_pc_lob: %11238: i6, io_in_uop_bits_taken: %11239: i1, io_in_uop_bits_imm_packed: %11240: i20, io_in_uop_bits_rob_idx: %11241: i7, io_in_uop_bits_ldq_idx: %11242: i5, io_in_uop_bits_stq_idx: %11243: i5, io_in_uop_bits_pdst: %11244: i7, io_in_uop_bits_prs1: %11245: i7, io_in_uop_bits_prs2: %11246: i7, io_in_uop_bits_prs3: %11247: i7, io_in_uop_bits_prs1_busy: %11248: i1, io_in_uop_bits_prs2_busy: %11249: i1, io_in_uop_bits_prs3_busy: %11250: i1, io_in_uop_bits_ppred_busy: %11251: i1, io_in_uop_bits_bypassable: %11252: i1, io_in_uop_bits_mem_cmd: %11253: i5, io_in_uop_bits_mem_size: %11254: i2, io_in_uop_bits_mem_signed: %11255: i1, io_in_uop_bits_is_fence: %11256: i1, io_in_uop_bits_is_amo: %11257: i1, io_in_uop_bits_uses_ldq: %11258: i1, io_in_uop_bits_uses_stq: %11259: i1, io_in_uop_bits_ldst_val: %11260: i1, io_in_uop_bits_dst_rtype: %11261: i2, io_in_uop_bits_lrs1_rtype: %11262: i2, io_in_uop_bits_lrs2_rtype: %11263: i2, io_in_uop_bits_fp_val: %11264: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_13.io_valid, %slots_13.io_will_be_valid, %slots_13.io_request, %slots_13.io_out_uop_uopc, %slots_13.io_out_uop_is_rvc, %slots_13.io_out_uop_fu_code, %slots_13.io_out_uop_iw_state, %slots_13.io_out_uop_iw_p1_poisoned, %slots_13.io_out_uop_iw_p2_poisoned, %slots_13.io_out_uop_is_br, %slots_13.io_out_uop_is_jalr, %slots_13.io_out_uop_is_jal, %slots_13.io_out_uop_is_sfb, %slots_13.io_out_uop_br_mask, %slots_13.io_out_uop_br_tag, %slots_13.io_out_uop_ftq_idx, %slots_13.io_out_uop_edge_inst, %slots_13.io_out_uop_pc_lob, %slots_13.io_out_uop_taken, %slots_13.io_out_uop_imm_packed, %slots_13.io_out_uop_rob_idx, %slots_13.io_out_uop_ldq_idx, %slots_13.io_out_uop_stq_idx, %slots_13.io_out_uop_pdst, %slots_13.io_out_uop_prs1, %slots_13.io_out_uop_prs2, %slots_13.io_out_uop_prs3, %slots_13.io_out_uop_prs1_busy, %slots_13.io_out_uop_prs2_busy, %slots_13.io_out_uop_prs3_busy, %slots_13.io_out_uop_ppred_busy, %slots_13.io_out_uop_bypassable, %slots_13.io_out_uop_mem_cmd, %slots_13.io_out_uop_mem_size, %slots_13.io_out_uop_mem_signed, %slots_13.io_out_uop_is_fence, %slots_13.io_out_uop_is_amo, %slots_13.io_out_uop_uses_ldq, %slots_13.io_out_uop_uses_stq, %slots_13.io_out_uop_ldst_val, %slots_13.io_out_uop_dst_rtype, %slots_13.io_out_uop_lrs1_rtype, %slots_13.io_out_uop_lrs2_rtype, %slots_13.io_out_uop_fp_val, %slots_13.io_uop_uopc, %slots_13.io_uop_is_rvc, %slots_13.io_uop_fu_code, %slots_13.io_uop_iw_p1_poisoned, %slots_13.io_uop_iw_p2_poisoned, %slots_13.io_uop_is_br, %slots_13.io_uop_is_jalr, %slots_13.io_uop_is_jal, %slots_13.io_uop_is_sfb, %slots_13.io_uop_br_mask, %slots_13.io_uop_br_tag, %slots_13.io_uop_ftq_idx, %slots_13.io_uop_edge_inst, %slots_13.io_uop_pc_lob, %slots_13.io_uop_taken, %slots_13.io_uop_imm_packed, %slots_13.io_uop_rob_idx, %slots_13.io_uop_ldq_idx, %slots_13.io_uop_stq_idx, %slots_13.io_uop_pdst, %slots_13.io_uop_prs1, %slots_13.io_uop_prs2, %slots_13.io_uop_bypassable, %slots_13.io_uop_mem_cmd, %slots_13.io_uop_mem_size, %slots_13.io_uop_mem_signed, %slots_13.io_uop_is_fence, %slots_13.io_uop_is_amo, %slots_13.io_uop_uses_ldq, %slots_13.io_uop_uses_stq, %slots_13.io_uop_ldst_val, %slots_13.io_uop_dst_rtype, %slots_13.io_uop_lrs1_rtype, %slots_13.io_uop_lrs2_rtype, %slots_13.io_uop_fp_val = hw.instance "slots_13" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %636: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %3265: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %3264: i1, io_in_uop_bits_uopc: %11265: i7, io_in_uop_bits_is_rvc: %11266: i1, io_in_uop_bits_fu_code: %11267: i10, io_in_uop_bits_iw_state: %11268: i2, io_in_uop_bits_iw_p1_poisoned: %11269: i1, io_in_uop_bits_iw_p2_poisoned: %11270: i1, io_in_uop_bits_is_br: %11271: i1, io_in_uop_bits_is_jalr: %11272: i1, io_in_uop_bits_is_jal: %11273: i1, io_in_uop_bits_is_sfb: %11274: i1, io_in_uop_bits_br_mask: %11275: i20, io_in_uop_bits_br_tag: %11276: i5, io_in_uop_bits_ftq_idx: %11277: i6, io_in_uop_bits_edge_inst: %11278: i1, io_in_uop_bits_pc_lob: %11279: i6, io_in_uop_bits_taken: %11280: i1, io_in_uop_bits_imm_packed: %11281: i20, io_in_uop_bits_rob_idx: %11282: i7, io_in_uop_bits_ldq_idx: %11283: i5, io_in_uop_bits_stq_idx: %11284: i5, io_in_uop_bits_pdst: %11285: i7, io_in_uop_bits_prs1: %11286: i7, io_in_uop_bits_prs2: %11287: i7, io_in_uop_bits_prs3: %11288: i7, io_in_uop_bits_prs1_busy: %11289: i1, io_in_uop_bits_prs2_busy: %11290: i1, io_in_uop_bits_prs3_busy: %11291: i1, io_in_uop_bits_ppred_busy: %11292: i1, io_in_uop_bits_bypassable: %11293: i1, io_in_uop_bits_mem_cmd: %11294: i5, io_in_uop_bits_mem_size: %11295: i2, io_in_uop_bits_mem_signed: %11296: i1, io_in_uop_bits_is_fence: %11297: i1, io_in_uop_bits_is_amo: %11298: i1, io_in_uop_bits_uses_ldq: %11299: i1, io_in_uop_bits_uses_stq: %11300: i1, io_in_uop_bits_ldst_val: %11301: i1, io_in_uop_bits_dst_rtype: %11302: i2, io_in_uop_bits_lrs1_rtype: %11303: i2, io_in_uop_bits_lrs2_rtype: %11304: i2, io_in_uop_bits_fp_val: %11305: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_14.io_valid, %slots_14.io_will_be_valid, %slots_14.io_request, %slots_14.io_out_uop_uopc, %slots_14.io_out_uop_is_rvc, %slots_14.io_out_uop_fu_code, %slots_14.io_out_uop_iw_state, %slots_14.io_out_uop_iw_p1_poisoned, %slots_14.io_out_uop_iw_p2_poisoned, %slots_14.io_out_uop_is_br, %slots_14.io_out_uop_is_jalr, %slots_14.io_out_uop_is_jal, %slots_14.io_out_uop_is_sfb, %slots_14.io_out_uop_br_mask, %slots_14.io_out_uop_br_tag, %slots_14.io_out_uop_ftq_idx, %slots_14.io_out_uop_edge_inst, %slots_14.io_out_uop_pc_lob, %slots_14.io_out_uop_taken, %slots_14.io_out_uop_imm_packed, %slots_14.io_out_uop_rob_idx, %slots_14.io_out_uop_ldq_idx, %slots_14.io_out_uop_stq_idx, %slots_14.io_out_uop_pdst, %slots_14.io_out_uop_prs1, %slots_14.io_out_uop_prs2, %slots_14.io_out_uop_prs3, %slots_14.io_out_uop_prs1_busy, %slots_14.io_out_uop_prs2_busy, %slots_14.io_out_uop_prs3_busy, %slots_14.io_out_uop_ppred_busy, %slots_14.io_out_uop_bypassable, %slots_14.io_out_uop_mem_cmd, %slots_14.io_out_uop_mem_size, %slots_14.io_out_uop_mem_signed, %slots_14.io_out_uop_is_fence, %slots_14.io_out_uop_is_amo, %slots_14.io_out_uop_uses_ldq, %slots_14.io_out_uop_uses_stq, %slots_14.io_out_uop_ldst_val, %slots_14.io_out_uop_dst_rtype, %slots_14.io_out_uop_lrs1_rtype, %slots_14.io_out_uop_lrs2_rtype, %slots_14.io_out_uop_fp_val, %slots_14.io_uop_uopc, %slots_14.io_uop_is_rvc, %slots_14.io_uop_fu_code, %slots_14.io_uop_iw_p1_poisoned, %slots_14.io_uop_iw_p2_poisoned, %slots_14.io_uop_is_br, %slots_14.io_uop_is_jalr, %slots_14.io_uop_is_jal, %slots_14.io_uop_is_sfb, %slots_14.io_uop_br_mask, %slots_14.io_uop_br_tag, %slots_14.io_uop_ftq_idx, %slots_14.io_uop_edge_inst, %slots_14.io_uop_pc_lob, %slots_14.io_uop_taken, %slots_14.io_uop_imm_packed, %slots_14.io_uop_rob_idx, %slots_14.io_uop_ldq_idx, %slots_14.io_uop_stq_idx, %slots_14.io_uop_pdst, %slots_14.io_uop_prs1, %slots_14.io_uop_prs2, %slots_14.io_uop_bypassable, %slots_14.io_uop_mem_cmd, %slots_14.io_uop_mem_size, %slots_14.io_uop_mem_signed, %slots_14.io_uop_is_fence, %slots_14.io_uop_is_amo, %slots_14.io_uop_uses_ldq, %slots_14.io_uop_uses_stq, %slots_14.io_uop_ldst_val, %slots_14.io_uop_dst_rtype, %slots_14.io_uop_lrs1_rtype, %slots_14.io_uop_lrs2_rtype, %slots_14.io_uop_fp_val = hw.instance "slots_14" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %670: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %3356: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %3355: i1, io_in_uop_bits_uopc: %11306: i7, io_in_uop_bits_is_rvc: %11307: i1, io_in_uop_bits_fu_code: %11308: i10, io_in_uop_bits_iw_state: %11309: i2, io_in_uop_bits_iw_p1_poisoned: %11310: i1, io_in_uop_bits_iw_p2_poisoned: %11311: i1, io_in_uop_bits_is_br: %11312: i1, io_in_uop_bits_is_jalr: %11313: i1, io_in_uop_bits_is_jal: %11314: i1, io_in_uop_bits_is_sfb: %11315: i1, io_in_uop_bits_br_mask: %11316: i20, io_in_uop_bits_br_tag: %11317: i5, io_in_uop_bits_ftq_idx: %11318: i6, io_in_uop_bits_edge_inst: %11319: i1, io_in_uop_bits_pc_lob: %11320: i6, io_in_uop_bits_taken: %11321: i1, io_in_uop_bits_imm_packed: %11322: i20, io_in_uop_bits_rob_idx: %11323: i7, io_in_uop_bits_ldq_idx: %11324: i5, io_in_uop_bits_stq_idx: %11325: i5, io_in_uop_bits_pdst: %11326: i7, io_in_uop_bits_prs1: %11327: i7, io_in_uop_bits_prs2: %11328: i7, io_in_uop_bits_prs3: %11329: i7, io_in_uop_bits_prs1_busy: %11330: i1, io_in_uop_bits_prs2_busy: %11331: i1, io_in_uop_bits_prs3_busy: %11332: i1, io_in_uop_bits_ppred_busy: %11333: i1, io_in_uop_bits_bypassable: %11334: i1, io_in_uop_bits_mem_cmd: %11335: i5, io_in_uop_bits_mem_size: %11336: i2, io_in_uop_bits_mem_signed: %11337: i1, io_in_uop_bits_is_fence: %11338: i1, io_in_uop_bits_is_amo: %11339: i1, io_in_uop_bits_uses_ldq: %11340: i1, io_in_uop_bits_uses_stq: %11341: i1, io_in_uop_bits_ldst_val: %11342: i1, io_in_uop_bits_dst_rtype: %11343: i2, io_in_uop_bits_lrs1_rtype: %11344: i2, io_in_uop_bits_lrs2_rtype: %11345: i2, io_in_uop_bits_fp_val: %11346: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_15.io_valid, %slots_15.io_will_be_valid, %slots_15.io_request, %slots_15.io_out_uop_uopc, %slots_15.io_out_uop_is_rvc, %slots_15.io_out_uop_fu_code, %slots_15.io_out_uop_iw_state, %slots_15.io_out_uop_iw_p1_poisoned, %slots_15.io_out_uop_iw_p2_poisoned, %slots_15.io_out_uop_is_br, %slots_15.io_out_uop_is_jalr, %slots_15.io_out_uop_is_jal, %slots_15.io_out_uop_is_sfb, %slots_15.io_out_uop_br_mask, %slots_15.io_out_uop_br_tag, %slots_15.io_out_uop_ftq_idx, %slots_15.io_out_uop_edge_inst, %slots_15.io_out_uop_pc_lob, %slots_15.io_out_uop_taken, %slots_15.io_out_uop_imm_packed, %slots_15.io_out_uop_rob_idx, %slots_15.io_out_uop_ldq_idx, %slots_15.io_out_uop_stq_idx, %slots_15.io_out_uop_pdst, %slots_15.io_out_uop_prs1, %slots_15.io_out_uop_prs2, %slots_15.io_out_uop_prs3, %slots_15.io_out_uop_prs1_busy, %slots_15.io_out_uop_prs2_busy, %slots_15.io_out_uop_prs3_busy, %slots_15.io_out_uop_ppred_busy, %slots_15.io_out_uop_bypassable, %slots_15.io_out_uop_mem_cmd, %slots_15.io_out_uop_mem_size, %slots_15.io_out_uop_mem_signed, %slots_15.io_out_uop_is_fence, %slots_15.io_out_uop_is_amo, %slots_15.io_out_uop_uses_ldq, %slots_15.io_out_uop_uses_stq, %slots_15.io_out_uop_ldst_val, %slots_15.io_out_uop_dst_rtype, %slots_15.io_out_uop_lrs1_rtype, %slots_15.io_out_uop_lrs2_rtype, %slots_15.io_out_uop_fp_val, %slots_15.io_uop_uopc, %slots_15.io_uop_is_rvc, %slots_15.io_uop_fu_code, %slots_15.io_uop_iw_p1_poisoned, %slots_15.io_uop_iw_p2_poisoned, %slots_15.io_uop_is_br, %slots_15.io_uop_is_jalr, %slots_15.io_uop_is_jal, %slots_15.io_uop_is_sfb, %slots_15.io_uop_br_mask, %slots_15.io_uop_br_tag, %slots_15.io_uop_ftq_idx, %slots_15.io_uop_edge_inst, %slots_15.io_uop_pc_lob, %slots_15.io_uop_taken, %slots_15.io_uop_imm_packed, %slots_15.io_uop_rob_idx, %slots_15.io_uop_ldq_idx, %slots_15.io_uop_stq_idx, %slots_15.io_uop_pdst, %slots_15.io_uop_prs1, %slots_15.io_uop_prs2, %slots_15.io_uop_bypassable, %slots_15.io_uop_mem_cmd, %slots_15.io_uop_mem_size, %slots_15.io_uop_mem_signed, %slots_15.io_uop_is_fence, %slots_15.io_uop_is_amo, %slots_15.io_uop_uses_ldq, %slots_15.io_uop_uses_stq, %slots_15.io_uop_ldst_val, %slots_15.io_uop_dst_rtype, %slots_15.io_uop_lrs1_rtype, %slots_15.io_uop_lrs2_rtype, %slots_15.io_uop_fp_val = hw.instance "slots_15" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %716: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %3447: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %3446: i1, io_in_uop_bits_uopc: %11347: i7, io_in_uop_bits_is_rvc: %11348: i1, io_in_uop_bits_fu_code: %11349: i10, io_in_uop_bits_iw_state: %11350: i2, io_in_uop_bits_iw_p1_poisoned: %11351: i1, io_in_uop_bits_iw_p2_poisoned: %11352: i1, io_in_uop_bits_is_br: %11353: i1, io_in_uop_bits_is_jalr: %11354: i1, io_in_uop_bits_is_jal: %11355: i1, io_in_uop_bits_is_sfb: %11356: i1, io_in_uop_bits_br_mask: %11357: i20, io_in_uop_bits_br_tag: %11358: i5, io_in_uop_bits_ftq_idx: %11359: i6, io_in_uop_bits_edge_inst: %11360: i1, io_in_uop_bits_pc_lob: %11361: i6, io_in_uop_bits_taken: %11362: i1, io_in_uop_bits_imm_packed: %11363: i20, io_in_uop_bits_rob_idx: %11364: i7, io_in_uop_bits_ldq_idx: %11365: i5, io_in_uop_bits_stq_idx: %11366: i5, io_in_uop_bits_pdst: %11367: i7, io_in_uop_bits_prs1: %11368: i7, io_in_uop_bits_prs2: %11369: i7, io_in_uop_bits_prs3: %11370: i7, io_in_uop_bits_prs1_busy: %11371: i1, io_in_uop_bits_prs2_busy: %11372: i1, io_in_uop_bits_prs3_busy: %11373: i1, io_in_uop_bits_ppred_busy: %11374: i1, io_in_uop_bits_bypassable: %11375: i1, io_in_uop_bits_mem_cmd: %11376: i5, io_in_uop_bits_mem_size: %11377: i2, io_in_uop_bits_mem_signed: %11378: i1, io_in_uop_bits_is_fence: %11379: i1, io_in_uop_bits_is_amo: %11380: i1, io_in_uop_bits_uses_ldq: %11381: i1, io_in_uop_bits_uses_stq: %11382: i1, io_in_uop_bits_ldst_val: %11383: i1, io_in_uop_bits_dst_rtype: %11384: i2, io_in_uop_bits_lrs1_rtype: %11385: i2, io_in_uop_bits_lrs2_rtype: %11386: i2, io_in_uop_bits_fp_val: %11387: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_16.io_valid, %slots_16.io_will_be_valid, %slots_16.io_request, %slots_16.io_out_uop_uopc, %slots_16.io_out_uop_is_rvc, %slots_16.io_out_uop_fu_code, %slots_16.io_out_uop_iw_state, %slots_16.io_out_uop_iw_p1_poisoned, %slots_16.io_out_uop_iw_p2_poisoned, %slots_16.io_out_uop_is_br, %slots_16.io_out_uop_is_jalr, %slots_16.io_out_uop_is_jal, %slots_16.io_out_uop_is_sfb, %slots_16.io_out_uop_br_mask, %slots_16.io_out_uop_br_tag, %slots_16.io_out_uop_ftq_idx, %slots_16.io_out_uop_edge_inst, %slots_16.io_out_uop_pc_lob, %slots_16.io_out_uop_taken, %slots_16.io_out_uop_imm_packed, %slots_16.io_out_uop_rob_idx, %slots_16.io_out_uop_ldq_idx, %slots_16.io_out_uop_stq_idx, %slots_16.io_out_uop_pdst, %slots_16.io_out_uop_prs1, %slots_16.io_out_uop_prs2, %slots_16.io_out_uop_prs3, %slots_16.io_out_uop_prs1_busy, %slots_16.io_out_uop_prs2_busy, %slots_16.io_out_uop_prs3_busy, %slots_16.io_out_uop_ppred_busy, %slots_16.io_out_uop_bypassable, %slots_16.io_out_uop_mem_cmd, %slots_16.io_out_uop_mem_size, %slots_16.io_out_uop_mem_signed, %slots_16.io_out_uop_is_fence, %slots_16.io_out_uop_is_amo, %slots_16.io_out_uop_uses_ldq, %slots_16.io_out_uop_uses_stq, %slots_16.io_out_uop_ldst_val, %slots_16.io_out_uop_dst_rtype, %slots_16.io_out_uop_lrs1_rtype, %slots_16.io_out_uop_lrs2_rtype, %slots_16.io_out_uop_fp_val, %slots_16.io_uop_uopc, %slots_16.io_uop_is_rvc, %slots_16.io_uop_fu_code, %slots_16.io_uop_iw_p1_poisoned, %slots_16.io_uop_iw_p2_poisoned, %slots_16.io_uop_is_br, %slots_16.io_uop_is_jalr, %slots_16.io_uop_is_jal, %slots_16.io_uop_is_sfb, %slots_16.io_uop_br_mask, %slots_16.io_uop_br_tag, %slots_16.io_uop_ftq_idx, %slots_16.io_uop_edge_inst, %slots_16.io_uop_pc_lob, %slots_16.io_uop_taken, %slots_16.io_uop_imm_packed, %slots_16.io_uop_rob_idx, %slots_16.io_uop_ldq_idx, %slots_16.io_uop_stq_idx, %slots_16.io_uop_pdst, %slots_16.io_uop_prs1, %slots_16.io_uop_prs2, %slots_16.io_uop_bypassable, %slots_16.io_uop_mem_cmd, %slots_16.io_uop_mem_size, %slots_16.io_uop_mem_signed, %slots_16.io_uop_is_fence, %slots_16.io_uop_is_amo, %slots_16.io_uop_uses_ldq, %slots_16.io_uop_uses_stq, %slots_16.io_uop_ldst_val, %slots_16.io_uop_dst_rtype, %slots_16.io_uop_lrs1_rtype, %slots_16.io_uop_lrs2_rtype, %slots_16.io_uop_fp_val = hw.instance "slots_16" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %750: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %3538: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %3537: i1, io_in_uop_bits_uopc: %11388: i7, io_in_uop_bits_is_rvc: %11389: i1, io_in_uop_bits_fu_code: %11390: i10, io_in_uop_bits_iw_state: %11391: i2, io_in_uop_bits_iw_p1_poisoned: %11392: i1, io_in_uop_bits_iw_p2_poisoned: %11393: i1, io_in_uop_bits_is_br: %11394: i1, io_in_uop_bits_is_jalr: %11395: i1, io_in_uop_bits_is_jal: %11396: i1, io_in_uop_bits_is_sfb: %11397: i1, io_in_uop_bits_br_mask: %11398: i20, io_in_uop_bits_br_tag: %11399: i5, io_in_uop_bits_ftq_idx: %11400: i6, io_in_uop_bits_edge_inst: %11401: i1, io_in_uop_bits_pc_lob: %11402: i6, io_in_uop_bits_taken: %11403: i1, io_in_uop_bits_imm_packed: %11404: i20, io_in_uop_bits_rob_idx: %11405: i7, io_in_uop_bits_ldq_idx: %11406: i5, io_in_uop_bits_stq_idx: %11407: i5, io_in_uop_bits_pdst: %11408: i7, io_in_uop_bits_prs1: %11409: i7, io_in_uop_bits_prs2: %11410: i7, io_in_uop_bits_prs3: %11411: i7, io_in_uop_bits_prs1_busy: %11412: i1, io_in_uop_bits_prs2_busy: %11413: i1, io_in_uop_bits_prs3_busy: %11414: i1, io_in_uop_bits_ppred_busy: %11415: i1, io_in_uop_bits_bypassable: %11416: i1, io_in_uop_bits_mem_cmd: %11417: i5, io_in_uop_bits_mem_size: %11418: i2, io_in_uop_bits_mem_signed: %11419: i1, io_in_uop_bits_is_fence: %11420: i1, io_in_uop_bits_is_amo: %11421: i1, io_in_uop_bits_uses_ldq: %11422: i1, io_in_uop_bits_uses_stq: %11423: i1, io_in_uop_bits_ldst_val: %11424: i1, io_in_uop_bits_dst_rtype: %11425: i2, io_in_uop_bits_lrs1_rtype: %11426: i2, io_in_uop_bits_lrs2_rtype: %11427: i2, io_in_uop_bits_fp_val: %11428: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_17.io_valid, %slots_17.io_will_be_valid, %slots_17.io_request, %slots_17.io_out_uop_uopc, %slots_17.io_out_uop_is_rvc, %slots_17.io_out_uop_fu_code, %slots_17.io_out_uop_iw_state, %slots_17.io_out_uop_iw_p1_poisoned, %slots_17.io_out_uop_iw_p2_poisoned, %slots_17.io_out_uop_is_br, %slots_17.io_out_uop_is_jalr, %slots_17.io_out_uop_is_jal, %slots_17.io_out_uop_is_sfb, %slots_17.io_out_uop_br_mask, %slots_17.io_out_uop_br_tag, %slots_17.io_out_uop_ftq_idx, %slots_17.io_out_uop_edge_inst, %slots_17.io_out_uop_pc_lob, %slots_17.io_out_uop_taken, %slots_17.io_out_uop_imm_packed, %slots_17.io_out_uop_rob_idx, %slots_17.io_out_uop_ldq_idx, %slots_17.io_out_uop_stq_idx, %slots_17.io_out_uop_pdst, %slots_17.io_out_uop_prs1, %slots_17.io_out_uop_prs2, %slots_17.io_out_uop_prs3, %slots_17.io_out_uop_prs1_busy, %slots_17.io_out_uop_prs2_busy, %slots_17.io_out_uop_prs3_busy, %slots_17.io_out_uop_ppred_busy, %slots_17.io_out_uop_bypassable, %slots_17.io_out_uop_mem_cmd, %slots_17.io_out_uop_mem_size, %slots_17.io_out_uop_mem_signed, %slots_17.io_out_uop_is_fence, %slots_17.io_out_uop_is_amo, %slots_17.io_out_uop_uses_ldq, %slots_17.io_out_uop_uses_stq, %slots_17.io_out_uop_ldst_val, %slots_17.io_out_uop_dst_rtype, %slots_17.io_out_uop_lrs1_rtype, %slots_17.io_out_uop_lrs2_rtype, %slots_17.io_out_uop_fp_val, %slots_17.io_uop_uopc, %slots_17.io_uop_is_rvc, %slots_17.io_uop_fu_code, %slots_17.io_uop_iw_p1_poisoned, %slots_17.io_uop_iw_p2_poisoned, %slots_17.io_uop_is_br, %slots_17.io_uop_is_jalr, %slots_17.io_uop_is_jal, %slots_17.io_uop_is_sfb, %slots_17.io_uop_br_mask, %slots_17.io_uop_br_tag, %slots_17.io_uop_ftq_idx, %slots_17.io_uop_edge_inst, %slots_17.io_uop_pc_lob, %slots_17.io_uop_taken, %slots_17.io_uop_imm_packed, %slots_17.io_uop_rob_idx, %slots_17.io_uop_ldq_idx, %slots_17.io_uop_stq_idx, %slots_17.io_uop_pdst, %slots_17.io_uop_prs1, %slots_17.io_uop_prs2, %slots_17.io_uop_bypassable, %slots_17.io_uop_mem_cmd, %slots_17.io_uop_mem_size, %slots_17.io_uop_mem_signed, %slots_17.io_uop_is_fence, %slots_17.io_uop_is_amo, %slots_17.io_uop_uses_ldq, %slots_17.io_uop_uses_stq, %slots_17.io_uop_ldst_val, %slots_17.io_uop_dst_rtype, %slots_17.io_uop_lrs1_rtype, %slots_17.io_uop_lrs2_rtype, %slots_17.io_uop_fp_val = hw.instance "slots_17" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %857: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %3629: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %3628: i1, io_in_uop_bits_uopc: %11429: i7, io_in_uop_bits_is_rvc: %11430: i1, io_in_uop_bits_fu_code: %11431: i10, io_in_uop_bits_iw_state: %11432: i2, io_in_uop_bits_iw_p1_poisoned: %11433: i1, io_in_uop_bits_iw_p2_poisoned: %11434: i1, io_in_uop_bits_is_br: %11435: i1, io_in_uop_bits_is_jalr: %11436: i1, io_in_uop_bits_is_jal: %11437: i1, io_in_uop_bits_is_sfb: %11438: i1, io_in_uop_bits_br_mask: %11439: i20, io_in_uop_bits_br_tag: %11440: i5, io_in_uop_bits_ftq_idx: %11441: i6, io_in_uop_bits_edge_inst: %11442: i1, io_in_uop_bits_pc_lob: %11443: i6, io_in_uop_bits_taken: %11444: i1, io_in_uop_bits_imm_packed: %11445: i20, io_in_uop_bits_rob_idx: %11446: i7, io_in_uop_bits_ldq_idx: %11447: i5, io_in_uop_bits_stq_idx: %11448: i5, io_in_uop_bits_pdst: %11449: i7, io_in_uop_bits_prs1: %11450: i7, io_in_uop_bits_prs2: %11451: i7, io_in_uop_bits_prs3: %11452: i7, io_in_uop_bits_prs1_busy: %11453: i1, io_in_uop_bits_prs2_busy: %11454: i1, io_in_uop_bits_prs3_busy: %11455: i1, io_in_uop_bits_ppred_busy: %11456: i1, io_in_uop_bits_bypassable: %11457: i1, io_in_uop_bits_mem_cmd: %11458: i5, io_in_uop_bits_mem_size: %11459: i2, io_in_uop_bits_mem_signed: %11460: i1, io_in_uop_bits_is_fence: %11461: i1, io_in_uop_bits_is_amo: %11462: i1, io_in_uop_bits_uses_ldq: %11463: i1, io_in_uop_bits_uses_stq: %11464: i1, io_in_uop_bits_ldst_val: %11465: i1, io_in_uop_bits_dst_rtype: %11466: i2, io_in_uop_bits_lrs1_rtype: %11467: i2, io_in_uop_bits_lrs2_rtype: %11468: i2, io_in_uop_bits_fp_val: %11469: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_18.io_valid, %slots_18.io_will_be_valid, %slots_18.io_request, %slots_18.io_out_uop_uopc, %slots_18.io_out_uop_is_rvc, %slots_18.io_out_uop_fu_code, %slots_18.io_out_uop_iw_state, %slots_18.io_out_uop_iw_p1_poisoned, %slots_18.io_out_uop_iw_p2_poisoned, %slots_18.io_out_uop_is_br, %slots_18.io_out_uop_is_jalr, %slots_18.io_out_uop_is_jal, %slots_18.io_out_uop_is_sfb, %slots_18.io_out_uop_br_mask, %slots_18.io_out_uop_br_tag, %slots_18.io_out_uop_ftq_idx, %slots_18.io_out_uop_edge_inst, %slots_18.io_out_uop_pc_lob, %slots_18.io_out_uop_taken, %slots_18.io_out_uop_imm_packed, %slots_18.io_out_uop_rob_idx, %slots_18.io_out_uop_ldq_idx, %slots_18.io_out_uop_stq_idx, %slots_18.io_out_uop_pdst, %slots_18.io_out_uop_prs1, %slots_18.io_out_uop_prs2, %slots_18.io_out_uop_prs3, %slots_18.io_out_uop_prs1_busy, %slots_18.io_out_uop_prs2_busy, %slots_18.io_out_uop_prs3_busy, %slots_18.io_out_uop_ppred_busy, %slots_18.io_out_uop_bypassable, %slots_18.io_out_uop_mem_cmd, %slots_18.io_out_uop_mem_size, %slots_18.io_out_uop_mem_signed, %slots_18.io_out_uop_is_fence, %slots_18.io_out_uop_is_amo, %slots_18.io_out_uop_uses_ldq, %slots_18.io_out_uop_uses_stq, %slots_18.io_out_uop_ldst_val, %slots_18.io_out_uop_dst_rtype, %slots_18.io_out_uop_lrs1_rtype, %slots_18.io_out_uop_lrs2_rtype, %slots_18.io_out_uop_fp_val, %slots_18.io_uop_uopc, %slots_18.io_uop_is_rvc, %slots_18.io_uop_fu_code, %slots_18.io_uop_iw_p1_poisoned, %slots_18.io_uop_iw_p2_poisoned, %slots_18.io_uop_is_br, %slots_18.io_uop_is_jalr, %slots_18.io_uop_is_jal, %slots_18.io_uop_is_sfb, %slots_18.io_uop_br_mask, %slots_18.io_uop_br_tag, %slots_18.io_uop_ftq_idx, %slots_18.io_uop_edge_inst, %slots_18.io_uop_pc_lob, %slots_18.io_uop_taken, %slots_18.io_uop_imm_packed, %slots_18.io_uop_rob_idx, %slots_18.io_uop_ldq_idx, %slots_18.io_uop_stq_idx, %slots_18.io_uop_pdst, %slots_18.io_uop_prs1, %slots_18.io_uop_prs2, %slots_18.io_uop_bypassable, %slots_18.io_uop_mem_cmd, %slots_18.io_uop_mem_size, %slots_18.io_uop_mem_signed, %slots_18.io_uop_is_fence, %slots_18.io_uop_is_amo, %slots_18.io_uop_uses_ldq, %slots_18.io_uop_uses_stq, %slots_18.io_uop_ldst_val, %slots_18.io_uop_dst_rtype, %slots_18.io_uop_lrs1_rtype, %slots_18.io_uop_lrs2_rtype, %slots_18.io_uop_fp_val = hw.instance "slots_18" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %816: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %3720: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %3719: i1, io_in_uop_bits_uopc: %11470: i7, io_in_uop_bits_is_rvc: %11471: i1, io_in_uop_bits_fu_code: %11472: i10, io_in_uop_bits_iw_state: %11473: i2, io_in_uop_bits_iw_p1_poisoned: %11474: i1, io_in_uop_bits_iw_p2_poisoned: %11475: i1, io_in_uop_bits_is_br: %11476: i1, io_in_uop_bits_is_jalr: %11477: i1, io_in_uop_bits_is_jal: %11478: i1, io_in_uop_bits_is_sfb: %11479: i1, io_in_uop_bits_br_mask: %11480: i20, io_in_uop_bits_br_tag: %11481: i5, io_in_uop_bits_ftq_idx: %11482: i6, io_in_uop_bits_edge_inst: %11483: i1, io_in_uop_bits_pc_lob: %11484: i6, io_in_uop_bits_taken: %11485: i1, io_in_uop_bits_imm_packed: %11486: i20, io_in_uop_bits_rob_idx: %11487: i7, io_in_uop_bits_ldq_idx: %11488: i5, io_in_uop_bits_stq_idx: %11489: i5, io_in_uop_bits_pdst: %11490: i7, io_in_uop_bits_prs1: %11491: i7, io_in_uop_bits_prs2: %11492: i7, io_in_uop_bits_prs3: %11493: i7, io_in_uop_bits_prs1_busy: %11494: i1, io_in_uop_bits_prs2_busy: %11495: i1, io_in_uop_bits_prs3_busy: %11496: i1, io_in_uop_bits_ppred_busy: %11497: i1, io_in_uop_bits_bypassable: %11498: i1, io_in_uop_bits_mem_cmd: %11499: i5, io_in_uop_bits_mem_size: %11500: i2, io_in_uop_bits_mem_signed: %11501: i1, io_in_uop_bits_is_fence: %11502: i1, io_in_uop_bits_is_amo: %11503: i1, io_in_uop_bits_uses_ldq: %11504: i1, io_in_uop_bits_uses_stq: %11505: i1, io_in_uop_bits_ldst_val: %11506: i1, io_in_uop_bits_dst_rtype: %11507: i2, io_in_uop_bits_lrs1_rtype: %11508: i2, io_in_uop_bits_lrs2_rtype: %11509: i2, io_in_uop_bits_fp_val: %11510: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_19.io_valid, %slots_19.io_will_be_valid, %slots_19.io_request, %slots_19.io_out_uop_uopc, %slots_19.io_out_uop_is_rvc, %slots_19.io_out_uop_fu_code, %slots_19.io_out_uop_iw_state, %slots_19.io_out_uop_iw_p1_poisoned, %slots_19.io_out_uop_iw_p2_poisoned, %slots_19.io_out_uop_is_br, %slots_19.io_out_uop_is_jalr, %slots_19.io_out_uop_is_jal, %slots_19.io_out_uop_is_sfb, %slots_19.io_out_uop_br_mask, %slots_19.io_out_uop_br_tag, %slots_19.io_out_uop_ftq_idx, %slots_19.io_out_uop_edge_inst, %slots_19.io_out_uop_pc_lob, %slots_19.io_out_uop_taken, %slots_19.io_out_uop_imm_packed, %slots_19.io_out_uop_rob_idx, %slots_19.io_out_uop_ldq_idx, %slots_19.io_out_uop_stq_idx, %slots_19.io_out_uop_pdst, %slots_19.io_out_uop_prs1, %slots_19.io_out_uop_prs2, %slots_19.io_out_uop_prs3, %slots_19.io_out_uop_prs1_busy, %slots_19.io_out_uop_prs2_busy, %slots_19.io_out_uop_prs3_busy, %slots_19.io_out_uop_ppred_busy, %slots_19.io_out_uop_bypassable, %slots_19.io_out_uop_mem_cmd, %slots_19.io_out_uop_mem_size, %slots_19.io_out_uop_mem_signed, %slots_19.io_out_uop_is_fence, %slots_19.io_out_uop_is_amo, %slots_19.io_out_uop_uses_ldq, %slots_19.io_out_uop_uses_stq, %slots_19.io_out_uop_ldst_val, %slots_19.io_out_uop_dst_rtype, %slots_19.io_out_uop_lrs1_rtype, %slots_19.io_out_uop_lrs2_rtype, %slots_19.io_out_uop_fp_val, %slots_19.io_uop_uopc, %slots_19.io_uop_is_rvc, %slots_19.io_uop_fu_code, %slots_19.io_uop_iw_p1_poisoned, %slots_19.io_uop_iw_p2_poisoned, %slots_19.io_uop_is_br, %slots_19.io_uop_is_jalr, %slots_19.io_uop_is_jal, %slots_19.io_uop_is_sfb, %slots_19.io_uop_br_mask, %slots_19.io_uop_br_tag, %slots_19.io_uop_ftq_idx, %slots_19.io_uop_edge_inst, %slots_19.io_uop_pc_lob, %slots_19.io_uop_taken, %slots_19.io_uop_imm_packed, %slots_19.io_uop_rob_idx, %slots_19.io_uop_ldq_idx, %slots_19.io_uop_stq_idx, %slots_19.io_uop_pdst, %slots_19.io_uop_prs1, %slots_19.io_uop_prs2, %slots_19.io_uop_bypassable, %slots_19.io_uop_mem_cmd, %slots_19.io_uop_mem_size, %slots_19.io_uop_mem_signed, %slots_19.io_uop_is_fence, %slots_19.io_uop_is_amo, %slots_19.io_uop_uses_ldq, %slots_19.io_uop_uses_stq, %slots_19.io_uop_ldst_val, %slots_19.io_uop_dst_rtype, %slots_19.io_uop_lrs1_rtype, %slots_19.io_uop_lrs2_rtype, %slots_19.io_uop_fp_val = hw.instance "slots_19" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %850: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %3811: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %3810: i1, io_in_uop_bits_uopc: %11511: i7, io_in_uop_bits_is_rvc: %11512: i1, io_in_uop_bits_fu_code: %11513: i10, io_in_uop_bits_iw_state: %11514: i2, io_in_uop_bits_iw_p1_poisoned: %11515: i1, io_in_uop_bits_iw_p2_poisoned: %11516: i1, io_in_uop_bits_is_br: %11517: i1, io_in_uop_bits_is_jalr: %11518: i1, io_in_uop_bits_is_jal: %11519: i1, io_in_uop_bits_is_sfb: %11520: i1, io_in_uop_bits_br_mask: %11521: i20, io_in_uop_bits_br_tag: %11522: i5, io_in_uop_bits_ftq_idx: %11523: i6, io_in_uop_bits_edge_inst: %11524: i1, io_in_uop_bits_pc_lob: %11525: i6, io_in_uop_bits_taken: %11526: i1, io_in_uop_bits_imm_packed: %11527: i20, io_in_uop_bits_rob_idx: %11528: i7, io_in_uop_bits_ldq_idx: %11529: i5, io_in_uop_bits_stq_idx: %11530: i5, io_in_uop_bits_pdst: %11531: i7, io_in_uop_bits_prs1: %11532: i7, io_in_uop_bits_prs2: %11533: i7, io_in_uop_bits_prs3: %11534: i7, io_in_uop_bits_prs1_busy: %11535: i1, io_in_uop_bits_prs2_busy: %11536: i1, io_in_uop_bits_prs3_busy: %11537: i1, io_in_uop_bits_ppred_busy: %11538: i1, io_in_uop_bits_bypassable: %11539: i1, io_in_uop_bits_mem_cmd: %11540: i5, io_in_uop_bits_mem_size: %11541: i2, io_in_uop_bits_mem_signed: %11542: i1, io_in_uop_bits_is_fence: %11543: i1, io_in_uop_bits_is_amo: %11544: i1, io_in_uop_bits_uses_ldq: %11545: i1, io_in_uop_bits_uses_stq: %11546: i1, io_in_uop_bits_ldst_val: %11547: i1, io_in_uop_bits_dst_rtype: %11548: i2, io_in_uop_bits_lrs1_rtype: %11549: i2, io_in_uop_bits_lrs2_rtype: %11550: i2, io_in_uop_bits_fp_val: %11551: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_20.io_valid, %slots_20.io_will_be_valid, %slots_20.io_request, %slots_20.io_out_uop_uopc, %slots_20.io_out_uop_is_rvc, %slots_20.io_out_uop_fu_code, %slots_20.io_out_uop_iw_state, %slots_20.io_out_uop_iw_p1_poisoned, %slots_20.io_out_uop_iw_p2_poisoned, %slots_20.io_out_uop_is_br, %slots_20.io_out_uop_is_jalr, %slots_20.io_out_uop_is_jal, %slots_20.io_out_uop_is_sfb, %slots_20.io_out_uop_br_mask, %slots_20.io_out_uop_br_tag, %slots_20.io_out_uop_ftq_idx, %slots_20.io_out_uop_edge_inst, %slots_20.io_out_uop_pc_lob, %slots_20.io_out_uop_taken, %slots_20.io_out_uop_imm_packed, %slots_20.io_out_uop_rob_idx, %slots_20.io_out_uop_ldq_idx, %slots_20.io_out_uop_stq_idx, %slots_20.io_out_uop_pdst, %slots_20.io_out_uop_prs1, %slots_20.io_out_uop_prs2, %slots_20.io_out_uop_prs3, %slots_20.io_out_uop_prs1_busy, %slots_20.io_out_uop_prs2_busy, %slots_20.io_out_uop_prs3_busy, %slots_20.io_out_uop_ppred_busy, %slots_20.io_out_uop_bypassable, %slots_20.io_out_uop_mem_cmd, %slots_20.io_out_uop_mem_size, %slots_20.io_out_uop_mem_signed, %slots_20.io_out_uop_is_fence, %slots_20.io_out_uop_is_amo, %slots_20.io_out_uop_uses_ldq, %slots_20.io_out_uop_uses_stq, %slots_20.io_out_uop_ldst_val, %slots_20.io_out_uop_dst_rtype, %slots_20.io_out_uop_lrs1_rtype, %slots_20.io_out_uop_lrs2_rtype, %slots_20.io_out_uop_fp_val, %slots_20.io_uop_uopc, %slots_20.io_uop_is_rvc, %slots_20.io_uop_fu_code, %slots_20.io_uop_iw_p1_poisoned, %slots_20.io_uop_iw_p2_poisoned, %slots_20.io_uop_is_br, %slots_20.io_uop_is_jalr, %slots_20.io_uop_is_jal, %slots_20.io_uop_is_sfb, %slots_20.io_uop_br_mask, %slots_20.io_uop_br_tag, %slots_20.io_uop_ftq_idx, %slots_20.io_uop_edge_inst, %slots_20.io_uop_pc_lob, %slots_20.io_uop_taken, %slots_20.io_uop_imm_packed, %slots_20.io_uop_rob_idx, %slots_20.io_uop_ldq_idx, %slots_20.io_uop_stq_idx, %slots_20.io_uop_pdst, %slots_20.io_uop_prs1, %slots_20.io_uop_prs2, %slots_20.io_uop_bypassable, %slots_20.io_uop_mem_cmd, %slots_20.io_uop_mem_size, %slots_20.io_uop_mem_signed, %slots_20.io_uop_is_fence, %slots_20.io_uop_is_amo, %slots_20.io_uop_uses_ldq, %slots_20.io_uop_uses_stq, %slots_20.io_uop_ldst_val, %slots_20.io_uop_dst_rtype, %slots_20.io_uop_lrs1_rtype, %slots_20.io_uop_lrs2_rtype, %slots_20.io_uop_fp_val = hw.instance "slots_20" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %902: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %3902: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %3901: i1, io_in_uop_bits_uopc: %11552: i7, io_in_uop_bits_is_rvc: %11553: i1, io_in_uop_bits_fu_code: %11554: i10, io_in_uop_bits_iw_state: %11555: i2, io_in_uop_bits_iw_p1_poisoned: %11556: i1, io_in_uop_bits_iw_p2_poisoned: %11557: i1, io_in_uop_bits_is_br: %11558: i1, io_in_uop_bits_is_jalr: %11559: i1, io_in_uop_bits_is_jal: %11560: i1, io_in_uop_bits_is_sfb: %11561: i1, io_in_uop_bits_br_mask: %11562: i20, io_in_uop_bits_br_tag: %11563: i5, io_in_uop_bits_ftq_idx: %11564: i6, io_in_uop_bits_edge_inst: %11565: i1, io_in_uop_bits_pc_lob: %11566: i6, io_in_uop_bits_taken: %11567: i1, io_in_uop_bits_imm_packed: %11568: i20, io_in_uop_bits_rob_idx: %11569: i7, io_in_uop_bits_ldq_idx: %11570: i5, io_in_uop_bits_stq_idx: %11571: i5, io_in_uop_bits_pdst: %11572: i7, io_in_uop_bits_prs1: %11573: i7, io_in_uop_bits_prs2: %11574: i7, io_in_uop_bits_prs3: %11575: i7, io_in_uop_bits_prs1_busy: %11576: i1, io_in_uop_bits_prs2_busy: %11577: i1, io_in_uop_bits_prs3_busy: %11578: i1, io_in_uop_bits_ppred_busy: %11579: i1, io_in_uop_bits_bypassable: %11580: i1, io_in_uop_bits_mem_cmd: %11581: i5, io_in_uop_bits_mem_size: %11582: i2, io_in_uop_bits_mem_signed: %11583: i1, io_in_uop_bits_is_fence: %11584: i1, io_in_uop_bits_is_amo: %11585: i1, io_in_uop_bits_uses_ldq: %11586: i1, io_in_uop_bits_uses_stq: %11587: i1, io_in_uop_bits_ldst_val: %11588: i1, io_in_uop_bits_dst_rtype: %11589: i2, io_in_uop_bits_lrs1_rtype: %11590: i2, io_in_uop_bits_lrs2_rtype: %11591: i2, io_in_uop_bits_fp_val: %11592: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_21.io_valid, %slots_21.io_will_be_valid, %slots_21.io_request, %slots_21.io_out_uop_uopc, %slots_21.io_out_uop_is_rvc, %slots_21.io_out_uop_fu_code, %slots_21.io_out_uop_iw_state, %slots_21.io_out_uop_iw_p1_poisoned, %slots_21.io_out_uop_iw_p2_poisoned, %slots_21.io_out_uop_is_br, %slots_21.io_out_uop_is_jalr, %slots_21.io_out_uop_is_jal, %slots_21.io_out_uop_is_sfb, %slots_21.io_out_uop_br_mask, %slots_21.io_out_uop_br_tag, %slots_21.io_out_uop_ftq_idx, %slots_21.io_out_uop_edge_inst, %slots_21.io_out_uop_pc_lob, %slots_21.io_out_uop_taken, %slots_21.io_out_uop_imm_packed, %slots_21.io_out_uop_rob_idx, %slots_21.io_out_uop_ldq_idx, %slots_21.io_out_uop_stq_idx, %slots_21.io_out_uop_pdst, %slots_21.io_out_uop_prs1, %slots_21.io_out_uop_prs2, %slots_21.io_out_uop_prs3, %slots_21.io_out_uop_prs1_busy, %slots_21.io_out_uop_prs2_busy, %slots_21.io_out_uop_prs3_busy, %slots_21.io_out_uop_ppred_busy, %slots_21.io_out_uop_bypassable, %slots_21.io_out_uop_mem_cmd, %slots_21.io_out_uop_mem_size, %slots_21.io_out_uop_mem_signed, %slots_21.io_out_uop_is_fence, %slots_21.io_out_uop_is_amo, %slots_21.io_out_uop_uses_ldq, %slots_21.io_out_uop_uses_stq, %slots_21.io_out_uop_ldst_val, %slots_21.io_out_uop_dst_rtype, %slots_21.io_out_uop_lrs1_rtype, %slots_21.io_out_uop_lrs2_rtype, %slots_21.io_out_uop_fp_val, %slots_21.io_uop_uopc, %slots_21.io_uop_is_rvc, %slots_21.io_uop_fu_code, %slots_21.io_uop_iw_p1_poisoned, %slots_21.io_uop_iw_p2_poisoned, %slots_21.io_uop_is_br, %slots_21.io_uop_is_jalr, %slots_21.io_uop_is_jal, %slots_21.io_uop_is_sfb, %slots_21.io_uop_br_mask, %slots_21.io_uop_br_tag, %slots_21.io_uop_ftq_idx, %slots_21.io_uop_edge_inst, %slots_21.io_uop_pc_lob, %slots_21.io_uop_taken, %slots_21.io_uop_imm_packed, %slots_21.io_uop_rob_idx, %slots_21.io_uop_ldq_idx, %slots_21.io_uop_stq_idx, %slots_21.io_uop_pdst, %slots_21.io_uop_prs1, %slots_21.io_uop_prs2, %slots_21.io_uop_bypassable, %slots_21.io_uop_mem_cmd, %slots_21.io_uop_mem_size, %slots_21.io_uop_mem_signed, %slots_21.io_uop_is_fence, %slots_21.io_uop_is_amo, %slots_21.io_uop_uses_ldq, %slots_21.io_uop_uses_stq, %slots_21.io_uop_ldst_val, %slots_21.io_uop_dst_rtype, %slots_21.io_uop_lrs1_rtype, %slots_21.io_uop_lrs2_rtype, %slots_21.io_uop_fp_val = hw.instance "slots_21" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %936: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %3993: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %3992: i1, io_in_uop_bits_uopc: %11593: i7, io_in_uop_bits_is_rvc: %11594: i1, io_in_uop_bits_fu_code: %11595: i10, io_in_uop_bits_iw_state: %11596: i2, io_in_uop_bits_iw_p1_poisoned: %11597: i1, io_in_uop_bits_iw_p2_poisoned: %11598: i1, io_in_uop_bits_is_br: %11599: i1, io_in_uop_bits_is_jalr: %11600: i1, io_in_uop_bits_is_jal: %11601: i1, io_in_uop_bits_is_sfb: %11602: i1, io_in_uop_bits_br_mask: %11603: i20, io_in_uop_bits_br_tag: %11604: i5, io_in_uop_bits_ftq_idx: %11605: i6, io_in_uop_bits_edge_inst: %11606: i1, io_in_uop_bits_pc_lob: %11607: i6, io_in_uop_bits_taken: %11608: i1, io_in_uop_bits_imm_packed: %11609: i20, io_in_uop_bits_rob_idx: %11610: i7, io_in_uop_bits_ldq_idx: %11611: i5, io_in_uop_bits_stq_idx: %11612: i5, io_in_uop_bits_pdst: %11613: i7, io_in_uop_bits_prs1: %11614: i7, io_in_uop_bits_prs2: %11615: i7, io_in_uop_bits_prs3: %11616: i7, io_in_uop_bits_prs1_busy: %11617: i1, io_in_uop_bits_prs2_busy: %11618: i1, io_in_uop_bits_prs3_busy: %11619: i1, io_in_uop_bits_ppred_busy: %11620: i1, io_in_uop_bits_bypassable: %11621: i1, io_in_uop_bits_mem_cmd: %11622: i5, io_in_uop_bits_mem_size: %11623: i2, io_in_uop_bits_mem_signed: %11624: i1, io_in_uop_bits_is_fence: %11625: i1, io_in_uop_bits_is_amo: %11626: i1, io_in_uop_bits_uses_ldq: %11627: i1, io_in_uop_bits_uses_stq: %11628: i1, io_in_uop_bits_ldst_val: %11629: i1, io_in_uop_bits_dst_rtype: %11630: i2, io_in_uop_bits_lrs1_rtype: %11631: i2, io_in_uop_bits_lrs2_rtype: %11632: i2, io_in_uop_bits_fp_val: %11633: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_22.io_valid, %slots_22.io_will_be_valid, %slots_22.io_request, %slots_22.io_out_uop_uopc, %slots_22.io_out_uop_is_rvc, %slots_22.io_out_uop_fu_code, %slots_22.io_out_uop_iw_state, %slots_22.io_out_uop_iw_p1_poisoned, %slots_22.io_out_uop_iw_p2_poisoned, %slots_22.io_out_uop_is_br, %slots_22.io_out_uop_is_jalr, %slots_22.io_out_uop_is_jal, %slots_22.io_out_uop_is_sfb, %slots_22.io_out_uop_br_mask, %slots_22.io_out_uop_br_tag, %slots_22.io_out_uop_ftq_idx, %slots_22.io_out_uop_edge_inst, %slots_22.io_out_uop_pc_lob, %slots_22.io_out_uop_taken, %slots_22.io_out_uop_imm_packed, %slots_22.io_out_uop_rob_idx, %slots_22.io_out_uop_ldq_idx, %slots_22.io_out_uop_stq_idx, %slots_22.io_out_uop_pdst, %slots_22.io_out_uop_prs1, %slots_22.io_out_uop_prs2, %slots_22.io_out_uop_prs3, %slots_22.io_out_uop_prs1_busy, %slots_22.io_out_uop_prs2_busy, %slots_22.io_out_uop_prs3_busy, %slots_22.io_out_uop_ppred_busy, %slots_22.io_out_uop_bypassable, %slots_22.io_out_uop_mem_cmd, %slots_22.io_out_uop_mem_size, %slots_22.io_out_uop_mem_signed, %slots_22.io_out_uop_is_fence, %slots_22.io_out_uop_is_amo, %slots_22.io_out_uop_uses_ldq, %slots_22.io_out_uop_uses_stq, %slots_22.io_out_uop_ldst_val, %slots_22.io_out_uop_dst_rtype, %slots_22.io_out_uop_lrs1_rtype, %slots_22.io_out_uop_lrs2_rtype, %slots_22.io_out_uop_fp_val, %slots_22.io_uop_uopc, %slots_22.io_uop_is_rvc, %slots_22.io_uop_fu_code, %slots_22.io_uop_iw_p1_poisoned, %slots_22.io_uop_iw_p2_poisoned, %slots_22.io_uop_is_br, %slots_22.io_uop_is_jalr, %slots_22.io_uop_is_jal, %slots_22.io_uop_is_sfb, %slots_22.io_uop_br_mask, %slots_22.io_uop_br_tag, %slots_22.io_uop_ftq_idx, %slots_22.io_uop_edge_inst, %slots_22.io_uop_pc_lob, %slots_22.io_uop_taken, %slots_22.io_uop_imm_packed, %slots_22.io_uop_rob_idx, %slots_22.io_uop_ldq_idx, %slots_22.io_uop_stq_idx, %slots_22.io_uop_pdst, %slots_22.io_uop_prs1, %slots_22.io_uop_prs2, %slots_22.io_uop_bypassable, %slots_22.io_uop_mem_cmd, %slots_22.io_uop_mem_size, %slots_22.io_uop_mem_signed, %slots_22.io_uop_is_fence, %slots_22.io_uop_is_amo, %slots_22.io_uop_uses_ldq, %slots_22.io_uop_uses_stq, %slots_22.io_uop_ldst_val, %slots_22.io_uop_dst_rtype, %slots_22.io_uop_lrs1_rtype, %slots_22.io_uop_lrs2_rtype, %slots_22.io_uop_fp_val = hw.instance "slots_22" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1043: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %4084: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %4083: i1, io_in_uop_bits_uopc: %11634: i7, io_in_uop_bits_is_rvc: %11635: i1, io_in_uop_bits_fu_code: %11636: i10, io_in_uop_bits_iw_state: %11637: i2, io_in_uop_bits_iw_p1_poisoned: %11638: i1, io_in_uop_bits_iw_p2_poisoned: %11639: i1, io_in_uop_bits_is_br: %11640: i1, io_in_uop_bits_is_jalr: %11641: i1, io_in_uop_bits_is_jal: %11642: i1, io_in_uop_bits_is_sfb: %11643: i1, io_in_uop_bits_br_mask: %11644: i20, io_in_uop_bits_br_tag: %11645: i5, io_in_uop_bits_ftq_idx: %11646: i6, io_in_uop_bits_edge_inst: %11647: i1, io_in_uop_bits_pc_lob: %11648: i6, io_in_uop_bits_taken: %11649: i1, io_in_uop_bits_imm_packed: %11650: i20, io_in_uop_bits_rob_idx: %11651: i7, io_in_uop_bits_ldq_idx: %11652: i5, io_in_uop_bits_stq_idx: %11653: i5, io_in_uop_bits_pdst: %11654: i7, io_in_uop_bits_prs1: %11655: i7, io_in_uop_bits_prs2: %11656: i7, io_in_uop_bits_prs3: %11657: i7, io_in_uop_bits_prs1_busy: %11658: i1, io_in_uop_bits_prs2_busy: %11659: i1, io_in_uop_bits_prs3_busy: %11660: i1, io_in_uop_bits_ppred_busy: %11661: i1, io_in_uop_bits_bypassable: %11662: i1, io_in_uop_bits_mem_cmd: %11663: i5, io_in_uop_bits_mem_size: %11664: i2, io_in_uop_bits_mem_signed: %11665: i1, io_in_uop_bits_is_fence: %11666: i1, io_in_uop_bits_is_amo: %11667: i1, io_in_uop_bits_uses_ldq: %11668: i1, io_in_uop_bits_uses_stq: %11669: i1, io_in_uop_bits_ldst_val: %11670: i1, io_in_uop_bits_dst_rtype: %11671: i2, io_in_uop_bits_lrs1_rtype: %11672: i2, io_in_uop_bits_lrs2_rtype: %11673: i2, io_in_uop_bits_fp_val: %11674: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_23.io_valid, %slots_23.io_will_be_valid, %slots_23.io_request, %slots_23.io_out_uop_uopc, %slots_23.io_out_uop_is_rvc, %slots_23.io_out_uop_fu_code, %slots_23.io_out_uop_iw_state, %slots_23.io_out_uop_iw_p1_poisoned, %slots_23.io_out_uop_iw_p2_poisoned, %slots_23.io_out_uop_is_br, %slots_23.io_out_uop_is_jalr, %slots_23.io_out_uop_is_jal, %slots_23.io_out_uop_is_sfb, %slots_23.io_out_uop_br_mask, %slots_23.io_out_uop_br_tag, %slots_23.io_out_uop_ftq_idx, %slots_23.io_out_uop_edge_inst, %slots_23.io_out_uop_pc_lob, %slots_23.io_out_uop_taken, %slots_23.io_out_uop_imm_packed, %slots_23.io_out_uop_rob_idx, %slots_23.io_out_uop_ldq_idx, %slots_23.io_out_uop_stq_idx, %slots_23.io_out_uop_pdst, %slots_23.io_out_uop_prs1, %slots_23.io_out_uop_prs2, %slots_23.io_out_uop_prs3, %slots_23.io_out_uop_prs1_busy, %slots_23.io_out_uop_prs2_busy, %slots_23.io_out_uop_prs3_busy, %slots_23.io_out_uop_ppred_busy, %slots_23.io_out_uop_bypassable, %slots_23.io_out_uop_mem_cmd, %slots_23.io_out_uop_mem_size, %slots_23.io_out_uop_mem_signed, %slots_23.io_out_uop_is_fence, %slots_23.io_out_uop_is_amo, %slots_23.io_out_uop_uses_ldq, %slots_23.io_out_uop_uses_stq, %slots_23.io_out_uop_ldst_val, %slots_23.io_out_uop_dst_rtype, %slots_23.io_out_uop_lrs1_rtype, %slots_23.io_out_uop_lrs2_rtype, %slots_23.io_out_uop_fp_val, %slots_23.io_uop_uopc, %slots_23.io_uop_is_rvc, %slots_23.io_uop_fu_code, %slots_23.io_uop_iw_p1_poisoned, %slots_23.io_uop_iw_p2_poisoned, %slots_23.io_uop_is_br, %slots_23.io_uop_is_jalr, %slots_23.io_uop_is_jal, %slots_23.io_uop_is_sfb, %slots_23.io_uop_br_mask, %slots_23.io_uop_br_tag, %slots_23.io_uop_ftq_idx, %slots_23.io_uop_edge_inst, %slots_23.io_uop_pc_lob, %slots_23.io_uop_taken, %slots_23.io_uop_imm_packed, %slots_23.io_uop_rob_idx, %slots_23.io_uop_ldq_idx, %slots_23.io_uop_stq_idx, %slots_23.io_uop_pdst, %slots_23.io_uop_prs1, %slots_23.io_uop_prs2, %slots_23.io_uop_bypassable, %slots_23.io_uop_mem_cmd, %slots_23.io_uop_mem_size, %slots_23.io_uop_mem_signed, %slots_23.io_uop_is_fence, %slots_23.io_uop_is_amo, %slots_23.io_uop_uses_ldq, %slots_23.io_uop_uses_stq, %slots_23.io_uop_ldst_val, %slots_23.io_uop_dst_rtype, %slots_23.io_uop_lrs1_rtype, %slots_23.io_uop_lrs2_rtype, %slots_23.io_uop_fp_val = hw.instance "slots_23" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1002: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %4175: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %4174: i1, io_in_uop_bits_uopc: %11675: i7, io_in_uop_bits_is_rvc: %11676: i1, io_in_uop_bits_fu_code: %11677: i10, io_in_uop_bits_iw_state: %11678: i2, io_in_uop_bits_iw_p1_poisoned: %11679: i1, io_in_uop_bits_iw_p2_poisoned: %11680: i1, io_in_uop_bits_is_br: %11681: i1, io_in_uop_bits_is_jalr: %11682: i1, io_in_uop_bits_is_jal: %11683: i1, io_in_uop_bits_is_sfb: %11684: i1, io_in_uop_bits_br_mask: %11685: i20, io_in_uop_bits_br_tag: %11686: i5, io_in_uop_bits_ftq_idx: %11687: i6, io_in_uop_bits_edge_inst: %11688: i1, io_in_uop_bits_pc_lob: %11689: i6, io_in_uop_bits_taken: %11690: i1, io_in_uop_bits_imm_packed: %11691: i20, io_in_uop_bits_rob_idx: %11692: i7, io_in_uop_bits_ldq_idx: %11693: i5, io_in_uop_bits_stq_idx: %11694: i5, io_in_uop_bits_pdst: %11695: i7, io_in_uop_bits_prs1: %11696: i7, io_in_uop_bits_prs2: %11697: i7, io_in_uop_bits_prs3: %11698: i7, io_in_uop_bits_prs1_busy: %11699: i1, io_in_uop_bits_prs2_busy: %11700: i1, io_in_uop_bits_prs3_busy: %11701: i1, io_in_uop_bits_ppred_busy: %11702: i1, io_in_uop_bits_bypassable: %11703: i1, io_in_uop_bits_mem_cmd: %11704: i5, io_in_uop_bits_mem_size: %11705: i2, io_in_uop_bits_mem_signed: %11706: i1, io_in_uop_bits_is_fence: %11707: i1, io_in_uop_bits_is_amo: %11708: i1, io_in_uop_bits_uses_ldq: %11709: i1, io_in_uop_bits_uses_stq: %11710: i1, io_in_uop_bits_ldst_val: %11711: i1, io_in_uop_bits_dst_rtype: %11712: i2, io_in_uop_bits_lrs1_rtype: %11713: i2, io_in_uop_bits_lrs2_rtype: %11714: i2, io_in_uop_bits_fp_val: %11715: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_24.io_valid, %slots_24.io_will_be_valid, %slots_24.io_request, %slots_24.io_out_uop_uopc, %slots_24.io_out_uop_is_rvc, %slots_24.io_out_uop_fu_code, %slots_24.io_out_uop_iw_state, %slots_24.io_out_uop_iw_p1_poisoned, %slots_24.io_out_uop_iw_p2_poisoned, %slots_24.io_out_uop_is_br, %slots_24.io_out_uop_is_jalr, %slots_24.io_out_uop_is_jal, %slots_24.io_out_uop_is_sfb, %slots_24.io_out_uop_br_mask, %slots_24.io_out_uop_br_tag, %slots_24.io_out_uop_ftq_idx, %slots_24.io_out_uop_edge_inst, %slots_24.io_out_uop_pc_lob, %slots_24.io_out_uop_taken, %slots_24.io_out_uop_imm_packed, %slots_24.io_out_uop_rob_idx, %slots_24.io_out_uop_ldq_idx, %slots_24.io_out_uop_stq_idx, %slots_24.io_out_uop_pdst, %slots_24.io_out_uop_prs1, %slots_24.io_out_uop_prs2, %slots_24.io_out_uop_prs3, %slots_24.io_out_uop_prs1_busy, %slots_24.io_out_uop_prs2_busy, %slots_24.io_out_uop_prs3_busy, %slots_24.io_out_uop_ppred_busy, %slots_24.io_out_uop_bypassable, %slots_24.io_out_uop_mem_cmd, %slots_24.io_out_uop_mem_size, %slots_24.io_out_uop_mem_signed, %slots_24.io_out_uop_is_fence, %slots_24.io_out_uop_is_amo, %slots_24.io_out_uop_uses_ldq, %slots_24.io_out_uop_uses_stq, %slots_24.io_out_uop_ldst_val, %slots_24.io_out_uop_dst_rtype, %slots_24.io_out_uop_lrs1_rtype, %slots_24.io_out_uop_lrs2_rtype, %slots_24.io_out_uop_fp_val, %slots_24.io_uop_uopc, %slots_24.io_uop_is_rvc, %slots_24.io_uop_fu_code, %slots_24.io_uop_iw_p1_poisoned, %slots_24.io_uop_iw_p2_poisoned, %slots_24.io_uop_is_br, %slots_24.io_uop_is_jalr, %slots_24.io_uop_is_jal, %slots_24.io_uop_is_sfb, %slots_24.io_uop_br_mask, %slots_24.io_uop_br_tag, %slots_24.io_uop_ftq_idx, %slots_24.io_uop_edge_inst, %slots_24.io_uop_pc_lob, %slots_24.io_uop_taken, %slots_24.io_uop_imm_packed, %slots_24.io_uop_rob_idx, %slots_24.io_uop_ldq_idx, %slots_24.io_uop_stq_idx, %slots_24.io_uop_pdst, %slots_24.io_uop_prs1, %slots_24.io_uop_prs2, %slots_24.io_uop_bypassable, %slots_24.io_uop_mem_cmd, %slots_24.io_uop_mem_size, %slots_24.io_uop_mem_signed, %slots_24.io_uop_is_fence, %slots_24.io_uop_is_amo, %slots_24.io_uop_uses_ldq, %slots_24.io_uop_uses_stq, %slots_24.io_uop_ldst_val, %slots_24.io_uop_dst_rtype, %slots_24.io_uop_lrs1_rtype, %slots_24.io_uop_lrs2_rtype, %slots_24.io_uop_fp_val = hw.instance "slots_24" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1036: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %4266: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %4265: i1, io_in_uop_bits_uopc: %11716: i7, io_in_uop_bits_is_rvc: %11717: i1, io_in_uop_bits_fu_code: %11718: i10, io_in_uop_bits_iw_state: %11719: i2, io_in_uop_bits_iw_p1_poisoned: %11720: i1, io_in_uop_bits_iw_p2_poisoned: %11721: i1, io_in_uop_bits_is_br: %11722: i1, io_in_uop_bits_is_jalr: %11723: i1, io_in_uop_bits_is_jal: %11724: i1, io_in_uop_bits_is_sfb: %11725: i1, io_in_uop_bits_br_mask: %11726: i20, io_in_uop_bits_br_tag: %11727: i5, io_in_uop_bits_ftq_idx: %11728: i6, io_in_uop_bits_edge_inst: %11729: i1, io_in_uop_bits_pc_lob: %11730: i6, io_in_uop_bits_taken: %11731: i1, io_in_uop_bits_imm_packed: %11732: i20, io_in_uop_bits_rob_idx: %11733: i7, io_in_uop_bits_ldq_idx: %11734: i5, io_in_uop_bits_stq_idx: %11735: i5, io_in_uop_bits_pdst: %11736: i7, io_in_uop_bits_prs1: %11737: i7, io_in_uop_bits_prs2: %11738: i7, io_in_uop_bits_prs3: %11739: i7, io_in_uop_bits_prs1_busy: %11740: i1, io_in_uop_bits_prs2_busy: %11741: i1, io_in_uop_bits_prs3_busy: %11742: i1, io_in_uop_bits_ppred_busy: %11743: i1, io_in_uop_bits_bypassable: %11744: i1, io_in_uop_bits_mem_cmd: %11745: i5, io_in_uop_bits_mem_size: %11746: i2, io_in_uop_bits_mem_signed: %11747: i1, io_in_uop_bits_is_fence: %11748: i1, io_in_uop_bits_is_amo: %11749: i1, io_in_uop_bits_uses_ldq: %11750: i1, io_in_uop_bits_uses_stq: %11751: i1, io_in_uop_bits_ldst_val: %11752: i1, io_in_uop_bits_dst_rtype: %11753: i2, io_in_uop_bits_lrs1_rtype: %11754: i2, io_in_uop_bits_lrs2_rtype: %11755: i2, io_in_uop_bits_fp_val: %11756: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_25.io_valid, %slots_25.io_will_be_valid, %slots_25.io_request, %slots_25.io_out_uop_uopc, %slots_25.io_out_uop_is_rvc, %slots_25.io_out_uop_fu_code, %slots_25.io_out_uop_iw_state, %slots_25.io_out_uop_iw_p1_poisoned, %slots_25.io_out_uop_iw_p2_poisoned, %slots_25.io_out_uop_is_br, %slots_25.io_out_uop_is_jalr, %slots_25.io_out_uop_is_jal, %slots_25.io_out_uop_is_sfb, %slots_25.io_out_uop_br_mask, %slots_25.io_out_uop_br_tag, %slots_25.io_out_uop_ftq_idx, %slots_25.io_out_uop_edge_inst, %slots_25.io_out_uop_pc_lob, %slots_25.io_out_uop_taken, %slots_25.io_out_uop_imm_packed, %slots_25.io_out_uop_rob_idx, %slots_25.io_out_uop_ldq_idx, %slots_25.io_out_uop_stq_idx, %slots_25.io_out_uop_pdst, %slots_25.io_out_uop_prs1, %slots_25.io_out_uop_prs2, %slots_25.io_out_uop_prs3, %slots_25.io_out_uop_prs1_busy, %slots_25.io_out_uop_prs2_busy, %slots_25.io_out_uop_prs3_busy, %slots_25.io_out_uop_ppred_busy, %slots_25.io_out_uop_bypassable, %slots_25.io_out_uop_mem_cmd, %slots_25.io_out_uop_mem_size, %slots_25.io_out_uop_mem_signed, %slots_25.io_out_uop_is_fence, %slots_25.io_out_uop_is_amo, %slots_25.io_out_uop_uses_ldq, %slots_25.io_out_uop_uses_stq, %slots_25.io_out_uop_ldst_val, %slots_25.io_out_uop_dst_rtype, %slots_25.io_out_uop_lrs1_rtype, %slots_25.io_out_uop_lrs2_rtype, %slots_25.io_out_uop_fp_val, %slots_25.io_uop_uopc, %slots_25.io_uop_is_rvc, %slots_25.io_uop_fu_code, %slots_25.io_uop_iw_p1_poisoned, %slots_25.io_uop_iw_p2_poisoned, %slots_25.io_uop_is_br, %slots_25.io_uop_is_jalr, %slots_25.io_uop_is_jal, %slots_25.io_uop_is_sfb, %slots_25.io_uop_br_mask, %slots_25.io_uop_br_tag, %slots_25.io_uop_ftq_idx, %slots_25.io_uop_edge_inst, %slots_25.io_uop_pc_lob, %slots_25.io_uop_taken, %slots_25.io_uop_imm_packed, %slots_25.io_uop_rob_idx, %slots_25.io_uop_ldq_idx, %slots_25.io_uop_stq_idx, %slots_25.io_uop_pdst, %slots_25.io_uop_prs1, %slots_25.io_uop_prs2, %slots_25.io_uop_bypassable, %slots_25.io_uop_mem_cmd, %slots_25.io_uop_mem_size, %slots_25.io_uop_mem_signed, %slots_25.io_uop_is_fence, %slots_25.io_uop_is_amo, %slots_25.io_uop_uses_ldq, %slots_25.io_uop_uses_stq, %slots_25.io_uop_ldst_val, %slots_25.io_uop_dst_rtype, %slots_25.io_uop_lrs1_rtype, %slots_25.io_uop_lrs2_rtype, %slots_25.io_uop_fp_val = hw.instance "slots_25" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1082: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %4357: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %4356: i1, io_in_uop_bits_uopc: %11757: i7, io_in_uop_bits_is_rvc: %11758: i1, io_in_uop_bits_fu_code: %11759: i10, io_in_uop_bits_iw_state: %11760: i2, io_in_uop_bits_iw_p1_poisoned: %11761: i1, io_in_uop_bits_iw_p2_poisoned: %11762: i1, io_in_uop_bits_is_br: %11763: i1, io_in_uop_bits_is_jalr: %11764: i1, io_in_uop_bits_is_jal: %11765: i1, io_in_uop_bits_is_sfb: %11766: i1, io_in_uop_bits_br_mask: %11767: i20, io_in_uop_bits_br_tag: %11768: i5, io_in_uop_bits_ftq_idx: %11769: i6, io_in_uop_bits_edge_inst: %11770: i1, io_in_uop_bits_pc_lob: %11771: i6, io_in_uop_bits_taken: %11772: i1, io_in_uop_bits_imm_packed: %11773: i20, io_in_uop_bits_rob_idx: %11774: i7, io_in_uop_bits_ldq_idx: %11775: i5, io_in_uop_bits_stq_idx: %11776: i5, io_in_uop_bits_pdst: %11777: i7, io_in_uop_bits_prs1: %11778: i7, io_in_uop_bits_prs2: %11779: i7, io_in_uop_bits_prs3: %11780: i7, io_in_uop_bits_prs1_busy: %11781: i1, io_in_uop_bits_prs2_busy: %11782: i1, io_in_uop_bits_prs3_busy: %11783: i1, io_in_uop_bits_ppred_busy: %11784: i1, io_in_uop_bits_bypassable: %11785: i1, io_in_uop_bits_mem_cmd: %11786: i5, io_in_uop_bits_mem_size: %11787: i2, io_in_uop_bits_mem_signed: %11788: i1, io_in_uop_bits_is_fence: %11789: i1, io_in_uop_bits_is_amo: %11790: i1, io_in_uop_bits_uses_ldq: %11791: i1, io_in_uop_bits_uses_stq: %11792: i1, io_in_uop_bits_ldst_val: %11793: i1, io_in_uop_bits_dst_rtype: %11794: i2, io_in_uop_bits_lrs1_rtype: %11795: i2, io_in_uop_bits_lrs2_rtype: %11796: i2, io_in_uop_bits_fp_val: %11797: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_26.io_valid, %slots_26.io_will_be_valid, %slots_26.io_request, %slots_26.io_out_uop_uopc, %slots_26.io_out_uop_is_rvc, %slots_26.io_out_uop_fu_code, %slots_26.io_out_uop_iw_state, %slots_26.io_out_uop_iw_p1_poisoned, %slots_26.io_out_uop_iw_p2_poisoned, %slots_26.io_out_uop_is_br, %slots_26.io_out_uop_is_jalr, %slots_26.io_out_uop_is_jal, %slots_26.io_out_uop_is_sfb, %slots_26.io_out_uop_br_mask, %slots_26.io_out_uop_br_tag, %slots_26.io_out_uop_ftq_idx, %slots_26.io_out_uop_edge_inst, %slots_26.io_out_uop_pc_lob, %slots_26.io_out_uop_taken, %slots_26.io_out_uop_imm_packed, %slots_26.io_out_uop_rob_idx, %slots_26.io_out_uop_ldq_idx, %slots_26.io_out_uop_stq_idx, %slots_26.io_out_uop_pdst, %slots_26.io_out_uop_prs1, %slots_26.io_out_uop_prs2, %slots_26.io_out_uop_prs3, %slots_26.io_out_uop_prs1_busy, %slots_26.io_out_uop_prs2_busy, %slots_26.io_out_uop_prs3_busy, %slots_26.io_out_uop_ppred_busy, %slots_26.io_out_uop_bypassable, %slots_26.io_out_uop_mem_cmd, %slots_26.io_out_uop_mem_size, %slots_26.io_out_uop_mem_signed, %slots_26.io_out_uop_is_fence, %slots_26.io_out_uop_is_amo, %slots_26.io_out_uop_uses_ldq, %slots_26.io_out_uop_uses_stq, %slots_26.io_out_uop_ldst_val, %slots_26.io_out_uop_dst_rtype, %slots_26.io_out_uop_lrs1_rtype, %slots_26.io_out_uop_lrs2_rtype, %slots_26.io_out_uop_fp_val, %slots_26.io_uop_uopc, %slots_26.io_uop_is_rvc, %slots_26.io_uop_fu_code, %slots_26.io_uop_iw_p1_poisoned, %slots_26.io_uop_iw_p2_poisoned, %slots_26.io_uop_is_br, %slots_26.io_uop_is_jalr, %slots_26.io_uop_is_jal, %slots_26.io_uop_is_sfb, %slots_26.io_uop_br_mask, %slots_26.io_uop_br_tag, %slots_26.io_uop_ftq_idx, %slots_26.io_uop_edge_inst, %slots_26.io_uop_pc_lob, %slots_26.io_uop_taken, %slots_26.io_uop_imm_packed, %slots_26.io_uop_rob_idx, %slots_26.io_uop_ldq_idx, %slots_26.io_uop_stq_idx, %slots_26.io_uop_pdst, %slots_26.io_uop_prs1, %slots_26.io_uop_prs2, %slots_26.io_uop_bypassable, %slots_26.io_uop_mem_cmd, %slots_26.io_uop_mem_size, %slots_26.io_uop_mem_signed, %slots_26.io_uop_is_fence, %slots_26.io_uop_is_amo, %slots_26.io_uop_uses_ldq, %slots_26.io_uop_uses_stq, %slots_26.io_uop_ldst_val, %slots_26.io_uop_dst_rtype, %slots_26.io_uop_lrs1_rtype, %slots_26.io_uop_lrs2_rtype, %slots_26.io_uop_fp_val = hw.instance "slots_26" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1116: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %4448: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %4447: i1, io_in_uop_bits_uopc: %11798: i7, io_in_uop_bits_is_rvc: %11799: i1, io_in_uop_bits_fu_code: %11800: i10, io_in_uop_bits_iw_state: %11801: i2, io_in_uop_bits_iw_p1_poisoned: %11802: i1, io_in_uop_bits_iw_p2_poisoned: %11803: i1, io_in_uop_bits_is_br: %11804: i1, io_in_uop_bits_is_jalr: %11805: i1, io_in_uop_bits_is_jal: %11806: i1, io_in_uop_bits_is_sfb: %11807: i1, io_in_uop_bits_br_mask: %11808: i20, io_in_uop_bits_br_tag: %11809: i5, io_in_uop_bits_ftq_idx: %11810: i6, io_in_uop_bits_edge_inst: %11811: i1, io_in_uop_bits_pc_lob: %11812: i6, io_in_uop_bits_taken: %11813: i1, io_in_uop_bits_imm_packed: %11814: i20, io_in_uop_bits_rob_idx: %11815: i7, io_in_uop_bits_ldq_idx: %11816: i5, io_in_uop_bits_stq_idx: %11817: i5, io_in_uop_bits_pdst: %11818: i7, io_in_uop_bits_prs1: %11819: i7, io_in_uop_bits_prs2: %11820: i7, io_in_uop_bits_prs3: %11821: i7, io_in_uop_bits_prs1_busy: %11822: i1, io_in_uop_bits_prs2_busy: %11823: i1, io_in_uop_bits_prs3_busy: %11824: i1, io_in_uop_bits_ppred_busy: %11825: i1, io_in_uop_bits_bypassable: %11826: i1, io_in_uop_bits_mem_cmd: %11827: i5, io_in_uop_bits_mem_size: %11828: i2, io_in_uop_bits_mem_signed: %11829: i1, io_in_uop_bits_is_fence: %11830: i1, io_in_uop_bits_is_amo: %11831: i1, io_in_uop_bits_uses_ldq: %11832: i1, io_in_uop_bits_uses_stq: %11833: i1, io_in_uop_bits_ldst_val: %11834: i1, io_in_uop_bits_dst_rtype: %11835: i2, io_in_uop_bits_lrs1_rtype: %11836: i2, io_in_uop_bits_lrs2_rtype: %11837: i2, io_in_uop_bits_fp_val: %11838: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_27.io_valid, %slots_27.io_will_be_valid, %slots_27.io_request, %slots_27.io_out_uop_uopc, %slots_27.io_out_uop_is_rvc, %slots_27.io_out_uop_fu_code, %slots_27.io_out_uop_iw_state, %slots_27.io_out_uop_iw_p1_poisoned, %slots_27.io_out_uop_iw_p2_poisoned, %slots_27.io_out_uop_is_br, %slots_27.io_out_uop_is_jalr, %slots_27.io_out_uop_is_jal, %slots_27.io_out_uop_is_sfb, %slots_27.io_out_uop_br_mask, %slots_27.io_out_uop_br_tag, %slots_27.io_out_uop_ftq_idx, %slots_27.io_out_uop_edge_inst, %slots_27.io_out_uop_pc_lob, %slots_27.io_out_uop_taken, %slots_27.io_out_uop_imm_packed, %slots_27.io_out_uop_rob_idx, %slots_27.io_out_uop_ldq_idx, %slots_27.io_out_uop_stq_idx, %slots_27.io_out_uop_pdst, %slots_27.io_out_uop_prs1, %slots_27.io_out_uop_prs2, %slots_27.io_out_uop_prs3, %slots_27.io_out_uop_prs1_busy, %slots_27.io_out_uop_prs2_busy, %slots_27.io_out_uop_prs3_busy, %slots_27.io_out_uop_ppred_busy, %slots_27.io_out_uop_bypassable, %slots_27.io_out_uop_mem_cmd, %slots_27.io_out_uop_mem_size, %slots_27.io_out_uop_mem_signed, %slots_27.io_out_uop_is_fence, %slots_27.io_out_uop_is_amo, %slots_27.io_out_uop_uses_ldq, %slots_27.io_out_uop_uses_stq, %slots_27.io_out_uop_ldst_val, %slots_27.io_out_uop_dst_rtype, %slots_27.io_out_uop_lrs1_rtype, %slots_27.io_out_uop_lrs2_rtype, %slots_27.io_out_uop_fp_val, %slots_27.io_uop_uopc, %slots_27.io_uop_is_rvc, %slots_27.io_uop_fu_code, %slots_27.io_uop_iw_p1_poisoned, %slots_27.io_uop_iw_p2_poisoned, %slots_27.io_uop_is_br, %slots_27.io_uop_is_jalr, %slots_27.io_uop_is_jal, %slots_27.io_uop_is_sfb, %slots_27.io_uop_br_mask, %slots_27.io_uop_br_tag, %slots_27.io_uop_ftq_idx, %slots_27.io_uop_edge_inst, %slots_27.io_uop_pc_lob, %slots_27.io_uop_taken, %slots_27.io_uop_imm_packed, %slots_27.io_uop_rob_idx, %slots_27.io_uop_ldq_idx, %slots_27.io_uop_stq_idx, %slots_27.io_uop_pdst, %slots_27.io_uop_prs1, %slots_27.io_uop_prs2, %slots_27.io_uop_bypassable, %slots_27.io_uop_mem_cmd, %slots_27.io_uop_mem_size, %slots_27.io_uop_mem_signed, %slots_27.io_uop_is_fence, %slots_27.io_uop_is_amo, %slots_27.io_uop_uses_ldq, %slots_27.io_uop_uses_stq, %slots_27.io_uop_ldst_val, %slots_27.io_uop_dst_rtype, %slots_27.io_uop_lrs1_rtype, %slots_27.io_uop_lrs2_rtype, %slots_27.io_uop_fp_val = hw.instance "slots_27" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1223: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %4539: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %4538: i1, io_in_uop_bits_uopc: %11839: i7, io_in_uop_bits_is_rvc: %11840: i1, io_in_uop_bits_fu_code: %11841: i10, io_in_uop_bits_iw_state: %11842: i2, io_in_uop_bits_iw_p1_poisoned: %11843: i1, io_in_uop_bits_iw_p2_poisoned: %11844: i1, io_in_uop_bits_is_br: %11845: i1, io_in_uop_bits_is_jalr: %11846: i1, io_in_uop_bits_is_jal: %11847: i1, io_in_uop_bits_is_sfb: %11848: i1, io_in_uop_bits_br_mask: %11849: i20, io_in_uop_bits_br_tag: %11850: i5, io_in_uop_bits_ftq_idx: %11851: i6, io_in_uop_bits_edge_inst: %11852: i1, io_in_uop_bits_pc_lob: %11853: i6, io_in_uop_bits_taken: %11854: i1, io_in_uop_bits_imm_packed: %11855: i20, io_in_uop_bits_rob_idx: %11856: i7, io_in_uop_bits_ldq_idx: %11857: i5, io_in_uop_bits_stq_idx: %11858: i5, io_in_uop_bits_pdst: %11859: i7, io_in_uop_bits_prs1: %11860: i7, io_in_uop_bits_prs2: %11861: i7, io_in_uop_bits_prs3: %11862: i7, io_in_uop_bits_prs1_busy: %11863: i1, io_in_uop_bits_prs2_busy: %11864: i1, io_in_uop_bits_prs3_busy: %11865: i1, io_in_uop_bits_ppred_busy: %11866: i1, io_in_uop_bits_bypassable: %11867: i1, io_in_uop_bits_mem_cmd: %11868: i5, io_in_uop_bits_mem_size: %11869: i2, io_in_uop_bits_mem_signed: %11870: i1, io_in_uop_bits_is_fence: %11871: i1, io_in_uop_bits_is_amo: %11872: i1, io_in_uop_bits_uses_ldq: %11873: i1, io_in_uop_bits_uses_stq: %11874: i1, io_in_uop_bits_ldst_val: %11875: i1, io_in_uop_bits_dst_rtype: %11876: i2, io_in_uop_bits_lrs1_rtype: %11877: i2, io_in_uop_bits_lrs2_rtype: %11878: i2, io_in_uop_bits_fp_val: %11879: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_28.io_valid, %slots_28.io_will_be_valid, %slots_28.io_request, %slots_28.io_out_uop_uopc, %slots_28.io_out_uop_is_rvc, %slots_28.io_out_uop_fu_code, %slots_28.io_out_uop_iw_state, %slots_28.io_out_uop_iw_p1_poisoned, %slots_28.io_out_uop_iw_p2_poisoned, %slots_28.io_out_uop_is_br, %slots_28.io_out_uop_is_jalr, %slots_28.io_out_uop_is_jal, %slots_28.io_out_uop_is_sfb, %slots_28.io_out_uop_br_mask, %slots_28.io_out_uop_br_tag, %slots_28.io_out_uop_ftq_idx, %slots_28.io_out_uop_edge_inst, %slots_28.io_out_uop_pc_lob, %slots_28.io_out_uop_taken, %slots_28.io_out_uop_imm_packed, %slots_28.io_out_uop_rob_idx, %slots_28.io_out_uop_ldq_idx, %slots_28.io_out_uop_stq_idx, %slots_28.io_out_uop_pdst, %slots_28.io_out_uop_prs1, %slots_28.io_out_uop_prs2, %slots_28.io_out_uop_prs3, %slots_28.io_out_uop_prs1_busy, %slots_28.io_out_uop_prs2_busy, %slots_28.io_out_uop_prs3_busy, %slots_28.io_out_uop_ppred_busy, %slots_28.io_out_uop_bypassable, %slots_28.io_out_uop_mem_cmd, %slots_28.io_out_uop_mem_size, %slots_28.io_out_uop_mem_signed, %slots_28.io_out_uop_is_fence, %slots_28.io_out_uop_is_amo, %slots_28.io_out_uop_uses_ldq, %slots_28.io_out_uop_uses_stq, %slots_28.io_out_uop_ldst_val, %slots_28.io_out_uop_dst_rtype, %slots_28.io_out_uop_lrs1_rtype, %slots_28.io_out_uop_lrs2_rtype, %slots_28.io_out_uop_fp_val, %slots_28.io_uop_uopc, %slots_28.io_uop_is_rvc, %slots_28.io_uop_fu_code, %slots_28.io_uop_iw_p1_poisoned, %slots_28.io_uop_iw_p2_poisoned, %slots_28.io_uop_is_br, %slots_28.io_uop_is_jalr, %slots_28.io_uop_is_jal, %slots_28.io_uop_is_sfb, %slots_28.io_uop_br_mask, %slots_28.io_uop_br_tag, %slots_28.io_uop_ftq_idx, %slots_28.io_uop_edge_inst, %slots_28.io_uop_pc_lob, %slots_28.io_uop_taken, %slots_28.io_uop_imm_packed, %slots_28.io_uop_rob_idx, %slots_28.io_uop_ldq_idx, %slots_28.io_uop_stq_idx, %slots_28.io_uop_pdst, %slots_28.io_uop_prs1, %slots_28.io_uop_prs2, %slots_28.io_uop_bypassable, %slots_28.io_uop_mem_cmd, %slots_28.io_uop_mem_size, %slots_28.io_uop_mem_signed, %slots_28.io_uop_is_fence, %slots_28.io_uop_is_amo, %slots_28.io_uop_uses_ldq, %slots_28.io_uop_uses_stq, %slots_28.io_uop_ldst_val, %slots_28.io_uop_dst_rtype, %slots_28.io_uop_lrs1_rtype, %slots_28.io_uop_lrs2_rtype, %slots_28.io_uop_fp_val = hw.instance "slots_28" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1182: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %4630: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %4629: i1, io_in_uop_bits_uopc: %11880: i7, io_in_uop_bits_is_rvc: %11881: i1, io_in_uop_bits_fu_code: %11882: i10, io_in_uop_bits_iw_state: %11883: i2, io_in_uop_bits_iw_p1_poisoned: %11884: i1, io_in_uop_bits_iw_p2_poisoned: %11885: i1, io_in_uop_bits_is_br: %11886: i1, io_in_uop_bits_is_jalr: %11887: i1, io_in_uop_bits_is_jal: %11888: i1, io_in_uop_bits_is_sfb: %11889: i1, io_in_uop_bits_br_mask: %11890: i20, io_in_uop_bits_br_tag: %11891: i5, io_in_uop_bits_ftq_idx: %11892: i6, io_in_uop_bits_edge_inst: %11893: i1, io_in_uop_bits_pc_lob: %11894: i6, io_in_uop_bits_taken: %11895: i1, io_in_uop_bits_imm_packed: %11896: i20, io_in_uop_bits_rob_idx: %11897: i7, io_in_uop_bits_ldq_idx: %11898: i5, io_in_uop_bits_stq_idx: %11899: i5, io_in_uop_bits_pdst: %11900: i7, io_in_uop_bits_prs1: %11901: i7, io_in_uop_bits_prs2: %11902: i7, io_in_uop_bits_prs3: %11903: i7, io_in_uop_bits_prs1_busy: %11904: i1, io_in_uop_bits_prs2_busy: %11905: i1, io_in_uop_bits_prs3_busy: %11906: i1, io_in_uop_bits_ppred_busy: %11907: i1, io_in_uop_bits_bypassable: %11908: i1, io_in_uop_bits_mem_cmd: %11909: i5, io_in_uop_bits_mem_size: %11910: i2, io_in_uop_bits_mem_signed: %11911: i1, io_in_uop_bits_is_fence: %11912: i1, io_in_uop_bits_is_amo: %11913: i1, io_in_uop_bits_uses_ldq: %11914: i1, io_in_uop_bits_uses_stq: %11915: i1, io_in_uop_bits_ldst_val: %11916: i1, io_in_uop_bits_dst_rtype: %11917: i2, io_in_uop_bits_lrs1_rtype: %11918: i2, io_in_uop_bits_lrs2_rtype: %11919: i2, io_in_uop_bits_fp_val: %11920: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_29.io_valid, %slots_29.io_will_be_valid, %slots_29.io_request, %slots_29.io_out_uop_uopc, %slots_29.io_out_uop_is_rvc, %slots_29.io_out_uop_fu_code, %slots_29.io_out_uop_iw_state, %slots_29.io_out_uop_iw_p1_poisoned, %slots_29.io_out_uop_iw_p2_poisoned, %slots_29.io_out_uop_is_br, %slots_29.io_out_uop_is_jalr, %slots_29.io_out_uop_is_jal, %slots_29.io_out_uop_is_sfb, %slots_29.io_out_uop_br_mask, %slots_29.io_out_uop_br_tag, %slots_29.io_out_uop_ftq_idx, %slots_29.io_out_uop_edge_inst, %slots_29.io_out_uop_pc_lob, %slots_29.io_out_uop_taken, %slots_29.io_out_uop_imm_packed, %slots_29.io_out_uop_rob_idx, %slots_29.io_out_uop_ldq_idx, %slots_29.io_out_uop_stq_idx, %slots_29.io_out_uop_pdst, %slots_29.io_out_uop_prs1, %slots_29.io_out_uop_prs2, %slots_29.io_out_uop_prs3, %slots_29.io_out_uop_prs1_busy, %slots_29.io_out_uop_prs2_busy, %slots_29.io_out_uop_prs3_busy, %slots_29.io_out_uop_ppred_busy, %slots_29.io_out_uop_bypassable, %slots_29.io_out_uop_mem_cmd, %slots_29.io_out_uop_mem_size, %slots_29.io_out_uop_mem_signed, %slots_29.io_out_uop_is_fence, %slots_29.io_out_uop_is_amo, %slots_29.io_out_uop_uses_ldq, %slots_29.io_out_uop_uses_stq, %slots_29.io_out_uop_ldst_val, %slots_29.io_out_uop_dst_rtype, %slots_29.io_out_uop_lrs1_rtype, %slots_29.io_out_uop_lrs2_rtype, %slots_29.io_out_uop_fp_val, %slots_29.io_uop_uopc, %slots_29.io_uop_is_rvc, %slots_29.io_uop_fu_code, %slots_29.io_uop_iw_p1_poisoned, %slots_29.io_uop_iw_p2_poisoned, %slots_29.io_uop_is_br, %slots_29.io_uop_is_jalr, %slots_29.io_uop_is_jal, %slots_29.io_uop_is_sfb, %slots_29.io_uop_br_mask, %slots_29.io_uop_br_tag, %slots_29.io_uop_ftq_idx, %slots_29.io_uop_edge_inst, %slots_29.io_uop_pc_lob, %slots_29.io_uop_taken, %slots_29.io_uop_imm_packed, %slots_29.io_uop_rob_idx, %slots_29.io_uop_ldq_idx, %slots_29.io_uop_stq_idx, %slots_29.io_uop_pdst, %slots_29.io_uop_prs1, %slots_29.io_uop_prs2, %slots_29.io_uop_bypassable, %slots_29.io_uop_mem_cmd, %slots_29.io_uop_mem_size, %slots_29.io_uop_mem_signed, %slots_29.io_uop_is_fence, %slots_29.io_uop_is_amo, %slots_29.io_uop_uses_ldq, %slots_29.io_uop_uses_stq, %slots_29.io_uop_ldst_val, %slots_29.io_uop_dst_rtype, %slots_29.io_uop_lrs1_rtype, %slots_29.io_uop_lrs2_rtype, %slots_29.io_uop_fp_val = hw.instance "slots_29" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1216: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %4721: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %4720: i1, io_in_uop_bits_uopc: %11921: i7, io_in_uop_bits_is_rvc: %11922: i1, io_in_uop_bits_fu_code: %11923: i10, io_in_uop_bits_iw_state: %11924: i2, io_in_uop_bits_iw_p1_poisoned: %11925: i1, io_in_uop_bits_iw_p2_poisoned: %11926: i1, io_in_uop_bits_is_br: %11927: i1, io_in_uop_bits_is_jalr: %11928: i1, io_in_uop_bits_is_jal: %11929: i1, io_in_uop_bits_is_sfb: %11930: i1, io_in_uop_bits_br_mask: %11931: i20, io_in_uop_bits_br_tag: %11932: i5, io_in_uop_bits_ftq_idx: %11933: i6, io_in_uop_bits_edge_inst: %11934: i1, io_in_uop_bits_pc_lob: %11935: i6, io_in_uop_bits_taken: %11936: i1, io_in_uop_bits_imm_packed: %11937: i20, io_in_uop_bits_rob_idx: %11938: i7, io_in_uop_bits_ldq_idx: %11939: i5, io_in_uop_bits_stq_idx: %11940: i5, io_in_uop_bits_pdst: %11941: i7, io_in_uop_bits_prs1: %11942: i7, io_in_uop_bits_prs2: %11943: i7, io_in_uop_bits_prs3: %11944: i7, io_in_uop_bits_prs1_busy: %11945: i1, io_in_uop_bits_prs2_busy: %11946: i1, io_in_uop_bits_prs3_busy: %11947: i1, io_in_uop_bits_ppred_busy: %11948: i1, io_in_uop_bits_bypassable: %11949: i1, io_in_uop_bits_mem_cmd: %11950: i5, io_in_uop_bits_mem_size: %11951: i2, io_in_uop_bits_mem_signed: %11952: i1, io_in_uop_bits_is_fence: %11953: i1, io_in_uop_bits_is_amo: %11954: i1, io_in_uop_bits_uses_ldq: %11955: i1, io_in_uop_bits_uses_stq: %11956: i1, io_in_uop_bits_ldst_val: %11957: i1, io_in_uop_bits_dst_rtype: %11958: i2, io_in_uop_bits_lrs1_rtype: %11959: i2, io_in_uop_bits_lrs2_rtype: %11960: i2, io_in_uop_bits_fp_val: %11961: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_30.io_valid, %slots_30.io_will_be_valid, %slots_30.io_request, %slots_30.io_out_uop_uopc, %slots_30.io_out_uop_is_rvc, %slots_30.io_out_uop_fu_code, %slots_30.io_out_uop_iw_state, %slots_30.io_out_uop_iw_p1_poisoned, %slots_30.io_out_uop_iw_p2_poisoned, %slots_30.io_out_uop_is_br, %slots_30.io_out_uop_is_jalr, %slots_30.io_out_uop_is_jal, %slots_30.io_out_uop_is_sfb, %slots_30.io_out_uop_br_mask, %slots_30.io_out_uop_br_tag, %slots_30.io_out_uop_ftq_idx, %slots_30.io_out_uop_edge_inst, %slots_30.io_out_uop_pc_lob, %slots_30.io_out_uop_taken, %slots_30.io_out_uop_imm_packed, %slots_30.io_out_uop_rob_idx, %slots_30.io_out_uop_ldq_idx, %slots_30.io_out_uop_stq_idx, %slots_30.io_out_uop_pdst, %slots_30.io_out_uop_prs1, %slots_30.io_out_uop_prs2, %slots_30.io_out_uop_prs3, %slots_30.io_out_uop_prs1_busy, %slots_30.io_out_uop_prs2_busy, %slots_30.io_out_uop_prs3_busy, %slots_30.io_out_uop_ppred_busy, %slots_30.io_out_uop_bypassable, %slots_30.io_out_uop_mem_cmd, %slots_30.io_out_uop_mem_size, %slots_30.io_out_uop_mem_signed, %slots_30.io_out_uop_is_fence, %slots_30.io_out_uop_is_amo, %slots_30.io_out_uop_uses_ldq, %slots_30.io_out_uop_uses_stq, %slots_30.io_out_uop_ldst_val, %slots_30.io_out_uop_dst_rtype, %slots_30.io_out_uop_lrs1_rtype, %slots_30.io_out_uop_lrs2_rtype, %slots_30.io_out_uop_fp_val, %slots_30.io_uop_uopc, %slots_30.io_uop_is_rvc, %slots_30.io_uop_fu_code, %slots_30.io_uop_iw_p1_poisoned, %slots_30.io_uop_iw_p2_poisoned, %slots_30.io_uop_is_br, %slots_30.io_uop_is_jalr, %slots_30.io_uop_is_jal, %slots_30.io_uop_is_sfb, %slots_30.io_uop_br_mask, %slots_30.io_uop_br_tag, %slots_30.io_uop_ftq_idx, %slots_30.io_uop_edge_inst, %slots_30.io_uop_pc_lob, %slots_30.io_uop_taken, %slots_30.io_uop_imm_packed, %slots_30.io_uop_rob_idx, %slots_30.io_uop_ldq_idx, %slots_30.io_uop_stq_idx, %slots_30.io_uop_pdst, %slots_30.io_uop_prs1, %slots_30.io_uop_prs2, %slots_30.io_uop_bypassable, %slots_30.io_uop_mem_cmd, %slots_30.io_uop_mem_size, %slots_30.io_uop_mem_signed, %slots_30.io_uop_is_fence, %slots_30.io_uop_is_amo, %slots_30.io_uop_uses_ldq, %slots_30.io_uop_uses_stq, %slots_30.io_uop_ldst_val, %slots_30.io_uop_dst_rtype, %slots_30.io_uop_lrs1_rtype, %slots_30.io_uop_lrs2_rtype, %slots_30.io_uop_fp_val = hw.instance "slots_30" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1265: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %4812: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %4811: i1, io_in_uop_bits_uopc: %11962: i7, io_in_uop_bits_is_rvc: %11963: i1, io_in_uop_bits_fu_code: %11964: i10, io_in_uop_bits_iw_state: %11965: i2, io_in_uop_bits_iw_p1_poisoned: %11966: i1, io_in_uop_bits_iw_p2_poisoned: %11967: i1, io_in_uop_bits_is_br: %11968: i1, io_in_uop_bits_is_jalr: %11969: i1, io_in_uop_bits_is_jal: %11970: i1, io_in_uop_bits_is_sfb: %11971: i1, io_in_uop_bits_br_mask: %11972: i20, io_in_uop_bits_br_tag: %11973: i5, io_in_uop_bits_ftq_idx: %11974: i6, io_in_uop_bits_edge_inst: %11975: i1, io_in_uop_bits_pc_lob: %11976: i6, io_in_uop_bits_taken: %11977: i1, io_in_uop_bits_imm_packed: %11978: i20, io_in_uop_bits_rob_idx: %11979: i7, io_in_uop_bits_ldq_idx: %11980: i5, io_in_uop_bits_stq_idx: %11981: i5, io_in_uop_bits_pdst: %11982: i7, io_in_uop_bits_prs1: %11983: i7, io_in_uop_bits_prs2: %11984: i7, io_in_uop_bits_prs3: %11985: i7, io_in_uop_bits_prs1_busy: %11986: i1, io_in_uop_bits_prs2_busy: %11987: i1, io_in_uop_bits_prs3_busy: %11988: i1, io_in_uop_bits_ppred_busy: %11989: i1, io_in_uop_bits_bypassable: %11990: i1, io_in_uop_bits_mem_cmd: %11991: i5, io_in_uop_bits_mem_size: %11992: i2, io_in_uop_bits_mem_signed: %11993: i1, io_in_uop_bits_is_fence: %11994: i1, io_in_uop_bits_is_amo: %11995: i1, io_in_uop_bits_uses_ldq: %11996: i1, io_in_uop_bits_uses_stq: %11997: i1, io_in_uop_bits_ldst_val: %11998: i1, io_in_uop_bits_dst_rtype: %11999: i2, io_in_uop_bits_lrs1_rtype: %12000: i2, io_in_uop_bits_lrs2_rtype: %12001: i2, io_in_uop_bits_fp_val: %12002: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_31.io_valid, %slots_31.io_will_be_valid, %slots_31.io_request, %slots_31.io_out_uop_uopc, %slots_31.io_out_uop_is_rvc, %slots_31.io_out_uop_fu_code, %slots_31.io_out_uop_iw_state, %slots_31.io_out_uop_iw_p1_poisoned, %slots_31.io_out_uop_iw_p2_poisoned, %slots_31.io_out_uop_is_br, %slots_31.io_out_uop_is_jalr, %slots_31.io_out_uop_is_jal, %slots_31.io_out_uop_is_sfb, %slots_31.io_out_uop_br_mask, %slots_31.io_out_uop_br_tag, %slots_31.io_out_uop_ftq_idx, %slots_31.io_out_uop_edge_inst, %slots_31.io_out_uop_pc_lob, %slots_31.io_out_uop_taken, %slots_31.io_out_uop_imm_packed, %slots_31.io_out_uop_rob_idx, %slots_31.io_out_uop_ldq_idx, %slots_31.io_out_uop_stq_idx, %slots_31.io_out_uop_pdst, %slots_31.io_out_uop_prs1, %slots_31.io_out_uop_prs2, %slots_31.io_out_uop_prs3, %slots_31.io_out_uop_prs1_busy, %slots_31.io_out_uop_prs2_busy, %slots_31.io_out_uop_prs3_busy, %slots_31.io_out_uop_ppred_busy, %slots_31.io_out_uop_bypassable, %slots_31.io_out_uop_mem_cmd, %slots_31.io_out_uop_mem_size, %slots_31.io_out_uop_mem_signed, %slots_31.io_out_uop_is_fence, %slots_31.io_out_uop_is_amo, %slots_31.io_out_uop_uses_ldq, %slots_31.io_out_uop_uses_stq, %slots_31.io_out_uop_ldst_val, %slots_31.io_out_uop_dst_rtype, %slots_31.io_out_uop_lrs1_rtype, %slots_31.io_out_uop_lrs2_rtype, %slots_31.io_out_uop_fp_val, %slots_31.io_uop_uopc, %slots_31.io_uop_is_rvc, %slots_31.io_uop_fu_code, %slots_31.io_uop_iw_p1_poisoned, %slots_31.io_uop_iw_p2_poisoned, %slots_31.io_uop_is_br, %slots_31.io_uop_is_jalr, %slots_31.io_uop_is_jal, %slots_31.io_uop_is_sfb, %slots_31.io_uop_br_mask, %slots_31.io_uop_br_tag, %slots_31.io_uop_ftq_idx, %slots_31.io_uop_edge_inst, %slots_31.io_uop_pc_lob, %slots_31.io_uop_taken, %slots_31.io_uop_imm_packed, %slots_31.io_uop_rob_idx, %slots_31.io_uop_ldq_idx, %slots_31.io_uop_stq_idx, %slots_31.io_uop_pdst, %slots_31.io_uop_prs1, %slots_31.io_uop_prs2, %slots_31.io_uop_bypassable, %slots_31.io_uop_mem_cmd, %slots_31.io_uop_mem_size, %slots_31.io_uop_mem_signed, %slots_31.io_uop_is_fence, %slots_31.io_uop_is_amo, %slots_31.io_uop_uses_ldq, %slots_31.io_uop_uses_stq, %slots_31.io_uop_ldst_val, %slots_31.io_uop_dst_rtype, %slots_31.io_uop_lrs1_rtype, %slots_31.io_uop_lrs2_rtype, %slots_31.io_uop_fp_val = hw.instance "slots_31" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1299: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %4903: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %4902: i1, io_in_uop_bits_uopc: %12003: i7, io_in_uop_bits_is_rvc: %12004: i1, io_in_uop_bits_fu_code: %12005: i10, io_in_uop_bits_iw_state: %12006: i2, io_in_uop_bits_iw_p1_poisoned: %12007: i1, io_in_uop_bits_iw_p2_poisoned: %12008: i1, io_in_uop_bits_is_br: %12009: i1, io_in_uop_bits_is_jalr: %12010: i1, io_in_uop_bits_is_jal: %12011: i1, io_in_uop_bits_is_sfb: %12012: i1, io_in_uop_bits_br_mask: %12013: i20, io_in_uop_bits_br_tag: %12014: i5, io_in_uop_bits_ftq_idx: %12015: i6, io_in_uop_bits_edge_inst: %12016: i1, io_in_uop_bits_pc_lob: %12017: i6, io_in_uop_bits_taken: %12018: i1, io_in_uop_bits_imm_packed: %12019: i20, io_in_uop_bits_rob_idx: %12020: i7, io_in_uop_bits_ldq_idx: %12021: i5, io_in_uop_bits_stq_idx: %12022: i5, io_in_uop_bits_pdst: %12023: i7, io_in_uop_bits_prs1: %12024: i7, io_in_uop_bits_prs2: %12025: i7, io_in_uop_bits_prs3: %12026: i7, io_in_uop_bits_prs1_busy: %12027: i1, io_in_uop_bits_prs2_busy: %12028: i1, io_in_uop_bits_prs3_busy: %12029: i1, io_in_uop_bits_ppred_busy: %12030: i1, io_in_uop_bits_bypassable: %12031: i1, io_in_uop_bits_mem_cmd: %12032: i5, io_in_uop_bits_mem_size: %12033: i2, io_in_uop_bits_mem_signed: %12034: i1, io_in_uop_bits_is_fence: %12035: i1, io_in_uop_bits_is_amo: %12036: i1, io_in_uop_bits_uses_ldq: %12037: i1, io_in_uop_bits_uses_stq: %12038: i1, io_in_uop_bits_ldst_val: %12039: i1, io_in_uop_bits_dst_rtype: %12040: i2, io_in_uop_bits_lrs1_rtype: %12041: i2, io_in_uop_bits_lrs2_rtype: %12042: i2, io_in_uop_bits_fp_val: %12043: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_32.io_valid, %slots_32.io_will_be_valid, %slots_32.io_request, %slots_32.io_out_uop_uopc, %slots_32.io_out_uop_is_rvc, %slots_32.io_out_uop_fu_code, %slots_32.io_out_uop_iw_state, %slots_32.io_out_uop_iw_p1_poisoned, %slots_32.io_out_uop_iw_p2_poisoned, %slots_32.io_out_uop_is_br, %slots_32.io_out_uop_is_jalr, %slots_32.io_out_uop_is_jal, %slots_32.io_out_uop_is_sfb, %slots_32.io_out_uop_br_mask, %slots_32.io_out_uop_br_tag, %slots_32.io_out_uop_ftq_idx, %slots_32.io_out_uop_edge_inst, %slots_32.io_out_uop_pc_lob, %slots_32.io_out_uop_taken, %slots_32.io_out_uop_imm_packed, %slots_32.io_out_uop_rob_idx, %slots_32.io_out_uop_ldq_idx, %slots_32.io_out_uop_stq_idx, %slots_32.io_out_uop_pdst, %slots_32.io_out_uop_prs1, %slots_32.io_out_uop_prs2, %slots_32.io_out_uop_prs3, %slots_32.io_out_uop_prs1_busy, %slots_32.io_out_uop_prs2_busy, %slots_32.io_out_uop_prs3_busy, %slots_32.io_out_uop_ppred_busy, %slots_32.io_out_uop_bypassable, %slots_32.io_out_uop_mem_cmd, %slots_32.io_out_uop_mem_size, %slots_32.io_out_uop_mem_signed, %slots_32.io_out_uop_is_fence, %slots_32.io_out_uop_is_amo, %slots_32.io_out_uop_uses_ldq, %slots_32.io_out_uop_uses_stq, %slots_32.io_out_uop_ldst_val, %slots_32.io_out_uop_dst_rtype, %slots_32.io_out_uop_lrs1_rtype, %slots_32.io_out_uop_lrs2_rtype, %slots_32.io_out_uop_fp_val, %slots_32.io_uop_uopc, %slots_32.io_uop_is_rvc, %slots_32.io_uop_fu_code, %slots_32.io_uop_iw_p1_poisoned, %slots_32.io_uop_iw_p2_poisoned, %slots_32.io_uop_is_br, %slots_32.io_uop_is_jalr, %slots_32.io_uop_is_jal, %slots_32.io_uop_is_sfb, %slots_32.io_uop_br_mask, %slots_32.io_uop_br_tag, %slots_32.io_uop_ftq_idx, %slots_32.io_uop_edge_inst, %slots_32.io_uop_pc_lob, %slots_32.io_uop_taken, %slots_32.io_uop_imm_packed, %slots_32.io_uop_rob_idx, %slots_32.io_uop_ldq_idx, %slots_32.io_uop_stq_idx, %slots_32.io_uop_pdst, %slots_32.io_uop_prs1, %slots_32.io_uop_prs2, %slots_32.io_uop_bypassable, %slots_32.io_uop_mem_cmd, %slots_32.io_uop_mem_size, %slots_32.io_uop_mem_signed, %slots_32.io_uop_is_fence, %slots_32.io_uop_is_amo, %slots_32.io_uop_uses_ldq, %slots_32.io_uop_uses_stq, %slots_32.io_uop_ldst_val, %slots_32.io_uop_dst_rtype, %slots_32.io_uop_lrs1_rtype, %slots_32.io_uop_lrs2_rtype, %slots_32.io_uop_fp_val = hw.instance "slots_32" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1406: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %4994: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %4993: i1, io_in_uop_bits_uopc: %12044: i7, io_in_uop_bits_is_rvc: %12045: i1, io_in_uop_bits_fu_code: %12046: i10, io_in_uop_bits_iw_state: %12047: i2, io_in_uop_bits_iw_p1_poisoned: %12048: i1, io_in_uop_bits_iw_p2_poisoned: %12049: i1, io_in_uop_bits_is_br: %12050: i1, io_in_uop_bits_is_jalr: %12051: i1, io_in_uop_bits_is_jal: %12052: i1, io_in_uop_bits_is_sfb: %12053: i1, io_in_uop_bits_br_mask: %12054: i20, io_in_uop_bits_br_tag: %12055: i5, io_in_uop_bits_ftq_idx: %12056: i6, io_in_uop_bits_edge_inst: %12057: i1, io_in_uop_bits_pc_lob: %12058: i6, io_in_uop_bits_taken: %12059: i1, io_in_uop_bits_imm_packed: %12060: i20, io_in_uop_bits_rob_idx: %12061: i7, io_in_uop_bits_ldq_idx: %12062: i5, io_in_uop_bits_stq_idx: %12063: i5, io_in_uop_bits_pdst: %12064: i7, io_in_uop_bits_prs1: %12065: i7, io_in_uop_bits_prs2: %12066: i7, io_in_uop_bits_prs3: %12067: i7, io_in_uop_bits_prs1_busy: %12068: i1, io_in_uop_bits_prs2_busy: %12069: i1, io_in_uop_bits_prs3_busy: %12070: i1, io_in_uop_bits_ppred_busy: %12071: i1, io_in_uop_bits_bypassable: %12072: i1, io_in_uop_bits_mem_cmd: %12073: i5, io_in_uop_bits_mem_size: %12074: i2, io_in_uop_bits_mem_signed: %12075: i1, io_in_uop_bits_is_fence: %12076: i1, io_in_uop_bits_is_amo: %12077: i1, io_in_uop_bits_uses_ldq: %12078: i1, io_in_uop_bits_uses_stq: %12079: i1, io_in_uop_bits_ldst_val: %12080: i1, io_in_uop_bits_dst_rtype: %12081: i2, io_in_uop_bits_lrs1_rtype: %12082: i2, io_in_uop_bits_lrs2_rtype: %12083: i2, io_in_uop_bits_fp_val: %12084: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_33.io_valid, %slots_33.io_will_be_valid, %slots_33.io_request, %slots_33.io_out_uop_uopc, %slots_33.io_out_uop_is_rvc, %slots_33.io_out_uop_fu_code, %slots_33.io_out_uop_iw_state, %slots_33.io_out_uop_iw_p1_poisoned, %slots_33.io_out_uop_iw_p2_poisoned, %slots_33.io_out_uop_is_br, %slots_33.io_out_uop_is_jalr, %slots_33.io_out_uop_is_jal, %slots_33.io_out_uop_is_sfb, %slots_33.io_out_uop_br_mask, %slots_33.io_out_uop_br_tag, %slots_33.io_out_uop_ftq_idx, %slots_33.io_out_uop_edge_inst, %slots_33.io_out_uop_pc_lob, %slots_33.io_out_uop_taken, %slots_33.io_out_uop_imm_packed, %slots_33.io_out_uop_rob_idx, %slots_33.io_out_uop_ldq_idx, %slots_33.io_out_uop_stq_idx, %slots_33.io_out_uop_pdst, %slots_33.io_out_uop_prs1, %slots_33.io_out_uop_prs2, %slots_33.io_out_uop_prs3, %slots_33.io_out_uop_prs1_busy, %slots_33.io_out_uop_prs2_busy, %slots_33.io_out_uop_prs3_busy, %slots_33.io_out_uop_ppred_busy, %slots_33.io_out_uop_bypassable, %slots_33.io_out_uop_mem_cmd, %slots_33.io_out_uop_mem_size, %slots_33.io_out_uop_mem_signed, %slots_33.io_out_uop_is_fence, %slots_33.io_out_uop_is_amo, %slots_33.io_out_uop_uses_ldq, %slots_33.io_out_uop_uses_stq, %slots_33.io_out_uop_ldst_val, %slots_33.io_out_uop_dst_rtype, %slots_33.io_out_uop_lrs1_rtype, %slots_33.io_out_uop_lrs2_rtype, %slots_33.io_out_uop_fp_val, %slots_33.io_uop_uopc, %slots_33.io_uop_is_rvc, %slots_33.io_uop_fu_code, %slots_33.io_uop_iw_p1_poisoned, %slots_33.io_uop_iw_p2_poisoned, %slots_33.io_uop_is_br, %slots_33.io_uop_is_jalr, %slots_33.io_uop_is_jal, %slots_33.io_uop_is_sfb, %slots_33.io_uop_br_mask, %slots_33.io_uop_br_tag, %slots_33.io_uop_ftq_idx, %slots_33.io_uop_edge_inst, %slots_33.io_uop_pc_lob, %slots_33.io_uop_taken, %slots_33.io_uop_imm_packed, %slots_33.io_uop_rob_idx, %slots_33.io_uop_ldq_idx, %slots_33.io_uop_stq_idx, %slots_33.io_uop_pdst, %slots_33.io_uop_prs1, %slots_33.io_uop_prs2, %slots_33.io_uop_bypassable, %slots_33.io_uop_mem_cmd, %slots_33.io_uop_mem_size, %slots_33.io_uop_mem_signed, %slots_33.io_uop_is_fence, %slots_33.io_uop_is_amo, %slots_33.io_uop_uses_ldq, %slots_33.io_uop_uses_stq, %slots_33.io_uop_ldst_val, %slots_33.io_uop_dst_rtype, %slots_33.io_uop_lrs1_rtype, %slots_33.io_uop_lrs2_rtype, %slots_33.io_uop_fp_val = hw.instance "slots_33" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1365: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %5085: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %5084: i1, io_in_uop_bits_uopc: %12085: i7, io_in_uop_bits_is_rvc: %12086: i1, io_in_uop_bits_fu_code: %12087: i10, io_in_uop_bits_iw_state: %12088: i2, io_in_uop_bits_iw_p1_poisoned: %12089: i1, io_in_uop_bits_iw_p2_poisoned: %12090: i1, io_in_uop_bits_is_br: %12091: i1, io_in_uop_bits_is_jalr: %12092: i1, io_in_uop_bits_is_jal: %12093: i1, io_in_uop_bits_is_sfb: %12094: i1, io_in_uop_bits_br_mask: %12095: i20, io_in_uop_bits_br_tag: %12096: i5, io_in_uop_bits_ftq_idx: %12097: i6, io_in_uop_bits_edge_inst: %12098: i1, io_in_uop_bits_pc_lob: %12099: i6, io_in_uop_bits_taken: %12100: i1, io_in_uop_bits_imm_packed: %12101: i20, io_in_uop_bits_rob_idx: %12102: i7, io_in_uop_bits_ldq_idx: %12103: i5, io_in_uop_bits_stq_idx: %12104: i5, io_in_uop_bits_pdst: %12105: i7, io_in_uop_bits_prs1: %12106: i7, io_in_uop_bits_prs2: %12107: i7, io_in_uop_bits_prs3: %12108: i7, io_in_uop_bits_prs1_busy: %12109: i1, io_in_uop_bits_prs2_busy: %12110: i1, io_in_uop_bits_prs3_busy: %12111: i1, io_in_uop_bits_ppred_busy: %12112: i1, io_in_uop_bits_bypassable: %12113: i1, io_in_uop_bits_mem_cmd: %12114: i5, io_in_uop_bits_mem_size: %12115: i2, io_in_uop_bits_mem_signed: %12116: i1, io_in_uop_bits_is_fence: %12117: i1, io_in_uop_bits_is_amo: %12118: i1, io_in_uop_bits_uses_ldq: %12119: i1, io_in_uop_bits_uses_stq: %12120: i1, io_in_uop_bits_ldst_val: %12121: i1, io_in_uop_bits_dst_rtype: %12122: i2, io_in_uop_bits_lrs1_rtype: %12123: i2, io_in_uop_bits_lrs2_rtype: %12124: i2, io_in_uop_bits_fp_val: %12125: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_34.io_valid, %slots_34.io_will_be_valid, %slots_34.io_request, %slots_34.io_out_uop_uopc, %slots_34.io_out_uop_is_rvc, %slots_34.io_out_uop_fu_code, %slots_34.io_out_uop_iw_state, %slots_34.io_out_uop_iw_p1_poisoned, %slots_34.io_out_uop_iw_p2_poisoned, %slots_34.io_out_uop_is_br, %slots_34.io_out_uop_is_jalr, %slots_34.io_out_uop_is_jal, %slots_34.io_out_uop_is_sfb, %slots_34.io_out_uop_br_mask, %slots_34.io_out_uop_br_tag, %slots_34.io_out_uop_ftq_idx, %slots_34.io_out_uop_edge_inst, %slots_34.io_out_uop_pc_lob, %slots_34.io_out_uop_taken, %slots_34.io_out_uop_imm_packed, %slots_34.io_out_uop_rob_idx, %slots_34.io_out_uop_ldq_idx, %slots_34.io_out_uop_stq_idx, %slots_34.io_out_uop_pdst, %slots_34.io_out_uop_prs1, %slots_34.io_out_uop_prs2, %slots_34.io_out_uop_prs3, %slots_34.io_out_uop_prs1_busy, %slots_34.io_out_uop_prs2_busy, %slots_34.io_out_uop_prs3_busy, %slots_34.io_out_uop_ppred_busy, %slots_34.io_out_uop_bypassable, %slots_34.io_out_uop_mem_cmd, %slots_34.io_out_uop_mem_size, %slots_34.io_out_uop_mem_signed, %slots_34.io_out_uop_is_fence, %slots_34.io_out_uop_is_amo, %slots_34.io_out_uop_uses_ldq, %slots_34.io_out_uop_uses_stq, %slots_34.io_out_uop_ldst_val, %slots_34.io_out_uop_dst_rtype, %slots_34.io_out_uop_lrs1_rtype, %slots_34.io_out_uop_lrs2_rtype, %slots_34.io_out_uop_fp_val, %slots_34.io_uop_uopc, %slots_34.io_uop_is_rvc, %slots_34.io_uop_fu_code, %slots_34.io_uop_iw_p1_poisoned, %slots_34.io_uop_iw_p2_poisoned, %slots_34.io_uop_is_br, %slots_34.io_uop_is_jalr, %slots_34.io_uop_is_jal, %slots_34.io_uop_is_sfb, %slots_34.io_uop_br_mask, %slots_34.io_uop_br_tag, %slots_34.io_uop_ftq_idx, %slots_34.io_uop_edge_inst, %slots_34.io_uop_pc_lob, %slots_34.io_uop_taken, %slots_34.io_uop_imm_packed, %slots_34.io_uop_rob_idx, %slots_34.io_uop_ldq_idx, %slots_34.io_uop_stq_idx, %slots_34.io_uop_pdst, %slots_34.io_uop_prs1, %slots_34.io_uop_prs2, %slots_34.io_uop_bypassable, %slots_34.io_uop_mem_cmd, %slots_34.io_uop_mem_size, %slots_34.io_uop_mem_signed, %slots_34.io_uop_is_fence, %slots_34.io_uop_is_amo, %slots_34.io_uop_uses_ldq, %slots_34.io_uop_uses_stq, %slots_34.io_uop_ldst_val, %slots_34.io_uop_dst_rtype, %slots_34.io_uop_lrs1_rtype, %slots_34.io_uop_lrs2_rtype, %slots_34.io_uop_fp_val = hw.instance "slots_34" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1399: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %5176: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %5175: i1, io_in_uop_bits_uopc: %12126: i7, io_in_uop_bits_is_rvc: %12127: i1, io_in_uop_bits_fu_code: %12128: i10, io_in_uop_bits_iw_state: %12129: i2, io_in_uop_bits_iw_p1_poisoned: %12130: i1, io_in_uop_bits_iw_p2_poisoned: %12131: i1, io_in_uop_bits_is_br: %12132: i1, io_in_uop_bits_is_jalr: %12133: i1, io_in_uop_bits_is_jal: %12134: i1, io_in_uop_bits_is_sfb: %12135: i1, io_in_uop_bits_br_mask: %12136: i20, io_in_uop_bits_br_tag: %12137: i5, io_in_uop_bits_ftq_idx: %12138: i6, io_in_uop_bits_edge_inst: %12139: i1, io_in_uop_bits_pc_lob: %12140: i6, io_in_uop_bits_taken: %12141: i1, io_in_uop_bits_imm_packed: %12142: i20, io_in_uop_bits_rob_idx: %12143: i7, io_in_uop_bits_ldq_idx: %12144: i5, io_in_uop_bits_stq_idx: %12145: i5, io_in_uop_bits_pdst: %12146: i7, io_in_uop_bits_prs1: %12147: i7, io_in_uop_bits_prs2: %12148: i7, io_in_uop_bits_prs3: %12149: i7, io_in_uop_bits_prs1_busy: %12150: i1, io_in_uop_bits_prs2_busy: %12151: i1, io_in_uop_bits_prs3_busy: %12152: i1, io_in_uop_bits_ppred_busy: %12153: i1, io_in_uop_bits_bypassable: %12154: i1, io_in_uop_bits_mem_cmd: %12155: i5, io_in_uop_bits_mem_size: %12156: i2, io_in_uop_bits_mem_signed: %12157: i1, io_in_uop_bits_is_fence: %12158: i1, io_in_uop_bits_is_amo: %12159: i1, io_in_uop_bits_uses_ldq: %12160: i1, io_in_uop_bits_uses_stq: %12161: i1, io_in_uop_bits_ldst_val: %12162: i1, io_in_uop_bits_dst_rtype: %12163: i2, io_in_uop_bits_lrs1_rtype: %12164: i2, io_in_uop_bits_lrs2_rtype: %12165: i2, io_in_uop_bits_fp_val: %12166: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_35.io_valid, %slots_35.io_will_be_valid, %slots_35.io_request, %slots_35.io_out_uop_uopc, %slots_35.io_out_uop_is_rvc, %slots_35.io_out_uop_fu_code, %slots_35.io_out_uop_iw_state, %slots_35.io_out_uop_iw_p1_poisoned, %slots_35.io_out_uop_iw_p2_poisoned, %slots_35.io_out_uop_is_br, %slots_35.io_out_uop_is_jalr, %slots_35.io_out_uop_is_jal, %slots_35.io_out_uop_is_sfb, %slots_35.io_out_uop_br_mask, %slots_35.io_out_uop_br_tag, %slots_35.io_out_uop_ftq_idx, %slots_35.io_out_uop_edge_inst, %slots_35.io_out_uop_pc_lob, %slots_35.io_out_uop_taken, %slots_35.io_out_uop_imm_packed, %slots_35.io_out_uop_rob_idx, %slots_35.io_out_uop_ldq_idx, %slots_35.io_out_uop_stq_idx, %slots_35.io_out_uop_pdst, %slots_35.io_out_uop_prs1, %slots_35.io_out_uop_prs2, %slots_35.io_out_uop_prs3, %slots_35.io_out_uop_prs1_busy, %slots_35.io_out_uop_prs2_busy, %slots_35.io_out_uop_prs3_busy, %slots_35.io_out_uop_ppred_busy, %slots_35.io_out_uop_bypassable, %slots_35.io_out_uop_mem_cmd, %slots_35.io_out_uop_mem_size, %slots_35.io_out_uop_mem_signed, %slots_35.io_out_uop_is_fence, %slots_35.io_out_uop_is_amo, %slots_35.io_out_uop_uses_ldq, %slots_35.io_out_uop_uses_stq, %slots_35.io_out_uop_ldst_val, %slots_35.io_out_uop_dst_rtype, %slots_35.io_out_uop_lrs1_rtype, %slots_35.io_out_uop_lrs2_rtype, %slots_35.io_out_uop_fp_val, %slots_35.io_uop_uopc, %slots_35.io_uop_is_rvc, %slots_35.io_uop_fu_code, %slots_35.io_uop_iw_p1_poisoned, %slots_35.io_uop_iw_p2_poisoned, %slots_35.io_uop_is_br, %slots_35.io_uop_is_jalr, %slots_35.io_uop_is_jal, %slots_35.io_uop_is_sfb, %slots_35.io_uop_br_mask, %slots_35.io_uop_br_tag, %slots_35.io_uop_ftq_idx, %slots_35.io_uop_edge_inst, %slots_35.io_uop_pc_lob, %slots_35.io_uop_taken, %slots_35.io_uop_imm_packed, %slots_35.io_uop_rob_idx, %slots_35.io_uop_ldq_idx, %slots_35.io_uop_stq_idx, %slots_35.io_uop_pdst, %slots_35.io_uop_prs1, %slots_35.io_uop_prs2, %slots_35.io_uop_bypassable, %slots_35.io_uop_mem_cmd, %slots_35.io_uop_mem_size, %slots_35.io_uop_mem_signed, %slots_35.io_uop_is_fence, %slots_35.io_uop_is_amo, %slots_35.io_uop_uses_ldq, %slots_35.io_uop_uses_stq, %slots_35.io_uop_ldst_val, %slots_35.io_uop_dst_rtype, %slots_35.io_uop_lrs1_rtype, %slots_35.io_uop_lrs2_rtype, %slots_35.io_uop_fp_val = hw.instance "slots_35" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1445: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %5267: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %5266: i1, io_in_uop_bits_uopc: %12167: i7, io_in_uop_bits_is_rvc: %12168: i1, io_in_uop_bits_fu_code: %12169: i10, io_in_uop_bits_iw_state: %12170: i2, io_in_uop_bits_iw_p1_poisoned: %12171: i1, io_in_uop_bits_iw_p2_poisoned: %12172: i1, io_in_uop_bits_is_br: %12173: i1, io_in_uop_bits_is_jalr: %12174: i1, io_in_uop_bits_is_jal: %12175: i1, io_in_uop_bits_is_sfb: %12176: i1, io_in_uop_bits_br_mask: %12177: i20, io_in_uop_bits_br_tag: %12178: i5, io_in_uop_bits_ftq_idx: %12179: i6, io_in_uop_bits_edge_inst: %12180: i1, io_in_uop_bits_pc_lob: %12181: i6, io_in_uop_bits_taken: %12182: i1, io_in_uop_bits_imm_packed: %12183: i20, io_in_uop_bits_rob_idx: %12184: i7, io_in_uop_bits_ldq_idx: %12185: i5, io_in_uop_bits_stq_idx: %12186: i5, io_in_uop_bits_pdst: %12187: i7, io_in_uop_bits_prs1: %12188: i7, io_in_uop_bits_prs2: %12189: i7, io_in_uop_bits_prs3: %12190: i7, io_in_uop_bits_prs1_busy: %12191: i1, io_in_uop_bits_prs2_busy: %12192: i1, io_in_uop_bits_prs3_busy: %12193: i1, io_in_uop_bits_ppred_busy: %12194: i1, io_in_uop_bits_bypassable: %12195: i1, io_in_uop_bits_mem_cmd: %12196: i5, io_in_uop_bits_mem_size: %12197: i2, io_in_uop_bits_mem_signed: %12198: i1, io_in_uop_bits_is_fence: %12199: i1, io_in_uop_bits_is_amo: %12200: i1, io_in_uop_bits_uses_ldq: %12201: i1, io_in_uop_bits_uses_stq: %12202: i1, io_in_uop_bits_ldst_val: %12203: i1, io_in_uop_bits_dst_rtype: %12204: i2, io_in_uop_bits_lrs1_rtype: %12205: i2, io_in_uop_bits_lrs2_rtype: %12206: i2, io_in_uop_bits_fp_val: %12207: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_36.io_valid, %slots_36.io_will_be_valid, %slots_36.io_request, %slots_36.io_out_uop_uopc, %slots_36.io_out_uop_is_rvc, %slots_36.io_out_uop_fu_code, %slots_36.io_out_uop_iw_state, %slots_36.io_out_uop_iw_p1_poisoned, %slots_36.io_out_uop_iw_p2_poisoned, %slots_36.io_out_uop_is_br, %slots_36.io_out_uop_is_jalr, %slots_36.io_out_uop_is_jal, %slots_36.io_out_uop_is_sfb, %slots_36.io_out_uop_br_mask, %slots_36.io_out_uop_br_tag, %slots_36.io_out_uop_ftq_idx, %slots_36.io_out_uop_edge_inst, %slots_36.io_out_uop_pc_lob, %slots_36.io_out_uop_taken, %slots_36.io_out_uop_imm_packed, %slots_36.io_out_uop_rob_idx, %slots_36.io_out_uop_ldq_idx, %slots_36.io_out_uop_stq_idx, %slots_36.io_out_uop_pdst, %slots_36.io_out_uop_prs1, %slots_36.io_out_uop_prs2, %slots_36.io_out_uop_prs3, %slots_36.io_out_uop_prs1_busy, %slots_36.io_out_uop_prs2_busy, %slots_36.io_out_uop_prs3_busy, %slots_36.io_out_uop_ppred_busy, %slots_36.io_out_uop_bypassable, %slots_36.io_out_uop_mem_cmd, %slots_36.io_out_uop_mem_size, %slots_36.io_out_uop_mem_signed, %slots_36.io_out_uop_is_fence, %slots_36.io_out_uop_is_amo, %slots_36.io_out_uop_uses_ldq, %slots_36.io_out_uop_uses_stq, %slots_36.io_out_uop_ldst_val, %slots_36.io_out_uop_dst_rtype, %slots_36.io_out_uop_lrs1_rtype, %slots_36.io_out_uop_lrs2_rtype, %slots_36.io_out_uop_fp_val, %slots_36.io_uop_uopc, %slots_36.io_uop_is_rvc, %slots_36.io_uop_fu_code, %slots_36.io_uop_iw_p1_poisoned, %slots_36.io_uop_iw_p2_poisoned, %slots_36.io_uop_is_br, %slots_36.io_uop_is_jalr, %slots_36.io_uop_is_jal, %slots_36.io_uop_is_sfb, %slots_36.io_uop_br_mask, %slots_36.io_uop_br_tag, %slots_36.io_uop_ftq_idx, %slots_36.io_uop_edge_inst, %slots_36.io_uop_pc_lob, %slots_36.io_uop_taken, %slots_36.io_uop_imm_packed, %slots_36.io_uop_rob_idx, %slots_36.io_uop_ldq_idx, %slots_36.io_uop_stq_idx, %slots_36.io_uop_pdst, %slots_36.io_uop_prs1, %slots_36.io_uop_prs2, %slots_36.io_uop_bypassable, %slots_36.io_uop_mem_cmd, %slots_36.io_uop_mem_size, %slots_36.io_uop_mem_signed, %slots_36.io_uop_is_fence, %slots_36.io_uop_is_amo, %slots_36.io_uop_uses_ldq, %slots_36.io_uop_uses_stq, %slots_36.io_uop_ldst_val, %slots_36.io_uop_dst_rtype, %slots_36.io_uop_lrs1_rtype, %slots_36.io_uop_lrs2_rtype, %slots_36.io_uop_fp_val = hw.instance "slots_36" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1479: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %5358: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %5357: i1, io_in_uop_bits_uopc: %12208: i7, io_in_uop_bits_is_rvc: %12209: i1, io_in_uop_bits_fu_code: %12210: i10, io_in_uop_bits_iw_state: %12211: i2, io_in_uop_bits_iw_p1_poisoned: %12213: i1, io_in_uop_bits_iw_p2_poisoned: %12215: i1, io_in_uop_bits_is_br: %12216: i1, io_in_uop_bits_is_jalr: %12217: i1, io_in_uop_bits_is_jal: %12218: i1, io_in_uop_bits_is_sfb: %12219: i1, io_in_uop_bits_br_mask: %12220: i20, io_in_uop_bits_br_tag: %12221: i5, io_in_uop_bits_ftq_idx: %12222: i6, io_in_uop_bits_edge_inst: %12223: i1, io_in_uop_bits_pc_lob: %12224: i6, io_in_uop_bits_taken: %12225: i1, io_in_uop_bits_imm_packed: %12226: i20, io_in_uop_bits_rob_idx: %12227: i7, io_in_uop_bits_ldq_idx: %12228: i5, io_in_uop_bits_stq_idx: %12229: i5, io_in_uop_bits_pdst: %12230: i7, io_in_uop_bits_prs1: %12231: i7, io_in_uop_bits_prs2: %12232: i7, io_in_uop_bits_prs3: %12233: i7, io_in_uop_bits_prs1_busy: %12234: i1, io_in_uop_bits_prs2_busy: %12235: i1, io_in_uop_bits_prs3_busy: %12237: i1, io_in_uop_bits_ppred_busy: %12239: i1, io_in_uop_bits_bypassable: %12240: i1, io_in_uop_bits_mem_cmd: %12241: i5, io_in_uop_bits_mem_size: %12242: i2, io_in_uop_bits_mem_signed: %12243: i1, io_in_uop_bits_is_fence: %12244: i1, io_in_uop_bits_is_amo: %12245: i1, io_in_uop_bits_uses_ldq: %12246: i1, io_in_uop_bits_uses_stq: %12247: i1, io_in_uop_bits_ldst_val: %12248: i1, io_in_uop_bits_dst_rtype: %12249: i2, io_in_uop_bits_lrs1_rtype: %12250: i2, io_in_uop_bits_lrs2_rtype: %12251: i2, io_in_uop_bits_fp_val: %12252: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_37.io_valid, %slots_37.io_will_be_valid, %slots_37.io_request, %slots_37.io_out_uop_uopc, %slots_37.io_out_uop_is_rvc, %slots_37.io_out_uop_fu_code, %slots_37.io_out_uop_iw_state, %slots_37.io_out_uop_iw_p1_poisoned, %slots_37.io_out_uop_iw_p2_poisoned, %slots_37.io_out_uop_is_br, %slots_37.io_out_uop_is_jalr, %slots_37.io_out_uop_is_jal, %slots_37.io_out_uop_is_sfb, %slots_37.io_out_uop_br_mask, %slots_37.io_out_uop_br_tag, %slots_37.io_out_uop_ftq_idx, %slots_37.io_out_uop_edge_inst, %slots_37.io_out_uop_pc_lob, %slots_37.io_out_uop_taken, %slots_37.io_out_uop_imm_packed, %slots_37.io_out_uop_rob_idx, %slots_37.io_out_uop_ldq_idx, %slots_37.io_out_uop_stq_idx, %slots_37.io_out_uop_pdst, %slots_37.io_out_uop_prs1, %slots_37.io_out_uop_prs2, %slots_37.io_out_uop_prs3, %slots_37.io_out_uop_prs1_busy, %slots_37.io_out_uop_prs2_busy, %slots_37.io_out_uop_prs3_busy, %slots_37.io_out_uop_ppred_busy, %slots_37.io_out_uop_bypassable, %slots_37.io_out_uop_mem_cmd, %slots_37.io_out_uop_mem_size, %slots_37.io_out_uop_mem_signed, %slots_37.io_out_uop_is_fence, %slots_37.io_out_uop_is_amo, %slots_37.io_out_uop_uses_ldq, %slots_37.io_out_uop_uses_stq, %slots_37.io_out_uop_ldst_val, %slots_37.io_out_uop_dst_rtype, %slots_37.io_out_uop_lrs1_rtype, %slots_37.io_out_uop_lrs2_rtype, %slots_37.io_out_uop_fp_val, %slots_37.io_uop_uopc, %slots_37.io_uop_is_rvc, %slots_37.io_uop_fu_code, %slots_37.io_uop_iw_p1_poisoned, %slots_37.io_uop_iw_p2_poisoned, %slots_37.io_uop_is_br, %slots_37.io_uop_is_jalr, %slots_37.io_uop_is_jal, %slots_37.io_uop_is_sfb, %slots_37.io_uop_br_mask, %slots_37.io_uop_br_tag, %slots_37.io_uop_ftq_idx, %slots_37.io_uop_edge_inst, %slots_37.io_uop_pc_lob, %slots_37.io_uop_taken, %slots_37.io_uop_imm_packed, %slots_37.io_uop_rob_idx, %slots_37.io_uop_ldq_idx, %slots_37.io_uop_stq_idx, %slots_37.io_uop_pdst, %slots_37.io_uop_prs1, %slots_37.io_uop_prs2, %slots_37.io_uop_bypassable, %slots_37.io_uop_mem_cmd, %slots_37.io_uop_mem_size, %slots_37.io_uop_mem_signed, %slots_37.io_uop_is_fence, %slots_37.io_uop_is_amo, %slots_37.io_uop_uses_ldq, %slots_37.io_uop_uses_stq, %slots_37.io_uop_ldst_val, %slots_37.io_uop_dst_rtype, %slots_37.io_uop_lrs1_rtype, %slots_37.io_uop_lrs2_rtype, %slots_37.io_uop_fp_val = hw.instance "slots_37" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1582: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %5449: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %5448: i1, io_in_uop_bits_uopc: %12253: i7, io_in_uop_bits_is_rvc: %12254: i1, io_in_uop_bits_fu_code: %12255: i10, io_in_uop_bits_iw_state: %12256: i2, io_in_uop_bits_iw_p1_poisoned: %12258: i1, io_in_uop_bits_iw_p2_poisoned: %12260: i1, io_in_uop_bits_is_br: %12261: i1, io_in_uop_bits_is_jalr: %12262: i1, io_in_uop_bits_is_jal: %12263: i1, io_in_uop_bits_is_sfb: %12264: i1, io_in_uop_bits_br_mask: %12265: i20, io_in_uop_bits_br_tag: %12266: i5, io_in_uop_bits_ftq_idx: %12267: i6, io_in_uop_bits_edge_inst: %12268: i1, io_in_uop_bits_pc_lob: %12269: i6, io_in_uop_bits_taken: %12270: i1, io_in_uop_bits_imm_packed: %12271: i20, io_in_uop_bits_rob_idx: %12272: i7, io_in_uop_bits_ldq_idx: %12273: i5, io_in_uop_bits_stq_idx: %12274: i5, io_in_uop_bits_pdst: %12275: i7, io_in_uop_bits_prs1: %12276: i7, io_in_uop_bits_prs2: %12277: i7, io_in_uop_bits_prs3: %12278: i7, io_in_uop_bits_prs1_busy: %12279: i1, io_in_uop_bits_prs2_busy: %12280: i1, io_in_uop_bits_prs3_busy: %12282: i1, io_in_uop_bits_ppred_busy: %12284: i1, io_in_uop_bits_bypassable: %12285: i1, io_in_uop_bits_mem_cmd: %12286: i5, io_in_uop_bits_mem_size: %12287: i2, io_in_uop_bits_mem_signed: %12288: i1, io_in_uop_bits_is_fence: %12289: i1, io_in_uop_bits_is_amo: %12290: i1, io_in_uop_bits_uses_ldq: %12291: i1, io_in_uop_bits_uses_stq: %12292: i1, io_in_uop_bits_ldst_val: %12293: i1, io_in_uop_bits_dst_rtype: %12294: i2, io_in_uop_bits_lrs1_rtype: %12295: i2, io_in_uop_bits_lrs2_rtype: %12296: i2, io_in_uop_bits_fp_val: %12297: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_38.io_valid, %slots_38.io_will_be_valid, %slots_38.io_request, %slots_38.io_out_uop_uopc, %slots_38.io_out_uop_is_rvc, %slots_38.io_out_uop_fu_code, %slots_38.io_out_uop_iw_state, %slots_38.io_out_uop_iw_p1_poisoned, %slots_38.io_out_uop_iw_p2_poisoned, %slots_38.io_out_uop_is_br, %slots_38.io_out_uop_is_jalr, %slots_38.io_out_uop_is_jal, %slots_38.io_out_uop_is_sfb, %slots_38.io_out_uop_br_mask, %slots_38.io_out_uop_br_tag, %slots_38.io_out_uop_ftq_idx, %slots_38.io_out_uop_edge_inst, %slots_38.io_out_uop_pc_lob, %slots_38.io_out_uop_taken, %slots_38.io_out_uop_imm_packed, %slots_38.io_out_uop_rob_idx, %slots_38.io_out_uop_ldq_idx, %slots_38.io_out_uop_stq_idx, %slots_38.io_out_uop_pdst, %slots_38.io_out_uop_prs1, %slots_38.io_out_uop_prs2, %slots_38.io_out_uop_prs3, %slots_38.io_out_uop_prs1_busy, %slots_38.io_out_uop_prs2_busy, %slots_38.io_out_uop_prs3_busy, %slots_38.io_out_uop_ppred_busy, %slots_38.io_out_uop_bypassable, %slots_38.io_out_uop_mem_cmd, %slots_38.io_out_uop_mem_size, %slots_38.io_out_uop_mem_signed, %slots_38.io_out_uop_is_fence, %slots_38.io_out_uop_is_amo, %slots_38.io_out_uop_uses_ldq, %slots_38.io_out_uop_uses_stq, %slots_38.io_out_uop_ldst_val, %slots_38.io_out_uop_dst_rtype, %slots_38.io_out_uop_lrs1_rtype, %slots_38.io_out_uop_lrs2_rtype, %slots_38.io_out_uop_fp_val, %slots_38.io_uop_uopc, %slots_38.io_uop_is_rvc, %slots_38.io_uop_fu_code, %slots_38.io_uop_iw_p1_poisoned, %slots_38.io_uop_iw_p2_poisoned, %slots_38.io_uop_is_br, %slots_38.io_uop_is_jalr, %slots_38.io_uop_is_jal, %slots_38.io_uop_is_sfb, %slots_38.io_uop_br_mask, %slots_38.io_uop_br_tag, %slots_38.io_uop_ftq_idx, %slots_38.io_uop_edge_inst, %slots_38.io_uop_pc_lob, %slots_38.io_uop_taken, %slots_38.io_uop_imm_packed, %slots_38.io_uop_rob_idx, %slots_38.io_uop_ldq_idx, %slots_38.io_uop_stq_idx, %slots_38.io_uop_pdst, %slots_38.io_uop_prs1, %slots_38.io_uop_prs2, %slots_38.io_uop_bypassable, %slots_38.io_uop_mem_cmd, %slots_38.io_uop_mem_size, %slots_38.io_uop_mem_signed, %slots_38.io_uop_is_fence, %slots_38.io_uop_is_amo, %slots_38.io_uop_uses_ldq, %slots_38.io_uop_uses_stq, %slots_38.io_uop_ldst_val, %slots_38.io_uop_dst_rtype, %slots_38.io_uop_lrs1_rtype, %slots_38.io_uop_lrs2_rtype, %slots_38.io_uop_fp_val = hw.instance "slots_38" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1545: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %5540: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %5539: i1, io_in_uop_bits_uopc: %12298: i7, io_in_uop_bits_is_rvc: %12299: i1, io_in_uop_bits_fu_code: %12300: i10, io_in_uop_bits_iw_state: %12301: i2, io_in_uop_bits_iw_p1_poisoned: %12303: i1, io_in_uop_bits_iw_p2_poisoned: %12305: i1, io_in_uop_bits_is_br: %12306: i1, io_in_uop_bits_is_jalr: %12307: i1, io_in_uop_bits_is_jal: %12308: i1, io_in_uop_bits_is_sfb: %12309: i1, io_in_uop_bits_br_mask: %12310: i20, io_in_uop_bits_br_tag: %12311: i5, io_in_uop_bits_ftq_idx: %12312: i6, io_in_uop_bits_edge_inst: %12313: i1, io_in_uop_bits_pc_lob: %12314: i6, io_in_uop_bits_taken: %12315: i1, io_in_uop_bits_imm_packed: %12316: i20, io_in_uop_bits_rob_idx: %12317: i7, io_in_uop_bits_ldq_idx: %12318: i5, io_in_uop_bits_stq_idx: %12319: i5, io_in_uop_bits_pdst: %12320: i7, io_in_uop_bits_prs1: %12321: i7, io_in_uop_bits_prs2: %12322: i7, io_in_uop_bits_prs3: %12323: i7, io_in_uop_bits_prs1_busy: %12324: i1, io_in_uop_bits_prs2_busy: %12325: i1, io_in_uop_bits_prs3_busy: %12327: i1, io_in_uop_bits_ppred_busy: %12329: i1, io_in_uop_bits_bypassable: %12330: i1, io_in_uop_bits_mem_cmd: %12331: i5, io_in_uop_bits_mem_size: %12332: i2, io_in_uop_bits_mem_signed: %12333: i1, io_in_uop_bits_is_fence: %12334: i1, io_in_uop_bits_is_amo: %12335: i1, io_in_uop_bits_uses_ldq: %12336: i1, io_in_uop_bits_uses_stq: %12337: i1, io_in_uop_bits_ldst_val: %12338: i1, io_in_uop_bits_dst_rtype: %12339: i2, io_in_uop_bits_lrs1_rtype: %12340: i2, io_in_uop_bits_lrs2_rtype: %12341: i2, io_in_uop_bits_fp_val: %12342: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %slots_39.io_valid, %slots_39.io_will_be_valid, %slots_39.io_request, %slots_39.io_out_uop_uopc, %slots_39.io_out_uop_is_rvc, %slots_39.io_out_uop_fu_code, %slots_39.io_out_uop_iw_state, %slots_39.io_out_uop_iw_p1_poisoned, %slots_39.io_out_uop_iw_p2_poisoned, %slots_39.io_out_uop_is_br, %slots_39.io_out_uop_is_jalr, %slots_39.io_out_uop_is_jal, %slots_39.io_out_uop_is_sfb, %slots_39.io_out_uop_br_mask, %slots_39.io_out_uop_br_tag, %slots_39.io_out_uop_ftq_idx, %slots_39.io_out_uop_edge_inst, %slots_39.io_out_uop_pc_lob, %slots_39.io_out_uop_taken, %slots_39.io_out_uop_imm_packed, %slots_39.io_out_uop_rob_idx, %slots_39.io_out_uop_ldq_idx, %slots_39.io_out_uop_stq_idx, %slots_39.io_out_uop_pdst, %slots_39.io_out_uop_prs1, %slots_39.io_out_uop_prs2, %slots_39.io_out_uop_prs3, %slots_39.io_out_uop_prs1_busy, %slots_39.io_out_uop_prs2_busy, %slots_39.io_out_uop_prs3_busy, %slots_39.io_out_uop_ppred_busy, %slots_39.io_out_uop_bypassable, %slots_39.io_out_uop_mem_cmd, %slots_39.io_out_uop_mem_size, %slots_39.io_out_uop_mem_signed, %slots_39.io_out_uop_is_fence, %slots_39.io_out_uop_is_amo, %slots_39.io_out_uop_uses_ldq, %slots_39.io_out_uop_uses_stq, %slots_39.io_out_uop_ldst_val, %slots_39.io_out_uop_dst_rtype, %slots_39.io_out_uop_lrs1_rtype, %slots_39.io_out_uop_lrs2_rtype, %slots_39.io_out_uop_fp_val, %slots_39.io_uop_uopc, %slots_39.io_uop_is_rvc, %slots_39.io_uop_fu_code, %slots_39.io_uop_iw_p1_poisoned, %slots_39.io_uop_iw_p2_poisoned, %slots_39.io_uop_is_br, %slots_39.io_uop_is_jalr, %slots_39.io_uop_is_jal, %slots_39.io_uop_is_sfb, %slots_39.io_uop_br_mask, %slots_39.io_uop_br_tag, %slots_39.io_uop_ftq_idx, %slots_39.io_uop_edge_inst, %slots_39.io_uop_pc_lob, %slots_39.io_uop_taken, %slots_39.io_uop_imm_packed, %slots_39.io_uop_rob_idx, %slots_39.io_uop_ldq_idx, %slots_39.io_uop_stq_idx, %slots_39.io_uop_pdst, %slots_39.io_uop_prs1, %slots_39.io_uop_prs2, %slots_39.io_uop_bypassable, %slots_39.io_uop_mem_cmd, %slots_39.io_uop_mem_size, %slots_39.io_uop_mem_signed, %slots_39.io_uop_is_fence, %slots_39.io_uop_is_amo, %slots_39.io_uop_uses_ldq, %slots_39.io_uop_uses_stq, %slots_39.io_uop_ldst_val, %slots_39.io_uop_dst_rtype, %slots_39.io_uop_lrs1_rtype, %slots_39.io_uop_lrs2_rtype, %slots_39.io_uop_fp_val = hw.instance "slots_39" @IssueSlot_32(clock: %clock: i1, reset: %reset: i1, io_grant: %1575: i1, io_brupdate_b1_resolve_mask: %io_brupdate_b1_resolve_mask: i20, io_brupdate_b1_mispredict_mask: %io_brupdate_b1_mispredict_mask: i20, io_kill: %io_flush_pipeline: i1, io_clear: %5623: i1, io_ldspec_miss: %io_ld_miss: i1, io_wakeup_ports_0_valid: %io_wakeup_ports_0_valid: i1, io_wakeup_ports_0_bits_pdst: %io_wakeup_ports_0_bits_pdst: i7, io_wakeup_ports_1_valid: %io_wakeup_ports_1_valid: i1, io_wakeup_ports_1_bits_pdst: %io_wakeup_ports_1_bits_pdst: i7, io_wakeup_ports_2_valid: %io_wakeup_ports_2_valid: i1, io_wakeup_ports_2_bits_pdst: %io_wakeup_ports_2_bits_pdst: i7, io_wakeup_ports_3_valid: %io_wakeup_ports_3_valid: i1, io_wakeup_ports_3_bits_pdst: %io_wakeup_ports_3_bits_pdst: i7, io_wakeup_ports_4_valid: %io_wakeup_ports_4_valid: i1, io_wakeup_ports_4_bits_pdst: %io_wakeup_ports_4_bits_pdst: i7, io_wakeup_ports_5_valid: %io_wakeup_ports_5_valid: i1, io_wakeup_ports_5_bits_pdst: %io_wakeup_ports_5_bits_pdst: i7, io_wakeup_ports_6_valid: %io_wakeup_ports_6_valid: i1, io_wakeup_ports_6_bits_pdst: %io_wakeup_ports_6_bits_pdst: i7, io_wakeup_ports_7_valid: %io_wakeup_ports_7_valid: i1, io_wakeup_ports_7_bits_pdst: %io_wakeup_ports_7_bits_pdst: i7, io_wakeup_ports_8_valid: %io_wakeup_ports_8_valid: i1, io_wakeup_ports_8_bits_pdst: %io_wakeup_ports_8_bits_pdst: i7, io_wakeup_ports_9_valid: %io_wakeup_ports_9_valid: i1, io_wakeup_ports_9_bits_pdst: %io_wakeup_ports_9_bits_pdst: i7, io_spec_ld_wakeup_0_valid: %io_spec_ld_wakeup_0_valid: i1, io_spec_ld_wakeup_0_bits: %io_spec_ld_wakeup_0_bits: i7, io_spec_ld_wakeup_1_valid: %io_spec_ld_wakeup_1_valid: i1, io_spec_ld_wakeup_1_bits: %io_spec_ld_wakeup_1_bits: i7, io_in_uop_valid: %5622: i1, io_in_uop_bits_uopc: %12343: i7, io_in_uop_bits_is_rvc: %12344: i1, io_in_uop_bits_fu_code: %12345: i10, io_in_uop_bits_iw_state: %12346: i2, io_in_uop_bits_iw_p1_poisoned: %false: i1, io_in_uop_bits_iw_p2_poisoned: %false: i1, io_in_uop_bits_is_br: %12347: i1, io_in_uop_bits_is_jalr: %12348: i1, io_in_uop_bits_is_jal: %12349: i1, io_in_uop_bits_is_sfb: %12350: i1, io_in_uop_bits_br_mask: %12351: i20, io_in_uop_bits_br_tag: %12352: i5, io_in_uop_bits_ftq_idx: %12353: i6, io_in_uop_bits_edge_inst: %12354: i1, io_in_uop_bits_pc_lob: %12355: i6, io_in_uop_bits_taken: %12356: i1, io_in_uop_bits_imm_packed: %12357: i20, io_in_uop_bits_rob_idx: %12358: i7, io_in_uop_bits_ldq_idx: %12359: i5, io_in_uop_bits_stq_idx: %12360: i5, io_in_uop_bits_pdst: %12361: i7, io_in_uop_bits_prs1: %12362: i7, io_in_uop_bits_prs2: %12363: i7, io_in_uop_bits_prs3: %12364: i7, io_in_uop_bits_prs1_busy: %12365: i1, io_in_uop_bits_prs2_busy: %12366: i1, io_in_uop_bits_prs3_busy: %false: i1, io_in_uop_bits_ppred_busy: %false: i1, io_in_uop_bits_bypassable: %12367: i1, io_in_uop_bits_mem_cmd: %12368: i5, io_in_uop_bits_mem_size: %12369: i2, io_in_uop_bits_mem_signed: %12370: i1, io_in_uop_bits_is_fence: %12371: i1, io_in_uop_bits_is_amo: %12372: i1, io_in_uop_bits_uses_ldq: %12373: i1, io_in_uop_bits_uses_stq: %12374: i1, io_in_uop_bits_ldst_val: %12375: i1, io_in_uop_bits_dst_rtype: %12376: i2, io_in_uop_bits_lrs1_rtype: %12377: i2, io_in_uop_bits_lrs2_rtype: %12378: i2, io_in_uop_bits_fp_val: %12379: i1) -> (io_valid: i1, io_will_be_valid: i1, io_request: i1, io_out_uop_uopc: i7, io_out_uop_is_rvc: i1, io_out_uop_fu_code: i10, io_out_uop_iw_state: i2, io_out_uop_iw_p1_poisoned: i1, io_out_uop_iw_p2_poisoned: i1, io_out_uop_is_br: i1, io_out_uop_is_jalr: i1, io_out_uop_is_jal: i1, io_out_uop_is_sfb: i1, io_out_uop_br_mask: i20, io_out_uop_br_tag: i5, io_out_uop_ftq_idx: i6, io_out_uop_edge_inst: i1, io_out_uop_pc_lob: i6, io_out_uop_taken: i1, io_out_uop_imm_packed: i20, io_out_uop_rob_idx: i7, io_out_uop_ldq_idx: i5, io_out_uop_stq_idx: i5, io_out_uop_pdst: i7, io_out_uop_prs1: i7, io_out_uop_prs2: i7, io_out_uop_prs3: i7, io_out_uop_prs1_busy: i1, io_out_uop_prs2_busy: i1, io_out_uop_prs3_busy: i1, io_out_uop_ppred_busy: i1, io_out_uop_bypassable: i1, io_out_uop_mem_cmd: i5, io_out_uop_mem_size: i2, io_out_uop_mem_signed: i1, io_out_uop_is_fence: i1, io_out_uop_is_amo: i1, io_out_uop_uses_ldq: i1, io_out_uop_uses_stq: i1, io_out_uop_ldst_val: i1, io_out_uop_dst_rtype: i2, io_out_uop_lrs1_rtype: i2, io_out_uop_lrs2_rtype: i2, io_out_uop_fp_val: i1, io_uop_uopc: i7, io_uop_is_rvc: i1, io_uop_fu_code: i10, io_uop_iw_p1_poisoned: i1, io_uop_iw_p2_poisoned: i1, io_uop_is_br: i1, io_uop_is_jalr: i1, io_uop_is_jal: i1, io_uop_is_sfb: i1, io_uop_br_mask: i20, io_uop_br_tag: i5, io_uop_ftq_idx: i6, io_uop_edge_inst: i1, io_uop_pc_lob: i6, io_uop_taken: i1, io_uop_imm_packed: i20, io_uop_rob_idx: i7, io_uop_ldq_idx: i5, io_uop_stq_idx: i5, io_uop_pdst: i7, io_uop_prs1: i7, io_uop_prs2: i7, io_uop_bypassable: i1, io_uop_mem_cmd: i5, io_uop_mem_size: i2, io_uop_mem_signed: i1, io_uop_is_fence: i1, io_uop_is_amo: i1, io_uop_uses_ldq: i1, io_uop_uses_stq: i1, io_uop_ldst_val: i1, io_uop_dst_rtype: i2, io_uop_lrs1_rtype: i2, io_uop_lrs2_rtype: i2, io_uop_fp_val: i1)
    %0 = comb.icmp eq %io_dis_uops_0_bits_uopc, %c2_i7 : i7
    %1 = comb.icmp ne %io_dis_uops_0_bits_lrs2_rtype, %c0_i2 : i2
    %2 = comb.xor %1, %true : i1
    %3 = comb.and %0, %2 : i1
    %4 = comb.icmp eq %io_dis_uops_0_bits_uopc, %c-61_i7 : i7
    %5 = comb.or %3, %4 : i1
    %6 = comb.and %0, %1 : i1
    %7 = comb.xor %6, %true : i1
    %8 = comb.mux %5, %c-2_i2, %c1_i2 {sv.namehint = "_uops_40_iw_state"} : i2
    %uops_40_iw_state = sv.wire sym @uops_40_iw_state  : !hw.inout<i2>
    sv.assign %uops_40_iw_state, %8 : i2
    %9 = comb.xor %6, %true : i1
    %10 = comb.or %5, %9 : i1
    %11 = comb.mux %10, %io_dis_uops_0_bits_lrs2_rtype, %c-2_i2 : i2
    %uops_40_lrs2_rtype = sv.wire sym @uops_40_lrs2_rtype  : !hw.inout<i2>
    sv.assign %uops_40_lrs2_rtype, %11 : i2
    %12 = comb.or %5, %7 : i1
    %13 = comb.and %12, %io_dis_uops_0_bits_prs2_busy : i1
    %uops_40_prs2_busy = sv.wire sym @uops_40_prs2_busy  : !hw.inout<i1>
    sv.assign %uops_40_prs2_busy, %13 : i1
    %14 = comb.icmp eq %io_dis_uops_1_bits_uopc, %c2_i7 : i7
    %15 = comb.icmp ne %io_dis_uops_1_bits_lrs2_rtype, %c0_i2 : i2
    %16 = comb.xor %15, %true : i1
    %17 = comb.and %14, %16 : i1
    %18 = comb.icmp eq %io_dis_uops_1_bits_uopc, %c-61_i7 : i7
    %19 = comb.or %17, %18 : i1
    %20 = comb.and %14, %15 : i1
    %21 = comb.xor %20, %true : i1
    %22 = comb.mux %19, %c-2_i2, %c1_i2 {sv.namehint = "_uops_41_iw_state"} : i2
    %uops_41_iw_state = sv.wire sym @uops_41_iw_state  : !hw.inout<i2>
    sv.assign %uops_41_iw_state, %22 : i2
    %23 = comb.xor %20, %true : i1
    %24 = comb.or %19, %23 : i1
    %25 = comb.mux %24, %io_dis_uops_1_bits_lrs2_rtype, %c-2_i2 : i2
    %uops_41_lrs2_rtype = sv.wire sym @uops_41_lrs2_rtype  : !hw.inout<i2>
    sv.assign %uops_41_lrs2_rtype, %25 : i2
    %26 = comb.or %19, %21 : i1
    %27 = comb.and %26, %io_dis_uops_1_bits_prs2_busy : i1
    %uops_41_prs2_busy = sv.wire sym @uops_41_prs2_busy  : !hw.inout<i1>
    sv.assign %uops_41_prs2_busy, %27 : i1
    %28 = comb.icmp eq %io_dis_uops_2_bits_uopc, %c2_i7 : i7
    %29 = comb.icmp ne %io_dis_uops_2_bits_lrs2_rtype, %c0_i2 : i2
    %30 = comb.xor %29, %true : i1
    %31 = comb.and %28, %30 : i1
    %32 = comb.icmp eq %io_dis_uops_2_bits_uopc, %c-61_i7 : i7
    %33 = comb.or %31, %32 : i1
    %34 = comb.and %28, %29 : i1
    %35 = comb.xor %34, %true : i1
    %36 = comb.mux %33, %c-2_i2, %c1_i2 {sv.namehint = "_uops_42_iw_state"} : i2
    %uops_42_iw_state = sv.wire sym @uops_42_iw_state  : !hw.inout<i2>
    sv.assign %uops_42_iw_state, %36 : i2
    %37 = comb.xor %34, %true : i1
    %38 = comb.or %33, %37 : i1
    %39 = comb.mux %38, %io_dis_uops_2_bits_lrs2_rtype, %c-2_i2 : i2
    %uops_42_lrs2_rtype = sv.wire sym @uops_42_lrs2_rtype  : !hw.inout<i2>
    sv.assign %uops_42_lrs2_rtype, %39 : i2
    %40 = comb.or %33, %35 : i1
    %41 = comb.and %40, %io_dis_uops_2_bits_prs2_busy : i1
    %uops_42_prs2_busy = sv.wire sym @uops_42_prs2_busy  : !hw.inout<i1>
    sv.assign %uops_42_prs2_busy, %41 : i1
    %42 = comb.icmp eq %io_dis_uops_3_bits_uopc, %c2_i7 : i7
    %43 = comb.icmp ne %io_dis_uops_3_bits_lrs2_rtype, %c0_i2 : i2
    %44 = comb.xor %43, %true : i1
    %45 = comb.and %42, %44 : i1
    %46 = comb.icmp eq %io_dis_uops_3_bits_uopc, %c-61_i7 : i7
    %47 = comb.or %45, %46 : i1
    %48 = comb.and %42, %43 : i1
    %49 = comb.xor %48, %true : i1
    %50 = comb.mux %47, %c-2_i2, %c1_i2 {sv.namehint = "_uops_43_iw_state"} : i2
    %uops_43_iw_state = sv.wire sym @uops_43_iw_state  : !hw.inout<i2>
    sv.assign %uops_43_iw_state, %50 : i2
    %51 = comb.xor %48, %true : i1
    %52 = comb.or %47, %51 : i1
    %53 = comb.mux %52, %io_dis_uops_3_bits_lrs2_rtype, %c-2_i2 : i2
    %uops_43_lrs2_rtype = sv.wire sym @uops_43_lrs2_rtype  : !hw.inout<i2>
    sv.assign %uops_43_lrs2_rtype, %53 : i2
    %54 = comb.or %47, %49 : i1
    %55 = comb.and %54, %io_dis_uops_3_bits_prs2_busy : i1
    %uops_43_prs2_busy = sv.wire sym @uops_43_prs2_busy  : !hw.inout<i1>
    sv.assign %uops_43_prs2_busy, %55 : i1
    %issue_slots_0_valid = sv.wire sym @issue_slots_0_valid  : !hw.inout<i1>
    sv.assign %issue_slots_0_valid, %slots_0.io_valid : i1
    %issue_slots_1_valid = sv.wire sym @issue_slots_1_valid  : !hw.inout<i1>
    sv.assign %issue_slots_1_valid, %slots_1.io_valid : i1
    %issue_slots_2_valid = sv.wire sym @issue_slots_2_valid  : !hw.inout<i1>
    sv.assign %issue_slots_2_valid, %slots_2.io_valid : i1
    %issue_slots_3_valid = sv.wire sym @issue_slots_3_valid  : !hw.inout<i1>
    sv.assign %issue_slots_3_valid, %slots_3.io_valid : i1
    %issue_slots_4_valid = sv.wire sym @issue_slots_4_valid  : !hw.inout<i1>
    sv.assign %issue_slots_4_valid, %slots_4.io_valid : i1
    %issue_slots_5_valid = sv.wire sym @issue_slots_5_valid  : !hw.inout<i1>
    sv.assign %issue_slots_5_valid, %slots_5.io_valid : i1
    %issue_slots_6_valid = sv.wire sym @issue_slots_6_valid  : !hw.inout<i1>
    sv.assign %issue_slots_6_valid, %slots_6.io_valid : i1
    %issue_slots_7_valid = sv.wire sym @issue_slots_7_valid  : !hw.inout<i1>
    sv.assign %issue_slots_7_valid, %slots_7.io_valid : i1
    %issue_slots_8_valid = sv.wire sym @issue_slots_8_valid  : !hw.inout<i1>
    sv.assign %issue_slots_8_valid, %slots_8.io_valid : i1
    %issue_slots_9_valid = sv.wire sym @issue_slots_9_valid  : !hw.inout<i1>
    sv.assign %issue_slots_9_valid, %slots_9.io_valid : i1
    %issue_slots_10_valid = sv.wire sym @issue_slots_10_valid  : !hw.inout<i1>
    sv.assign %issue_slots_10_valid, %slots_10.io_valid : i1
    %issue_slots_11_valid = sv.wire sym @issue_slots_11_valid  : !hw.inout<i1>
    sv.assign %issue_slots_11_valid, %slots_11.io_valid : i1
    %issue_slots_12_valid = sv.wire sym @issue_slots_12_valid  : !hw.inout<i1>
    sv.assign %issue_slots_12_valid, %slots_12.io_valid : i1
    %issue_slots_13_valid = sv.wire sym @issue_slots_13_valid  : !hw.inout<i1>
    sv.assign %issue_slots_13_valid, %slots_13.io_valid : i1
    %issue_slots_14_valid = sv.wire sym @issue_slots_14_valid  : !hw.inout<i1>
    sv.assign %issue_slots_14_valid, %slots_14.io_valid : i1
    %issue_slots_15_valid = sv.wire sym @issue_slots_15_valid  : !hw.inout<i1>
    sv.assign %issue_slots_15_valid, %slots_15.io_valid : i1
    %issue_slots_16_valid = sv.wire sym @issue_slots_16_valid  : !hw.inout<i1>
    sv.assign %issue_slots_16_valid, %slots_16.io_valid : i1
    %issue_slots_17_valid = sv.wire sym @issue_slots_17_valid  : !hw.inout<i1>
    sv.assign %issue_slots_17_valid, %slots_17.io_valid : i1
    %issue_slots_18_valid = sv.wire sym @issue_slots_18_valid  : !hw.inout<i1>
    sv.assign %issue_slots_18_valid, %slots_18.io_valid : i1
    %issue_slots_19_valid = sv.wire sym @issue_slots_19_valid  : !hw.inout<i1>
    sv.assign %issue_slots_19_valid, %slots_19.io_valid : i1
    %issue_slots_20_valid = sv.wire sym @issue_slots_20_valid  : !hw.inout<i1>
    sv.assign %issue_slots_20_valid, %slots_20.io_valid : i1
    %issue_slots_21_valid = sv.wire sym @issue_slots_21_valid  : !hw.inout<i1>
    sv.assign %issue_slots_21_valid, %slots_21.io_valid : i1
    %issue_slots_22_valid = sv.wire sym @issue_slots_22_valid  : !hw.inout<i1>
    sv.assign %issue_slots_22_valid, %slots_22.io_valid : i1
    %issue_slots_23_valid = sv.wire sym @issue_slots_23_valid  : !hw.inout<i1>
    sv.assign %issue_slots_23_valid, %slots_23.io_valid : i1
    %issue_slots_24_valid = sv.wire sym @issue_slots_24_valid  : !hw.inout<i1>
    sv.assign %issue_slots_24_valid, %slots_24.io_valid : i1
    %issue_slots_25_valid = sv.wire sym @issue_slots_25_valid  : !hw.inout<i1>
    sv.assign %issue_slots_25_valid, %slots_25.io_valid : i1
    %issue_slots_26_valid = sv.wire sym @issue_slots_26_valid  : !hw.inout<i1>
    sv.assign %issue_slots_26_valid, %slots_26.io_valid : i1
    %issue_slots_27_valid = sv.wire sym @issue_slots_27_valid  : !hw.inout<i1>
    sv.assign %issue_slots_27_valid, %slots_27.io_valid : i1
    %issue_slots_28_valid = sv.wire sym @issue_slots_28_valid  : !hw.inout<i1>
    sv.assign %issue_slots_28_valid, %slots_28.io_valid : i1
    %issue_slots_29_valid = sv.wire sym @issue_slots_29_valid  : !hw.inout<i1>
    sv.assign %issue_slots_29_valid, %slots_29.io_valid : i1
    %issue_slots_30_valid = sv.wire sym @issue_slots_30_valid  : !hw.inout<i1>
    sv.assign %issue_slots_30_valid, %slots_30.io_valid : i1
    %issue_slots_31_valid = sv.wire sym @issue_slots_31_valid  : !hw.inout<i1>
    sv.assign %issue_slots_31_valid, %slots_31.io_valid : i1
    %issue_slots_32_valid = sv.wire sym @issue_slots_32_valid  : !hw.inout<i1>
    sv.assign %issue_slots_32_valid, %slots_32.io_valid : i1
    %issue_slots_33_valid = sv.wire sym @issue_slots_33_valid  : !hw.inout<i1>
    sv.assign %issue_slots_33_valid, %slots_33.io_valid : i1
    %issue_slots_34_valid = sv.wire sym @issue_slots_34_valid  : !hw.inout<i1>
    sv.assign %issue_slots_34_valid, %slots_34.io_valid : i1
    %issue_slots_35_valid = sv.wire sym @issue_slots_35_valid  : !hw.inout<i1>
    sv.assign %issue_slots_35_valid, %slots_35.io_valid : i1
    %issue_slots_36_valid = sv.wire sym @issue_slots_36_valid  : !hw.inout<i1>
    sv.assign %issue_slots_36_valid, %slots_36.io_valid : i1
    %issue_slots_37_valid = sv.wire sym @issue_slots_37_valid  : !hw.inout<i1>
    sv.assign %issue_slots_37_valid, %slots_37.io_valid : i1
    %issue_slots_38_valid = sv.wire sym @issue_slots_38_valid  : !hw.inout<i1>
    sv.assign %issue_slots_38_valid, %slots_38.io_valid : i1
    %issue_slots_39_valid = sv.wire sym @issue_slots_39_valid  : !hw.inout<i1>
    sv.assign %issue_slots_39_valid, %slots_39.io_valid : i1
    %56 = comb.concat %false, %slots_0.io_valid : i1, i1
    %57 = comb.concat %false, %slots_1.io_valid : i1, i1
    %58 = comb.add %56, %57 {sv.namehint = "_count_T"} : i2
    %59 = comb.concat %false, %slots_3.io_valid : i1, i1
    %60 = comb.concat %false, %slots_4.io_valid : i1, i1
    %61 = comb.concat %false, %slots_2.io_valid : i1, i1
    %62 = comb.add %61, %59, %60 : i2
    %63 = comb.concat %false, %58 : i1, i2
    %64 = comb.concat %false, %62 : i1, i2
    %65 = comb.add %63, %64 {sv.namehint = "_count_T_6"} : i3
    %66 = comb.concat %false, %slots_5.io_valid : i1, i1
    %67 = comb.concat %false, %slots_6.io_valid : i1, i1
    %68 = comb.add %66, %67 {sv.namehint = "_count_T_8"} : i2
    %69 = comb.concat %false, %slots_8.io_valid : i1, i1
    %70 = comb.concat %false, %slots_9.io_valid : i1, i1
    %71 = comb.concat %false, %slots_7.io_valid : i1, i1
    %72 = comb.add %71, %69, %70 : i2
    %73 = comb.concat %false, %68 : i1, i2
    %74 = comb.concat %false, %72 : i1, i2
    %75 = comb.add %73, %74 {sv.namehint = "_count_T_14"} : i3
    %76 = comb.concat %false, %65 : i1, i3
    %77 = comb.concat %false, %75 : i1, i3
    %78 = comb.add %76, %77 {sv.namehint = "_count_T_16"} : i4
    %79 = comb.concat %false, %slots_10.io_valid : i1, i1
    %80 = comb.concat %false, %slots_11.io_valid : i1, i1
    %81 = comb.add %79, %80 {sv.namehint = "_count_T_18"} : i2
    %82 = comb.concat %false, %slots_13.io_valid : i1, i1
    %83 = comb.concat %false, %slots_14.io_valid : i1, i1
    %84 = comb.concat %false, %slots_12.io_valid : i1, i1
    %85 = comb.add %84, %82, %83 : i2
    %86 = comb.concat %false, %81 : i1, i2
    %87 = comb.concat %false, %85 : i1, i2
    %88 = comb.add %86, %87 {sv.namehint = "_count_T_24"} : i3
    %89 = comb.concat %false, %slots_15.io_valid : i1, i1
    %90 = comb.concat %false, %slots_16.io_valid : i1, i1
    %91 = comb.add %89, %90 {sv.namehint = "_count_T_26"} : i2
    %92 = comb.concat %false, %slots_18.io_valid : i1, i1
    %93 = comb.concat %false, %slots_19.io_valid : i1, i1
    %94 = comb.concat %false, %slots_17.io_valid : i1, i1
    %95 = comb.add %94, %92, %93 : i2
    %96 = comb.concat %false, %91 : i1, i2
    %97 = comb.concat %false, %95 : i1, i2
    %98 = comb.add %96, %97 {sv.namehint = "_count_T_32"} : i3
    %99 = comb.concat %false, %88 : i1, i3
    %100 = comb.concat %false, %98 : i1, i3
    %101 = comb.add %99, %100 {sv.namehint = "_count_T_34"} : i4
    %102 = comb.concat %false, %78 : i1, i4
    %103 = comb.concat %false, %101 : i1, i4
    %104 = comb.add %102, %103 {sv.namehint = "_count_T_36"} : i5
    %105 = comb.concat %false, %slots_20.io_valid : i1, i1
    %106 = comb.concat %false, %slots_21.io_valid : i1, i1
    %107 = comb.add %105, %106 {sv.namehint = "_count_T_38"} : i2
    %108 = comb.concat %false, %slots_23.io_valid : i1, i1
    %109 = comb.concat %false, %slots_24.io_valid : i1, i1
    %110 = comb.concat %false, %slots_22.io_valid : i1, i1
    %111 = comb.add %110, %108, %109 : i2
    %112 = comb.concat %false, %107 : i1, i2
    %113 = comb.concat %false, %111 : i1, i2
    %114 = comb.add %112, %113 {sv.namehint = "_count_T_44"} : i3
    %115 = comb.concat %false, %slots_25.io_valid : i1, i1
    %116 = comb.concat %false, %slots_26.io_valid : i1, i1
    %117 = comb.add %115, %116 {sv.namehint = "_count_T_46"} : i2
    %118 = comb.concat %false, %slots_28.io_valid : i1, i1
    %119 = comb.concat %false, %slots_29.io_valid : i1, i1
    %120 = comb.concat %false, %slots_27.io_valid : i1, i1
    %121 = comb.add %120, %118, %119 : i2
    %122 = comb.concat %false, %117 : i1, i2
    %123 = comb.concat %false, %121 : i1, i2
    %124 = comb.add %122, %123 {sv.namehint = "_count_T_52"} : i3
    %125 = comb.concat %false, %114 : i1, i3
    %126 = comb.concat %false, %124 : i1, i3
    %127 = comb.add %125, %126 {sv.namehint = "_count_T_54"} : i4
    %128 = comb.concat %false, %slots_30.io_valid : i1, i1
    %129 = comb.concat %false, %slots_31.io_valid : i1, i1
    %130 = comb.add %128, %129 {sv.namehint = "_count_T_56"} : i2
    %131 = comb.concat %false, %slots_33.io_valid : i1, i1
    %132 = comb.concat %false, %slots_34.io_valid : i1, i1
    %133 = comb.concat %false, %slots_32.io_valid : i1, i1
    %134 = comb.add %133, %131, %132 : i2
    %135 = comb.concat %false, %130 : i1, i2
    %136 = comb.concat %false, %134 : i1, i2
    %137 = comb.add %135, %136 {sv.namehint = "_count_T_62"} : i3
    %138 = comb.concat %false, %slots_35.io_valid : i1, i1
    %139 = comb.concat %false, %slots_36.io_valid : i1, i1
    %140 = comb.add %138, %139 {sv.namehint = "_count_T_64"} : i2
    %141 = comb.concat %false, %slots_38.io_valid : i1, i1
    %142 = comb.concat %false, %slots_39.io_valid : i1, i1
    %143 = comb.concat %false, %slots_37.io_valid : i1, i1
    %144 = comb.add %143, %141, %142 : i2
    %145 = comb.concat %false, %140 : i1, i2
    %146 = comb.concat %false, %144 : i1, i2
    %147 = comb.add %145, %146 {sv.namehint = "_count_T_70"} : i3
    %148 = comb.concat %false, %137 : i1, i3
    %149 = comb.concat %false, %147 : i1, i3
    %150 = comb.add %148, %149 {sv.namehint = "_count_T_72"} : i4
    %151 = comb.concat %false, %127 : i1, i4
    %152 = comb.concat %false, %150 : i1, i4
    %153 = comb.add %151, %152 {sv.namehint = "_count_T_74"} : i5
    %154 = comb.concat %false, %104 : i1, i5
    %155 = comb.concat %false, %153 : i1, i5
    %156 = comb.add %154, %155 {sv.namehint = "_count_T_76"} : i6
    %count = sv.wire sym @count  : !hw.inout<i6>
    sv.assign %count, %156 : i6
    %issue_slots_0_request = sv.wire sym @issue_slots_0_request  : !hw.inout<i1>
    sv.assign %issue_slots_0_request, %slots_0.io_request : i1
    %issue_slots_0_uop_fu_code = sv.wire sym @issue_slots_0_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_0_uop_fu_code, %slots_0.io_uop_fu_code : i10
    %157 = comb.and %slots_0.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_2"} : i10
    %158 = comb.icmp ne %157, %c0_i10 {sv.namehint = "_can_allocate_2"} : i10
    %can_allocate_2 = sv.wire sym @can_allocate_2  : !hw.inout<i1>
    sv.assign %can_allocate_2, %158 : i1
    %159 = comb.and %slots_0.io_request, %158 : i1
    %160 = comb.extract %slots_0.io_uop_fu_code from 0 : (i10) -> i1
    %161 = comb.extract %slots_0.io_uop_fu_code from 5 : (i10) -> i1
    %162 = comb.concat %161, %160 : i1, i1
    %163 = comb.icmp ne %162, %c0_i2 : i2
    %can_allocate_1 = sv.wire sym @can_allocate_1  : !hw.inout<i1>
    sv.assign %can_allocate_1, %163 : i1
    %164 = comb.and %slots_0.io_request, %163 : i1
    %165 = comb.and %slots_0.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T"} : i10
    %166 = comb.icmp ne %165, %c0_i10 {sv.namehint = "_can_allocate"} : i10
    %can_allocate = sv.wire sym @can_allocate  : !hw.inout<i1>
    sv.assign %can_allocate, %166 : i1
    %167 = comb.and %slots_0.io_request, %166 : i1
    %168 = comb.or %164, %167 : i1
    %169 = comb.or %159, %168 : i1
    %170 = comb.xor %169, %true : i1
    %171 = comb.and %slots_0.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_3"} : i10
    %172 = comb.icmp ne %171, %c0_i10 {sv.namehint = "_can_allocate_3"} : i10
    %can_allocate_3 = sv.wire sym @can_allocate_3  : !hw.inout<i1>
    sv.assign %can_allocate_3, %172 : i1
    %173 = comb.and %slots_0.io_request, %170, %172 : i1
    %174 = comb.xor %168, %true : i1
    %175 = comb.and %slots_0.io_request, %174, %158 : i1
    %176 = comb.xor %167, %true : i1
    %177 = comb.and %slots_0.io_request, %176, %163 : i1
    %178 = comb.or %173, %175, %177, %167 {sv.namehint = "_issue_slots_0_grant"} : i1
    %issue_slots_0_grant = sv.wire sym @issue_slots_0_grant  : !hw.inout<i1>
    sv.assign %issue_slots_0_grant, %178 : i1
    %issue_slots_1_request = sv.wire sym @issue_slots_1_request  : !hw.inout<i1>
    sv.assign %issue_slots_1_request, %slots_1.io_request : i1
    %issue_slots_1_uop_fu_code = sv.wire sym @issue_slots_1_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_1_uop_fu_code, %slots_1.io_uop_fu_code : i10
    %179 = comb.and %slots_1.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_6"} : i10
    %180 = comb.icmp ne %179, %c0_i10 {sv.namehint = "_can_allocate_6"} : i10
    %can_allocate_6 = sv.wire sym @can_allocate_6  : !hw.inout<i1>
    sv.assign %can_allocate_6, %180 : i1
    %181 = comb.xor %175, %true : i1
    %182 = comb.and %slots_1.io_request, %180, %181 : i1
    %183 = comb.extract %slots_1.io_uop_fu_code from 0 : (i10) -> i1
    %184 = comb.extract %slots_1.io_uop_fu_code from 5 : (i10) -> i1
    %185 = comb.concat %184, %183 : i1, i1
    %186 = comb.icmp ne %185, %c0_i2 : i2
    %can_allocate_5 = sv.wire sym @can_allocate_5  : !hw.inout<i1>
    sv.assign %can_allocate_5, %186 : i1
    %187 = comb.xor %177, %true : i1
    %188 = comb.and %slots_1.io_request, %186, %187 : i1
    %189 = comb.and %slots_1.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_4"} : i10
    %190 = comb.icmp ne %189, %c0_i10 {sv.namehint = "_can_allocate_4"} : i10
    %can_allocate_4 = sv.wire sym @can_allocate_4  : !hw.inout<i1>
    sv.assign %can_allocate_4, %190 : i1
    %191 = comb.and %slots_1.io_request, %190 : i1
    %192 = comb.and %191, %176 : i1
    %193 = comb.or %188, %192 : i1
    %194 = comb.or %182, %193 : i1
    %195 = comb.xor %194, %true : i1
    %196 = comb.and %slots_1.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_7"} : i10
    %197 = comb.icmp ne %196, %c0_i10 {sv.namehint = "_can_allocate_7"} : i10
    %can_allocate_7 = sv.wire sym @can_allocate_7  : !hw.inout<i1>
    sv.assign %can_allocate_7, %197 : i1
    %198 = comb.and %slots_1.io_request, %195, %197 : i1
    %199 = comb.xor %173, %true : i1
    %200 = comb.and %198, %199 : i1
    %201 = comb.xor %193, %true : i1
    %202 = comb.and %slots_1.io_request, %201, %180 : i1
    %203 = comb.and %202, %181 : i1
    %204 = comb.xor %192, %true : i1
    %205 = comb.and %slots_1.io_request, %204, %186 : i1
    %206 = comb.and %205, %187 : i1
    %207 = comb.or %200, %203, %206, %192 {sv.namehint = "_issue_slots_1_grant"} : i1
    %issue_slots_1_grant = sv.wire sym @issue_slots_1_grant  : !hw.inout<i1>
    sv.assign %issue_slots_1_grant, %207 : i1
    %208 = comb.concat %false, %178 : i1, i1
    %209 = comb.concat %false, %207 : i1, i1
    %210 = comb.add %208, %209 : i2
    %issue_slots_3_request = sv.wire sym @issue_slots_3_request  : !hw.inout<i1>
    sv.assign %issue_slots_3_request, %slots_3.io_request : i1
    %issue_slots_3_uop_fu_code = sv.wire sym @issue_slots_3_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_3_uop_fu_code, %slots_3.io_uop_fu_code : i10
    %211 = comb.and %slots_3.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_14"} : i10
    %212 = comb.icmp ne %211, %c0_i10 {sv.namehint = "_can_allocate_14"} : i10
    %can_allocate_14 = sv.wire sym @can_allocate_14  : !hw.inout<i1>
    sv.assign %can_allocate_14, %212 : i1
    %issue_slots_2_request = sv.wire sym @issue_slots_2_request  : !hw.inout<i1>
    sv.assign %issue_slots_2_request, %slots_2.io_request : i1
    %issue_slots_2_uop_fu_code = sv.wire sym @issue_slots_2_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_2_uop_fu_code, %slots_2.io_uop_fu_code : i10
    %213 = comb.extract %slots_2.io_uop_fu_code from 0 : (i10) -> i1
    %214 = comb.extract %slots_2.io_uop_fu_code from 5 : (i10) -> i1
    %215 = comb.concat %214, %213 : i1, i1
    %216 = comb.icmp ne %215, %c0_i2 : i2
    %can_allocate_9 = sv.wire sym @can_allocate_9  : !hw.inout<i1>
    sv.assign %can_allocate_9, %216 : i1
    %217 = comb.or %205, %177 : i1
    %218 = comb.xor %217, %true : i1
    %219 = comb.and %slots_2.io_request, %216, %218 : i1
    %220 = comb.and %slots_2.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_8"} : i10
    %221 = comb.icmp ne %220, %c0_i10 {sv.namehint = "_can_allocate_8"} : i10
    %can_allocate_8 = sv.wire sym @can_allocate_8  : !hw.inout<i1>
    sv.assign %can_allocate_8, %221 : i1
    %222 = comb.and %slots_2.io_request, %221 : i1
    %223 = comb.or %191, %167 : i1
    %224 = comb.xor %223, %true : i1
    %225 = comb.and %222, %224 : i1
    %226 = comb.or %219, %225 : i1
    %227 = comb.xor %226, %true : i1
    %228 = comb.and %slots_2.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_10"} : i10
    %229 = comb.icmp ne %228, %c0_i10 {sv.namehint = "_can_allocate_10"} : i10
    %can_allocate_10 = sv.wire sym @can_allocate_10  : !hw.inout<i1>
    sv.assign %can_allocate_10, %229 : i1
    %230 = comb.and %slots_2.io_request, %227, %229 : i1
    %231 = comb.or %202, %175 : i1
    %232 = comb.or %230, %231 : i1
    %233 = comb.xor %232, %true : i1
    %234 = comb.and %slots_3.io_request, %212, %233 : i1
    %235 = comb.extract %slots_3.io_uop_fu_code from 0 : (i10) -> i1
    %236 = comb.extract %slots_3.io_uop_fu_code from 5 : (i10) -> i1
    %237 = comb.concat %236, %235 : i1, i1
    %238 = comb.icmp ne %237, %c0_i2 : i2
    %can_allocate_13 = sv.wire sym @can_allocate_13  : !hw.inout<i1>
    sv.assign %can_allocate_13, %238 : i1
    %239 = comb.xor %225, %true : i1
    %240 = comb.and %slots_2.io_request, %239, %216 : i1
    %241 = comb.or %240, %217 : i1
    %242 = comb.xor %241, %true : i1
    %243 = comb.and %slots_3.io_request, %238, %242 : i1
    %244 = comb.and %slots_3.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_12"} : i10
    %245 = comb.icmp ne %244, %c0_i10 {sv.namehint = "_can_allocate_12"} : i10
    %can_allocate_12 = sv.wire sym @can_allocate_12  : !hw.inout<i1>
    sv.assign %can_allocate_12, %245 : i1
    %246 = comb.and %slots_3.io_request, %245 : i1
    %247 = comb.or %222, %223 : i1
    %248 = comb.xor %247, %true : i1
    %249 = comb.and %246, %248 : i1
    %250 = comb.or %243, %249 : i1
    %251 = comb.or %234, %250 : i1
    %252 = comb.xor %251, %true : i1
    %253 = comb.and %slots_3.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_15"} : i10
    %254 = comb.icmp ne %253, %c0_i10 {sv.namehint = "_can_allocate_15"} : i10
    %can_allocate_15 = sv.wire sym @can_allocate_15  : !hw.inout<i1>
    sv.assign %can_allocate_15, %254 : i1
    %255 = comb.and %slots_3.io_request, %252, %254 : i1
    %256 = comb.xor %231, %true : i1
    %257 = comb.and %slots_2.io_request, %229, %256 : i1
    %258 = comb.or %257, %226 : i1
    %259 = comb.xor %258, %true : i1
    %260 = comb.and %slots_2.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_11"} : i10
    %261 = comb.icmp ne %260, %c0_i10 {sv.namehint = "_can_allocate_11"} : i10
    %can_allocate_11 = sv.wire sym @can_allocate_11  : !hw.inout<i1>
    sv.assign %can_allocate_11, %261 : i1
    %262 = comb.and %slots_2.io_request, %259, %261 : i1
    %263 = comb.or %198, %173 : i1
    %264 = comb.or %262, %263 : i1
    %265 = comb.xor %264, %true : i1
    %266 = comb.and %255, %265 : i1
    %267 = comb.xor %250, %true : i1
    %268 = comb.and %slots_3.io_request, %267, %212 : i1
    %269 = comb.and %268, %233 : i1
    %270 = comb.xor %249, %true : i1
    %271 = comb.and %slots_3.io_request, %270, %238 : i1
    %272 = comb.and %271, %242 : i1
    %273 = comb.or %266, %269, %272, %249 {sv.namehint = "_issue_slots_3_grant"} : i1
    %issue_slots_3_grant = sv.wire sym @issue_slots_3_grant  : !hw.inout<i1>
    sv.assign %issue_slots_3_grant, %273 : i1
    %issue_slots_4_request = sv.wire sym @issue_slots_4_request  : !hw.inout<i1>
    sv.assign %issue_slots_4_request, %slots_4.io_request : i1
    %issue_slots_4_uop_fu_code = sv.wire sym @issue_slots_4_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_4_uop_fu_code, %slots_4.io_uop_fu_code : i10
    %274 = comb.and %slots_4.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_18"} : i10
    %275 = comb.icmp ne %274, %c0_i10 {sv.namehint = "_can_allocate_18"} : i10
    %can_allocate_18 = sv.wire sym @can_allocate_18  : !hw.inout<i1>
    sv.assign %can_allocate_18, %275 : i1
    %276 = comb.or %268, %232 : i1
    %277 = comb.xor %276, %true : i1
    %278 = comb.and %slots_4.io_request, %275, %277 : i1
    %279 = comb.extract %slots_4.io_uop_fu_code from 0 : (i10) -> i1
    %280 = comb.extract %slots_4.io_uop_fu_code from 5 : (i10) -> i1
    %281 = comb.concat %280, %279 : i1, i1
    %282 = comb.icmp ne %281, %c0_i2 : i2
    %can_allocate_17 = sv.wire sym @can_allocate_17  : !hw.inout<i1>
    sv.assign %can_allocate_17, %282 : i1
    %283 = comb.or %271, %241 : i1
    %284 = comb.xor %283, %true : i1
    %285 = comb.and %slots_4.io_request, %282, %284 : i1
    %286 = comb.and %slots_4.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_16"} : i10
    %287 = comb.icmp ne %286, %c0_i10 {sv.namehint = "_can_allocate_16"} : i10
    %can_allocate_16 = sv.wire sym @can_allocate_16  : !hw.inout<i1>
    sv.assign %can_allocate_16, %287 : i1
    %288 = comb.and %slots_4.io_request, %287 : i1
    %289 = comb.or %246, %247 : i1
    %290 = comb.xor %289, %true : i1
    %291 = comb.and %288, %290 : i1
    %292 = comb.or %285, %291 : i1
    %293 = comb.or %278, %292 : i1
    %294 = comb.xor %293, %true : i1
    %295 = comb.and %slots_4.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_19"} : i10
    %296 = comb.icmp ne %295, %c0_i10 {sv.namehint = "_can_allocate_19"} : i10
    %can_allocate_19 = sv.wire sym @can_allocate_19  : !hw.inout<i1>
    sv.assign %can_allocate_19, %296 : i1
    %297 = comb.and %slots_4.io_request, %294, %296 : i1
    %298 = comb.or %255, %264 : i1
    %299 = comb.xor %298, %true : i1
    %300 = comb.and %297, %299 : i1
    %301 = comb.xor %292, %true : i1
    %302 = comb.and %slots_4.io_request, %301, %275 : i1
    %303 = comb.and %302, %277 : i1
    %304 = comb.xor %291, %true : i1
    %305 = comb.and %slots_4.io_request, %304, %282 : i1
    %306 = comb.and %305, %284 : i1
    %307 = comb.or %300, %303, %306, %291 {sv.namehint = "_issue_slots_4_grant"} : i1
    %issue_slots_4_grant = sv.wire sym @issue_slots_4_grant  : !hw.inout<i1>
    sv.assign %issue_slots_4_grant, %307 : i1
    %308 = comb.concat %false, %273 : i1, i1
    %309 = comb.concat %false, %307 : i1, i1
    %310 = comb.xor %263, %true : i1
    %311 = comb.and %262, %310 : i1
    %312 = comb.and %230, %256 : i1
    %313 = comb.and %240, %218 : i1
    %314 = comb.or %311, %312, %313, %225 {sv.namehint = "_issue_slots_2_grant"} : i1
    %issue_slots_2_grant = sv.wire sym @issue_slots_2_grant  : !hw.inout<i1>
    sv.assign %issue_slots_2_grant, %314 : i1
    %315 = comb.concat %false, %314 : i1, i1
    %316 = comb.add %315, %308, %309 : i2
    %317 = comb.concat %false, %210 : i1, i2
    %318 = comb.concat %false, %316 : i1, i2
    %319 = comb.add %317, %318 : i3
    %issue_slots_5_request = sv.wire sym @issue_slots_5_request  : !hw.inout<i1>
    sv.assign %issue_slots_5_request, %slots_5.io_request : i1
    %issue_slots_5_uop_fu_code = sv.wire sym @issue_slots_5_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_5_uop_fu_code, %slots_5.io_uop_fu_code : i10
    %320 = comb.and %slots_5.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_22"} : i10
    %321 = comb.icmp ne %320, %c0_i10 {sv.namehint = "_can_allocate_22"} : i10
    %can_allocate_22 = sv.wire sym @can_allocate_22  : !hw.inout<i1>
    sv.assign %can_allocate_22, %321 : i1
    %322 = comb.or %302, %276 : i1
    %323 = comb.xor %322, %true : i1
    %324 = comb.and %slots_5.io_request, %321, %323 : i1
    %325 = comb.extract %slots_5.io_uop_fu_code from 0 : (i10) -> i1
    %326 = comb.extract %slots_5.io_uop_fu_code from 5 : (i10) -> i1
    %327 = comb.concat %326, %325 : i1, i1
    %328 = comb.icmp ne %327, %c0_i2 : i2
    %can_allocate_21 = sv.wire sym @can_allocate_21  : !hw.inout<i1>
    sv.assign %can_allocate_21, %328 : i1
    %329 = comb.or %305, %283 : i1
    %330 = comb.xor %329, %true : i1
    %331 = comb.and %slots_5.io_request, %328, %330 : i1
    %332 = comb.and %slots_5.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_20"} : i10
    %333 = comb.icmp ne %332, %c0_i10 {sv.namehint = "_can_allocate_20"} : i10
    %can_allocate_20 = sv.wire sym @can_allocate_20  : !hw.inout<i1>
    sv.assign %can_allocate_20, %333 : i1
    %334 = comb.and %slots_5.io_request, %333 : i1
    %335 = comb.or %288, %289 : i1
    %336 = comb.xor %335, %true : i1
    %337 = comb.and %334, %336 : i1
    %338 = comb.or %331, %337 : i1
    %339 = comb.or %324, %338 : i1
    %340 = comb.xor %339, %true : i1
    %341 = comb.and %slots_5.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_23"} : i10
    %342 = comb.icmp ne %341, %c0_i10 {sv.namehint = "_can_allocate_23"} : i10
    %can_allocate_23 = sv.wire sym @can_allocate_23  : !hw.inout<i1>
    sv.assign %can_allocate_23, %342 : i1
    %343 = comb.and %slots_5.io_request, %340, %342 : i1
    %344 = comb.or %297, %298 : i1
    %345 = comb.xor %344, %true : i1
    %346 = comb.and %343, %345 : i1
    %347 = comb.xor %338, %true : i1
    %348 = comb.and %slots_5.io_request, %347, %321 : i1
    %349 = comb.and %348, %323 : i1
    %350 = comb.xor %337, %true : i1
    %351 = comb.and %slots_5.io_request, %350, %328 : i1
    %352 = comb.and %351, %330 : i1
    %353 = comb.or %346, %349, %352, %337 {sv.namehint = "_issue_slots_5_grant"} : i1
    %issue_slots_5_grant = sv.wire sym @issue_slots_5_grant  : !hw.inout<i1>
    sv.assign %issue_slots_5_grant, %353 : i1
    %issue_slots_6_request = sv.wire sym @issue_slots_6_request  : !hw.inout<i1>
    sv.assign %issue_slots_6_request, %slots_6.io_request : i1
    %issue_slots_6_uop_fu_code = sv.wire sym @issue_slots_6_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_6_uop_fu_code, %slots_6.io_uop_fu_code : i10
    %354 = comb.and %slots_6.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_26"} : i10
    %355 = comb.icmp ne %354, %c0_i10 {sv.namehint = "_can_allocate_26"} : i10
    %can_allocate_26 = sv.wire sym @can_allocate_26  : !hw.inout<i1>
    sv.assign %can_allocate_26, %355 : i1
    %356 = comb.or %348, %322 : i1
    %357 = comb.xor %356, %true : i1
    %358 = comb.and %slots_6.io_request, %355, %357 : i1
    %359 = comb.extract %slots_6.io_uop_fu_code from 0 : (i10) -> i1
    %360 = comb.extract %slots_6.io_uop_fu_code from 5 : (i10) -> i1
    %361 = comb.concat %360, %359 : i1, i1
    %362 = comb.icmp ne %361, %c0_i2 : i2
    %can_allocate_25 = sv.wire sym @can_allocate_25  : !hw.inout<i1>
    sv.assign %can_allocate_25, %362 : i1
    %363 = comb.or %351, %329 : i1
    %364 = comb.xor %363, %true : i1
    %365 = comb.and %slots_6.io_request, %362, %364 : i1
    %366 = comb.and %slots_6.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_24"} : i10
    %367 = comb.icmp ne %366, %c0_i10 {sv.namehint = "_can_allocate_24"} : i10
    %can_allocate_24 = sv.wire sym @can_allocate_24  : !hw.inout<i1>
    sv.assign %can_allocate_24, %367 : i1
    %368 = comb.and %slots_6.io_request, %367 : i1
    %369 = comb.or %334, %335 : i1
    %370 = comb.xor %369, %true : i1
    %371 = comb.and %368, %370 : i1
    %372 = comb.or %365, %371 : i1
    %373 = comb.or %358, %372 : i1
    %374 = comb.xor %373, %true : i1
    %375 = comb.and %slots_6.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_27"} : i10
    %376 = comb.icmp ne %375, %c0_i10 {sv.namehint = "_can_allocate_27"} : i10
    %can_allocate_27 = sv.wire sym @can_allocate_27  : !hw.inout<i1>
    sv.assign %can_allocate_27, %376 : i1
    %377 = comb.and %slots_6.io_request, %374, %376 : i1
    %378 = comb.or %343, %344 : i1
    %379 = comb.xor %378, %true : i1
    %380 = comb.and %377, %379 : i1
    %381 = comb.xor %372, %true : i1
    %382 = comb.and %slots_6.io_request, %381, %355 : i1
    %383 = comb.and %382, %357 : i1
    %384 = comb.xor %371, %true : i1
    %385 = comb.and %slots_6.io_request, %384, %362 : i1
    %386 = comb.and %385, %364 : i1
    %387 = comb.or %380, %383, %386, %371 {sv.namehint = "_issue_slots_6_grant"} : i1
    %issue_slots_6_grant = sv.wire sym @issue_slots_6_grant  : !hw.inout<i1>
    sv.assign %issue_slots_6_grant, %387 : i1
    %388 = comb.concat %false, %353 : i1, i1
    %389 = comb.concat %false, %387 : i1, i1
    %390 = comb.add %388, %389 : i2
    %issue_slots_8_request = sv.wire sym @issue_slots_8_request  : !hw.inout<i1>
    sv.assign %issue_slots_8_request, %slots_8.io_request : i1
    %issue_slots_8_uop_fu_code = sv.wire sym @issue_slots_8_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_8_uop_fu_code, %slots_8.io_uop_fu_code : i10
    %391 = comb.and %slots_8.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_34"} : i10
    %392 = comb.icmp ne %391, %c0_i10 {sv.namehint = "_can_allocate_34"} : i10
    %can_allocate_34 = sv.wire sym @can_allocate_34  : !hw.inout<i1>
    sv.assign %can_allocate_34, %392 : i1
    %issue_slots_7_request = sv.wire sym @issue_slots_7_request  : !hw.inout<i1>
    sv.assign %issue_slots_7_request, %slots_7.io_request : i1
    %issue_slots_7_uop_fu_code = sv.wire sym @issue_slots_7_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_7_uop_fu_code, %slots_7.io_uop_fu_code : i10
    %393 = comb.extract %slots_7.io_uop_fu_code from 0 : (i10) -> i1
    %394 = comb.extract %slots_7.io_uop_fu_code from 5 : (i10) -> i1
    %395 = comb.concat %394, %393 : i1, i1
    %396 = comb.icmp ne %395, %c0_i2 : i2
    %can_allocate_29 = sv.wire sym @can_allocate_29  : !hw.inout<i1>
    sv.assign %can_allocate_29, %396 : i1
    %397 = comb.or %385, %363 : i1
    %398 = comb.xor %397, %true : i1
    %399 = comb.and %slots_7.io_request, %396, %398 : i1
    %400 = comb.and %slots_7.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_28"} : i10
    %401 = comb.icmp ne %400, %c0_i10 {sv.namehint = "_can_allocate_28"} : i10
    %can_allocate_28 = sv.wire sym @can_allocate_28  : !hw.inout<i1>
    sv.assign %can_allocate_28, %401 : i1
    %402 = comb.and %slots_7.io_request, %401 : i1
    %403 = comb.or %368, %369 : i1
    %404 = comb.xor %403, %true : i1
    %405 = comb.and %402, %404 : i1
    %406 = comb.or %399, %405 : i1
    %407 = comb.xor %406, %true : i1
    %408 = comb.and %slots_7.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_30"} : i10
    %409 = comb.icmp ne %408, %c0_i10 {sv.namehint = "_can_allocate_30"} : i10
    %can_allocate_30 = sv.wire sym @can_allocate_30  : !hw.inout<i1>
    sv.assign %can_allocate_30, %409 : i1
    %410 = comb.and %slots_7.io_request, %407, %409 : i1
    %411 = comb.or %382, %356 : i1
    %412 = comb.or %410, %411 : i1
    %413 = comb.xor %412, %true : i1
    %414 = comb.and %slots_8.io_request, %392, %413 : i1
    %415 = comb.extract %slots_8.io_uop_fu_code from 0 : (i10) -> i1
    %416 = comb.extract %slots_8.io_uop_fu_code from 5 : (i10) -> i1
    %417 = comb.concat %416, %415 : i1, i1
    %418 = comb.icmp ne %417, %c0_i2 : i2
    %can_allocate_33 = sv.wire sym @can_allocate_33  : !hw.inout<i1>
    sv.assign %can_allocate_33, %418 : i1
    %419 = comb.xor %405, %true : i1
    %420 = comb.and %slots_7.io_request, %419, %396 : i1
    %421 = comb.or %420, %397 : i1
    %422 = comb.xor %421, %true : i1
    %423 = comb.and %slots_8.io_request, %418, %422 : i1
    %424 = comb.and %slots_8.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_32"} : i10
    %425 = comb.icmp ne %424, %c0_i10 {sv.namehint = "_can_allocate_32"} : i10
    %can_allocate_32 = sv.wire sym @can_allocate_32  : !hw.inout<i1>
    sv.assign %can_allocate_32, %425 : i1
    %426 = comb.and %slots_8.io_request, %425 : i1
    %427 = comb.or %402, %403 : i1
    %428 = comb.xor %427, %true : i1
    %429 = comb.and %426, %428 : i1
    %430 = comb.or %423, %429 : i1
    %431 = comb.or %414, %430 : i1
    %432 = comb.xor %431, %true : i1
    %433 = comb.and %slots_8.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_35"} : i10
    %434 = comb.icmp ne %433, %c0_i10 {sv.namehint = "_can_allocate_35"} : i10
    %can_allocate_35 = sv.wire sym @can_allocate_35  : !hw.inout<i1>
    sv.assign %can_allocate_35, %434 : i1
    %435 = comb.and %slots_8.io_request, %432, %434 : i1
    %436 = comb.xor %411, %true : i1
    %437 = comb.and %slots_7.io_request, %409, %436 : i1
    %438 = comb.or %437, %406 : i1
    %439 = comb.xor %438, %true : i1
    %440 = comb.and %slots_7.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_31"} : i10
    %441 = comb.icmp ne %440, %c0_i10 {sv.namehint = "_can_allocate_31"} : i10
    %can_allocate_31 = sv.wire sym @can_allocate_31  : !hw.inout<i1>
    sv.assign %can_allocate_31, %441 : i1
    %442 = comb.and %slots_7.io_request, %439, %441 : i1
    %443 = comb.or %377, %378 : i1
    %444 = comb.or %442, %443 : i1
    %445 = comb.xor %444, %true : i1
    %446 = comb.and %435, %445 : i1
    %447 = comb.xor %430, %true : i1
    %448 = comb.and %slots_8.io_request, %447, %392 : i1
    %449 = comb.and %448, %413 : i1
    %450 = comb.xor %429, %true : i1
    %451 = comb.and %slots_8.io_request, %450, %418 : i1
    %452 = comb.and %451, %422 : i1
    %453 = comb.or %446, %449, %452, %429 {sv.namehint = "_issue_slots_8_grant"} : i1
    %issue_slots_8_grant = sv.wire sym @issue_slots_8_grant  : !hw.inout<i1>
    sv.assign %issue_slots_8_grant, %453 : i1
    %issue_slots_9_request = sv.wire sym @issue_slots_9_request  : !hw.inout<i1>
    sv.assign %issue_slots_9_request, %slots_9.io_request : i1
    %issue_slots_9_uop_fu_code = sv.wire sym @issue_slots_9_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_9_uop_fu_code, %slots_9.io_uop_fu_code : i10
    %454 = comb.and %slots_9.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_38"} : i10
    %455 = comb.icmp ne %454, %c0_i10 {sv.namehint = "_can_allocate_38"} : i10
    %can_allocate_38 = sv.wire sym @can_allocate_38  : !hw.inout<i1>
    sv.assign %can_allocate_38, %455 : i1
    %456 = comb.or %448, %412 : i1
    %457 = comb.xor %456, %true : i1
    %458 = comb.and %slots_9.io_request, %455, %457 : i1
    %459 = comb.extract %slots_9.io_uop_fu_code from 0 : (i10) -> i1
    %460 = comb.extract %slots_9.io_uop_fu_code from 5 : (i10) -> i1
    %461 = comb.concat %460, %459 : i1, i1
    %462 = comb.icmp ne %461, %c0_i2 : i2
    %can_allocate_37 = sv.wire sym @can_allocate_37  : !hw.inout<i1>
    sv.assign %can_allocate_37, %462 : i1
    %463 = comb.or %451, %421 : i1
    %464 = comb.xor %463, %true : i1
    %465 = comb.and %slots_9.io_request, %462, %464 : i1
    %466 = comb.and %slots_9.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_36"} : i10
    %467 = comb.icmp ne %466, %c0_i10 {sv.namehint = "_can_allocate_36"} : i10
    %can_allocate_36 = sv.wire sym @can_allocate_36  : !hw.inout<i1>
    sv.assign %can_allocate_36, %467 : i1
    %468 = comb.and %slots_9.io_request, %467 : i1
    %469 = comb.or %426, %427 : i1
    %470 = comb.xor %469, %true : i1
    %471 = comb.and %468, %470 : i1
    %472 = comb.or %465, %471 : i1
    %473 = comb.or %458, %472 : i1
    %474 = comb.xor %473, %true : i1
    %475 = comb.and %slots_9.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_39"} : i10
    %476 = comb.icmp ne %475, %c0_i10 {sv.namehint = "_can_allocate_39"} : i10
    %can_allocate_39 = sv.wire sym @can_allocate_39  : !hw.inout<i1>
    sv.assign %can_allocate_39, %476 : i1
    %477 = comb.and %slots_9.io_request, %474, %476 : i1
    %478 = comb.or %435, %444 : i1
    %479 = comb.xor %478, %true : i1
    %480 = comb.and %477, %479 : i1
    %481 = comb.xor %472, %true : i1
    %482 = comb.and %slots_9.io_request, %481, %455 : i1
    %483 = comb.and %482, %457 : i1
    %484 = comb.xor %471, %true : i1
    %485 = comb.and %slots_9.io_request, %484, %462 : i1
    %486 = comb.and %485, %464 : i1
    %487 = comb.or %480, %483, %486, %471 {sv.namehint = "_issue_slots_9_grant"} : i1
    %issue_slots_9_grant = sv.wire sym @issue_slots_9_grant  : !hw.inout<i1>
    sv.assign %issue_slots_9_grant, %487 : i1
    %488 = comb.concat %false, %453 : i1, i1
    %489 = comb.concat %false, %487 : i1, i1
    %490 = comb.xor %443, %true : i1
    %491 = comb.and %442, %490 : i1
    %492 = comb.and %410, %436 : i1
    %493 = comb.and %420, %398 : i1
    %494 = comb.or %491, %492, %493, %405 {sv.namehint = "_issue_slots_7_grant"} : i1
    %issue_slots_7_grant = sv.wire sym @issue_slots_7_grant  : !hw.inout<i1>
    sv.assign %issue_slots_7_grant, %494 : i1
    %495 = comb.concat %false, %494 : i1, i1
    %496 = comb.add %495, %488, %489 : i2
    %497 = comb.concat %false, %390 : i1, i2
    %498 = comb.concat %false, %496 : i1, i2
    %499 = comb.add %497, %498 : i3
    %500 = comb.concat %false, %319 : i1, i3
    %501 = comb.concat %false, %499 : i1, i3
    %502 = comb.add %500, %501 : i4
    %issue_slots_10_request = sv.wire sym @issue_slots_10_request  : !hw.inout<i1>
    sv.assign %issue_slots_10_request, %slots_10.io_request : i1
    %issue_slots_10_uop_fu_code = sv.wire sym @issue_slots_10_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_10_uop_fu_code, %slots_10.io_uop_fu_code : i10
    %503 = comb.and %slots_10.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_42"} : i10
    %504 = comb.icmp ne %503, %c0_i10 {sv.namehint = "_can_allocate_42"} : i10
    %can_allocate_42 = sv.wire sym @can_allocate_42  : !hw.inout<i1>
    sv.assign %can_allocate_42, %504 : i1
    %505 = comb.or %482, %456 : i1
    %506 = comb.xor %505, %true : i1
    %507 = comb.and %slots_10.io_request, %504, %506 : i1
    %508 = comb.extract %slots_10.io_uop_fu_code from 0 : (i10) -> i1
    %509 = comb.extract %slots_10.io_uop_fu_code from 5 : (i10) -> i1
    %510 = comb.concat %509, %508 : i1, i1
    %511 = comb.icmp ne %510, %c0_i2 : i2
    %can_allocate_41 = sv.wire sym @can_allocate_41  : !hw.inout<i1>
    sv.assign %can_allocate_41, %511 : i1
    %512 = comb.or %485, %463 : i1
    %513 = comb.xor %512, %true : i1
    %514 = comb.and %slots_10.io_request, %511, %513 : i1
    %515 = comb.and %slots_10.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_40"} : i10
    %516 = comb.icmp ne %515, %c0_i10 {sv.namehint = "_can_allocate_40"} : i10
    %can_allocate_40 = sv.wire sym @can_allocate_40  : !hw.inout<i1>
    sv.assign %can_allocate_40, %516 : i1
    %517 = comb.and %slots_10.io_request, %516 : i1
    %518 = comb.or %468, %469 : i1
    %519 = comb.xor %518, %true : i1
    %520 = comb.and %517, %519 : i1
    %521 = comb.or %514, %520 : i1
    %522 = comb.or %507, %521 : i1
    %523 = comb.xor %522, %true : i1
    %524 = comb.and %slots_10.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_43"} : i10
    %525 = comb.icmp ne %524, %c0_i10 {sv.namehint = "_can_allocate_43"} : i10
    %can_allocate_43 = sv.wire sym @can_allocate_43  : !hw.inout<i1>
    sv.assign %can_allocate_43, %525 : i1
    %526 = comb.and %slots_10.io_request, %523, %525 : i1
    %527 = comb.or %477, %478 : i1
    %528 = comb.xor %527, %true : i1
    %529 = comb.and %526, %528 : i1
    %530 = comb.xor %521, %true : i1
    %531 = comb.and %slots_10.io_request, %530, %504 : i1
    %532 = comb.and %531, %506 : i1
    %533 = comb.xor %520, %true : i1
    %534 = comb.and %slots_10.io_request, %533, %511 : i1
    %535 = comb.and %534, %513 : i1
    %536 = comb.or %529, %532, %535, %520 {sv.namehint = "_issue_slots_10_grant"} : i1
    %issue_slots_10_grant = sv.wire sym @issue_slots_10_grant  : !hw.inout<i1>
    sv.assign %issue_slots_10_grant, %536 : i1
    %issue_slots_11_request = sv.wire sym @issue_slots_11_request  : !hw.inout<i1>
    sv.assign %issue_slots_11_request, %slots_11.io_request : i1
    %issue_slots_11_uop_fu_code = sv.wire sym @issue_slots_11_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_11_uop_fu_code, %slots_11.io_uop_fu_code : i10
    %537 = comb.and %slots_11.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_46"} : i10
    %538 = comb.icmp ne %537, %c0_i10 {sv.namehint = "_can_allocate_46"} : i10
    %can_allocate_46 = sv.wire sym @can_allocate_46  : !hw.inout<i1>
    sv.assign %can_allocate_46, %538 : i1
    %539 = comb.or %531, %505 : i1
    %540 = comb.xor %539, %true : i1
    %541 = comb.and %slots_11.io_request, %538, %540 : i1
    %542 = comb.extract %slots_11.io_uop_fu_code from 0 : (i10) -> i1
    %543 = comb.extract %slots_11.io_uop_fu_code from 5 : (i10) -> i1
    %544 = comb.concat %543, %542 : i1, i1
    %545 = comb.icmp ne %544, %c0_i2 : i2
    %can_allocate_45 = sv.wire sym @can_allocate_45  : !hw.inout<i1>
    sv.assign %can_allocate_45, %545 : i1
    %546 = comb.or %534, %512 : i1
    %547 = comb.xor %546, %true : i1
    %548 = comb.and %slots_11.io_request, %545, %547 : i1
    %549 = comb.and %slots_11.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_44"} : i10
    %550 = comb.icmp ne %549, %c0_i10 {sv.namehint = "_can_allocate_44"} : i10
    %can_allocate_44 = sv.wire sym @can_allocate_44  : !hw.inout<i1>
    sv.assign %can_allocate_44, %550 : i1
    %551 = comb.and %slots_11.io_request, %550 : i1
    %552 = comb.or %517, %518 : i1
    %553 = comb.xor %552, %true : i1
    %554 = comb.and %551, %553 : i1
    %555 = comb.or %548, %554 : i1
    %556 = comb.or %541, %555 : i1
    %557 = comb.xor %556, %true : i1
    %558 = comb.and %slots_11.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_47"} : i10
    %559 = comb.icmp ne %558, %c0_i10 {sv.namehint = "_can_allocate_47"} : i10
    %can_allocate_47 = sv.wire sym @can_allocate_47  : !hw.inout<i1>
    sv.assign %can_allocate_47, %559 : i1
    %560 = comb.and %slots_11.io_request, %557, %559 : i1
    %561 = comb.or %526, %527 : i1
    %562 = comb.xor %561, %true : i1
    %563 = comb.and %560, %562 : i1
    %564 = comb.xor %555, %true : i1
    %565 = comb.and %slots_11.io_request, %564, %538 : i1
    %566 = comb.and %565, %540 : i1
    %567 = comb.xor %554, %true : i1
    %568 = comb.and %slots_11.io_request, %567, %545 : i1
    %569 = comb.and %568, %547 : i1
    %570 = comb.or %563, %566, %569, %554 {sv.namehint = "_issue_slots_11_grant"} : i1
    %issue_slots_11_grant = sv.wire sym @issue_slots_11_grant  : !hw.inout<i1>
    sv.assign %issue_slots_11_grant, %570 : i1
    %571 = comb.concat %false, %536 : i1, i1
    %572 = comb.concat %false, %570 : i1, i1
    %573 = comb.add %571, %572 : i2
    %issue_slots_13_request = sv.wire sym @issue_slots_13_request  : !hw.inout<i1>
    sv.assign %issue_slots_13_request, %slots_13.io_request : i1
    %issue_slots_13_uop_fu_code = sv.wire sym @issue_slots_13_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_13_uop_fu_code, %slots_13.io_uop_fu_code : i10
    %574 = comb.and %slots_13.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_54"} : i10
    %575 = comb.icmp ne %574, %c0_i10 {sv.namehint = "_can_allocate_54"} : i10
    %can_allocate_54 = sv.wire sym @can_allocate_54  : !hw.inout<i1>
    sv.assign %can_allocate_54, %575 : i1
    %issue_slots_12_request = sv.wire sym @issue_slots_12_request  : !hw.inout<i1>
    sv.assign %issue_slots_12_request, %slots_12.io_request : i1
    %issue_slots_12_uop_fu_code = sv.wire sym @issue_slots_12_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_12_uop_fu_code, %slots_12.io_uop_fu_code : i10
    %576 = comb.extract %slots_12.io_uop_fu_code from 0 : (i10) -> i1
    %577 = comb.extract %slots_12.io_uop_fu_code from 5 : (i10) -> i1
    %578 = comb.concat %577, %576 : i1, i1
    %579 = comb.icmp ne %578, %c0_i2 : i2
    %can_allocate_49 = sv.wire sym @can_allocate_49  : !hw.inout<i1>
    sv.assign %can_allocate_49, %579 : i1
    %580 = comb.or %568, %546 : i1
    %581 = comb.xor %580, %true : i1
    %582 = comb.and %slots_12.io_request, %579, %581 : i1
    %583 = comb.and %slots_12.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_48"} : i10
    %584 = comb.icmp ne %583, %c0_i10 {sv.namehint = "_can_allocate_48"} : i10
    %can_allocate_48 = sv.wire sym @can_allocate_48  : !hw.inout<i1>
    sv.assign %can_allocate_48, %584 : i1
    %585 = comb.and %slots_12.io_request, %584 : i1
    %586 = comb.or %551, %552 : i1
    %587 = comb.xor %586, %true : i1
    %588 = comb.and %585, %587 : i1
    %589 = comb.or %582, %588 : i1
    %590 = comb.xor %589, %true : i1
    %591 = comb.and %slots_12.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_50"} : i10
    %592 = comb.icmp ne %591, %c0_i10 {sv.namehint = "_can_allocate_50"} : i10
    %can_allocate_50 = sv.wire sym @can_allocate_50  : !hw.inout<i1>
    sv.assign %can_allocate_50, %592 : i1
    %593 = comb.and %slots_12.io_request, %590, %592 : i1
    %594 = comb.or %565, %539 : i1
    %595 = comb.or %593, %594 : i1
    %596 = comb.xor %595, %true : i1
    %597 = comb.and %slots_13.io_request, %575, %596 : i1
    %598 = comb.extract %slots_13.io_uop_fu_code from 0 : (i10) -> i1
    %599 = comb.extract %slots_13.io_uop_fu_code from 5 : (i10) -> i1
    %600 = comb.concat %599, %598 : i1, i1
    %601 = comb.icmp ne %600, %c0_i2 : i2
    %can_allocate_53 = sv.wire sym @can_allocate_53  : !hw.inout<i1>
    sv.assign %can_allocate_53, %601 : i1
    %602 = comb.xor %588, %true : i1
    %603 = comb.and %slots_12.io_request, %602, %579 : i1
    %604 = comb.or %603, %580 : i1
    %605 = comb.xor %604, %true : i1
    %606 = comb.and %slots_13.io_request, %601, %605 : i1
    %607 = comb.and %slots_13.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_52"} : i10
    %608 = comb.icmp ne %607, %c0_i10 {sv.namehint = "_can_allocate_52"} : i10
    %can_allocate_52 = sv.wire sym @can_allocate_52  : !hw.inout<i1>
    sv.assign %can_allocate_52, %608 : i1
    %609 = comb.and %slots_13.io_request, %608 : i1
    %610 = comb.or %585, %586 : i1
    %611 = comb.xor %610, %true : i1
    %612 = comb.and %609, %611 : i1
    %613 = comb.or %606, %612 : i1
    %614 = comb.or %597, %613 : i1
    %615 = comb.xor %614, %true : i1
    %616 = comb.and %slots_13.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_55"} : i10
    %617 = comb.icmp ne %616, %c0_i10 {sv.namehint = "_can_allocate_55"} : i10
    %can_allocate_55 = sv.wire sym @can_allocate_55  : !hw.inout<i1>
    sv.assign %can_allocate_55, %617 : i1
    %618 = comb.and %slots_13.io_request, %615, %617 : i1
    %619 = comb.xor %594, %true : i1
    %620 = comb.and %slots_12.io_request, %592, %619 : i1
    %621 = comb.or %620, %589 : i1
    %622 = comb.xor %621, %true : i1
    %623 = comb.and %slots_12.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_51"} : i10
    %624 = comb.icmp ne %623, %c0_i10 {sv.namehint = "_can_allocate_51"} : i10
    %can_allocate_51 = sv.wire sym @can_allocate_51  : !hw.inout<i1>
    sv.assign %can_allocate_51, %624 : i1
    %625 = comb.and %slots_12.io_request, %622, %624 : i1
    %626 = comb.or %560, %561 : i1
    %627 = comb.or %625, %626 : i1
    %628 = comb.xor %627, %true : i1
    %629 = comb.and %618, %628 : i1
    %630 = comb.xor %613, %true : i1
    %631 = comb.and %slots_13.io_request, %630, %575 : i1
    %632 = comb.and %631, %596 : i1
    %633 = comb.xor %612, %true : i1
    %634 = comb.and %slots_13.io_request, %633, %601 : i1
    %635 = comb.and %634, %605 : i1
    %636 = comb.or %629, %632, %635, %612 {sv.namehint = "_issue_slots_13_grant"} : i1
    %issue_slots_13_grant = sv.wire sym @issue_slots_13_grant  : !hw.inout<i1>
    sv.assign %issue_slots_13_grant, %636 : i1
    %issue_slots_14_request = sv.wire sym @issue_slots_14_request  : !hw.inout<i1>
    sv.assign %issue_slots_14_request, %slots_14.io_request : i1
    %issue_slots_14_uop_fu_code = sv.wire sym @issue_slots_14_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_14_uop_fu_code, %slots_14.io_uop_fu_code : i10
    %637 = comb.and %slots_14.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_58"} : i10
    %638 = comb.icmp ne %637, %c0_i10 {sv.namehint = "_can_allocate_58"} : i10
    %can_allocate_58 = sv.wire sym @can_allocate_58  : !hw.inout<i1>
    sv.assign %can_allocate_58, %638 : i1
    %639 = comb.or %631, %595 : i1
    %640 = comb.xor %639, %true : i1
    %641 = comb.and %slots_14.io_request, %638, %640 : i1
    %642 = comb.extract %slots_14.io_uop_fu_code from 0 : (i10) -> i1
    %643 = comb.extract %slots_14.io_uop_fu_code from 5 : (i10) -> i1
    %644 = comb.concat %643, %642 : i1, i1
    %645 = comb.icmp ne %644, %c0_i2 : i2
    %can_allocate_57 = sv.wire sym @can_allocate_57  : !hw.inout<i1>
    sv.assign %can_allocate_57, %645 : i1
    %646 = comb.or %634, %604 : i1
    %647 = comb.xor %646, %true : i1
    %648 = comb.and %slots_14.io_request, %645, %647 : i1
    %649 = comb.and %slots_14.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_56"} : i10
    %650 = comb.icmp ne %649, %c0_i10 {sv.namehint = "_can_allocate_56"} : i10
    %can_allocate_56 = sv.wire sym @can_allocate_56  : !hw.inout<i1>
    sv.assign %can_allocate_56, %650 : i1
    %651 = comb.and %slots_14.io_request, %650 : i1
    %652 = comb.or %609, %610 : i1
    %653 = comb.xor %652, %true : i1
    %654 = comb.and %651, %653 : i1
    %655 = comb.or %648, %654 : i1
    %656 = comb.or %641, %655 : i1
    %657 = comb.xor %656, %true : i1
    %658 = comb.and %slots_14.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_59"} : i10
    %659 = comb.icmp ne %658, %c0_i10 {sv.namehint = "_can_allocate_59"} : i10
    %can_allocate_59 = sv.wire sym @can_allocate_59  : !hw.inout<i1>
    sv.assign %can_allocate_59, %659 : i1
    %660 = comb.and %slots_14.io_request, %657, %659 : i1
    %661 = comb.or %618, %627 : i1
    %662 = comb.xor %661, %true : i1
    %663 = comb.and %660, %662 : i1
    %664 = comb.xor %655, %true : i1
    %665 = comb.and %slots_14.io_request, %664, %638 : i1
    %666 = comb.and %665, %640 : i1
    %667 = comb.xor %654, %true : i1
    %668 = comb.and %slots_14.io_request, %667, %645 : i1
    %669 = comb.and %668, %647 : i1
    %670 = comb.or %663, %666, %669, %654 {sv.namehint = "_issue_slots_14_grant"} : i1
    %issue_slots_14_grant = sv.wire sym @issue_slots_14_grant  : !hw.inout<i1>
    sv.assign %issue_slots_14_grant, %670 : i1
    %671 = comb.concat %false, %636 : i1, i1
    %672 = comb.concat %false, %670 : i1, i1
    %673 = comb.xor %626, %true : i1
    %674 = comb.and %625, %673 : i1
    %675 = comb.and %593, %619 : i1
    %676 = comb.and %603, %581 : i1
    %677 = comb.or %674, %675, %676, %588 {sv.namehint = "_issue_slots_12_grant"} : i1
    %issue_slots_12_grant = sv.wire sym @issue_slots_12_grant  : !hw.inout<i1>
    sv.assign %issue_slots_12_grant, %677 : i1
    %678 = comb.concat %false, %677 : i1, i1
    %679 = comb.add %678, %671, %672 : i2
    %680 = comb.concat %false, %573 : i1, i2
    %681 = comb.concat %false, %679 : i1, i2
    %682 = comb.add %680, %681 : i3
    %issue_slots_15_request = sv.wire sym @issue_slots_15_request  : !hw.inout<i1>
    sv.assign %issue_slots_15_request, %slots_15.io_request : i1
    %issue_slots_15_uop_fu_code = sv.wire sym @issue_slots_15_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_15_uop_fu_code, %slots_15.io_uop_fu_code : i10
    %683 = comb.and %slots_15.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_62"} : i10
    %684 = comb.icmp ne %683, %c0_i10 {sv.namehint = "_can_allocate_62"} : i10
    %can_allocate_62 = sv.wire sym @can_allocate_62  : !hw.inout<i1>
    sv.assign %can_allocate_62, %684 : i1
    %685 = comb.or %665, %639 : i1
    %686 = comb.xor %685, %true : i1
    %687 = comb.and %slots_15.io_request, %684, %686 : i1
    %688 = comb.extract %slots_15.io_uop_fu_code from 0 : (i10) -> i1
    %689 = comb.extract %slots_15.io_uop_fu_code from 5 : (i10) -> i1
    %690 = comb.concat %689, %688 : i1, i1
    %691 = comb.icmp ne %690, %c0_i2 : i2
    %can_allocate_61 = sv.wire sym @can_allocate_61  : !hw.inout<i1>
    sv.assign %can_allocate_61, %691 : i1
    %692 = comb.or %668, %646 : i1
    %693 = comb.xor %692, %true : i1
    %694 = comb.and %slots_15.io_request, %691, %693 : i1
    %695 = comb.and %slots_15.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_60"} : i10
    %696 = comb.icmp ne %695, %c0_i10 {sv.namehint = "_can_allocate_60"} : i10
    %can_allocate_60 = sv.wire sym @can_allocate_60  : !hw.inout<i1>
    sv.assign %can_allocate_60, %696 : i1
    %697 = comb.and %slots_15.io_request, %696 : i1
    %698 = comb.or %651, %652 : i1
    %699 = comb.xor %698, %true : i1
    %700 = comb.and %697, %699 : i1
    %701 = comb.or %694, %700 : i1
    %702 = comb.or %687, %701 : i1
    %703 = comb.xor %702, %true : i1
    %704 = comb.and %slots_15.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_63"} : i10
    %705 = comb.icmp ne %704, %c0_i10 {sv.namehint = "_can_allocate_63"} : i10
    %can_allocate_63 = sv.wire sym @can_allocate_63  : !hw.inout<i1>
    sv.assign %can_allocate_63, %705 : i1
    %706 = comb.and %slots_15.io_request, %703, %705 : i1
    %707 = comb.or %660, %661 : i1
    %708 = comb.xor %707, %true : i1
    %709 = comb.and %706, %708 : i1
    %710 = comb.xor %701, %true : i1
    %711 = comb.and %slots_15.io_request, %710, %684 : i1
    %712 = comb.and %711, %686 : i1
    %713 = comb.xor %700, %true : i1
    %714 = comb.and %slots_15.io_request, %713, %691 : i1
    %715 = comb.and %714, %693 : i1
    %716 = comb.or %709, %712, %715, %700 {sv.namehint = "_issue_slots_15_grant"} : i1
    %issue_slots_15_grant = sv.wire sym @issue_slots_15_grant  : !hw.inout<i1>
    sv.assign %issue_slots_15_grant, %716 : i1
    %issue_slots_16_request = sv.wire sym @issue_slots_16_request  : !hw.inout<i1>
    sv.assign %issue_slots_16_request, %slots_16.io_request : i1
    %issue_slots_16_uop_fu_code = sv.wire sym @issue_slots_16_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_16_uop_fu_code, %slots_16.io_uop_fu_code : i10
    %717 = comb.and %slots_16.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_66"} : i10
    %718 = comb.icmp ne %717, %c0_i10 {sv.namehint = "_can_allocate_66"} : i10
    %can_allocate_66 = sv.wire sym @can_allocate_66  : !hw.inout<i1>
    sv.assign %can_allocate_66, %718 : i1
    %719 = comb.or %711, %685 : i1
    %720 = comb.xor %719, %true : i1
    %721 = comb.and %slots_16.io_request, %718, %720 : i1
    %722 = comb.extract %slots_16.io_uop_fu_code from 0 : (i10) -> i1
    %723 = comb.extract %slots_16.io_uop_fu_code from 5 : (i10) -> i1
    %724 = comb.concat %723, %722 : i1, i1
    %725 = comb.icmp ne %724, %c0_i2 : i2
    %can_allocate_65 = sv.wire sym @can_allocate_65  : !hw.inout<i1>
    sv.assign %can_allocate_65, %725 : i1
    %726 = comb.or %714, %692 : i1
    %727 = comb.xor %726, %true : i1
    %728 = comb.and %slots_16.io_request, %725, %727 : i1
    %729 = comb.and %slots_16.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_64"} : i10
    %730 = comb.icmp ne %729, %c0_i10 {sv.namehint = "_can_allocate_64"} : i10
    %can_allocate_64 = sv.wire sym @can_allocate_64  : !hw.inout<i1>
    sv.assign %can_allocate_64, %730 : i1
    %731 = comb.and %slots_16.io_request, %730 : i1
    %732 = comb.or %697, %698 : i1
    %733 = comb.xor %732, %true : i1
    %734 = comb.and %731, %733 : i1
    %735 = comb.or %728, %734 : i1
    %736 = comb.or %721, %735 : i1
    %737 = comb.xor %736, %true : i1
    %738 = comb.and %slots_16.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_67"} : i10
    %739 = comb.icmp ne %738, %c0_i10 {sv.namehint = "_can_allocate_67"} : i10
    %can_allocate_67 = sv.wire sym @can_allocate_67  : !hw.inout<i1>
    sv.assign %can_allocate_67, %739 : i1
    %740 = comb.and %slots_16.io_request, %737, %739 : i1
    %741 = comb.or %706, %707 : i1
    %742 = comb.xor %741, %true : i1
    %743 = comb.and %740, %742 : i1
    %744 = comb.xor %735, %true : i1
    %745 = comb.and %slots_16.io_request, %744, %718 : i1
    %746 = comb.and %745, %720 : i1
    %747 = comb.xor %734, %true : i1
    %748 = comb.and %slots_16.io_request, %747, %725 : i1
    %749 = comb.and %748, %727 : i1
    %750 = comb.or %743, %746, %749, %734 {sv.namehint = "_issue_slots_16_grant"} : i1
    %issue_slots_16_grant = sv.wire sym @issue_slots_16_grant  : !hw.inout<i1>
    sv.assign %issue_slots_16_grant, %750 : i1
    %751 = comb.concat %false, %716 : i1, i1
    %752 = comb.concat %false, %750 : i1, i1
    %753 = comb.add %751, %752 : i2
    %issue_slots_18_request = sv.wire sym @issue_slots_18_request  : !hw.inout<i1>
    sv.assign %issue_slots_18_request, %slots_18.io_request : i1
    %issue_slots_18_uop_fu_code = sv.wire sym @issue_slots_18_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_18_uop_fu_code, %slots_18.io_uop_fu_code : i10
    %754 = comb.and %slots_18.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_74"} : i10
    %755 = comb.icmp ne %754, %c0_i10 {sv.namehint = "_can_allocate_74"} : i10
    %can_allocate_74 = sv.wire sym @can_allocate_74  : !hw.inout<i1>
    sv.assign %can_allocate_74, %755 : i1
    %issue_slots_17_request = sv.wire sym @issue_slots_17_request  : !hw.inout<i1>
    sv.assign %issue_slots_17_request, %slots_17.io_request : i1
    %issue_slots_17_uop_fu_code = sv.wire sym @issue_slots_17_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_17_uop_fu_code, %slots_17.io_uop_fu_code : i10
    %756 = comb.extract %slots_17.io_uop_fu_code from 0 : (i10) -> i1
    %757 = comb.extract %slots_17.io_uop_fu_code from 5 : (i10) -> i1
    %758 = comb.concat %757, %756 : i1, i1
    %759 = comb.icmp ne %758, %c0_i2 : i2
    %can_allocate_69 = sv.wire sym @can_allocate_69  : !hw.inout<i1>
    sv.assign %can_allocate_69, %759 : i1
    %760 = comb.or %748, %726 : i1
    %761 = comb.xor %760, %true : i1
    %762 = comb.and %slots_17.io_request, %759, %761 : i1
    %763 = comb.and %slots_17.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_68"} : i10
    %764 = comb.icmp ne %763, %c0_i10 {sv.namehint = "_can_allocate_68"} : i10
    %can_allocate_68 = sv.wire sym @can_allocate_68  : !hw.inout<i1>
    sv.assign %can_allocate_68, %764 : i1
    %765 = comb.and %slots_17.io_request, %764 : i1
    %766 = comb.or %731, %732 : i1
    %767 = comb.xor %766, %true : i1
    %768 = comb.and %765, %767 : i1
    %769 = comb.or %762, %768 : i1
    %770 = comb.xor %769, %true : i1
    %771 = comb.and %slots_17.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_70"} : i10
    %772 = comb.icmp ne %771, %c0_i10 {sv.namehint = "_can_allocate_70"} : i10
    %can_allocate_70 = sv.wire sym @can_allocate_70  : !hw.inout<i1>
    sv.assign %can_allocate_70, %772 : i1
    %773 = comb.and %slots_17.io_request, %770, %772 : i1
    %774 = comb.or %745, %719 : i1
    %775 = comb.or %773, %774 : i1
    %776 = comb.xor %775, %true : i1
    %777 = comb.and %slots_18.io_request, %755, %776 : i1
    %778 = comb.extract %slots_18.io_uop_fu_code from 0 : (i10) -> i1
    %779 = comb.extract %slots_18.io_uop_fu_code from 5 : (i10) -> i1
    %780 = comb.concat %779, %778 : i1, i1
    %781 = comb.icmp ne %780, %c0_i2 : i2
    %can_allocate_73 = sv.wire sym @can_allocate_73  : !hw.inout<i1>
    sv.assign %can_allocate_73, %781 : i1
    %782 = comb.xor %768, %true : i1
    %783 = comb.and %slots_17.io_request, %782, %759 : i1
    %784 = comb.or %783, %760 : i1
    %785 = comb.xor %784, %true : i1
    %786 = comb.and %slots_18.io_request, %781, %785 : i1
    %787 = comb.and %slots_18.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_72"} : i10
    %788 = comb.icmp ne %787, %c0_i10 {sv.namehint = "_can_allocate_72"} : i10
    %can_allocate_72 = sv.wire sym @can_allocate_72  : !hw.inout<i1>
    sv.assign %can_allocate_72, %788 : i1
    %789 = comb.and %slots_18.io_request, %788 : i1
    %790 = comb.or %765, %766 : i1
    %791 = comb.xor %790, %true : i1
    %792 = comb.and %789, %791 : i1
    %793 = comb.or %786, %792 : i1
    %794 = comb.or %777, %793 : i1
    %795 = comb.xor %794, %true : i1
    %796 = comb.and %slots_18.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_75"} : i10
    %797 = comb.icmp ne %796, %c0_i10 {sv.namehint = "_can_allocate_75"} : i10
    %can_allocate_75 = sv.wire sym @can_allocate_75  : !hw.inout<i1>
    sv.assign %can_allocate_75, %797 : i1
    %798 = comb.and %slots_18.io_request, %795, %797 : i1
    %799 = comb.xor %774, %true : i1
    %800 = comb.and %slots_17.io_request, %772, %799 : i1
    %801 = comb.or %800, %769 : i1
    %802 = comb.xor %801, %true : i1
    %803 = comb.and %slots_17.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_71"} : i10
    %804 = comb.icmp ne %803, %c0_i10 {sv.namehint = "_can_allocate_71"} : i10
    %can_allocate_71 = sv.wire sym @can_allocate_71  : !hw.inout<i1>
    sv.assign %can_allocate_71, %804 : i1
    %805 = comb.and %slots_17.io_request, %802, %804 : i1
    %806 = comb.or %740, %741 : i1
    %807 = comb.or %805, %806 : i1
    %808 = comb.xor %807, %true : i1
    %809 = comb.and %798, %808 : i1
    %810 = comb.xor %793, %true : i1
    %811 = comb.and %slots_18.io_request, %810, %755 : i1
    %812 = comb.and %811, %776 : i1
    %813 = comb.xor %792, %true : i1
    %814 = comb.and %slots_18.io_request, %813, %781 : i1
    %815 = comb.and %814, %785 : i1
    %816 = comb.or %809, %812, %815, %792 {sv.namehint = "_issue_slots_18_grant"} : i1
    %issue_slots_18_grant = sv.wire sym @issue_slots_18_grant  : !hw.inout<i1>
    sv.assign %issue_slots_18_grant, %816 : i1
    %issue_slots_19_request = sv.wire sym @issue_slots_19_request  : !hw.inout<i1>
    sv.assign %issue_slots_19_request, %slots_19.io_request : i1
    %issue_slots_19_uop_fu_code = sv.wire sym @issue_slots_19_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_19_uop_fu_code, %slots_19.io_uop_fu_code : i10
    %817 = comb.and %slots_19.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_78"} : i10
    %818 = comb.icmp ne %817, %c0_i10 {sv.namehint = "_can_allocate_78"} : i10
    %can_allocate_78 = sv.wire sym @can_allocate_78  : !hw.inout<i1>
    sv.assign %can_allocate_78, %818 : i1
    %819 = comb.or %811, %775 : i1
    %820 = comb.xor %819, %true : i1
    %821 = comb.and %slots_19.io_request, %818, %820 : i1
    %822 = comb.extract %slots_19.io_uop_fu_code from 0 : (i10) -> i1
    %823 = comb.extract %slots_19.io_uop_fu_code from 5 : (i10) -> i1
    %824 = comb.concat %823, %822 : i1, i1
    %825 = comb.icmp ne %824, %c0_i2 : i2
    %can_allocate_77 = sv.wire sym @can_allocate_77  : !hw.inout<i1>
    sv.assign %can_allocate_77, %825 : i1
    %826 = comb.or %814, %784 : i1
    %827 = comb.xor %826, %true : i1
    %828 = comb.and %slots_19.io_request, %825, %827 : i1
    %829 = comb.and %slots_19.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_76"} : i10
    %830 = comb.icmp ne %829, %c0_i10 {sv.namehint = "_can_allocate_76"} : i10
    %can_allocate_76 = sv.wire sym @can_allocate_76  : !hw.inout<i1>
    sv.assign %can_allocate_76, %830 : i1
    %831 = comb.and %slots_19.io_request, %830 : i1
    %832 = comb.or %789, %790 : i1
    %833 = comb.xor %832, %true : i1
    %834 = comb.and %831, %833 : i1
    %835 = comb.or %828, %834 : i1
    %836 = comb.or %821, %835 : i1
    %837 = comb.xor %836, %true : i1
    %838 = comb.and %slots_19.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_79"} : i10
    %839 = comb.icmp ne %838, %c0_i10 {sv.namehint = "_can_allocate_79"} : i10
    %can_allocate_79 = sv.wire sym @can_allocate_79  : !hw.inout<i1>
    sv.assign %can_allocate_79, %839 : i1
    %840 = comb.and %slots_19.io_request, %837, %839 : i1
    %841 = comb.or %798, %807 : i1
    %842 = comb.xor %841, %true : i1
    %843 = comb.and %840, %842 : i1
    %844 = comb.xor %835, %true : i1
    %845 = comb.and %slots_19.io_request, %844, %818 : i1
    %846 = comb.and %845, %820 : i1
    %847 = comb.xor %834, %true : i1
    %848 = comb.and %slots_19.io_request, %847, %825 : i1
    %849 = comb.and %848, %827 : i1
    %850 = comb.or %843, %846, %849, %834 {sv.namehint = "_issue_slots_19_grant"} : i1
    %issue_slots_19_grant = sv.wire sym @issue_slots_19_grant  : !hw.inout<i1>
    sv.assign %issue_slots_19_grant, %850 : i1
    %851 = comb.concat %false, %816 : i1, i1
    %852 = comb.concat %false, %850 : i1, i1
    %853 = comb.xor %806, %true : i1
    %854 = comb.and %805, %853 : i1
    %855 = comb.and %773, %799 : i1
    %856 = comb.and %783, %761 : i1
    %857 = comb.or %854, %855, %856, %768 {sv.namehint = "_issue_slots_17_grant"} : i1
    %issue_slots_17_grant = sv.wire sym @issue_slots_17_grant  : !hw.inout<i1>
    sv.assign %issue_slots_17_grant, %857 : i1
    %858 = comb.concat %false, %857 : i1, i1
    %859 = comb.add %858, %851, %852 : i2
    %860 = comb.concat %false, %753 : i1, i2
    %861 = comb.concat %false, %859 : i1, i2
    %862 = comb.add %860, %861 : i3
    %863 = comb.concat %false, %682 : i1, i3
    %864 = comb.concat %false, %862 : i1, i3
    %865 = comb.add %863, %864 : i4
    %866 = comb.concat %false, %502 : i1, i4
    %867 = comb.concat %false, %865 : i1, i4
    %868 = comb.add %866, %867 : i5
    %issue_slots_20_request = sv.wire sym @issue_slots_20_request  : !hw.inout<i1>
    sv.assign %issue_slots_20_request, %slots_20.io_request : i1
    %issue_slots_20_uop_fu_code = sv.wire sym @issue_slots_20_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_20_uop_fu_code, %slots_20.io_uop_fu_code : i10
    %869 = comb.and %slots_20.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_82"} : i10
    %870 = comb.icmp ne %869, %c0_i10 {sv.namehint = "_can_allocate_82"} : i10
    %can_allocate_82 = sv.wire sym @can_allocate_82  : !hw.inout<i1>
    sv.assign %can_allocate_82, %870 : i1
    %871 = comb.or %845, %819 : i1
    %872 = comb.xor %871, %true : i1
    %873 = comb.and %slots_20.io_request, %870, %872 : i1
    %874 = comb.extract %slots_20.io_uop_fu_code from 0 : (i10) -> i1
    %875 = comb.extract %slots_20.io_uop_fu_code from 5 : (i10) -> i1
    %876 = comb.concat %875, %874 : i1, i1
    %877 = comb.icmp ne %876, %c0_i2 : i2
    %can_allocate_81 = sv.wire sym @can_allocate_81  : !hw.inout<i1>
    sv.assign %can_allocate_81, %877 : i1
    %878 = comb.or %848, %826 : i1
    %879 = comb.xor %878, %true : i1
    %880 = comb.and %slots_20.io_request, %877, %879 : i1
    %881 = comb.and %slots_20.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_80"} : i10
    %882 = comb.icmp ne %881, %c0_i10 {sv.namehint = "_can_allocate_80"} : i10
    %can_allocate_80 = sv.wire sym @can_allocate_80  : !hw.inout<i1>
    sv.assign %can_allocate_80, %882 : i1
    %883 = comb.and %slots_20.io_request, %882 : i1
    %884 = comb.or %831, %832 : i1
    %885 = comb.xor %884, %true : i1
    %886 = comb.and %883, %885 : i1
    %887 = comb.or %880, %886 : i1
    %888 = comb.or %873, %887 : i1
    %889 = comb.xor %888, %true : i1
    %890 = comb.and %slots_20.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_83"} : i10
    %891 = comb.icmp ne %890, %c0_i10 {sv.namehint = "_can_allocate_83"} : i10
    %can_allocate_83 = sv.wire sym @can_allocate_83  : !hw.inout<i1>
    sv.assign %can_allocate_83, %891 : i1
    %892 = comb.and %slots_20.io_request, %889, %891 : i1
    %893 = comb.or %840, %841 : i1
    %894 = comb.xor %893, %true : i1
    %895 = comb.and %892, %894 : i1
    %896 = comb.xor %887, %true : i1
    %897 = comb.and %slots_20.io_request, %896, %870 : i1
    %898 = comb.and %897, %872 : i1
    %899 = comb.xor %886, %true : i1
    %900 = comb.and %slots_20.io_request, %899, %877 : i1
    %901 = comb.and %900, %879 : i1
    %902 = comb.or %895, %898, %901, %886 {sv.namehint = "_issue_slots_20_grant"} : i1
    %issue_slots_20_grant = sv.wire sym @issue_slots_20_grant  : !hw.inout<i1>
    sv.assign %issue_slots_20_grant, %902 : i1
    %issue_slots_21_request = sv.wire sym @issue_slots_21_request  : !hw.inout<i1>
    sv.assign %issue_slots_21_request, %slots_21.io_request : i1
    %issue_slots_21_uop_fu_code = sv.wire sym @issue_slots_21_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_21_uop_fu_code, %slots_21.io_uop_fu_code : i10
    %903 = comb.and %slots_21.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_86"} : i10
    %904 = comb.icmp ne %903, %c0_i10 {sv.namehint = "_can_allocate_86"} : i10
    %can_allocate_86 = sv.wire sym @can_allocate_86  : !hw.inout<i1>
    sv.assign %can_allocate_86, %904 : i1
    %905 = comb.or %897, %871 : i1
    %906 = comb.xor %905, %true : i1
    %907 = comb.and %slots_21.io_request, %904, %906 : i1
    %908 = comb.extract %slots_21.io_uop_fu_code from 0 : (i10) -> i1
    %909 = comb.extract %slots_21.io_uop_fu_code from 5 : (i10) -> i1
    %910 = comb.concat %909, %908 : i1, i1
    %911 = comb.icmp ne %910, %c0_i2 : i2
    %can_allocate_85 = sv.wire sym @can_allocate_85  : !hw.inout<i1>
    sv.assign %can_allocate_85, %911 : i1
    %912 = comb.or %900, %878 : i1
    %913 = comb.xor %912, %true : i1
    %914 = comb.and %slots_21.io_request, %911, %913 : i1
    %915 = comb.and %slots_21.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_84"} : i10
    %916 = comb.icmp ne %915, %c0_i10 {sv.namehint = "_can_allocate_84"} : i10
    %can_allocate_84 = sv.wire sym @can_allocate_84  : !hw.inout<i1>
    sv.assign %can_allocate_84, %916 : i1
    %917 = comb.and %slots_21.io_request, %916 : i1
    %918 = comb.or %883, %884 : i1
    %919 = comb.xor %918, %true : i1
    %920 = comb.and %917, %919 : i1
    %921 = comb.or %914, %920 : i1
    %922 = comb.or %907, %921 : i1
    %923 = comb.xor %922, %true : i1
    %924 = comb.and %slots_21.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_87"} : i10
    %925 = comb.icmp ne %924, %c0_i10 {sv.namehint = "_can_allocate_87"} : i10
    %can_allocate_87 = sv.wire sym @can_allocate_87  : !hw.inout<i1>
    sv.assign %can_allocate_87, %925 : i1
    %926 = comb.and %slots_21.io_request, %923, %925 : i1
    %927 = comb.or %892, %893 : i1
    %928 = comb.xor %927, %true : i1
    %929 = comb.and %926, %928 : i1
    %930 = comb.xor %921, %true : i1
    %931 = comb.and %slots_21.io_request, %930, %904 : i1
    %932 = comb.and %931, %906 : i1
    %933 = comb.xor %920, %true : i1
    %934 = comb.and %slots_21.io_request, %933, %911 : i1
    %935 = comb.and %934, %913 : i1
    %936 = comb.or %929, %932, %935, %920 {sv.namehint = "_issue_slots_21_grant"} : i1
    %issue_slots_21_grant = sv.wire sym @issue_slots_21_grant  : !hw.inout<i1>
    sv.assign %issue_slots_21_grant, %936 : i1
    %937 = comb.concat %false, %902 : i1, i1
    %938 = comb.concat %false, %936 : i1, i1
    %939 = comb.add %937, %938 : i2
    %issue_slots_23_request = sv.wire sym @issue_slots_23_request  : !hw.inout<i1>
    sv.assign %issue_slots_23_request, %slots_23.io_request : i1
    %issue_slots_23_uop_fu_code = sv.wire sym @issue_slots_23_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_23_uop_fu_code, %slots_23.io_uop_fu_code : i10
    %940 = comb.and %slots_23.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_94"} : i10
    %941 = comb.icmp ne %940, %c0_i10 {sv.namehint = "_can_allocate_94"} : i10
    %can_allocate_94 = sv.wire sym @can_allocate_94  : !hw.inout<i1>
    sv.assign %can_allocate_94, %941 : i1
    %issue_slots_22_request = sv.wire sym @issue_slots_22_request  : !hw.inout<i1>
    sv.assign %issue_slots_22_request, %slots_22.io_request : i1
    %issue_slots_22_uop_fu_code = sv.wire sym @issue_slots_22_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_22_uop_fu_code, %slots_22.io_uop_fu_code : i10
    %942 = comb.extract %slots_22.io_uop_fu_code from 0 : (i10) -> i1
    %943 = comb.extract %slots_22.io_uop_fu_code from 5 : (i10) -> i1
    %944 = comb.concat %943, %942 : i1, i1
    %945 = comb.icmp ne %944, %c0_i2 : i2
    %can_allocate_89 = sv.wire sym @can_allocate_89  : !hw.inout<i1>
    sv.assign %can_allocate_89, %945 : i1
    %946 = comb.or %934, %912 : i1
    %947 = comb.xor %946, %true : i1
    %948 = comb.and %slots_22.io_request, %945, %947 : i1
    %949 = comb.and %slots_22.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_88"} : i10
    %950 = comb.icmp ne %949, %c0_i10 {sv.namehint = "_can_allocate_88"} : i10
    %can_allocate_88 = sv.wire sym @can_allocate_88  : !hw.inout<i1>
    sv.assign %can_allocate_88, %950 : i1
    %951 = comb.and %slots_22.io_request, %950 : i1
    %952 = comb.or %917, %918 : i1
    %953 = comb.xor %952, %true : i1
    %954 = comb.and %951, %953 : i1
    %955 = comb.or %948, %954 : i1
    %956 = comb.xor %955, %true : i1
    %957 = comb.and %slots_22.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_90"} : i10
    %958 = comb.icmp ne %957, %c0_i10 {sv.namehint = "_can_allocate_90"} : i10
    %can_allocate_90 = sv.wire sym @can_allocate_90  : !hw.inout<i1>
    sv.assign %can_allocate_90, %958 : i1
    %959 = comb.and %slots_22.io_request, %956, %958 : i1
    %960 = comb.or %931, %905 : i1
    %961 = comb.or %959, %960 : i1
    %962 = comb.xor %961, %true : i1
    %963 = comb.and %slots_23.io_request, %941, %962 : i1
    %964 = comb.extract %slots_23.io_uop_fu_code from 0 : (i10) -> i1
    %965 = comb.extract %slots_23.io_uop_fu_code from 5 : (i10) -> i1
    %966 = comb.concat %965, %964 : i1, i1
    %967 = comb.icmp ne %966, %c0_i2 : i2
    %can_allocate_93 = sv.wire sym @can_allocate_93  : !hw.inout<i1>
    sv.assign %can_allocate_93, %967 : i1
    %968 = comb.xor %954, %true : i1
    %969 = comb.and %slots_22.io_request, %968, %945 : i1
    %970 = comb.or %969, %946 : i1
    %971 = comb.xor %970, %true : i1
    %972 = comb.and %slots_23.io_request, %967, %971 : i1
    %973 = comb.and %slots_23.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_92"} : i10
    %974 = comb.icmp ne %973, %c0_i10 {sv.namehint = "_can_allocate_92"} : i10
    %can_allocate_92 = sv.wire sym @can_allocate_92  : !hw.inout<i1>
    sv.assign %can_allocate_92, %974 : i1
    %975 = comb.and %slots_23.io_request, %974 : i1
    %976 = comb.or %951, %952 : i1
    %977 = comb.xor %976, %true : i1
    %978 = comb.and %975, %977 : i1
    %979 = comb.or %972, %978 : i1
    %980 = comb.or %963, %979 : i1
    %981 = comb.xor %980, %true : i1
    %982 = comb.and %slots_23.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_95"} : i10
    %983 = comb.icmp ne %982, %c0_i10 {sv.namehint = "_can_allocate_95"} : i10
    %can_allocate_95 = sv.wire sym @can_allocate_95  : !hw.inout<i1>
    sv.assign %can_allocate_95, %983 : i1
    %984 = comb.and %slots_23.io_request, %981, %983 : i1
    %985 = comb.xor %960, %true : i1
    %986 = comb.and %slots_22.io_request, %958, %985 : i1
    %987 = comb.or %986, %955 : i1
    %988 = comb.xor %987, %true : i1
    %989 = comb.and %slots_22.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_91"} : i10
    %990 = comb.icmp ne %989, %c0_i10 {sv.namehint = "_can_allocate_91"} : i10
    %can_allocate_91 = sv.wire sym @can_allocate_91  : !hw.inout<i1>
    sv.assign %can_allocate_91, %990 : i1
    %991 = comb.and %slots_22.io_request, %988, %990 : i1
    %992 = comb.or %926, %927 : i1
    %993 = comb.or %991, %992 : i1
    %994 = comb.xor %993, %true : i1
    %995 = comb.and %984, %994 : i1
    %996 = comb.xor %979, %true : i1
    %997 = comb.and %slots_23.io_request, %996, %941 : i1
    %998 = comb.and %997, %962 : i1
    %999 = comb.xor %978, %true : i1
    %1000 = comb.and %slots_23.io_request, %999, %967 : i1
    %1001 = comb.and %1000, %971 : i1
    %1002 = comb.or %995, %998, %1001, %978 {sv.namehint = "_issue_slots_23_grant"} : i1
    %issue_slots_23_grant = sv.wire sym @issue_slots_23_grant  : !hw.inout<i1>
    sv.assign %issue_slots_23_grant, %1002 : i1
    %issue_slots_24_request = sv.wire sym @issue_slots_24_request  : !hw.inout<i1>
    sv.assign %issue_slots_24_request, %slots_24.io_request : i1
    %issue_slots_24_uop_fu_code = sv.wire sym @issue_slots_24_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_24_uop_fu_code, %slots_24.io_uop_fu_code : i10
    %1003 = comb.and %slots_24.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_98"} : i10
    %1004 = comb.icmp ne %1003, %c0_i10 {sv.namehint = "_can_allocate_98"} : i10
    %can_allocate_98 = sv.wire sym @can_allocate_98  : !hw.inout<i1>
    sv.assign %can_allocate_98, %1004 : i1
    %1005 = comb.or %997, %961 : i1
    %1006 = comb.xor %1005, %true : i1
    %1007 = comb.and %slots_24.io_request, %1004, %1006 : i1
    %1008 = comb.extract %slots_24.io_uop_fu_code from 0 : (i10) -> i1
    %1009 = comb.extract %slots_24.io_uop_fu_code from 5 : (i10) -> i1
    %1010 = comb.concat %1009, %1008 : i1, i1
    %1011 = comb.icmp ne %1010, %c0_i2 : i2
    %can_allocate_97 = sv.wire sym @can_allocate_97  : !hw.inout<i1>
    sv.assign %can_allocate_97, %1011 : i1
    %1012 = comb.or %1000, %970 : i1
    %1013 = comb.xor %1012, %true : i1
    %1014 = comb.and %slots_24.io_request, %1011, %1013 : i1
    %1015 = comb.and %slots_24.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_96"} : i10
    %1016 = comb.icmp ne %1015, %c0_i10 {sv.namehint = "_can_allocate_96"} : i10
    %can_allocate_96 = sv.wire sym @can_allocate_96  : !hw.inout<i1>
    sv.assign %can_allocate_96, %1016 : i1
    %1017 = comb.and %slots_24.io_request, %1016 : i1
    %1018 = comb.or %975, %976 : i1
    %1019 = comb.xor %1018, %true : i1
    %1020 = comb.and %1017, %1019 : i1
    %1021 = comb.or %1014, %1020 : i1
    %1022 = comb.or %1007, %1021 : i1
    %1023 = comb.xor %1022, %true : i1
    %1024 = comb.and %slots_24.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_99"} : i10
    %1025 = comb.icmp ne %1024, %c0_i10 {sv.namehint = "_can_allocate_99"} : i10
    %can_allocate_99 = sv.wire sym @can_allocate_99  : !hw.inout<i1>
    sv.assign %can_allocate_99, %1025 : i1
    %1026 = comb.and %slots_24.io_request, %1023, %1025 : i1
    %1027 = comb.or %984, %993 : i1
    %1028 = comb.xor %1027, %true : i1
    %1029 = comb.and %1026, %1028 : i1
    %1030 = comb.xor %1021, %true : i1
    %1031 = comb.and %slots_24.io_request, %1030, %1004 : i1
    %1032 = comb.and %1031, %1006 : i1
    %1033 = comb.xor %1020, %true : i1
    %1034 = comb.and %slots_24.io_request, %1033, %1011 : i1
    %1035 = comb.and %1034, %1013 : i1
    %1036 = comb.or %1029, %1032, %1035, %1020 {sv.namehint = "_issue_slots_24_grant"} : i1
    %issue_slots_24_grant = sv.wire sym @issue_slots_24_grant  : !hw.inout<i1>
    sv.assign %issue_slots_24_grant, %1036 : i1
    %1037 = comb.concat %false, %1002 : i1, i1
    %1038 = comb.concat %false, %1036 : i1, i1
    %1039 = comb.xor %992, %true : i1
    %1040 = comb.and %991, %1039 : i1
    %1041 = comb.and %959, %985 : i1
    %1042 = comb.and %969, %947 : i1
    %1043 = comb.or %1040, %1041, %1042, %954 {sv.namehint = "_issue_slots_22_grant"} : i1
    %issue_slots_22_grant = sv.wire sym @issue_slots_22_grant  : !hw.inout<i1>
    sv.assign %issue_slots_22_grant, %1043 : i1
    %1044 = comb.concat %false, %1043 : i1, i1
    %1045 = comb.add %1044, %1037, %1038 : i2
    %1046 = comb.concat %false, %939 : i1, i2
    %1047 = comb.concat %false, %1045 : i1, i2
    %1048 = comb.add %1046, %1047 : i3
    %issue_slots_25_request = sv.wire sym @issue_slots_25_request  : !hw.inout<i1>
    sv.assign %issue_slots_25_request, %slots_25.io_request : i1
    %issue_slots_25_uop_fu_code = sv.wire sym @issue_slots_25_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_25_uop_fu_code, %slots_25.io_uop_fu_code : i10
    %1049 = comb.and %slots_25.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_102"} : i10
    %1050 = comb.icmp ne %1049, %c0_i10 {sv.namehint = "_can_allocate_102"} : i10
    %can_allocate_102 = sv.wire sym @can_allocate_102  : !hw.inout<i1>
    sv.assign %can_allocate_102, %1050 : i1
    %1051 = comb.or %1031, %1005 : i1
    %1052 = comb.xor %1051, %true : i1
    %1053 = comb.and %slots_25.io_request, %1050, %1052 : i1
    %1054 = comb.extract %slots_25.io_uop_fu_code from 0 : (i10) -> i1
    %1055 = comb.extract %slots_25.io_uop_fu_code from 5 : (i10) -> i1
    %1056 = comb.concat %1055, %1054 : i1, i1
    %1057 = comb.icmp ne %1056, %c0_i2 : i2
    %can_allocate_101 = sv.wire sym @can_allocate_101  : !hw.inout<i1>
    sv.assign %can_allocate_101, %1057 : i1
    %1058 = comb.or %1034, %1012 : i1
    %1059 = comb.xor %1058, %true : i1
    %1060 = comb.and %slots_25.io_request, %1057, %1059 : i1
    %1061 = comb.and %slots_25.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_100"} : i10
    %1062 = comb.icmp ne %1061, %c0_i10 {sv.namehint = "_can_allocate_100"} : i10
    %can_allocate_100 = sv.wire sym @can_allocate_100  : !hw.inout<i1>
    sv.assign %can_allocate_100, %1062 : i1
    %1063 = comb.and %slots_25.io_request, %1062 : i1
    %1064 = comb.or %1017, %1018 : i1
    %1065 = comb.xor %1064, %true : i1
    %1066 = comb.and %1063, %1065 : i1
    %1067 = comb.or %1060, %1066 : i1
    %1068 = comb.or %1053, %1067 : i1
    %1069 = comb.xor %1068, %true : i1
    %1070 = comb.and %slots_25.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_103"} : i10
    %1071 = comb.icmp ne %1070, %c0_i10 {sv.namehint = "_can_allocate_103"} : i10
    %can_allocate_103 = sv.wire sym @can_allocate_103  : !hw.inout<i1>
    sv.assign %can_allocate_103, %1071 : i1
    %1072 = comb.and %slots_25.io_request, %1069, %1071 : i1
    %1073 = comb.or %1026, %1027 : i1
    %1074 = comb.xor %1073, %true : i1
    %1075 = comb.and %1072, %1074 : i1
    %1076 = comb.xor %1067, %true : i1
    %1077 = comb.and %slots_25.io_request, %1076, %1050 : i1
    %1078 = comb.and %1077, %1052 : i1
    %1079 = comb.xor %1066, %true : i1
    %1080 = comb.and %slots_25.io_request, %1079, %1057 : i1
    %1081 = comb.and %1080, %1059 : i1
    %1082 = comb.or %1075, %1078, %1081, %1066 {sv.namehint = "_issue_slots_25_grant"} : i1
    %issue_slots_25_grant = sv.wire sym @issue_slots_25_grant  : !hw.inout<i1>
    sv.assign %issue_slots_25_grant, %1082 : i1
    %issue_slots_26_request = sv.wire sym @issue_slots_26_request  : !hw.inout<i1>
    sv.assign %issue_slots_26_request, %slots_26.io_request : i1
    %issue_slots_26_uop_fu_code = sv.wire sym @issue_slots_26_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_26_uop_fu_code, %slots_26.io_uop_fu_code : i10
    %1083 = comb.and %slots_26.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_106"} : i10
    %1084 = comb.icmp ne %1083, %c0_i10 {sv.namehint = "_can_allocate_106"} : i10
    %can_allocate_106 = sv.wire sym @can_allocate_106  : !hw.inout<i1>
    sv.assign %can_allocate_106, %1084 : i1
    %1085 = comb.or %1077, %1051 : i1
    %1086 = comb.xor %1085, %true : i1
    %1087 = comb.and %slots_26.io_request, %1084, %1086 : i1
    %1088 = comb.extract %slots_26.io_uop_fu_code from 0 : (i10) -> i1
    %1089 = comb.extract %slots_26.io_uop_fu_code from 5 : (i10) -> i1
    %1090 = comb.concat %1089, %1088 : i1, i1
    %1091 = comb.icmp ne %1090, %c0_i2 : i2
    %can_allocate_105 = sv.wire sym @can_allocate_105  : !hw.inout<i1>
    sv.assign %can_allocate_105, %1091 : i1
    %1092 = comb.or %1080, %1058 : i1
    %1093 = comb.xor %1092, %true : i1
    %1094 = comb.and %slots_26.io_request, %1091, %1093 : i1
    %1095 = comb.and %slots_26.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_104"} : i10
    %1096 = comb.icmp ne %1095, %c0_i10 {sv.namehint = "_can_allocate_104"} : i10
    %can_allocate_104 = sv.wire sym @can_allocate_104  : !hw.inout<i1>
    sv.assign %can_allocate_104, %1096 : i1
    %1097 = comb.and %slots_26.io_request, %1096 : i1
    %1098 = comb.or %1063, %1064 : i1
    %1099 = comb.xor %1098, %true : i1
    %1100 = comb.and %1097, %1099 : i1
    %1101 = comb.or %1094, %1100 : i1
    %1102 = comb.or %1087, %1101 : i1
    %1103 = comb.xor %1102, %true : i1
    %1104 = comb.and %slots_26.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_107"} : i10
    %1105 = comb.icmp ne %1104, %c0_i10 {sv.namehint = "_can_allocate_107"} : i10
    %can_allocate_107 = sv.wire sym @can_allocate_107  : !hw.inout<i1>
    sv.assign %can_allocate_107, %1105 : i1
    %1106 = comb.and %slots_26.io_request, %1103, %1105 : i1
    %1107 = comb.or %1072, %1073 : i1
    %1108 = comb.xor %1107, %true : i1
    %1109 = comb.and %1106, %1108 : i1
    %1110 = comb.xor %1101, %true : i1
    %1111 = comb.and %slots_26.io_request, %1110, %1084 : i1
    %1112 = comb.and %1111, %1086 : i1
    %1113 = comb.xor %1100, %true : i1
    %1114 = comb.and %slots_26.io_request, %1113, %1091 : i1
    %1115 = comb.and %1114, %1093 : i1
    %1116 = comb.or %1109, %1112, %1115, %1100 {sv.namehint = "_issue_slots_26_grant"} : i1
    %issue_slots_26_grant = sv.wire sym @issue_slots_26_grant  : !hw.inout<i1>
    sv.assign %issue_slots_26_grant, %1116 : i1
    %1117 = comb.concat %false, %1082 : i1, i1
    %1118 = comb.concat %false, %1116 : i1, i1
    %1119 = comb.add %1117, %1118 : i2
    %issue_slots_28_request = sv.wire sym @issue_slots_28_request  : !hw.inout<i1>
    sv.assign %issue_slots_28_request, %slots_28.io_request : i1
    %issue_slots_28_uop_fu_code = sv.wire sym @issue_slots_28_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_28_uop_fu_code, %slots_28.io_uop_fu_code : i10
    %1120 = comb.and %slots_28.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_114"} : i10
    %1121 = comb.icmp ne %1120, %c0_i10 {sv.namehint = "_can_allocate_114"} : i10
    %can_allocate_114 = sv.wire sym @can_allocate_114  : !hw.inout<i1>
    sv.assign %can_allocate_114, %1121 : i1
    %issue_slots_27_request = sv.wire sym @issue_slots_27_request  : !hw.inout<i1>
    sv.assign %issue_slots_27_request, %slots_27.io_request : i1
    %issue_slots_27_uop_fu_code = sv.wire sym @issue_slots_27_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_27_uop_fu_code, %slots_27.io_uop_fu_code : i10
    %1122 = comb.extract %slots_27.io_uop_fu_code from 0 : (i10) -> i1
    %1123 = comb.extract %slots_27.io_uop_fu_code from 5 : (i10) -> i1
    %1124 = comb.concat %1123, %1122 : i1, i1
    %1125 = comb.icmp ne %1124, %c0_i2 : i2
    %can_allocate_109 = sv.wire sym @can_allocate_109  : !hw.inout<i1>
    sv.assign %can_allocate_109, %1125 : i1
    %1126 = comb.or %1114, %1092 : i1
    %1127 = comb.xor %1126, %true : i1
    %1128 = comb.and %slots_27.io_request, %1125, %1127 : i1
    %1129 = comb.and %slots_27.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_108"} : i10
    %1130 = comb.icmp ne %1129, %c0_i10 {sv.namehint = "_can_allocate_108"} : i10
    %can_allocate_108 = sv.wire sym @can_allocate_108  : !hw.inout<i1>
    sv.assign %can_allocate_108, %1130 : i1
    %1131 = comb.and %slots_27.io_request, %1130 : i1
    %1132 = comb.or %1097, %1098 : i1
    %1133 = comb.xor %1132, %true : i1
    %1134 = comb.and %1131, %1133 : i1
    %1135 = comb.or %1128, %1134 : i1
    %1136 = comb.xor %1135, %true : i1
    %1137 = comb.and %slots_27.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_110"} : i10
    %1138 = comb.icmp ne %1137, %c0_i10 {sv.namehint = "_can_allocate_110"} : i10
    %can_allocate_110 = sv.wire sym @can_allocate_110  : !hw.inout<i1>
    sv.assign %can_allocate_110, %1138 : i1
    %1139 = comb.and %slots_27.io_request, %1136, %1138 : i1
    %1140 = comb.or %1111, %1085 : i1
    %1141 = comb.or %1139, %1140 : i1
    %1142 = comb.xor %1141, %true : i1
    %1143 = comb.and %slots_28.io_request, %1121, %1142 : i1
    %1144 = comb.extract %slots_28.io_uop_fu_code from 0 : (i10) -> i1
    %1145 = comb.extract %slots_28.io_uop_fu_code from 5 : (i10) -> i1
    %1146 = comb.concat %1145, %1144 : i1, i1
    %1147 = comb.icmp ne %1146, %c0_i2 : i2
    %can_allocate_113 = sv.wire sym @can_allocate_113  : !hw.inout<i1>
    sv.assign %can_allocate_113, %1147 : i1
    %1148 = comb.xor %1134, %true : i1
    %1149 = comb.and %slots_27.io_request, %1148, %1125 : i1
    %1150 = comb.or %1149, %1126 : i1
    %1151 = comb.xor %1150, %true : i1
    %1152 = comb.and %slots_28.io_request, %1147, %1151 : i1
    %1153 = comb.and %slots_28.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_112"} : i10
    %1154 = comb.icmp ne %1153, %c0_i10 {sv.namehint = "_can_allocate_112"} : i10
    %can_allocate_112 = sv.wire sym @can_allocate_112  : !hw.inout<i1>
    sv.assign %can_allocate_112, %1154 : i1
    %1155 = comb.and %slots_28.io_request, %1154 : i1
    %1156 = comb.or %1131, %1132 : i1
    %1157 = comb.xor %1156, %true : i1
    %1158 = comb.and %1155, %1157 : i1
    %1159 = comb.or %1152, %1158 : i1
    %1160 = comb.or %1143, %1159 : i1
    %1161 = comb.xor %1160, %true : i1
    %1162 = comb.and %slots_28.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_115"} : i10
    %1163 = comb.icmp ne %1162, %c0_i10 {sv.namehint = "_can_allocate_115"} : i10
    %can_allocate_115 = sv.wire sym @can_allocate_115  : !hw.inout<i1>
    sv.assign %can_allocate_115, %1163 : i1
    %1164 = comb.and %slots_28.io_request, %1161, %1163 : i1
    %1165 = comb.xor %1140, %true : i1
    %1166 = comb.and %slots_27.io_request, %1138, %1165 : i1
    %1167 = comb.or %1166, %1135 : i1
    %1168 = comb.xor %1167, %true : i1
    %1169 = comb.and %slots_27.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_111"} : i10
    %1170 = comb.icmp ne %1169, %c0_i10 {sv.namehint = "_can_allocate_111"} : i10
    %can_allocate_111 = sv.wire sym @can_allocate_111  : !hw.inout<i1>
    sv.assign %can_allocate_111, %1170 : i1
    %1171 = comb.and %slots_27.io_request, %1168, %1170 : i1
    %1172 = comb.or %1106, %1107 : i1
    %1173 = comb.or %1171, %1172 : i1
    %1174 = comb.xor %1173, %true : i1
    %1175 = comb.and %1164, %1174 : i1
    %1176 = comb.xor %1159, %true : i1
    %1177 = comb.and %slots_28.io_request, %1176, %1121 : i1
    %1178 = comb.and %1177, %1142 : i1
    %1179 = comb.xor %1158, %true : i1
    %1180 = comb.and %slots_28.io_request, %1179, %1147 : i1
    %1181 = comb.and %1180, %1151 : i1
    %1182 = comb.or %1175, %1178, %1181, %1158 {sv.namehint = "_issue_slots_28_grant"} : i1
    %issue_slots_28_grant = sv.wire sym @issue_slots_28_grant  : !hw.inout<i1>
    sv.assign %issue_slots_28_grant, %1182 : i1
    %issue_slots_29_request = sv.wire sym @issue_slots_29_request  : !hw.inout<i1>
    sv.assign %issue_slots_29_request, %slots_29.io_request : i1
    %issue_slots_29_uop_fu_code = sv.wire sym @issue_slots_29_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_29_uop_fu_code, %slots_29.io_uop_fu_code : i10
    %1183 = comb.and %slots_29.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_118"} : i10
    %1184 = comb.icmp ne %1183, %c0_i10 {sv.namehint = "_can_allocate_118"} : i10
    %can_allocate_118 = sv.wire sym @can_allocate_118  : !hw.inout<i1>
    sv.assign %can_allocate_118, %1184 : i1
    %1185 = comb.or %1177, %1141 : i1
    %1186 = comb.xor %1185, %true : i1
    %1187 = comb.and %slots_29.io_request, %1184, %1186 : i1
    %1188 = comb.extract %slots_29.io_uop_fu_code from 0 : (i10) -> i1
    %1189 = comb.extract %slots_29.io_uop_fu_code from 5 : (i10) -> i1
    %1190 = comb.concat %1189, %1188 : i1, i1
    %1191 = comb.icmp ne %1190, %c0_i2 : i2
    %can_allocate_117 = sv.wire sym @can_allocate_117  : !hw.inout<i1>
    sv.assign %can_allocate_117, %1191 : i1
    %1192 = comb.or %1180, %1150 : i1
    %1193 = comb.xor %1192, %true : i1
    %1194 = comb.and %slots_29.io_request, %1191, %1193 : i1
    %1195 = comb.and %slots_29.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_116"} : i10
    %1196 = comb.icmp ne %1195, %c0_i10 {sv.namehint = "_can_allocate_116"} : i10
    %can_allocate_116 = sv.wire sym @can_allocate_116  : !hw.inout<i1>
    sv.assign %can_allocate_116, %1196 : i1
    %1197 = comb.and %slots_29.io_request, %1196 : i1
    %1198 = comb.or %1155, %1156 : i1
    %1199 = comb.xor %1198, %true : i1
    %1200 = comb.and %1197, %1199 : i1
    %1201 = comb.or %1194, %1200 : i1
    %1202 = comb.or %1187, %1201 : i1
    %1203 = comb.xor %1202, %true : i1
    %1204 = comb.and %slots_29.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_119"} : i10
    %1205 = comb.icmp ne %1204, %c0_i10 {sv.namehint = "_can_allocate_119"} : i10
    %can_allocate_119 = sv.wire sym @can_allocate_119  : !hw.inout<i1>
    sv.assign %can_allocate_119, %1205 : i1
    %1206 = comb.and %slots_29.io_request, %1203, %1205 : i1
    %1207 = comb.or %1164, %1173 : i1
    %1208 = comb.xor %1207, %true : i1
    %1209 = comb.and %1206, %1208 : i1
    %1210 = comb.xor %1201, %true : i1
    %1211 = comb.and %slots_29.io_request, %1210, %1184 : i1
    %1212 = comb.and %1211, %1186 : i1
    %1213 = comb.xor %1200, %true : i1
    %1214 = comb.and %slots_29.io_request, %1213, %1191 : i1
    %1215 = comb.and %1214, %1193 : i1
    %1216 = comb.or %1209, %1212, %1215, %1200 {sv.namehint = "_issue_slots_29_grant"} : i1
    %issue_slots_29_grant = sv.wire sym @issue_slots_29_grant  : !hw.inout<i1>
    sv.assign %issue_slots_29_grant, %1216 : i1
    %1217 = comb.concat %false, %1182 : i1, i1
    %1218 = comb.concat %false, %1216 : i1, i1
    %1219 = comb.xor %1172, %true : i1
    %1220 = comb.and %1171, %1219 : i1
    %1221 = comb.and %1139, %1165 : i1
    %1222 = comb.and %1149, %1127 : i1
    %1223 = comb.or %1220, %1221, %1222, %1134 {sv.namehint = "_issue_slots_27_grant"} : i1
    %issue_slots_27_grant = sv.wire sym @issue_slots_27_grant  : !hw.inout<i1>
    sv.assign %issue_slots_27_grant, %1223 : i1
    %1224 = comb.concat %false, %1223 : i1, i1
    %1225 = comb.add %1224, %1217, %1218 : i2
    %1226 = comb.concat %false, %1119 : i1, i2
    %1227 = comb.concat %false, %1225 : i1, i2
    %1228 = comb.add %1226, %1227 : i3
    %1229 = comb.concat %false, %1048 : i1, i3
    %1230 = comb.concat %false, %1228 : i1, i3
    %1231 = comb.add %1229, %1230 : i4
    %issue_slots_30_request = sv.wire sym @issue_slots_30_request  : !hw.inout<i1>
    sv.assign %issue_slots_30_request, %slots_30.io_request : i1
    %issue_slots_30_uop_fu_code = sv.wire sym @issue_slots_30_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_30_uop_fu_code, %slots_30.io_uop_fu_code : i10
    %1232 = comb.and %slots_30.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_122"} : i10
    %1233 = comb.icmp ne %1232, %c0_i10 {sv.namehint = "_can_allocate_122"} : i10
    %can_allocate_122 = sv.wire sym @can_allocate_122  : !hw.inout<i1>
    sv.assign %can_allocate_122, %1233 : i1
    %1234 = comb.or %1211, %1185 : i1
    %1235 = comb.xor %1234, %true : i1
    %1236 = comb.and %slots_30.io_request, %1233, %1235 : i1
    %1237 = comb.extract %slots_30.io_uop_fu_code from 0 : (i10) -> i1
    %1238 = comb.extract %slots_30.io_uop_fu_code from 5 : (i10) -> i1
    %1239 = comb.concat %1238, %1237 : i1, i1
    %1240 = comb.icmp ne %1239, %c0_i2 : i2
    %can_allocate_121 = sv.wire sym @can_allocate_121  : !hw.inout<i1>
    sv.assign %can_allocate_121, %1240 : i1
    %1241 = comb.or %1214, %1192 : i1
    %1242 = comb.xor %1241, %true : i1
    %1243 = comb.and %slots_30.io_request, %1240, %1242 : i1
    %1244 = comb.and %slots_30.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_120"} : i10
    %1245 = comb.icmp ne %1244, %c0_i10 {sv.namehint = "_can_allocate_120"} : i10
    %can_allocate_120 = sv.wire sym @can_allocate_120  : !hw.inout<i1>
    sv.assign %can_allocate_120, %1245 : i1
    %1246 = comb.and %slots_30.io_request, %1245 : i1
    %1247 = comb.or %1197, %1198 : i1
    %1248 = comb.xor %1247, %true : i1
    %1249 = comb.and %1246, %1248 : i1
    %1250 = comb.or %1243, %1249 : i1
    %1251 = comb.or %1236, %1250 : i1
    %1252 = comb.xor %1251, %true : i1
    %1253 = comb.and %slots_30.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_123"} : i10
    %1254 = comb.icmp ne %1253, %c0_i10 {sv.namehint = "_can_allocate_123"} : i10
    %can_allocate_123 = sv.wire sym @can_allocate_123  : !hw.inout<i1>
    sv.assign %can_allocate_123, %1254 : i1
    %1255 = comb.and %slots_30.io_request, %1252, %1254 : i1
    %1256 = comb.or %1206, %1207 : i1
    %1257 = comb.xor %1256, %true : i1
    %1258 = comb.and %1255, %1257 : i1
    %1259 = comb.xor %1250, %true : i1
    %1260 = comb.and %slots_30.io_request, %1259, %1233 : i1
    %1261 = comb.and %1260, %1235 : i1
    %1262 = comb.xor %1249, %true : i1
    %1263 = comb.and %slots_30.io_request, %1262, %1240 : i1
    %1264 = comb.and %1263, %1242 : i1
    %1265 = comb.or %1258, %1261, %1264, %1249 {sv.namehint = "_issue_slots_30_grant"} : i1
    %issue_slots_30_grant = sv.wire sym @issue_slots_30_grant  : !hw.inout<i1>
    sv.assign %issue_slots_30_grant, %1265 : i1
    %issue_slots_31_request = sv.wire sym @issue_slots_31_request  : !hw.inout<i1>
    sv.assign %issue_slots_31_request, %slots_31.io_request : i1
    %issue_slots_31_uop_fu_code = sv.wire sym @issue_slots_31_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_31_uop_fu_code, %slots_31.io_uop_fu_code : i10
    %1266 = comb.and %slots_31.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_126"} : i10
    %1267 = comb.icmp ne %1266, %c0_i10 {sv.namehint = "_can_allocate_126"} : i10
    %can_allocate_126 = sv.wire sym @can_allocate_126  : !hw.inout<i1>
    sv.assign %can_allocate_126, %1267 : i1
    %1268 = comb.or %1260, %1234 : i1
    %1269 = comb.xor %1268, %true : i1
    %1270 = comb.and %slots_31.io_request, %1267, %1269 : i1
    %1271 = comb.extract %slots_31.io_uop_fu_code from 0 : (i10) -> i1
    %1272 = comb.extract %slots_31.io_uop_fu_code from 5 : (i10) -> i1
    %1273 = comb.concat %1272, %1271 : i1, i1
    %1274 = comb.icmp ne %1273, %c0_i2 : i2
    %can_allocate_125 = sv.wire sym @can_allocate_125  : !hw.inout<i1>
    sv.assign %can_allocate_125, %1274 : i1
    %1275 = comb.or %1263, %1241 : i1
    %1276 = comb.xor %1275, %true : i1
    %1277 = comb.and %slots_31.io_request, %1274, %1276 : i1
    %1278 = comb.and %slots_31.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_124"} : i10
    %1279 = comb.icmp ne %1278, %c0_i10 {sv.namehint = "_can_allocate_124"} : i10
    %can_allocate_124 = sv.wire sym @can_allocate_124  : !hw.inout<i1>
    sv.assign %can_allocate_124, %1279 : i1
    %1280 = comb.and %slots_31.io_request, %1279 : i1
    %1281 = comb.or %1246, %1247 : i1
    %1282 = comb.xor %1281, %true : i1
    %1283 = comb.and %1280, %1282 : i1
    %1284 = comb.or %1277, %1283 : i1
    %1285 = comb.or %1270, %1284 : i1
    %1286 = comb.xor %1285, %true : i1
    %1287 = comb.and %slots_31.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_127"} : i10
    %1288 = comb.icmp ne %1287, %c0_i10 {sv.namehint = "_can_allocate_127"} : i10
    %can_allocate_127 = sv.wire sym @can_allocate_127  : !hw.inout<i1>
    sv.assign %can_allocate_127, %1288 : i1
    %1289 = comb.and %slots_31.io_request, %1286, %1288 : i1
    %1290 = comb.or %1255, %1256 : i1
    %1291 = comb.xor %1290, %true : i1
    %1292 = comb.and %1289, %1291 : i1
    %1293 = comb.xor %1284, %true : i1
    %1294 = comb.and %slots_31.io_request, %1293, %1267 : i1
    %1295 = comb.and %1294, %1269 : i1
    %1296 = comb.xor %1283, %true : i1
    %1297 = comb.and %slots_31.io_request, %1296, %1274 : i1
    %1298 = comb.and %1297, %1276 : i1
    %1299 = comb.or %1292, %1295, %1298, %1283 {sv.namehint = "_issue_slots_31_grant"} : i1
    %issue_slots_31_grant = sv.wire sym @issue_slots_31_grant  : !hw.inout<i1>
    sv.assign %issue_slots_31_grant, %1299 : i1
    %1300 = comb.concat %false, %1265 : i1, i1
    %1301 = comb.concat %false, %1299 : i1, i1
    %1302 = comb.add %1300, %1301 : i2
    %issue_slots_33_request = sv.wire sym @issue_slots_33_request  : !hw.inout<i1>
    sv.assign %issue_slots_33_request, %slots_33.io_request : i1
    %issue_slots_33_uop_fu_code = sv.wire sym @issue_slots_33_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_33_uop_fu_code, %slots_33.io_uop_fu_code : i10
    %1303 = comb.and %slots_33.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_134"} : i10
    %1304 = comb.icmp ne %1303, %c0_i10 {sv.namehint = "_can_allocate_134"} : i10
    %can_allocate_134 = sv.wire sym @can_allocate_134  : !hw.inout<i1>
    sv.assign %can_allocate_134, %1304 : i1
    %issue_slots_32_request = sv.wire sym @issue_slots_32_request  : !hw.inout<i1>
    sv.assign %issue_slots_32_request, %slots_32.io_request : i1
    %issue_slots_32_uop_fu_code = sv.wire sym @issue_slots_32_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_32_uop_fu_code, %slots_32.io_uop_fu_code : i10
    %1305 = comb.extract %slots_32.io_uop_fu_code from 0 : (i10) -> i1
    %1306 = comb.extract %slots_32.io_uop_fu_code from 5 : (i10) -> i1
    %1307 = comb.concat %1306, %1305 : i1, i1
    %1308 = comb.icmp ne %1307, %c0_i2 : i2
    %can_allocate_129 = sv.wire sym @can_allocate_129  : !hw.inout<i1>
    sv.assign %can_allocate_129, %1308 : i1
    %1309 = comb.or %1297, %1275 : i1
    %1310 = comb.xor %1309, %true : i1
    %1311 = comb.and %slots_32.io_request, %1308, %1310 : i1
    %1312 = comb.and %slots_32.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_128"} : i10
    %1313 = comb.icmp ne %1312, %c0_i10 {sv.namehint = "_can_allocate_128"} : i10
    %can_allocate_128 = sv.wire sym @can_allocate_128  : !hw.inout<i1>
    sv.assign %can_allocate_128, %1313 : i1
    %1314 = comb.and %slots_32.io_request, %1313 : i1
    %1315 = comb.or %1280, %1281 : i1
    %1316 = comb.xor %1315, %true : i1
    %1317 = comb.and %1314, %1316 : i1
    %1318 = comb.or %1311, %1317 : i1
    %1319 = comb.xor %1318, %true : i1
    %1320 = comb.and %slots_32.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_130"} : i10
    %1321 = comb.icmp ne %1320, %c0_i10 {sv.namehint = "_can_allocate_130"} : i10
    %can_allocate_130 = sv.wire sym @can_allocate_130  : !hw.inout<i1>
    sv.assign %can_allocate_130, %1321 : i1
    %1322 = comb.and %slots_32.io_request, %1319, %1321 : i1
    %1323 = comb.or %1294, %1268 : i1
    %1324 = comb.or %1322, %1323 : i1
    %1325 = comb.xor %1324, %true : i1
    %1326 = comb.and %slots_33.io_request, %1304, %1325 : i1
    %1327 = comb.extract %slots_33.io_uop_fu_code from 0 : (i10) -> i1
    %1328 = comb.extract %slots_33.io_uop_fu_code from 5 : (i10) -> i1
    %1329 = comb.concat %1328, %1327 : i1, i1
    %1330 = comb.icmp ne %1329, %c0_i2 : i2
    %can_allocate_133 = sv.wire sym @can_allocate_133  : !hw.inout<i1>
    sv.assign %can_allocate_133, %1330 : i1
    %1331 = comb.xor %1317, %true : i1
    %1332 = comb.and %slots_32.io_request, %1331, %1308 : i1
    %1333 = comb.or %1332, %1309 : i1
    %1334 = comb.xor %1333, %true : i1
    %1335 = comb.and %slots_33.io_request, %1330, %1334 : i1
    %1336 = comb.and %slots_33.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_132"} : i10
    %1337 = comb.icmp ne %1336, %c0_i10 {sv.namehint = "_can_allocate_132"} : i10
    %can_allocate_132 = sv.wire sym @can_allocate_132  : !hw.inout<i1>
    sv.assign %can_allocate_132, %1337 : i1
    %1338 = comb.and %slots_33.io_request, %1337 : i1
    %1339 = comb.or %1314, %1315 : i1
    %1340 = comb.xor %1339, %true : i1
    %1341 = comb.and %1338, %1340 : i1
    %1342 = comb.or %1335, %1341 : i1
    %1343 = comb.or %1326, %1342 : i1
    %1344 = comb.xor %1343, %true : i1
    %1345 = comb.and %slots_33.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_135"} : i10
    %1346 = comb.icmp ne %1345, %c0_i10 {sv.namehint = "_can_allocate_135"} : i10
    %can_allocate_135 = sv.wire sym @can_allocate_135  : !hw.inout<i1>
    sv.assign %can_allocate_135, %1346 : i1
    %1347 = comb.and %slots_33.io_request, %1344, %1346 : i1
    %1348 = comb.xor %1323, %true : i1
    %1349 = comb.and %slots_32.io_request, %1321, %1348 : i1
    %1350 = comb.or %1349, %1318 : i1
    %1351 = comb.xor %1350, %true : i1
    %1352 = comb.and %slots_32.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_131"} : i10
    %1353 = comb.icmp ne %1352, %c0_i10 {sv.namehint = "_can_allocate_131"} : i10
    %can_allocate_131 = sv.wire sym @can_allocate_131  : !hw.inout<i1>
    sv.assign %can_allocate_131, %1353 : i1
    %1354 = comb.and %slots_32.io_request, %1351, %1353 : i1
    %1355 = comb.or %1289, %1290 : i1
    %1356 = comb.or %1354, %1355 : i1
    %1357 = comb.xor %1356, %true : i1
    %1358 = comb.and %1347, %1357 : i1
    %1359 = comb.xor %1342, %true : i1
    %1360 = comb.and %slots_33.io_request, %1359, %1304 : i1
    %1361 = comb.and %1360, %1325 : i1
    %1362 = comb.xor %1341, %true : i1
    %1363 = comb.and %slots_33.io_request, %1362, %1330 : i1
    %1364 = comb.and %1363, %1334 : i1
    %1365 = comb.or %1358, %1361, %1364, %1341 {sv.namehint = "_issue_slots_33_grant"} : i1
    %issue_slots_33_grant = sv.wire sym @issue_slots_33_grant  : !hw.inout<i1>
    sv.assign %issue_slots_33_grant, %1365 : i1
    %issue_slots_34_request = sv.wire sym @issue_slots_34_request  : !hw.inout<i1>
    sv.assign %issue_slots_34_request, %slots_34.io_request : i1
    %issue_slots_34_uop_fu_code = sv.wire sym @issue_slots_34_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_34_uop_fu_code, %slots_34.io_uop_fu_code : i10
    %1366 = comb.and %slots_34.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_138"} : i10
    %1367 = comb.icmp ne %1366, %c0_i10 {sv.namehint = "_can_allocate_138"} : i10
    %can_allocate_138 = sv.wire sym @can_allocate_138  : !hw.inout<i1>
    sv.assign %can_allocate_138, %1367 : i1
    %1368 = comb.or %1360, %1324 : i1
    %1369 = comb.xor %1368, %true : i1
    %1370 = comb.and %slots_34.io_request, %1367, %1369 : i1
    %1371 = comb.extract %slots_34.io_uop_fu_code from 0 : (i10) -> i1
    %1372 = comb.extract %slots_34.io_uop_fu_code from 5 : (i10) -> i1
    %1373 = comb.concat %1372, %1371 : i1, i1
    %1374 = comb.icmp ne %1373, %c0_i2 : i2
    %can_allocate_137 = sv.wire sym @can_allocate_137  : !hw.inout<i1>
    sv.assign %can_allocate_137, %1374 : i1
    %1375 = comb.or %1363, %1333 : i1
    %1376 = comb.xor %1375, %true : i1
    %1377 = comb.and %slots_34.io_request, %1374, %1376 : i1
    %1378 = comb.and %slots_34.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_136"} : i10
    %1379 = comb.icmp ne %1378, %c0_i10 {sv.namehint = "_can_allocate_136"} : i10
    %can_allocate_136 = sv.wire sym @can_allocate_136  : !hw.inout<i1>
    sv.assign %can_allocate_136, %1379 : i1
    %1380 = comb.and %slots_34.io_request, %1379 : i1
    %1381 = comb.or %1338, %1339 : i1
    %1382 = comb.xor %1381, %true : i1
    %1383 = comb.and %1380, %1382 : i1
    %1384 = comb.or %1377, %1383 : i1
    %1385 = comb.or %1370, %1384 : i1
    %1386 = comb.xor %1385, %true : i1
    %1387 = comb.and %slots_34.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_139"} : i10
    %1388 = comb.icmp ne %1387, %c0_i10 {sv.namehint = "_can_allocate_139"} : i10
    %can_allocate_139 = sv.wire sym @can_allocate_139  : !hw.inout<i1>
    sv.assign %can_allocate_139, %1388 : i1
    %1389 = comb.and %slots_34.io_request, %1386, %1388 : i1
    %1390 = comb.or %1347, %1356 : i1
    %1391 = comb.xor %1390, %true : i1
    %1392 = comb.and %1389, %1391 : i1
    %1393 = comb.xor %1384, %true : i1
    %1394 = comb.and %slots_34.io_request, %1393, %1367 : i1
    %1395 = comb.and %1394, %1369 : i1
    %1396 = comb.xor %1383, %true : i1
    %1397 = comb.and %slots_34.io_request, %1396, %1374 : i1
    %1398 = comb.and %1397, %1376 : i1
    %1399 = comb.or %1392, %1395, %1398, %1383 {sv.namehint = "_issue_slots_34_grant"} : i1
    %issue_slots_34_grant = sv.wire sym @issue_slots_34_grant  : !hw.inout<i1>
    sv.assign %issue_slots_34_grant, %1399 : i1
    %1400 = comb.concat %false, %1365 : i1, i1
    %1401 = comb.concat %false, %1399 : i1, i1
    %1402 = comb.xor %1355, %true : i1
    %1403 = comb.and %1354, %1402 : i1
    %1404 = comb.and %1322, %1348 : i1
    %1405 = comb.and %1332, %1310 : i1
    %1406 = comb.or %1403, %1404, %1405, %1317 {sv.namehint = "_issue_slots_32_grant"} : i1
    %issue_slots_32_grant = sv.wire sym @issue_slots_32_grant  : !hw.inout<i1>
    sv.assign %issue_slots_32_grant, %1406 : i1
    %1407 = comb.concat %false, %1406 : i1, i1
    %1408 = comb.add %1407, %1400, %1401 : i2
    %1409 = comb.concat %false, %1302 : i1, i2
    %1410 = comb.concat %false, %1408 : i1, i2
    %1411 = comb.add %1409, %1410 : i3
    %issue_slots_35_request = sv.wire sym @issue_slots_35_request  : !hw.inout<i1>
    sv.assign %issue_slots_35_request, %slots_35.io_request : i1
    %issue_slots_35_uop_fu_code = sv.wire sym @issue_slots_35_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_35_uop_fu_code, %slots_35.io_uop_fu_code : i10
    %1412 = comb.and %slots_35.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_142"} : i10
    %1413 = comb.icmp ne %1412, %c0_i10 {sv.namehint = "_can_allocate_142"} : i10
    %can_allocate_142 = sv.wire sym @can_allocate_142  : !hw.inout<i1>
    sv.assign %can_allocate_142, %1413 : i1
    %1414 = comb.or %1394, %1368 : i1
    %1415 = comb.xor %1414, %true : i1
    %1416 = comb.and %slots_35.io_request, %1413, %1415 : i1
    %1417 = comb.extract %slots_35.io_uop_fu_code from 0 : (i10) -> i1
    %1418 = comb.extract %slots_35.io_uop_fu_code from 5 : (i10) -> i1
    %1419 = comb.concat %1418, %1417 : i1, i1
    %1420 = comb.icmp ne %1419, %c0_i2 : i2
    %can_allocate_141 = sv.wire sym @can_allocate_141  : !hw.inout<i1>
    sv.assign %can_allocate_141, %1420 : i1
    %1421 = comb.or %1397, %1375 : i1
    %1422 = comb.xor %1421, %true : i1
    %1423 = comb.and %slots_35.io_request, %1420, %1422 : i1
    %1424 = comb.and %slots_35.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_140"} : i10
    %1425 = comb.icmp ne %1424, %c0_i10 {sv.namehint = "_can_allocate_140"} : i10
    %can_allocate_140 = sv.wire sym @can_allocate_140  : !hw.inout<i1>
    sv.assign %can_allocate_140, %1425 : i1
    %1426 = comb.and %slots_35.io_request, %1425 : i1
    %1427 = comb.or %1380, %1381 : i1
    %1428 = comb.xor %1427, %true : i1
    %1429 = comb.and %1426, %1428 : i1
    %1430 = comb.or %1423, %1429 : i1
    %1431 = comb.or %1416, %1430 : i1
    %1432 = comb.xor %1431, %true : i1
    %1433 = comb.and %slots_35.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_143"} : i10
    %1434 = comb.icmp ne %1433, %c0_i10 {sv.namehint = "_can_allocate_143"} : i10
    %can_allocate_143 = sv.wire sym @can_allocate_143  : !hw.inout<i1>
    sv.assign %can_allocate_143, %1434 : i1
    %1435 = comb.and %slots_35.io_request, %1432, %1434 : i1
    %1436 = comb.or %1389, %1390 : i1
    %1437 = comb.xor %1436, %true : i1
    %1438 = comb.and %1435, %1437 : i1
    %1439 = comb.xor %1430, %true : i1
    %1440 = comb.and %slots_35.io_request, %1439, %1413 : i1
    %1441 = comb.and %1440, %1415 : i1
    %1442 = comb.xor %1429, %true : i1
    %1443 = comb.and %slots_35.io_request, %1442, %1420 : i1
    %1444 = comb.and %1443, %1422 : i1
    %1445 = comb.or %1438, %1441, %1444, %1429 {sv.namehint = "_issue_slots_35_grant"} : i1
    %issue_slots_35_grant = sv.wire sym @issue_slots_35_grant  : !hw.inout<i1>
    sv.assign %issue_slots_35_grant, %1445 : i1
    %issue_slots_36_request = sv.wire sym @issue_slots_36_request  : !hw.inout<i1>
    sv.assign %issue_slots_36_request, %slots_36.io_request : i1
    %issue_slots_36_uop_fu_code = sv.wire sym @issue_slots_36_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_36_uop_fu_code, %slots_36.io_uop_fu_code : i10
    %1446 = comb.and %slots_36.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_146"} : i10
    %1447 = comb.icmp ne %1446, %c0_i10 {sv.namehint = "_can_allocate_146"} : i10
    %can_allocate_146 = sv.wire sym @can_allocate_146  : !hw.inout<i1>
    sv.assign %can_allocate_146, %1447 : i1
    %1448 = comb.or %1440, %1414 : i1
    %1449 = comb.xor %1448, %true : i1
    %1450 = comb.and %slots_36.io_request, %1447, %1449 : i1
    %1451 = comb.extract %slots_36.io_uop_fu_code from 0 : (i10) -> i1
    %1452 = comb.extract %slots_36.io_uop_fu_code from 5 : (i10) -> i1
    %1453 = comb.concat %1452, %1451 : i1, i1
    %1454 = comb.icmp ne %1453, %c0_i2 : i2
    %can_allocate_145 = sv.wire sym @can_allocate_145  : !hw.inout<i1>
    sv.assign %can_allocate_145, %1454 : i1
    %1455 = comb.or %1443, %1421 : i1
    %1456 = comb.xor %1455, %true : i1
    %1457 = comb.and %slots_36.io_request, %1454, %1456 : i1
    %1458 = comb.and %slots_36.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_144"} : i10
    %1459 = comb.icmp ne %1458, %c0_i10 {sv.namehint = "_can_allocate_144"} : i10
    %can_allocate_144 = sv.wire sym @can_allocate_144  : !hw.inout<i1>
    sv.assign %can_allocate_144, %1459 : i1
    %1460 = comb.and %slots_36.io_request, %1459 : i1
    %1461 = comb.or %1426, %1427 : i1
    %1462 = comb.xor %1461, %true : i1
    %1463 = comb.and %1460, %1462 : i1
    %1464 = comb.or %1457, %1463 : i1
    %1465 = comb.or %1450, %1464 : i1
    %1466 = comb.xor %1465, %true : i1
    %1467 = comb.and %slots_36.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_147"} : i10
    %1468 = comb.icmp ne %1467, %c0_i10 {sv.namehint = "_can_allocate_147"} : i10
    %can_allocate_147 = sv.wire sym @can_allocate_147  : !hw.inout<i1>
    sv.assign %can_allocate_147, %1468 : i1
    %1469 = comb.and %slots_36.io_request, %1466, %1468 : i1
    %1470 = comb.or %1435, %1436 : i1
    %1471 = comb.xor %1470, %true : i1
    %1472 = comb.and %1469, %1471 : i1
    %1473 = comb.xor %1464, %true : i1
    %1474 = comb.and %slots_36.io_request, %1473, %1447 : i1
    %1475 = comb.and %1474, %1449 : i1
    %1476 = comb.xor %1463, %true : i1
    %1477 = comb.and %slots_36.io_request, %1476, %1454 : i1
    %1478 = comb.and %1477, %1456 : i1
    %1479 = comb.or %1472, %1475, %1478, %1463 {sv.namehint = "_issue_slots_36_grant"} : i1
    %issue_slots_36_grant = sv.wire sym @issue_slots_36_grant  : !hw.inout<i1>
    sv.assign %issue_slots_36_grant, %1479 : i1
    %1480 = comb.concat %false, %1445 : i1, i1
    %1481 = comb.concat %false, %1479 : i1, i1
    %1482 = comb.add %1480, %1481 : i2
    %issue_slots_38_request = sv.wire sym @issue_slots_38_request  : !hw.inout<i1>
    sv.assign %issue_slots_38_request, %slots_38.io_request : i1
    %issue_slots_38_uop_fu_code = sv.wire sym @issue_slots_38_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_38_uop_fu_code, %slots_38.io_uop_fu_code : i10
    %1483 = comb.and %slots_38.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_154"} : i10
    %1484 = comb.icmp ne %1483, %c0_i10 {sv.namehint = "_can_allocate_154"} : i10
    %can_allocate_154 = sv.wire sym @can_allocate_154  : !hw.inout<i1>
    sv.assign %can_allocate_154, %1484 : i1
    %issue_slots_37_request = sv.wire sym @issue_slots_37_request  : !hw.inout<i1>
    sv.assign %issue_slots_37_request, %slots_37.io_request : i1
    %issue_slots_37_uop_fu_code = sv.wire sym @issue_slots_37_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_37_uop_fu_code, %slots_37.io_uop_fu_code : i10
    %1485 = comb.extract %slots_37.io_uop_fu_code from 0 : (i10) -> i1
    %1486 = comb.extract %slots_37.io_uop_fu_code from 5 : (i10) -> i1
    %1487 = comb.concat %1486, %1485 : i1, i1
    %1488 = comb.icmp ne %1487, %c0_i2 : i2
    %can_allocate_149 = sv.wire sym @can_allocate_149  : !hw.inout<i1>
    sv.assign %can_allocate_149, %1488 : i1
    %1489 = comb.or %1477, %1455 : i1
    %1490 = comb.xor %1489, %true : i1
    %1491 = comb.and %slots_37.io_request, %1488, %1490 : i1
    %1492 = comb.and %slots_37.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_148"} : i10
    %1493 = comb.icmp ne %1492, %c0_i10 {sv.namehint = "_can_allocate_148"} : i10
    %can_allocate_148 = sv.wire sym @can_allocate_148  : !hw.inout<i1>
    sv.assign %can_allocate_148, %1493 : i1
    %1494 = comb.and %slots_37.io_request, %1493 : i1
    %1495 = comb.or %1460, %1461 : i1
    %1496 = comb.xor %1495, %true : i1
    %1497 = comb.and %1494, %1496 : i1
    %1498 = comb.or %1491, %1497 : i1
    %1499 = comb.xor %1498, %true : i1
    %1500 = comb.and %slots_37.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_150"} : i10
    %1501 = comb.icmp ne %1500, %c0_i10 {sv.namehint = "_can_allocate_150"} : i10
    %can_allocate_150 = sv.wire sym @can_allocate_150  : !hw.inout<i1>
    sv.assign %can_allocate_150, %1501 : i1
    %1502 = comb.and %slots_37.io_request, %1499, %1501 : i1
    %1503 = comb.or %1474, %1448 : i1
    %1504 = comb.or %1502, %1503 : i1
    %1505 = comb.xor %1504, %true : i1
    %1506 = comb.and %slots_38.io_request, %1484, %1505 : i1
    %1507 = comb.extract %slots_38.io_uop_fu_code from 0 : (i10) -> i1
    %1508 = comb.extract %slots_38.io_uop_fu_code from 5 : (i10) -> i1
    %1509 = comb.concat %1508, %1507 : i1, i1
    %1510 = comb.icmp ne %1509, %c0_i2 : i2
    %can_allocate_153 = sv.wire sym @can_allocate_153  : !hw.inout<i1>
    sv.assign %can_allocate_153, %1510 : i1
    %1511 = comb.xor %1497, %true : i1
    %1512 = comb.and %slots_37.io_request, %1511, %1488 : i1
    %1513 = comb.or %1512, %1489 : i1
    %1514 = comb.xor %1513, %true : i1
    %1515 = comb.and %slots_38.io_request, %1510, %1514 : i1
    %1516 = comb.and %slots_38.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_152"} : i10
    %1517 = comb.icmp ne %1516, %c0_i10 {sv.namehint = "_can_allocate_152"} : i10
    %can_allocate_152 = sv.wire sym @can_allocate_152  : !hw.inout<i1>
    sv.assign %can_allocate_152, %1517 : i1
    %1518 = comb.and %slots_38.io_request, %1517 : i1
    %1519 = comb.or %1494, %1495 : i1
    %1520 = comb.xor %1519, %true : i1
    %1521 = comb.and %1518, %1520 : i1
    %1522 = comb.or %1515, %1521 : i1
    %1523 = comb.or %1506, %1522 : i1
    %1524 = comb.xor %1523, %true : i1
    %1525 = comb.and %slots_38.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_155"} : i10
    %1526 = comb.icmp ne %1525, %c0_i10 {sv.namehint = "_can_allocate_155"} : i10
    %can_allocate_155 = sv.wire sym @can_allocate_155  : !hw.inout<i1>
    sv.assign %can_allocate_155, %1526 : i1
    %1527 = comb.and %slots_38.io_request, %1524, %1526 : i1
    %1528 = comb.xor %1503, %true : i1
    %1529 = comb.and %slots_37.io_request, %1501, %1528 : i1
    %1530 = comb.or %1529, %1498 : i1
    %1531 = comb.xor %1530, %true : i1
    %1532 = comb.and %slots_37.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_151"} : i10
    %1533 = comb.icmp ne %1532, %c0_i10 {sv.namehint = "_can_allocate_151"} : i10
    %can_allocate_151 = sv.wire sym @can_allocate_151  : !hw.inout<i1>
    sv.assign %can_allocate_151, %1533 : i1
    %1534 = comb.and %slots_37.io_request, %1531, %1533 : i1
    %1535 = comb.or %1469, %1470 : i1
    %1536 = comb.or %1534, %1535 : i1
    %1537 = comb.xor %1536, %true : i1
    %1538 = comb.and %1527, %1537 : i1
    %1539 = comb.xor %1522, %true : i1
    %1540 = comb.and %slots_38.io_request, %1539, %1484 : i1
    %1541 = comb.and %1540, %1505 : i1
    %1542 = comb.xor %1521, %true : i1
    %1543 = comb.and %slots_38.io_request, %1542, %1510 : i1
    %1544 = comb.and %1543, %1514 : i1
    %1545 = comb.or %1538, %1541, %1544, %1521 {sv.namehint = "_issue_slots_38_grant"} : i1
    %issue_slots_38_grant = sv.wire sym @issue_slots_38_grant  : !hw.inout<i1>
    sv.assign %issue_slots_38_grant, %1545 : i1
    %issue_slots_39_request = sv.wire sym @issue_slots_39_request  : !hw.inout<i1>
    sv.assign %issue_slots_39_request, %slots_39.io_request : i1
    %issue_slots_39_uop_fu_code = sv.wire sym @issue_slots_39_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_39_uop_fu_code, %slots_39.io_uop_fu_code : i10
    %1546 = comb.and %slots_39.io_uop_fu_code, %io_fu_types_2 {sv.namehint = "_can_allocate_T_158"} : i10
    %1547 = comb.icmp ne %1546, %c0_i10 {sv.namehint = "_can_allocate_158"} : i10
    %can_allocate_158 = sv.wire sym @can_allocate_158  : !hw.inout<i1>
    sv.assign %can_allocate_158, %1547 : i1
    %1548 = comb.or %1540, %1504 : i1
    %1549 = comb.xor %1548, %true : i1
    %1550 = comb.and %slots_39.io_request, %1547, %1549 : i1
    %1551 = comb.extract %slots_39.io_uop_fu_code from 0 : (i10) -> i1
    %1552 = comb.extract %slots_39.io_uop_fu_code from 5 : (i10) -> i1
    %1553 = comb.concat %1552, %1551 : i1, i1
    %1554 = comb.icmp ne %1553, %c0_i2 : i2
    %can_allocate_157 = sv.wire sym @can_allocate_157  : !hw.inout<i1>
    sv.assign %can_allocate_157, %1554 : i1
    %1555 = comb.or %1543, %1513 : i1
    %1556 = comb.xor %1555, %true : i1
    %1557 = comb.and %slots_39.io_request, %1554, %1556 : i1
    %1558 = comb.and %slots_39.io_uop_fu_code, %io_fu_types_0 {sv.namehint = "_can_allocate_T_156"} : i10
    %1559 = comb.icmp ne %1558, %c0_i10 {sv.namehint = "_can_allocate_156"} : i10
    %can_allocate_156 = sv.wire sym @can_allocate_156  : !hw.inout<i1>
    sv.assign %can_allocate_156, %1559 : i1
    %1560 = comb.or %1518, %1519 : i1
    %1561 = comb.xor %1560, %true : i1
    %1562 = comb.and %slots_39.io_request, %1559, %1561 : i1
    %1563 = comb.or %1557, %1562 : i1
    %1564 = comb.or %1550, %1563 : i1
    %1565 = comb.xor %1564, %true : i1
    %1566 = comb.and %slots_39.io_uop_fu_code, %io_fu_types_3 {sv.namehint = "_can_allocate_T_159"} : i10
    %1567 = comb.icmp ne %1566, %c0_i10 {sv.namehint = "_can_allocate_159"} : i10
    %can_allocate_159 = sv.wire sym @can_allocate_159  : !hw.inout<i1>
    sv.assign %can_allocate_159, %1567 : i1
    %1568 = comb.or %1527, %1536 : i1
    %1569 = comb.xor %1568, %true : i1
    %1570 = comb.and %slots_39.io_request, %1565, %1567, %1569 : i1
    %1571 = comb.xor %1563, %true : i1
    %1572 = comb.and %slots_39.io_request, %1571, %1547, %1549 : i1
    %1573 = comb.xor %1562, %true : i1
    %1574 = comb.and %slots_39.io_request, %1573, %1554, %1556 : i1
    %1575 = comb.or %1570, %1572, %1574, %1562 {sv.namehint = "_issue_slots_39_grant"} : i1
    %issue_slots_39_grant = sv.wire sym @issue_slots_39_grant  : !hw.inout<i1>
    sv.assign %issue_slots_39_grant, %1575 : i1
    %1576 = comb.concat %false, %1545 : i1, i1
    %1577 = comb.concat %false, %1575 : i1, i1
    %1578 = comb.xor %1535, %true : i1
    %1579 = comb.and %1534, %1578 : i1
    %1580 = comb.and %1502, %1528 : i1
    %1581 = comb.and %1512, %1490 : i1
    %1582 = comb.or %1579, %1580, %1581, %1497 {sv.namehint = "_issue_slots_37_grant"} : i1
    %issue_slots_37_grant = sv.wire sym @issue_slots_37_grant  : !hw.inout<i1>
    sv.assign %issue_slots_37_grant, %1582 : i1
    %1583 = comb.concat %false, %1582 : i1, i1
    %1584 = comb.add %1583, %1576, %1577 : i2
    %1585 = comb.concat %false, %1482 : i1, i2
    %1586 = comb.concat %false, %1584 : i1, i2
    %1587 = comb.add %1585, %1586 : i3
    %1588 = comb.concat %false, %1411 : i1, i3
    %1589 = comb.concat %false, %1587 : i1, i3
    %1590 = comb.add %1588, %1589 : i4
    %1591 = comb.concat %false, %1231 : i1, i4
    %1592 = comb.concat %false, %1590 : i1, i4
    %1593 = comb.add %1591, %1592 : i5
    %1594 = comb.concat %false, %868 : i1, i5
    %1595 = comb.concat %false, %1593 : i1, i5
    %1596 = comb.add %1594, %1595 : i6
    %1597 = comb.icmp ult %1596, %c5_i6 : i6
    %1598 = comb.or %1597, %reset : i1
    %1599 = comb.xor %1598, %true : i1
    %1600 = comb.xor %slots_0.io_valid, %true {sv.namehint = "_vacants_0"} : i1
    %vacants_0 = sv.wire sym @vacants_0  : !hw.inout<i1>
    sv.assign %vacants_0, %1600 : i1
    %1601 = comb.xor %slots_1.io_valid, %true {sv.namehint = "_vacants_1"} : i1
    %vacants_1 = sv.wire sym @vacants_1  : !hw.inout<i1>
    sv.assign %vacants_1, %1601 : i1
    %1602 = comb.xor %slots_2.io_valid, %true {sv.namehint = "_vacants_2"} : i1
    %vacants_2 = sv.wire sym @vacants_2  : !hw.inout<i1>
    sv.assign %vacants_2, %1602 : i1
    %1603 = comb.xor %slots_3.io_valid, %true {sv.namehint = "_vacants_3"} : i1
    %vacants_3 = sv.wire sym @vacants_3  : !hw.inout<i1>
    sv.assign %vacants_3, %1603 : i1
    %1604 = comb.xor %slots_4.io_valid, %true {sv.namehint = "_vacants_4"} : i1
    %vacants_4 = sv.wire sym @vacants_4  : !hw.inout<i1>
    sv.assign %vacants_4, %1604 : i1
    %1605 = comb.xor %slots_5.io_valid, %true {sv.namehint = "_vacants_5"} : i1
    %vacants_5 = sv.wire sym @vacants_5  : !hw.inout<i1>
    sv.assign %vacants_5, %1605 : i1
    %1606 = comb.xor %slots_6.io_valid, %true {sv.namehint = "_vacants_6"} : i1
    %vacants_6 = sv.wire sym @vacants_6  : !hw.inout<i1>
    sv.assign %vacants_6, %1606 : i1
    %1607 = comb.xor %slots_7.io_valid, %true {sv.namehint = "_vacants_7"} : i1
    %vacants_7 = sv.wire sym @vacants_7  : !hw.inout<i1>
    sv.assign %vacants_7, %1607 : i1
    %1608 = comb.xor %slots_8.io_valid, %true {sv.namehint = "_vacants_8"} : i1
    %vacants_8 = sv.wire sym @vacants_8  : !hw.inout<i1>
    sv.assign %vacants_8, %1608 : i1
    %1609 = comb.xor %slots_9.io_valid, %true {sv.namehint = "_vacants_9"} : i1
    %vacants_9 = sv.wire sym @vacants_9  : !hw.inout<i1>
    sv.assign %vacants_9, %1609 : i1
    %1610 = comb.xor %slots_10.io_valid, %true {sv.namehint = "_vacants_10"} : i1
    %vacants_10 = sv.wire sym @vacants_10  : !hw.inout<i1>
    sv.assign %vacants_10, %1610 : i1
    %1611 = comb.xor %slots_11.io_valid, %true {sv.namehint = "_vacants_11"} : i1
    %vacants_11 = sv.wire sym @vacants_11  : !hw.inout<i1>
    sv.assign %vacants_11, %1611 : i1
    %1612 = comb.xor %slots_12.io_valid, %true {sv.namehint = "_vacants_12"} : i1
    %vacants_12 = sv.wire sym @vacants_12  : !hw.inout<i1>
    sv.assign %vacants_12, %1612 : i1
    %1613 = comb.xor %slots_13.io_valid, %true {sv.namehint = "_vacants_13"} : i1
    %vacants_13 = sv.wire sym @vacants_13  : !hw.inout<i1>
    sv.assign %vacants_13, %1613 : i1
    %1614 = comb.xor %slots_14.io_valid, %true {sv.namehint = "_vacants_14"} : i1
    %vacants_14 = sv.wire sym @vacants_14  : !hw.inout<i1>
    sv.assign %vacants_14, %1614 : i1
    %1615 = comb.xor %slots_15.io_valid, %true {sv.namehint = "_vacants_15"} : i1
    %vacants_15 = sv.wire sym @vacants_15  : !hw.inout<i1>
    sv.assign %vacants_15, %1615 : i1
    %1616 = comb.xor %slots_16.io_valid, %true {sv.namehint = "_vacants_16"} : i1
    %vacants_16 = sv.wire sym @vacants_16  : !hw.inout<i1>
    sv.assign %vacants_16, %1616 : i1
    %1617 = comb.xor %slots_17.io_valid, %true {sv.namehint = "_vacants_17"} : i1
    %vacants_17 = sv.wire sym @vacants_17  : !hw.inout<i1>
    sv.assign %vacants_17, %1617 : i1
    %1618 = comb.xor %slots_18.io_valid, %true {sv.namehint = "_vacants_18"} : i1
    %vacants_18 = sv.wire sym @vacants_18  : !hw.inout<i1>
    sv.assign %vacants_18, %1618 : i1
    %1619 = comb.xor %slots_19.io_valid, %true {sv.namehint = "_vacants_19"} : i1
    %vacants_19 = sv.wire sym @vacants_19  : !hw.inout<i1>
    sv.assign %vacants_19, %1619 : i1
    %1620 = comb.xor %slots_20.io_valid, %true {sv.namehint = "_vacants_20"} : i1
    %vacants_20 = sv.wire sym @vacants_20  : !hw.inout<i1>
    sv.assign %vacants_20, %1620 : i1
    %1621 = comb.xor %slots_21.io_valid, %true {sv.namehint = "_vacants_21"} : i1
    %vacants_21 = sv.wire sym @vacants_21  : !hw.inout<i1>
    sv.assign %vacants_21, %1621 : i1
    %1622 = comb.xor %slots_22.io_valid, %true {sv.namehint = "_vacants_22"} : i1
    %vacants_22 = sv.wire sym @vacants_22  : !hw.inout<i1>
    sv.assign %vacants_22, %1622 : i1
    %1623 = comb.xor %slots_23.io_valid, %true {sv.namehint = "_vacants_23"} : i1
    %vacants_23 = sv.wire sym @vacants_23  : !hw.inout<i1>
    sv.assign %vacants_23, %1623 : i1
    %1624 = comb.xor %slots_24.io_valid, %true {sv.namehint = "_vacants_24"} : i1
    %vacants_24 = sv.wire sym @vacants_24  : !hw.inout<i1>
    sv.assign %vacants_24, %1624 : i1
    %1625 = comb.xor %slots_25.io_valid, %true {sv.namehint = "_vacants_25"} : i1
    %vacants_25 = sv.wire sym @vacants_25  : !hw.inout<i1>
    sv.assign %vacants_25, %1625 : i1
    %1626 = comb.xor %slots_26.io_valid, %true {sv.namehint = "_vacants_26"} : i1
    %vacants_26 = sv.wire sym @vacants_26  : !hw.inout<i1>
    sv.assign %vacants_26, %1626 : i1
    %1627 = comb.xor %slots_27.io_valid, %true {sv.namehint = "_vacants_27"} : i1
    %vacants_27 = sv.wire sym @vacants_27  : !hw.inout<i1>
    sv.assign %vacants_27, %1627 : i1
    %1628 = comb.xor %slots_28.io_valid, %true {sv.namehint = "_vacants_28"} : i1
    %vacants_28 = sv.wire sym @vacants_28  : !hw.inout<i1>
    sv.assign %vacants_28, %1628 : i1
    %1629 = comb.xor %slots_29.io_valid, %true {sv.namehint = "_vacants_29"} : i1
    %vacants_29 = sv.wire sym @vacants_29  : !hw.inout<i1>
    sv.assign %vacants_29, %1629 : i1
    %1630 = comb.xor %slots_30.io_valid, %true {sv.namehint = "_vacants_30"} : i1
    %vacants_30 = sv.wire sym @vacants_30  : !hw.inout<i1>
    sv.assign %vacants_30, %1630 : i1
    %1631 = comb.xor %slots_31.io_valid, %true {sv.namehint = "_vacants_31"} : i1
    %vacants_31 = sv.wire sym @vacants_31  : !hw.inout<i1>
    sv.assign %vacants_31, %1631 : i1
    %1632 = comb.xor %slots_32.io_valid, %true {sv.namehint = "_vacants_32"} : i1
    %vacants_32 = sv.wire sym @vacants_32  : !hw.inout<i1>
    sv.assign %vacants_32, %1632 : i1
    %1633 = comb.xor %slots_33.io_valid, %true {sv.namehint = "_vacants_33"} : i1
    %vacants_33 = sv.wire sym @vacants_33  : !hw.inout<i1>
    sv.assign %vacants_33, %1633 : i1
    %1634 = comb.xor %slots_34.io_valid, %true {sv.namehint = "_vacants_34"} : i1
    %vacants_34 = sv.wire sym @vacants_34  : !hw.inout<i1>
    sv.assign %vacants_34, %1634 : i1
    %1635 = comb.xor %slots_35.io_valid, %true {sv.namehint = "_vacants_35"} : i1
    %vacants_35 = sv.wire sym @vacants_35  : !hw.inout<i1>
    sv.assign %vacants_35, %1635 : i1
    %1636 = comb.xor %slots_36.io_valid, %true {sv.namehint = "_vacants_36"} : i1
    %vacants_36 = sv.wire sym @vacants_36  : !hw.inout<i1>
    sv.assign %vacants_36, %1636 : i1
    %1637 = comb.xor %slots_37.io_valid, %true {sv.namehint = "_vacants_37"} : i1
    %vacants_37 = sv.wire sym @vacants_37  : !hw.inout<i1>
    sv.assign %vacants_37, %1637 : i1
    %1638 = comb.xor %slots_38.io_valid, %true {sv.namehint = "_vacants_38"} : i1
    %vacants_38 = sv.wire sym @vacants_38  : !hw.inout<i1>
    sv.assign %vacants_38, %1638 : i1
    %1639 = comb.xor %slots_39.io_valid, %true {sv.namehint = "_vacants_39"} : i1
    %vacants_39 = sv.wire sym @vacants_39  : !hw.inout<i1>
    sv.assign %vacants_39, %1639 : i1
    %1640 = comb.xor %io_dis_uops_0_valid, %true {sv.namehint = "_vacants_40"} : i1
    %vacants_40 = sv.wire sym @vacants_40  : !hw.inout<i1>
    sv.assign %vacants_40, %1640 : i1
    %1641 = comb.xor %io_dis_uops_1_valid, %true {sv.namehint = "_vacants_41"} : i1
    %vacants_41 = sv.wire sym @vacants_41  : !hw.inout<i1>
    sv.assign %vacants_41, %1641 : i1
    %1642 = comb.xor %io_dis_uops_2_valid, %true {sv.namehint = "_vacants_42"} : i1
    %vacants_42 = sv.wire sym @vacants_42  : !hw.inout<i1>
    sv.assign %vacants_42, %1642 : i1
    %1643 = comb.concat %c0_i3, %1600 : i3, i1
    %next = sv.wire sym @next  : !hw.inout<i4>
    sv.assign %next, %1643 : i4
    %1644 = comb.and %slots_0.io_valid, %1601 : i1
    %1645 = comb.concat %c0_i3, %1600 : i3, i1
    %1646 = comb.concat %c0_i2, %1600, %false : i2, i1, i1
    %1647 = comb.mux %slots_1.io_valid, %1645, %1646 : i4
    %1648 = comb.mux %1644, %c1_i4, %1647 : i4
    %next_1 = sv.wire sym @next_1  : !hw.inout<i4>
    sv.assign %next_1, %1648 : i4
    %1649 = comb.extract %1648 from 0 : (i4) -> i2
    %1650 = comb.icmp eq %1649, %c0_i2 : i2
    %1651 = comb.and %1650, %1602 : i1
    %1652 = comb.extract %1648 from 0 : (i4) -> i3
    %1653 = comb.concat %1652, %false : i3, i1
    %1654 = comb.mux %slots_2.io_valid, %1648, %1653 : i4
    %1655 = comb.mux %1651, %c1_i4, %1654 : i4
    %next_2 = sv.wire sym @next_2  : !hw.inout<i4>
    sv.assign %next_2, %1655 : i4
    %1656 = comb.icmp eq %1655, %c0_i4 : i4
    %1657 = comb.and %1656, %1603 : i1
    %1658 = comb.extract %1655 from 3 : (i4) -> i1
    %1659 = comb.or %1658, %slots_3.io_valid : i1
    %1660 = comb.extract %1655 from 0 : (i4) -> i3
    %1661 = comb.concat %1660, %false : i3, i1
    %1662 = comb.mux %1659, %1655, %1661 : i4
    %1663 = comb.mux %1657, %c1_i4, %1662 : i4
    %next_3 = sv.wire sym @next_3  : !hw.inout<i4>
    sv.assign %next_3, %1663 : i4
    %1664 = comb.icmp eq %1663, %c0_i4 : i4
    %1665 = comb.and %1664, %1604 : i1
    %1666 = comb.extract %1663 from 3 : (i4) -> i1
    %1667 = comb.or %1666, %slots_4.io_valid : i1
    %1668 = comb.extract %1663 from 0 : (i4) -> i3
    %1669 = comb.concat %1668, %false : i3, i1
    %1670 = comb.mux %1667, %1663, %1669 : i4
    %1671 = comb.mux %1665, %c1_i4, %1670 : i4
    %next_4 = sv.wire sym @next_4  : !hw.inout<i4>
    sv.assign %next_4, %1671 : i4
    %1672 = comb.icmp eq %1671, %c0_i4 : i4
    %1673 = comb.and %1672, %1605 : i1
    %1674 = comb.extract %1671 from 3 : (i4) -> i1
    %1675 = comb.or %1674, %slots_5.io_valid : i1
    %1676 = comb.extract %1671 from 0 : (i4) -> i3
    %1677 = comb.concat %1676, %false : i3, i1
    %1678 = comb.mux %1675, %1671, %1677 : i4
    %1679 = comb.mux %1673, %c1_i4, %1678 : i4
    %next_5 = sv.wire sym @next_5  : !hw.inout<i4>
    sv.assign %next_5, %1679 : i4
    %1680 = comb.icmp eq %1679, %c0_i4 : i4
    %1681 = comb.and %1680, %1606 : i1
    %1682 = comb.extract %1679 from 3 : (i4) -> i1
    %1683 = comb.or %1682, %slots_6.io_valid : i1
    %1684 = comb.extract %1679 from 0 : (i4) -> i3
    %1685 = comb.concat %1684, %false : i3, i1
    %1686 = comb.mux %1683, %1679, %1685 : i4
    %1687 = comb.mux %1681, %c1_i4, %1686 : i4
    %next_6 = sv.wire sym @next_6  : !hw.inout<i4>
    sv.assign %next_6, %1687 : i4
    %1688 = comb.icmp eq %1687, %c0_i4 : i4
    %1689 = comb.and %1688, %1607 : i1
    %1690 = comb.extract %1687 from 3 : (i4) -> i1
    %1691 = comb.or %1690, %slots_7.io_valid : i1
    %1692 = comb.extract %1687 from 0 : (i4) -> i3
    %1693 = comb.concat %1692, %false : i3, i1
    %1694 = comb.mux %1691, %1687, %1693 : i4
    %1695 = comb.mux %1689, %c1_i4, %1694 : i4
    %next_7 = sv.wire sym @next_7  : !hw.inout<i4>
    sv.assign %next_7, %1695 : i4
    %1696 = comb.icmp eq %1695, %c0_i4 : i4
    %1697 = comb.and %1696, %1608 : i1
    %1698 = comb.extract %1695 from 3 : (i4) -> i1
    %1699 = comb.or %1698, %slots_8.io_valid : i1
    %1700 = comb.extract %1695 from 0 : (i4) -> i3
    %1701 = comb.concat %1700, %false : i3, i1
    %1702 = comb.mux %1699, %1695, %1701 : i4
    %1703 = comb.mux %1697, %c1_i4, %1702 : i4
    %next_8 = sv.wire sym @next_8  : !hw.inout<i4>
    sv.assign %next_8, %1703 : i4
    %1704 = comb.icmp eq %1703, %c0_i4 : i4
    %1705 = comb.and %1704, %1609 : i1
    %1706 = comb.extract %1703 from 3 : (i4) -> i1
    %1707 = comb.or %1706, %slots_9.io_valid : i1
    %1708 = comb.extract %1703 from 0 : (i4) -> i3
    %1709 = comb.concat %1708, %false : i3, i1
    %1710 = comb.mux %1707, %1703, %1709 : i4
    %1711 = comb.mux %1705, %c1_i4, %1710 : i4
    %next_9 = sv.wire sym @next_9  : !hw.inout<i4>
    sv.assign %next_9, %1711 : i4
    %1712 = comb.icmp eq %1711, %c0_i4 : i4
    %1713 = comb.and %1712, %1610 : i1
    %1714 = comb.extract %1711 from 3 : (i4) -> i1
    %1715 = comb.or %1714, %slots_10.io_valid : i1
    %1716 = comb.extract %1711 from 0 : (i4) -> i3
    %1717 = comb.concat %1716, %false : i3, i1
    %1718 = comb.mux %1715, %1711, %1717 : i4
    %1719 = comb.mux %1713, %c1_i4, %1718 : i4
    %next_10 = sv.wire sym @next_10  : !hw.inout<i4>
    sv.assign %next_10, %1719 : i4
    %1720 = comb.icmp eq %1719, %c0_i4 : i4
    %1721 = comb.and %1720, %1611 : i1
    %1722 = comb.extract %1719 from 3 : (i4) -> i1
    %1723 = comb.or %1722, %slots_11.io_valid : i1
    %1724 = comb.extract %1719 from 0 : (i4) -> i3
    %1725 = comb.concat %1724, %false : i3, i1
    %1726 = comb.mux %1723, %1719, %1725 : i4
    %1727 = comb.mux %1721, %c1_i4, %1726 : i4
    %next_11 = sv.wire sym @next_11  : !hw.inout<i4>
    sv.assign %next_11, %1727 : i4
    %1728 = comb.icmp eq %1727, %c0_i4 : i4
    %1729 = comb.and %1728, %1612 : i1
    %1730 = comb.extract %1727 from 3 : (i4) -> i1
    %1731 = comb.or %1730, %slots_12.io_valid : i1
    %1732 = comb.extract %1727 from 0 : (i4) -> i3
    %1733 = comb.concat %1732, %false : i3, i1
    %1734 = comb.mux %1731, %1727, %1733 : i4
    %1735 = comb.mux %1729, %c1_i4, %1734 : i4
    %next_12 = sv.wire sym @next_12  : !hw.inout<i4>
    sv.assign %next_12, %1735 : i4
    %1736 = comb.icmp eq %1735, %c0_i4 : i4
    %1737 = comb.and %1736, %1613 : i1
    %1738 = comb.extract %1735 from 3 : (i4) -> i1
    %1739 = comb.or %1738, %slots_13.io_valid : i1
    %1740 = comb.extract %1735 from 0 : (i4) -> i3
    %1741 = comb.concat %1740, %false : i3, i1
    %1742 = comb.mux %1739, %1735, %1741 : i4
    %1743 = comb.mux %1737, %c1_i4, %1742 : i4
    %next_13 = sv.wire sym @next_13  : !hw.inout<i4>
    sv.assign %next_13, %1743 : i4
    %1744 = comb.icmp eq %1743, %c0_i4 : i4
    %1745 = comb.and %1744, %1614 : i1
    %1746 = comb.extract %1743 from 3 : (i4) -> i1
    %1747 = comb.or %1746, %slots_14.io_valid : i1
    %1748 = comb.extract %1743 from 0 : (i4) -> i3
    %1749 = comb.concat %1748, %false : i3, i1
    %1750 = comb.mux %1747, %1743, %1749 : i4
    %1751 = comb.mux %1745, %c1_i4, %1750 : i4
    %next_14 = sv.wire sym @next_14  : !hw.inout<i4>
    sv.assign %next_14, %1751 : i4
    %1752 = comb.icmp eq %1751, %c0_i4 : i4
    %1753 = comb.and %1752, %1615 : i1
    %1754 = comb.extract %1751 from 3 : (i4) -> i1
    %1755 = comb.or %1754, %slots_15.io_valid : i1
    %1756 = comb.extract %1751 from 0 : (i4) -> i3
    %1757 = comb.concat %1756, %false : i3, i1
    %1758 = comb.mux %1755, %1751, %1757 : i4
    %1759 = comb.mux %1753, %c1_i4, %1758 : i4
    %next_15 = sv.wire sym @next_15  : !hw.inout<i4>
    sv.assign %next_15, %1759 : i4
    %1760 = comb.icmp eq %1759, %c0_i4 : i4
    %1761 = comb.and %1760, %1616 : i1
    %1762 = comb.extract %1759 from 3 : (i4) -> i1
    %1763 = comb.or %1762, %slots_16.io_valid : i1
    %1764 = comb.extract %1759 from 0 : (i4) -> i3
    %1765 = comb.concat %1764, %false : i3, i1
    %1766 = comb.mux %1763, %1759, %1765 : i4
    %1767 = comb.mux %1761, %c1_i4, %1766 : i4
    %next_16 = sv.wire sym @next_16  : !hw.inout<i4>
    sv.assign %next_16, %1767 : i4
    %1768 = comb.icmp eq %1767, %c0_i4 : i4
    %1769 = comb.and %1768, %1617 : i1
    %1770 = comb.extract %1767 from 3 : (i4) -> i1
    %1771 = comb.or %1770, %slots_17.io_valid : i1
    %1772 = comb.extract %1767 from 0 : (i4) -> i3
    %1773 = comb.concat %1772, %false : i3, i1
    %1774 = comb.mux %1771, %1767, %1773 : i4
    %1775 = comb.mux %1769, %c1_i4, %1774 : i4
    %next_17 = sv.wire sym @next_17  : !hw.inout<i4>
    sv.assign %next_17, %1775 : i4
    %1776 = comb.icmp eq %1775, %c0_i4 : i4
    %1777 = comb.and %1776, %1618 : i1
    %1778 = comb.extract %1775 from 3 : (i4) -> i1
    %1779 = comb.or %1778, %slots_18.io_valid : i1
    %1780 = comb.extract %1775 from 0 : (i4) -> i3
    %1781 = comb.concat %1780, %false : i3, i1
    %1782 = comb.mux %1779, %1775, %1781 : i4
    %1783 = comb.mux %1777, %c1_i4, %1782 : i4
    %next_18 = sv.wire sym @next_18  : !hw.inout<i4>
    sv.assign %next_18, %1783 : i4
    %1784 = comb.icmp eq %1783, %c0_i4 : i4
    %1785 = comb.and %1784, %1619 : i1
    %1786 = comb.extract %1783 from 3 : (i4) -> i1
    %1787 = comb.or %1786, %slots_19.io_valid : i1
    %1788 = comb.extract %1783 from 0 : (i4) -> i3
    %1789 = comb.concat %1788, %false : i3, i1
    %1790 = comb.mux %1787, %1783, %1789 : i4
    %1791 = comb.mux %1785, %c1_i4, %1790 : i4
    %next_19 = sv.wire sym @next_19  : !hw.inout<i4>
    sv.assign %next_19, %1791 : i4
    %1792 = comb.icmp eq %1791, %c0_i4 : i4
    %1793 = comb.and %1792, %1620 : i1
    %1794 = comb.extract %1791 from 3 : (i4) -> i1
    %1795 = comb.or %1794, %slots_20.io_valid : i1
    %1796 = comb.extract %1791 from 0 : (i4) -> i3
    %1797 = comb.concat %1796, %false : i3, i1
    %1798 = comb.mux %1795, %1791, %1797 : i4
    %1799 = comb.mux %1793, %c1_i4, %1798 : i4
    %next_20 = sv.wire sym @next_20  : !hw.inout<i4>
    sv.assign %next_20, %1799 : i4
    %1800 = comb.icmp eq %1799, %c0_i4 : i4
    %1801 = comb.and %1800, %1621 : i1
    %1802 = comb.extract %1799 from 3 : (i4) -> i1
    %1803 = comb.or %1802, %slots_21.io_valid : i1
    %1804 = comb.extract %1799 from 0 : (i4) -> i3
    %1805 = comb.concat %1804, %false : i3, i1
    %1806 = comb.mux %1803, %1799, %1805 : i4
    %1807 = comb.mux %1801, %c1_i4, %1806 : i4
    %next_21 = sv.wire sym @next_21  : !hw.inout<i4>
    sv.assign %next_21, %1807 : i4
    %1808 = comb.icmp eq %1807, %c0_i4 : i4
    %1809 = comb.and %1808, %1622 : i1
    %1810 = comb.extract %1807 from 3 : (i4) -> i1
    %1811 = comb.or %1810, %slots_22.io_valid : i1
    %1812 = comb.extract %1807 from 0 : (i4) -> i3
    %1813 = comb.concat %1812, %false : i3, i1
    %1814 = comb.mux %1811, %1807, %1813 : i4
    %1815 = comb.mux %1809, %c1_i4, %1814 : i4
    %next_22 = sv.wire sym @next_22  : !hw.inout<i4>
    sv.assign %next_22, %1815 : i4
    %1816 = comb.icmp eq %1815, %c0_i4 : i4
    %1817 = comb.and %1816, %1623 : i1
    %1818 = comb.extract %1815 from 3 : (i4) -> i1
    %1819 = comb.or %1818, %slots_23.io_valid : i1
    %1820 = comb.extract %1815 from 0 : (i4) -> i3
    %1821 = comb.concat %1820, %false : i3, i1
    %1822 = comb.mux %1819, %1815, %1821 : i4
    %1823 = comb.mux %1817, %c1_i4, %1822 : i4
    %next_23 = sv.wire sym @next_23  : !hw.inout<i4>
    sv.assign %next_23, %1823 : i4
    %1824 = comb.icmp eq %1823, %c0_i4 : i4
    %1825 = comb.and %1824, %1624 : i1
    %1826 = comb.extract %1823 from 3 : (i4) -> i1
    %1827 = comb.or %1826, %slots_24.io_valid : i1
    %1828 = comb.extract %1823 from 0 : (i4) -> i3
    %1829 = comb.concat %1828, %false : i3, i1
    %1830 = comb.mux %1827, %1823, %1829 : i4
    %1831 = comb.mux %1825, %c1_i4, %1830 : i4
    %next_24 = sv.wire sym @next_24  : !hw.inout<i4>
    sv.assign %next_24, %1831 : i4
    %1832 = comb.icmp eq %1831, %c0_i4 : i4
    %1833 = comb.and %1832, %1625 : i1
    %1834 = comb.extract %1831 from 3 : (i4) -> i1
    %1835 = comb.or %1834, %slots_25.io_valid : i1
    %1836 = comb.extract %1831 from 0 : (i4) -> i3
    %1837 = comb.concat %1836, %false : i3, i1
    %1838 = comb.mux %1835, %1831, %1837 : i4
    %1839 = comb.mux %1833, %c1_i4, %1838 : i4
    %next_25 = sv.wire sym @next_25  : !hw.inout<i4>
    sv.assign %next_25, %1839 : i4
    %1840 = comb.icmp eq %1839, %c0_i4 : i4
    %1841 = comb.and %1840, %1626 : i1
    %1842 = comb.extract %1839 from 3 : (i4) -> i1
    %1843 = comb.or %1842, %slots_26.io_valid : i1
    %1844 = comb.extract %1839 from 0 : (i4) -> i3
    %1845 = comb.concat %1844, %false : i3, i1
    %1846 = comb.mux %1843, %1839, %1845 : i4
    %1847 = comb.mux %1841, %c1_i4, %1846 : i4
    %next_26 = sv.wire sym @next_26  : !hw.inout<i4>
    sv.assign %next_26, %1847 : i4
    %1848 = comb.icmp eq %1847, %c0_i4 : i4
    %1849 = comb.and %1848, %1627 : i1
    %1850 = comb.extract %1847 from 3 : (i4) -> i1
    %1851 = comb.or %1850, %slots_27.io_valid : i1
    %1852 = comb.extract %1847 from 0 : (i4) -> i3
    %1853 = comb.concat %1852, %false : i3, i1
    %1854 = comb.mux %1851, %1847, %1853 : i4
    %1855 = comb.mux %1849, %c1_i4, %1854 : i4
    %next_27 = sv.wire sym @next_27  : !hw.inout<i4>
    sv.assign %next_27, %1855 : i4
    %1856 = comb.icmp eq %1855, %c0_i4 : i4
    %1857 = comb.and %1856, %1628 : i1
    %1858 = comb.extract %1855 from 3 : (i4) -> i1
    %1859 = comb.or %1858, %slots_28.io_valid : i1
    %1860 = comb.extract %1855 from 0 : (i4) -> i3
    %1861 = comb.concat %1860, %false : i3, i1
    %1862 = comb.mux %1859, %1855, %1861 : i4
    %1863 = comb.mux %1857, %c1_i4, %1862 : i4
    %next_28 = sv.wire sym @next_28  : !hw.inout<i4>
    sv.assign %next_28, %1863 : i4
    %1864 = comb.icmp eq %1863, %c0_i4 : i4
    %1865 = comb.and %1864, %1629 : i1
    %1866 = comb.extract %1863 from 3 : (i4) -> i1
    %1867 = comb.or %1866, %slots_29.io_valid : i1
    %1868 = comb.extract %1863 from 0 : (i4) -> i3
    %1869 = comb.concat %1868, %false : i3, i1
    %1870 = comb.mux %1867, %1863, %1869 : i4
    %1871 = comb.mux %1865, %c1_i4, %1870 : i4
    %next_29 = sv.wire sym @next_29  : !hw.inout<i4>
    sv.assign %next_29, %1871 : i4
    %1872 = comb.icmp eq %1871, %c0_i4 : i4
    %1873 = comb.and %1872, %1630 : i1
    %1874 = comb.extract %1871 from 3 : (i4) -> i1
    %1875 = comb.or %1874, %slots_30.io_valid : i1
    %1876 = comb.extract %1871 from 0 : (i4) -> i3
    %1877 = comb.concat %1876, %false : i3, i1
    %1878 = comb.mux %1875, %1871, %1877 : i4
    %1879 = comb.mux %1873, %c1_i4, %1878 : i4
    %next_30 = sv.wire sym @next_30  : !hw.inout<i4>
    sv.assign %next_30, %1879 : i4
    %1880 = comb.icmp eq %1879, %c0_i4 : i4
    %1881 = comb.and %1880, %1631 : i1
    %1882 = comb.extract %1879 from 3 : (i4) -> i1
    %1883 = comb.or %1882, %slots_31.io_valid : i1
    %1884 = comb.extract %1879 from 0 : (i4) -> i3
    %1885 = comb.concat %1884, %false : i3, i1
    %1886 = comb.mux %1883, %1879, %1885 : i4
    %1887 = comb.mux %1881, %c1_i4, %1886 : i4
    %next_31 = sv.wire sym @next_31  : !hw.inout<i4>
    sv.assign %next_31, %1887 : i4
    %1888 = comb.icmp eq %1887, %c0_i4 : i4
    %1889 = comb.and %1888, %1632 : i1
    %1890 = comb.extract %1887 from 3 : (i4) -> i1
    %1891 = comb.or %1890, %slots_32.io_valid : i1
    %1892 = comb.extract %1887 from 0 : (i4) -> i3
    %1893 = comb.concat %1892, %false : i3, i1
    %1894 = comb.mux %1891, %1887, %1893 : i4
    %1895 = comb.mux %1889, %c1_i4, %1894 : i4
    %next_32 = sv.wire sym @next_32  : !hw.inout<i4>
    sv.assign %next_32, %1895 : i4
    %1896 = comb.icmp eq %1895, %c0_i4 : i4
    %1897 = comb.and %1896, %1633 : i1
    %1898 = comb.extract %1895 from 3 : (i4) -> i1
    %1899 = comb.or %1898, %slots_33.io_valid : i1
    %1900 = comb.extract %1895 from 0 : (i4) -> i3
    %1901 = comb.concat %1900, %false : i3, i1
    %1902 = comb.mux %1899, %1895, %1901 : i4
    %1903 = comb.mux %1897, %c1_i4, %1902 : i4
    %next_33 = sv.wire sym @next_33  : !hw.inout<i4>
    sv.assign %next_33, %1903 : i4
    %1904 = comb.icmp eq %1903, %c0_i4 : i4
    %1905 = comb.and %1904, %1634 : i1
    %1906 = comb.extract %1903 from 3 : (i4) -> i1
    %1907 = comb.or %1906, %slots_34.io_valid : i1
    %1908 = comb.extract %1903 from 0 : (i4) -> i3
    %1909 = comb.concat %1908, %false : i3, i1
    %1910 = comb.mux %1907, %1903, %1909 : i4
    %1911 = comb.mux %1905, %c1_i4, %1910 : i4
    %next_34 = sv.wire sym @next_34  : !hw.inout<i4>
    sv.assign %next_34, %1911 : i4
    %1912 = comb.icmp eq %1911, %c0_i4 : i4
    %1913 = comb.and %1912, %1635 : i1
    %1914 = comb.extract %1911 from 3 : (i4) -> i1
    %1915 = comb.or %1914, %slots_35.io_valid : i1
    %1916 = comb.extract %1911 from 0 : (i4) -> i3
    %1917 = comb.concat %1916, %false : i3, i1
    %1918 = comb.mux %1915, %1911, %1917 : i4
    %1919 = comb.mux %1913, %c1_i4, %1918 : i4
    %next_35 = sv.wire sym @next_35  : !hw.inout<i4>
    sv.assign %next_35, %1919 : i4
    %1920 = comb.icmp eq %1919, %c0_i4 : i4
    %1921 = comb.and %1920, %1636 : i1
    %1922 = comb.extract %1919 from 3 : (i4) -> i1
    %1923 = comb.or %1922, %slots_36.io_valid : i1
    %1924 = comb.extract %1919 from 0 : (i4) -> i3
    %1925 = comb.concat %1924, %false : i3, i1
    %1926 = comb.mux %1923, %1919, %1925 : i4
    %1927 = comb.mux %1921, %c1_i4, %1926 : i4
    %next_36 = sv.wire sym @next_36  : !hw.inout<i4>
    sv.assign %next_36, %1927 : i4
    %1928 = comb.icmp eq %1927, %c0_i4 : i4
    %1929 = comb.and %1928, %1637 : i1
    %1930 = comb.extract %1927 from 3 : (i4) -> i1
    %1931 = comb.or %1930, %slots_37.io_valid : i1
    %1932 = comb.extract %1927 from 0 : (i4) -> i3
    %1933 = comb.concat %1932, %false : i3, i1
    %1934 = comb.mux %1931, %1927, %1933 : i4
    %1935 = comb.mux %1929, %c1_i4, %1934 : i4
    %next_37 = sv.wire sym @next_37  : !hw.inout<i4>
    sv.assign %next_37, %1935 : i4
    %1936 = comb.icmp eq %1935, %c0_i4 : i4
    %1937 = comb.and %1936, %1638 : i1
    %1938 = comb.extract %1935 from 3 : (i4) -> i1
    %1939 = comb.or %1938, %slots_38.io_valid : i1
    %1940 = comb.extract %1935 from 0 : (i4) -> i3
    %1941 = comb.concat %1940, %false : i3, i1
    %1942 = comb.mux %1939, %1935, %1941 : i4
    %1943 = comb.mux %1937, %c1_i4, %1942 : i4
    %next_38 = sv.wire sym @next_38  : !hw.inout<i4>
    sv.assign %next_38, %1943 : i4
    %1944 = comb.icmp eq %1943, %c0_i4 : i4
    %1945 = comb.and %1944, %1639 : i1
    %1946 = comb.extract %1943 from 3 : (i4) -> i1
    %1947 = comb.or %1946, %slots_39.io_valid : i1
    %1948 = comb.extract %1943 from 0 : (i4) -> i3
    %1949 = comb.concat %1948, %false : i3, i1
    %1950 = comb.mux %1947, %1943, %1949 : i4
    %1951 = comb.mux %1945, %c1_i4, %1950 : i4
    %next_39 = sv.wire sym @next_39  : !hw.inout<i4>
    sv.assign %next_39, %1951 : i4
    %1952 = comb.icmp eq %1951, %c0_i4 : i4
    %1953 = comb.and %1952, %1640 : i1
    %1954 = comb.extract %1951 from 3 : (i4) -> i1
    %1955 = comb.or %1954, %io_dis_uops_0_valid : i1
    %1956 = comb.extract %1951 from 0 : (i4) -> i3
    %1957 = comb.concat %1956, %false : i3, i1
    %1958 = comb.mux %1955, %1951, %1957 : i4
    %1959 = comb.mux %1953, %c1_i4, %1958 : i4
    %next_40 = sv.wire sym @next_40  : !hw.inout<i4>
    sv.assign %next_40, %1959 : i4
    %1960 = comb.icmp eq %1959, %c0_i4 : i4
    %1961 = comb.and %1960, %1641 : i1
    %1962 = comb.extract %1959 from 3 : (i4) -> i1
    %1963 = comb.or %1962, %io_dis_uops_1_valid : i1
    %1964 = comb.extract %1959 from 0 : (i4) -> i3
    %1965 = comb.concat %1964, %false : i3, i1
    %1966 = comb.mux %1963, %1959, %1965 : i4
    %1967 = comb.mux %1961, %c1_i4, %1966 : i4
    %next_41 = sv.wire sym @next_41  : !hw.inout<i4>
    sv.assign %next_41, %1967 : i4
    %1968 = comb.icmp eq %1967, %c0_i4 : i4
    %1969 = comb.and %1968, %1642 : i1
    %1970 = comb.extract %1967 from 3 : (i4) -> i1
    %1971 = comb.or %1970, %io_dis_uops_2_valid : i1
    %1972 = comb.extract %1967 from 0 : (i4) -> i3
    %1973 = comb.concat %1972, %false : i3, i1
    %1974 = comb.mux %1971, %1967, %1973 : i4
    %1975 = comb.mux %1969, %c1_i4, %1974 : i4
    %1976 = comb.xor %io_dis_uops_0_bits_exception, %true {sv.namehint = "_will_be_valid_T"} : i1
    %1977 = comb.xor %io_dis_uops_0_bits_is_fence, %true {sv.namehint = "_will_be_valid_T_2"} : i1
    %1978 = comb.xor %io_dis_uops_0_bits_is_fencei, %true {sv.namehint = "_will_be_valid_T_4"} : i1
    %1979 = comb.and %io_dis_uops_0_valid, %1976, %1977, %1978 {sv.namehint = "_will_be_valid_40"} : i1
    %will_be_valid_40 = sv.wire sym @will_be_valid_40  : !hw.inout<i1>
    sv.assign %will_be_valid_40, %1979 : i1
    %1980 = comb.xor %io_dis_uops_1_bits_exception, %true {sv.namehint = "_will_be_valid_T_5"} : i1
    %1981 = comb.xor %io_dis_uops_1_bits_is_fence, %true {sv.namehint = "_will_be_valid_T_7"} : i1
    %1982 = comb.xor %io_dis_uops_1_bits_is_fencei, %true {sv.namehint = "_will_be_valid_T_9"} : i1
    %1983 = comb.and %io_dis_uops_1_valid, %1980, %1981, %1982 {sv.namehint = "_will_be_valid_41"} : i1
    %will_be_valid_41 = sv.wire sym @will_be_valid_41  : !hw.inout<i1>
    sv.assign %will_be_valid_41, %1983 : i1
    %1984 = comb.xor %io_dis_uops_2_bits_exception, %true {sv.namehint = "_will_be_valid_T_10"} : i1
    %1985 = comb.xor %io_dis_uops_2_bits_is_fence, %true {sv.namehint = "_will_be_valid_T_12"} : i1
    %1986 = comb.xor %io_dis_uops_2_bits_is_fencei, %true {sv.namehint = "_will_be_valid_T_14"} : i1
    %1987 = comb.and %io_dis_uops_2_valid, %1984, %1985, %1986 {sv.namehint = "_will_be_valid_42"} : i1
    %will_be_valid_42 = sv.wire sym @will_be_valid_42  : !hw.inout<i1>
    sv.assign %will_be_valid_42, %1987 : i1
    %1988 = comb.xor %io_dis_uops_3_bits_exception, %true {sv.namehint = "_will_be_valid_T_15"} : i1
    %1989 = comb.xor %io_dis_uops_3_bits_is_fence, %true {sv.namehint = "_will_be_valid_T_17"} : i1
    %1990 = comb.xor %io_dis_uops_3_bits_is_fencei, %true {sv.namehint = "_will_be_valid_T_19"} : i1
    %1991 = comb.and %io_dis_uops_3_valid, %1988, %1989, %1990 {sv.namehint = "_will_be_valid_43"} : i1
    %will_be_valid_43 = sv.wire sym @will_be_valid_43  : !hw.inout<i1>
    sv.assign %will_be_valid_43, %1991 : i1
    %issue_slots_1_will_be_valid = sv.wire sym @issue_slots_1_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_1_will_be_valid, %slots_1.io_will_be_valid : i1
    %1992 = comb.and %1600, %slots_1.io_will_be_valid : i1
    %issue_slots_1_out_uop_fp_val = sv.wire sym @issue_slots_1_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_fp_val, %slots_1.io_out_uop_fp_val : i1
    %issue_slots_1_out_uop_lrs2_rtype = sv.wire sym @issue_slots_1_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_1_out_uop_lrs2_rtype, %slots_1.io_out_uop_lrs2_rtype : i2
    %issue_slots_1_out_uop_lrs1_rtype = sv.wire sym @issue_slots_1_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_1_out_uop_lrs1_rtype, %slots_1.io_out_uop_lrs1_rtype : i2
    %issue_slots_1_out_uop_dst_rtype = sv.wire sym @issue_slots_1_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_1_out_uop_dst_rtype, %slots_1.io_out_uop_dst_rtype : i2
    %issue_slots_1_out_uop_ldst_val = sv.wire sym @issue_slots_1_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_ldst_val, %slots_1.io_out_uop_ldst_val : i1
    %issue_slots_1_out_uop_uses_stq = sv.wire sym @issue_slots_1_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_uses_stq, %slots_1.io_out_uop_uses_stq : i1
    %issue_slots_1_out_uop_uses_ldq = sv.wire sym @issue_slots_1_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_uses_ldq, %slots_1.io_out_uop_uses_ldq : i1
    %issue_slots_1_out_uop_is_amo = sv.wire sym @issue_slots_1_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_is_amo, %slots_1.io_out_uop_is_amo : i1
    %issue_slots_1_out_uop_is_fence = sv.wire sym @issue_slots_1_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_is_fence, %slots_1.io_out_uop_is_fence : i1
    %issue_slots_1_out_uop_mem_signed = sv.wire sym @issue_slots_1_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_mem_signed, %slots_1.io_out_uop_mem_signed : i1
    %issue_slots_1_out_uop_mem_size = sv.wire sym @issue_slots_1_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_1_out_uop_mem_size, %slots_1.io_out_uop_mem_size : i2
    %issue_slots_1_out_uop_mem_cmd = sv.wire sym @issue_slots_1_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_1_out_uop_mem_cmd, %slots_1.io_out_uop_mem_cmd : i5
    %issue_slots_1_out_uop_bypassable = sv.wire sym @issue_slots_1_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_bypassable, %slots_1.io_out_uop_bypassable : i1
    %issue_slots_1_out_uop_ppred_busy = sv.wire sym @issue_slots_1_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_ppred_busy, %slots_1.io_out_uop_ppred_busy : i1
    %issue_slots_1_out_uop_prs3_busy = sv.wire sym @issue_slots_1_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_prs3_busy, %slots_1.io_out_uop_prs3_busy : i1
    %issue_slots_1_out_uop_prs2_busy = sv.wire sym @issue_slots_1_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_prs2_busy, %slots_1.io_out_uop_prs2_busy : i1
    %issue_slots_1_out_uop_prs1_busy = sv.wire sym @issue_slots_1_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_prs1_busy, %slots_1.io_out_uop_prs1_busy : i1
    %issue_slots_1_out_uop_prs3 = sv.wire sym @issue_slots_1_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_1_out_uop_prs3, %slots_1.io_out_uop_prs3 : i7
    %issue_slots_1_out_uop_prs2 = sv.wire sym @issue_slots_1_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_1_out_uop_prs2, %slots_1.io_out_uop_prs2 : i7
    %issue_slots_1_out_uop_prs1 = sv.wire sym @issue_slots_1_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_1_out_uop_prs1, %slots_1.io_out_uop_prs1 : i7
    %issue_slots_1_out_uop_pdst = sv.wire sym @issue_slots_1_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_1_out_uop_pdst, %slots_1.io_out_uop_pdst : i7
    %issue_slots_1_out_uop_stq_idx = sv.wire sym @issue_slots_1_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_1_out_uop_stq_idx, %slots_1.io_out_uop_stq_idx : i5
    %issue_slots_1_out_uop_ldq_idx = sv.wire sym @issue_slots_1_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_1_out_uop_ldq_idx, %slots_1.io_out_uop_ldq_idx : i5
    %issue_slots_1_out_uop_rob_idx = sv.wire sym @issue_slots_1_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_1_out_uop_rob_idx, %slots_1.io_out_uop_rob_idx : i7
    %issue_slots_1_out_uop_imm_packed = sv.wire sym @issue_slots_1_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_1_out_uop_imm_packed, %slots_1.io_out_uop_imm_packed : i20
    %issue_slots_1_out_uop_taken = sv.wire sym @issue_slots_1_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_taken, %slots_1.io_out_uop_taken : i1
    %issue_slots_1_out_uop_pc_lob = sv.wire sym @issue_slots_1_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_1_out_uop_pc_lob, %slots_1.io_out_uop_pc_lob : i6
    %issue_slots_1_out_uop_edge_inst = sv.wire sym @issue_slots_1_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_edge_inst, %slots_1.io_out_uop_edge_inst : i1
    %issue_slots_1_out_uop_ftq_idx = sv.wire sym @issue_slots_1_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_1_out_uop_ftq_idx, %slots_1.io_out_uop_ftq_idx : i6
    %issue_slots_1_out_uop_br_tag = sv.wire sym @issue_slots_1_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_1_out_uop_br_tag, %slots_1.io_out_uop_br_tag : i5
    %issue_slots_1_out_uop_br_mask = sv.wire sym @issue_slots_1_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_1_out_uop_br_mask, %slots_1.io_out_uop_br_mask : i20
    %issue_slots_1_out_uop_is_sfb = sv.wire sym @issue_slots_1_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_is_sfb, %slots_1.io_out_uop_is_sfb : i1
    %issue_slots_1_out_uop_is_jal = sv.wire sym @issue_slots_1_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_is_jal, %slots_1.io_out_uop_is_jal : i1
    %issue_slots_1_out_uop_is_jalr = sv.wire sym @issue_slots_1_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_is_jalr, %slots_1.io_out_uop_is_jalr : i1
    %issue_slots_1_out_uop_is_br = sv.wire sym @issue_slots_1_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_is_br, %slots_1.io_out_uop_is_br : i1
    %issue_slots_1_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_1_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_iw_p2_poisoned, %slots_1.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_1_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_1_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_iw_p1_poisoned, %slots_1.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_1_out_uop_iw_state = sv.wire sym @issue_slots_1_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_1_out_uop_iw_state, %slots_1.io_out_uop_iw_state : i2
    %issue_slots_1_out_uop_fu_code = sv.wire sym @issue_slots_1_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_1_out_uop_fu_code, %slots_1.io_out_uop_fu_code : i10
    %issue_slots_1_out_uop_is_rvc = sv.wire sym @issue_slots_1_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_1_out_uop_is_rvc, %slots_1.io_out_uop_is_rvc : i1
    %issue_slots_1_out_uop_uopc = sv.wire sym @issue_slots_1_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_1_out_uop_uopc, %slots_1.io_out_uop_uopc : i7
    %1993 = comb.extract %1648 from 0 : (i4) -> i2
    %1994 = comb.icmp eq %1993, %c-2_i2 : i2
    %issue_slots_2_will_be_valid = sv.wire sym @issue_slots_2_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_2_will_be_valid, %slots_2.io_will_be_valid : i1
    %1995 = comb.mux %1994, %slots_2.io_will_be_valid, %1992 : i1
    %issue_slots_2_out_uop_fp_val = sv.wire sym @issue_slots_2_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_fp_val, %slots_2.io_out_uop_fp_val : i1
    %1996 = comb.mux %1994, %slots_2.io_out_uop_fp_val, %slots_1.io_out_uop_fp_val : i1
    %issue_slots_2_out_uop_lrs2_rtype = sv.wire sym @issue_slots_2_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_2_out_uop_lrs2_rtype, %slots_2.io_out_uop_lrs2_rtype : i2
    %1997 = comb.mux %1994, %slots_2.io_out_uop_lrs2_rtype, %slots_1.io_out_uop_lrs2_rtype : i2
    %issue_slots_2_out_uop_lrs1_rtype = sv.wire sym @issue_slots_2_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_2_out_uop_lrs1_rtype, %slots_2.io_out_uop_lrs1_rtype : i2
    %1998 = comb.mux %1994, %slots_2.io_out_uop_lrs1_rtype, %slots_1.io_out_uop_lrs1_rtype : i2
    %issue_slots_2_out_uop_dst_rtype = sv.wire sym @issue_slots_2_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_2_out_uop_dst_rtype, %slots_2.io_out_uop_dst_rtype : i2
    %1999 = comb.mux %1994, %slots_2.io_out_uop_dst_rtype, %slots_1.io_out_uop_dst_rtype : i2
    %issue_slots_2_out_uop_ldst_val = sv.wire sym @issue_slots_2_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_ldst_val, %slots_2.io_out_uop_ldst_val : i1
    %2000 = comb.mux %1994, %slots_2.io_out_uop_ldst_val, %slots_1.io_out_uop_ldst_val : i1
    %issue_slots_2_out_uop_uses_stq = sv.wire sym @issue_slots_2_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_uses_stq, %slots_2.io_out_uop_uses_stq : i1
    %2001 = comb.mux %1994, %slots_2.io_out_uop_uses_stq, %slots_1.io_out_uop_uses_stq : i1
    %issue_slots_2_out_uop_uses_ldq = sv.wire sym @issue_slots_2_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_uses_ldq, %slots_2.io_out_uop_uses_ldq : i1
    %2002 = comb.mux %1994, %slots_2.io_out_uop_uses_ldq, %slots_1.io_out_uop_uses_ldq : i1
    %issue_slots_2_out_uop_is_amo = sv.wire sym @issue_slots_2_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_is_amo, %slots_2.io_out_uop_is_amo : i1
    %2003 = comb.mux %1994, %slots_2.io_out_uop_is_amo, %slots_1.io_out_uop_is_amo : i1
    %issue_slots_2_out_uop_is_fence = sv.wire sym @issue_slots_2_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_is_fence, %slots_2.io_out_uop_is_fence : i1
    %2004 = comb.mux %1994, %slots_2.io_out_uop_is_fence, %slots_1.io_out_uop_is_fence : i1
    %issue_slots_2_out_uop_mem_signed = sv.wire sym @issue_slots_2_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_mem_signed, %slots_2.io_out_uop_mem_signed : i1
    %2005 = comb.mux %1994, %slots_2.io_out_uop_mem_signed, %slots_1.io_out_uop_mem_signed : i1
    %issue_slots_2_out_uop_mem_size = sv.wire sym @issue_slots_2_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_2_out_uop_mem_size, %slots_2.io_out_uop_mem_size : i2
    %2006 = comb.mux %1994, %slots_2.io_out_uop_mem_size, %slots_1.io_out_uop_mem_size : i2
    %issue_slots_2_out_uop_mem_cmd = sv.wire sym @issue_slots_2_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_2_out_uop_mem_cmd, %slots_2.io_out_uop_mem_cmd : i5
    %2007 = comb.mux %1994, %slots_2.io_out_uop_mem_cmd, %slots_1.io_out_uop_mem_cmd : i5
    %issue_slots_2_out_uop_bypassable = sv.wire sym @issue_slots_2_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_bypassable, %slots_2.io_out_uop_bypassable : i1
    %2008 = comb.mux %1994, %slots_2.io_out_uop_bypassable, %slots_1.io_out_uop_bypassable : i1
    %issue_slots_2_out_uop_ppred_busy = sv.wire sym @issue_slots_2_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_ppred_busy, %slots_2.io_out_uop_ppred_busy : i1
    %2009 = comb.mux %1994, %slots_2.io_out_uop_ppred_busy, %slots_1.io_out_uop_ppred_busy : i1
    %issue_slots_2_out_uop_prs3_busy = sv.wire sym @issue_slots_2_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_prs3_busy, %slots_2.io_out_uop_prs3_busy : i1
    %2010 = comb.mux %1994, %slots_2.io_out_uop_prs3_busy, %slots_1.io_out_uop_prs3_busy : i1
    %issue_slots_2_out_uop_prs2_busy = sv.wire sym @issue_slots_2_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_prs2_busy, %slots_2.io_out_uop_prs2_busy : i1
    %2011 = comb.mux %1994, %slots_2.io_out_uop_prs2_busy, %slots_1.io_out_uop_prs2_busy : i1
    %issue_slots_2_out_uop_prs1_busy = sv.wire sym @issue_slots_2_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_prs1_busy, %slots_2.io_out_uop_prs1_busy : i1
    %2012 = comb.mux %1994, %slots_2.io_out_uop_prs1_busy, %slots_1.io_out_uop_prs1_busy : i1
    %issue_slots_2_out_uop_prs3 = sv.wire sym @issue_slots_2_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_2_out_uop_prs3, %slots_2.io_out_uop_prs3 : i7
    %2013 = comb.mux %1994, %slots_2.io_out_uop_prs3, %slots_1.io_out_uop_prs3 : i7
    %issue_slots_2_out_uop_prs2 = sv.wire sym @issue_slots_2_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_2_out_uop_prs2, %slots_2.io_out_uop_prs2 : i7
    %2014 = comb.mux %1994, %slots_2.io_out_uop_prs2, %slots_1.io_out_uop_prs2 : i7
    %issue_slots_2_out_uop_prs1 = sv.wire sym @issue_slots_2_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_2_out_uop_prs1, %slots_2.io_out_uop_prs1 : i7
    %2015 = comb.mux %1994, %slots_2.io_out_uop_prs1, %slots_1.io_out_uop_prs1 : i7
    %issue_slots_2_out_uop_pdst = sv.wire sym @issue_slots_2_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_2_out_uop_pdst, %slots_2.io_out_uop_pdst : i7
    %2016 = comb.mux %1994, %slots_2.io_out_uop_pdst, %slots_1.io_out_uop_pdst : i7
    %issue_slots_2_out_uop_stq_idx = sv.wire sym @issue_slots_2_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_2_out_uop_stq_idx, %slots_2.io_out_uop_stq_idx : i5
    %2017 = comb.mux %1994, %slots_2.io_out_uop_stq_idx, %slots_1.io_out_uop_stq_idx : i5
    %issue_slots_2_out_uop_ldq_idx = sv.wire sym @issue_slots_2_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_2_out_uop_ldq_idx, %slots_2.io_out_uop_ldq_idx : i5
    %2018 = comb.mux %1994, %slots_2.io_out_uop_ldq_idx, %slots_1.io_out_uop_ldq_idx : i5
    %issue_slots_2_out_uop_rob_idx = sv.wire sym @issue_slots_2_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_2_out_uop_rob_idx, %slots_2.io_out_uop_rob_idx : i7
    %2019 = comb.mux %1994, %slots_2.io_out_uop_rob_idx, %slots_1.io_out_uop_rob_idx : i7
    %issue_slots_2_out_uop_imm_packed = sv.wire sym @issue_slots_2_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_2_out_uop_imm_packed, %slots_2.io_out_uop_imm_packed : i20
    %2020 = comb.mux %1994, %slots_2.io_out_uop_imm_packed, %slots_1.io_out_uop_imm_packed : i20
    %issue_slots_2_out_uop_taken = sv.wire sym @issue_slots_2_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_taken, %slots_2.io_out_uop_taken : i1
    %2021 = comb.mux %1994, %slots_2.io_out_uop_taken, %slots_1.io_out_uop_taken : i1
    %issue_slots_2_out_uop_pc_lob = sv.wire sym @issue_slots_2_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_2_out_uop_pc_lob, %slots_2.io_out_uop_pc_lob : i6
    %2022 = comb.mux %1994, %slots_2.io_out_uop_pc_lob, %slots_1.io_out_uop_pc_lob : i6
    %issue_slots_2_out_uop_edge_inst = sv.wire sym @issue_slots_2_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_edge_inst, %slots_2.io_out_uop_edge_inst : i1
    %2023 = comb.mux %1994, %slots_2.io_out_uop_edge_inst, %slots_1.io_out_uop_edge_inst : i1
    %issue_slots_2_out_uop_ftq_idx = sv.wire sym @issue_slots_2_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_2_out_uop_ftq_idx, %slots_2.io_out_uop_ftq_idx : i6
    %2024 = comb.mux %1994, %slots_2.io_out_uop_ftq_idx, %slots_1.io_out_uop_ftq_idx : i6
    %issue_slots_2_out_uop_br_tag = sv.wire sym @issue_slots_2_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_2_out_uop_br_tag, %slots_2.io_out_uop_br_tag : i5
    %2025 = comb.mux %1994, %slots_2.io_out_uop_br_tag, %slots_1.io_out_uop_br_tag : i5
    %issue_slots_2_out_uop_br_mask = sv.wire sym @issue_slots_2_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_2_out_uop_br_mask, %slots_2.io_out_uop_br_mask : i20
    %2026 = comb.mux %1994, %slots_2.io_out_uop_br_mask, %slots_1.io_out_uop_br_mask : i20
    %issue_slots_2_out_uop_is_sfb = sv.wire sym @issue_slots_2_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_is_sfb, %slots_2.io_out_uop_is_sfb : i1
    %2027 = comb.mux %1994, %slots_2.io_out_uop_is_sfb, %slots_1.io_out_uop_is_sfb : i1
    %issue_slots_2_out_uop_is_jal = sv.wire sym @issue_slots_2_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_is_jal, %slots_2.io_out_uop_is_jal : i1
    %2028 = comb.mux %1994, %slots_2.io_out_uop_is_jal, %slots_1.io_out_uop_is_jal : i1
    %issue_slots_2_out_uop_is_jalr = sv.wire sym @issue_slots_2_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_is_jalr, %slots_2.io_out_uop_is_jalr : i1
    %2029 = comb.mux %1994, %slots_2.io_out_uop_is_jalr, %slots_1.io_out_uop_is_jalr : i1
    %issue_slots_2_out_uop_is_br = sv.wire sym @issue_slots_2_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_is_br, %slots_2.io_out_uop_is_br : i1
    %2030 = comb.mux %1994, %slots_2.io_out_uop_is_br, %slots_1.io_out_uop_is_br : i1
    %issue_slots_2_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_2_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_iw_p2_poisoned, %slots_2.io_out_uop_iw_p2_poisoned : i1
    %2031 = comb.mux %1994, %slots_2.io_out_uop_iw_p2_poisoned, %slots_1.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_2_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_2_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_iw_p1_poisoned, %slots_2.io_out_uop_iw_p1_poisoned : i1
    %2032 = comb.mux %1994, %slots_2.io_out_uop_iw_p1_poisoned, %slots_1.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_2_out_uop_iw_state = sv.wire sym @issue_slots_2_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_2_out_uop_iw_state, %slots_2.io_out_uop_iw_state : i2
    %2033 = comb.mux %1994, %slots_2.io_out_uop_iw_state, %slots_1.io_out_uop_iw_state : i2
    %issue_slots_2_out_uop_fu_code = sv.wire sym @issue_slots_2_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_2_out_uop_fu_code, %slots_2.io_out_uop_fu_code : i10
    %2034 = comb.mux %1994, %slots_2.io_out_uop_fu_code, %slots_1.io_out_uop_fu_code : i10
    %issue_slots_2_out_uop_is_rvc = sv.wire sym @issue_slots_2_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_2_out_uop_is_rvc, %slots_2.io_out_uop_is_rvc : i1
    %2035 = comb.mux %1994, %slots_2.io_out_uop_is_rvc, %slots_1.io_out_uop_is_rvc : i1
    %issue_slots_2_out_uop_uopc = sv.wire sym @issue_slots_2_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_2_out_uop_uopc, %slots_2.io_out_uop_uopc : i7
    %2036 = comb.mux %1994, %slots_2.io_out_uop_uopc, %slots_1.io_out_uop_uopc : i7
    %2037 = comb.icmp eq %1655, %c4_i4 : i4
    %issue_slots_3_will_be_valid = sv.wire sym @issue_slots_3_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_3_will_be_valid, %slots_3.io_will_be_valid : i1
    %2038 = comb.mux %2037, %slots_3.io_will_be_valid, %1995 : i1
    %issue_slots_3_out_uop_fp_val = sv.wire sym @issue_slots_3_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_fp_val, %slots_3.io_out_uop_fp_val : i1
    %2039 = comb.mux %2037, %slots_3.io_out_uop_fp_val, %1996 : i1
    %issue_slots_3_out_uop_lrs2_rtype = sv.wire sym @issue_slots_3_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_3_out_uop_lrs2_rtype, %slots_3.io_out_uop_lrs2_rtype : i2
    %2040 = comb.mux %2037, %slots_3.io_out_uop_lrs2_rtype, %1997 : i2
    %issue_slots_3_out_uop_lrs1_rtype = sv.wire sym @issue_slots_3_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_3_out_uop_lrs1_rtype, %slots_3.io_out_uop_lrs1_rtype : i2
    %2041 = comb.mux %2037, %slots_3.io_out_uop_lrs1_rtype, %1998 : i2
    %issue_slots_3_out_uop_dst_rtype = sv.wire sym @issue_slots_3_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_3_out_uop_dst_rtype, %slots_3.io_out_uop_dst_rtype : i2
    %2042 = comb.mux %2037, %slots_3.io_out_uop_dst_rtype, %1999 : i2
    %issue_slots_3_out_uop_ldst_val = sv.wire sym @issue_slots_3_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_ldst_val, %slots_3.io_out_uop_ldst_val : i1
    %2043 = comb.mux %2037, %slots_3.io_out_uop_ldst_val, %2000 : i1
    %issue_slots_3_out_uop_uses_stq = sv.wire sym @issue_slots_3_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_uses_stq, %slots_3.io_out_uop_uses_stq : i1
    %2044 = comb.mux %2037, %slots_3.io_out_uop_uses_stq, %2001 : i1
    %issue_slots_3_out_uop_uses_ldq = sv.wire sym @issue_slots_3_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_uses_ldq, %slots_3.io_out_uop_uses_ldq : i1
    %2045 = comb.mux %2037, %slots_3.io_out_uop_uses_ldq, %2002 : i1
    %issue_slots_3_out_uop_is_amo = sv.wire sym @issue_slots_3_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_is_amo, %slots_3.io_out_uop_is_amo : i1
    %2046 = comb.mux %2037, %slots_3.io_out_uop_is_amo, %2003 : i1
    %issue_slots_3_out_uop_is_fence = sv.wire sym @issue_slots_3_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_is_fence, %slots_3.io_out_uop_is_fence : i1
    %2047 = comb.mux %2037, %slots_3.io_out_uop_is_fence, %2004 : i1
    %issue_slots_3_out_uop_mem_signed = sv.wire sym @issue_slots_3_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_mem_signed, %slots_3.io_out_uop_mem_signed : i1
    %2048 = comb.mux %2037, %slots_3.io_out_uop_mem_signed, %2005 : i1
    %issue_slots_3_out_uop_mem_size = sv.wire sym @issue_slots_3_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_3_out_uop_mem_size, %slots_3.io_out_uop_mem_size : i2
    %2049 = comb.mux %2037, %slots_3.io_out_uop_mem_size, %2006 : i2
    %issue_slots_3_out_uop_mem_cmd = sv.wire sym @issue_slots_3_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_3_out_uop_mem_cmd, %slots_3.io_out_uop_mem_cmd : i5
    %2050 = comb.mux %2037, %slots_3.io_out_uop_mem_cmd, %2007 : i5
    %issue_slots_3_out_uop_bypassable = sv.wire sym @issue_slots_3_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_bypassable, %slots_3.io_out_uop_bypassable : i1
    %2051 = comb.mux %2037, %slots_3.io_out_uop_bypassable, %2008 : i1
    %issue_slots_3_out_uop_ppred_busy = sv.wire sym @issue_slots_3_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_ppred_busy, %slots_3.io_out_uop_ppred_busy : i1
    %2052 = comb.mux %2037, %slots_3.io_out_uop_ppred_busy, %2009 : i1
    %issue_slots_3_out_uop_prs3_busy = sv.wire sym @issue_slots_3_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_prs3_busy, %slots_3.io_out_uop_prs3_busy : i1
    %2053 = comb.mux %2037, %slots_3.io_out_uop_prs3_busy, %2010 : i1
    %issue_slots_3_out_uop_prs2_busy = sv.wire sym @issue_slots_3_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_prs2_busy, %slots_3.io_out_uop_prs2_busy : i1
    %2054 = comb.mux %2037, %slots_3.io_out_uop_prs2_busy, %2011 : i1
    %issue_slots_3_out_uop_prs1_busy = sv.wire sym @issue_slots_3_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_prs1_busy, %slots_3.io_out_uop_prs1_busy : i1
    %2055 = comb.mux %2037, %slots_3.io_out_uop_prs1_busy, %2012 : i1
    %issue_slots_3_out_uop_prs3 = sv.wire sym @issue_slots_3_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_3_out_uop_prs3, %slots_3.io_out_uop_prs3 : i7
    %2056 = comb.mux %2037, %slots_3.io_out_uop_prs3, %2013 : i7
    %issue_slots_3_out_uop_prs2 = sv.wire sym @issue_slots_3_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_3_out_uop_prs2, %slots_3.io_out_uop_prs2 : i7
    %2057 = comb.mux %2037, %slots_3.io_out_uop_prs2, %2014 : i7
    %issue_slots_3_out_uop_prs1 = sv.wire sym @issue_slots_3_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_3_out_uop_prs1, %slots_3.io_out_uop_prs1 : i7
    %2058 = comb.mux %2037, %slots_3.io_out_uop_prs1, %2015 : i7
    %issue_slots_3_out_uop_pdst = sv.wire sym @issue_slots_3_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_3_out_uop_pdst, %slots_3.io_out_uop_pdst : i7
    %2059 = comb.mux %2037, %slots_3.io_out_uop_pdst, %2016 : i7
    %issue_slots_3_out_uop_stq_idx = sv.wire sym @issue_slots_3_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_3_out_uop_stq_idx, %slots_3.io_out_uop_stq_idx : i5
    %2060 = comb.mux %2037, %slots_3.io_out_uop_stq_idx, %2017 : i5
    %issue_slots_3_out_uop_ldq_idx = sv.wire sym @issue_slots_3_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_3_out_uop_ldq_idx, %slots_3.io_out_uop_ldq_idx : i5
    %2061 = comb.mux %2037, %slots_3.io_out_uop_ldq_idx, %2018 : i5
    %issue_slots_3_out_uop_rob_idx = sv.wire sym @issue_slots_3_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_3_out_uop_rob_idx, %slots_3.io_out_uop_rob_idx : i7
    %2062 = comb.mux %2037, %slots_3.io_out_uop_rob_idx, %2019 : i7
    %issue_slots_3_out_uop_imm_packed = sv.wire sym @issue_slots_3_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_3_out_uop_imm_packed, %slots_3.io_out_uop_imm_packed : i20
    %2063 = comb.mux %2037, %slots_3.io_out_uop_imm_packed, %2020 : i20
    %issue_slots_3_out_uop_taken = sv.wire sym @issue_slots_3_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_taken, %slots_3.io_out_uop_taken : i1
    %2064 = comb.mux %2037, %slots_3.io_out_uop_taken, %2021 : i1
    %issue_slots_3_out_uop_pc_lob = sv.wire sym @issue_slots_3_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_3_out_uop_pc_lob, %slots_3.io_out_uop_pc_lob : i6
    %2065 = comb.mux %2037, %slots_3.io_out_uop_pc_lob, %2022 : i6
    %issue_slots_3_out_uop_edge_inst = sv.wire sym @issue_slots_3_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_edge_inst, %slots_3.io_out_uop_edge_inst : i1
    %2066 = comb.mux %2037, %slots_3.io_out_uop_edge_inst, %2023 : i1
    %issue_slots_3_out_uop_ftq_idx = sv.wire sym @issue_slots_3_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_3_out_uop_ftq_idx, %slots_3.io_out_uop_ftq_idx : i6
    %2067 = comb.mux %2037, %slots_3.io_out_uop_ftq_idx, %2024 : i6
    %issue_slots_3_out_uop_br_tag = sv.wire sym @issue_slots_3_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_3_out_uop_br_tag, %slots_3.io_out_uop_br_tag : i5
    %2068 = comb.mux %2037, %slots_3.io_out_uop_br_tag, %2025 : i5
    %issue_slots_3_out_uop_br_mask = sv.wire sym @issue_slots_3_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_3_out_uop_br_mask, %slots_3.io_out_uop_br_mask : i20
    %2069 = comb.mux %2037, %slots_3.io_out_uop_br_mask, %2026 : i20
    %issue_slots_3_out_uop_is_sfb = sv.wire sym @issue_slots_3_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_is_sfb, %slots_3.io_out_uop_is_sfb : i1
    %2070 = comb.mux %2037, %slots_3.io_out_uop_is_sfb, %2027 : i1
    %issue_slots_3_out_uop_is_jal = sv.wire sym @issue_slots_3_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_is_jal, %slots_3.io_out_uop_is_jal : i1
    %2071 = comb.mux %2037, %slots_3.io_out_uop_is_jal, %2028 : i1
    %issue_slots_3_out_uop_is_jalr = sv.wire sym @issue_slots_3_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_is_jalr, %slots_3.io_out_uop_is_jalr : i1
    %2072 = comb.mux %2037, %slots_3.io_out_uop_is_jalr, %2029 : i1
    %issue_slots_3_out_uop_is_br = sv.wire sym @issue_slots_3_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_is_br, %slots_3.io_out_uop_is_br : i1
    %2073 = comb.mux %2037, %slots_3.io_out_uop_is_br, %2030 : i1
    %issue_slots_3_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_3_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_iw_p2_poisoned, %slots_3.io_out_uop_iw_p2_poisoned : i1
    %2074 = comb.mux %2037, %slots_3.io_out_uop_iw_p2_poisoned, %2031 : i1
    %issue_slots_3_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_3_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_iw_p1_poisoned, %slots_3.io_out_uop_iw_p1_poisoned : i1
    %2075 = comb.mux %2037, %slots_3.io_out_uop_iw_p1_poisoned, %2032 : i1
    %issue_slots_3_out_uop_iw_state = sv.wire sym @issue_slots_3_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_3_out_uop_iw_state, %slots_3.io_out_uop_iw_state : i2
    %2076 = comb.mux %2037, %slots_3.io_out_uop_iw_state, %2033 : i2
    %issue_slots_3_out_uop_fu_code = sv.wire sym @issue_slots_3_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_3_out_uop_fu_code, %slots_3.io_out_uop_fu_code : i10
    %2077 = comb.mux %2037, %slots_3.io_out_uop_fu_code, %2034 : i10
    %issue_slots_3_out_uop_is_rvc = sv.wire sym @issue_slots_3_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_3_out_uop_is_rvc, %slots_3.io_out_uop_is_rvc : i1
    %2078 = comb.mux %2037, %slots_3.io_out_uop_is_rvc, %2035 : i1
    %issue_slots_3_out_uop_uopc = sv.wire sym @issue_slots_3_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_3_out_uop_uopc, %slots_3.io_out_uop_uopc : i7
    %2079 = comb.mux %2037, %slots_3.io_out_uop_uopc, %2036 : i7
    %2080 = comb.icmp eq %1663, %c-8_i4 : i4
    %issue_slots_4_will_be_valid = sv.wire sym @issue_slots_4_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_4_will_be_valid, %slots_4.io_will_be_valid : i1
    %2081 = comb.mux %2080, %slots_4.io_will_be_valid, %2038 {sv.namehint = "_issue_slots_0_in_uop_valid"} : i1
    %issue_slots_0_in_uop_valid = sv.wire sym @issue_slots_0_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_0_in_uop_valid, %2081 : i1
    %issue_slots_4_out_uop_fp_val = sv.wire sym @issue_slots_4_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_fp_val, %slots_4.io_out_uop_fp_val : i1
    %issue_slots_4_out_uop_lrs2_rtype = sv.wire sym @issue_slots_4_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_4_out_uop_lrs2_rtype, %slots_4.io_out_uop_lrs2_rtype : i2
    %issue_slots_4_out_uop_lrs1_rtype = sv.wire sym @issue_slots_4_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_4_out_uop_lrs1_rtype, %slots_4.io_out_uop_lrs1_rtype : i2
    %issue_slots_4_out_uop_dst_rtype = sv.wire sym @issue_slots_4_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_4_out_uop_dst_rtype, %slots_4.io_out_uop_dst_rtype : i2
    %issue_slots_4_out_uop_ldst_val = sv.wire sym @issue_slots_4_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_ldst_val, %slots_4.io_out_uop_ldst_val : i1
    %issue_slots_4_out_uop_uses_stq = sv.wire sym @issue_slots_4_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_uses_stq, %slots_4.io_out_uop_uses_stq : i1
    %issue_slots_4_out_uop_uses_ldq = sv.wire sym @issue_slots_4_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_uses_ldq, %slots_4.io_out_uop_uses_ldq : i1
    %issue_slots_4_out_uop_is_amo = sv.wire sym @issue_slots_4_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_is_amo, %slots_4.io_out_uop_is_amo : i1
    %issue_slots_4_out_uop_is_fence = sv.wire sym @issue_slots_4_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_is_fence, %slots_4.io_out_uop_is_fence : i1
    %issue_slots_4_out_uop_mem_signed = sv.wire sym @issue_slots_4_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_mem_signed, %slots_4.io_out_uop_mem_signed : i1
    %issue_slots_4_out_uop_mem_size = sv.wire sym @issue_slots_4_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_4_out_uop_mem_size, %slots_4.io_out_uop_mem_size : i2
    %issue_slots_4_out_uop_mem_cmd = sv.wire sym @issue_slots_4_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_4_out_uop_mem_cmd, %slots_4.io_out_uop_mem_cmd : i5
    %issue_slots_4_out_uop_bypassable = sv.wire sym @issue_slots_4_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_bypassable, %slots_4.io_out_uop_bypassable : i1
    %issue_slots_4_out_uop_ppred_busy = sv.wire sym @issue_slots_4_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_ppred_busy, %slots_4.io_out_uop_ppred_busy : i1
    %issue_slots_4_out_uop_prs3_busy = sv.wire sym @issue_slots_4_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_prs3_busy, %slots_4.io_out_uop_prs3_busy : i1
    %issue_slots_4_out_uop_prs2_busy = sv.wire sym @issue_slots_4_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_prs2_busy, %slots_4.io_out_uop_prs2_busy : i1
    %issue_slots_4_out_uop_prs1_busy = sv.wire sym @issue_slots_4_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_prs1_busy, %slots_4.io_out_uop_prs1_busy : i1
    %issue_slots_4_out_uop_prs3 = sv.wire sym @issue_slots_4_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_4_out_uop_prs3, %slots_4.io_out_uop_prs3 : i7
    %issue_slots_4_out_uop_prs2 = sv.wire sym @issue_slots_4_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_4_out_uop_prs2, %slots_4.io_out_uop_prs2 : i7
    %issue_slots_4_out_uop_prs1 = sv.wire sym @issue_slots_4_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_4_out_uop_prs1, %slots_4.io_out_uop_prs1 : i7
    %issue_slots_4_out_uop_pdst = sv.wire sym @issue_slots_4_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_4_out_uop_pdst, %slots_4.io_out_uop_pdst : i7
    %issue_slots_4_out_uop_stq_idx = sv.wire sym @issue_slots_4_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_4_out_uop_stq_idx, %slots_4.io_out_uop_stq_idx : i5
    %issue_slots_4_out_uop_ldq_idx = sv.wire sym @issue_slots_4_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_4_out_uop_ldq_idx, %slots_4.io_out_uop_ldq_idx : i5
    %issue_slots_4_out_uop_rob_idx = sv.wire sym @issue_slots_4_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_4_out_uop_rob_idx, %slots_4.io_out_uop_rob_idx : i7
    %issue_slots_4_out_uop_imm_packed = sv.wire sym @issue_slots_4_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_4_out_uop_imm_packed, %slots_4.io_out_uop_imm_packed : i20
    %issue_slots_4_out_uop_taken = sv.wire sym @issue_slots_4_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_taken, %slots_4.io_out_uop_taken : i1
    %issue_slots_4_out_uop_pc_lob = sv.wire sym @issue_slots_4_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_4_out_uop_pc_lob, %slots_4.io_out_uop_pc_lob : i6
    %issue_slots_4_out_uop_edge_inst = sv.wire sym @issue_slots_4_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_edge_inst, %slots_4.io_out_uop_edge_inst : i1
    %issue_slots_4_out_uop_ftq_idx = sv.wire sym @issue_slots_4_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_4_out_uop_ftq_idx, %slots_4.io_out_uop_ftq_idx : i6
    %issue_slots_4_out_uop_br_tag = sv.wire sym @issue_slots_4_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_4_out_uop_br_tag, %slots_4.io_out_uop_br_tag : i5
    %issue_slots_4_out_uop_br_mask = sv.wire sym @issue_slots_4_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_4_out_uop_br_mask, %slots_4.io_out_uop_br_mask : i20
    %issue_slots_4_out_uop_is_sfb = sv.wire sym @issue_slots_4_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_is_sfb, %slots_4.io_out_uop_is_sfb : i1
    %issue_slots_4_out_uop_is_jal = sv.wire sym @issue_slots_4_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_is_jal, %slots_4.io_out_uop_is_jal : i1
    %issue_slots_4_out_uop_is_jalr = sv.wire sym @issue_slots_4_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_is_jalr, %slots_4.io_out_uop_is_jalr : i1
    %issue_slots_4_out_uop_is_br = sv.wire sym @issue_slots_4_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_is_br, %slots_4.io_out_uop_is_br : i1
    %issue_slots_4_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_4_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_iw_p2_poisoned, %slots_4.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_4_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_4_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_iw_p1_poisoned, %slots_4.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_4_out_uop_iw_state = sv.wire sym @issue_slots_4_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_4_out_uop_iw_state, %slots_4.io_out_uop_iw_state : i2
    %issue_slots_4_out_uop_fu_code = sv.wire sym @issue_slots_4_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_4_out_uop_fu_code, %slots_4.io_out_uop_fu_code : i10
    %issue_slots_4_out_uop_is_rvc = sv.wire sym @issue_slots_4_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_4_out_uop_is_rvc, %slots_4.io_out_uop_is_rvc : i1
    %issue_slots_4_out_uop_uopc = sv.wire sym @issue_slots_4_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_4_out_uop_uopc, %slots_4.io_out_uop_uopc : i7
    %2082 = comb.extract %1648 from 0 : (i4) -> i2
    %2083 = comb.icmp eq %2082, %c1_i2 : i2
    %2084 = comb.and %2083, %slots_2.io_will_be_valid : i1
    %2085 = comb.icmp eq %1655, %c2_i4 : i4
    %2086 = comb.mux %2085, %slots_3.io_will_be_valid, %2084 : i1
    %2087 = comb.mux %2085, %slots_3.io_out_uop_fp_val, %slots_2.io_out_uop_fp_val : i1
    %2088 = comb.mux %2085, %slots_3.io_out_uop_lrs2_rtype, %slots_2.io_out_uop_lrs2_rtype : i2
    %2089 = comb.mux %2085, %slots_3.io_out_uop_lrs1_rtype, %slots_2.io_out_uop_lrs1_rtype : i2
    %2090 = comb.mux %2085, %slots_3.io_out_uop_dst_rtype, %slots_2.io_out_uop_dst_rtype : i2
    %2091 = comb.mux %2085, %slots_3.io_out_uop_ldst_val, %slots_2.io_out_uop_ldst_val : i1
    %2092 = comb.mux %2085, %slots_3.io_out_uop_uses_stq, %slots_2.io_out_uop_uses_stq : i1
    %2093 = comb.mux %2085, %slots_3.io_out_uop_uses_ldq, %slots_2.io_out_uop_uses_ldq : i1
    %2094 = comb.mux %2085, %slots_3.io_out_uop_is_amo, %slots_2.io_out_uop_is_amo : i1
    %2095 = comb.mux %2085, %slots_3.io_out_uop_is_fence, %slots_2.io_out_uop_is_fence : i1
    %2096 = comb.mux %2085, %slots_3.io_out_uop_mem_signed, %slots_2.io_out_uop_mem_signed : i1
    %2097 = comb.mux %2085, %slots_3.io_out_uop_mem_size, %slots_2.io_out_uop_mem_size : i2
    %2098 = comb.mux %2085, %slots_3.io_out_uop_mem_cmd, %slots_2.io_out_uop_mem_cmd : i5
    %2099 = comb.mux %2085, %slots_3.io_out_uop_bypassable, %slots_2.io_out_uop_bypassable : i1
    %2100 = comb.mux %2085, %slots_3.io_out_uop_ppred_busy, %slots_2.io_out_uop_ppred_busy : i1
    %2101 = comb.mux %2085, %slots_3.io_out_uop_prs3_busy, %slots_2.io_out_uop_prs3_busy : i1
    %2102 = comb.mux %2085, %slots_3.io_out_uop_prs2_busy, %slots_2.io_out_uop_prs2_busy : i1
    %2103 = comb.mux %2085, %slots_3.io_out_uop_prs1_busy, %slots_2.io_out_uop_prs1_busy : i1
    %2104 = comb.mux %2085, %slots_3.io_out_uop_prs3, %slots_2.io_out_uop_prs3 : i7
    %2105 = comb.mux %2085, %slots_3.io_out_uop_prs2, %slots_2.io_out_uop_prs2 : i7
    %2106 = comb.mux %2085, %slots_3.io_out_uop_prs1, %slots_2.io_out_uop_prs1 : i7
    %2107 = comb.mux %2085, %slots_3.io_out_uop_pdst, %slots_2.io_out_uop_pdst : i7
    %2108 = comb.mux %2085, %slots_3.io_out_uop_stq_idx, %slots_2.io_out_uop_stq_idx : i5
    %2109 = comb.mux %2085, %slots_3.io_out_uop_ldq_idx, %slots_2.io_out_uop_ldq_idx : i5
    %2110 = comb.mux %2085, %slots_3.io_out_uop_rob_idx, %slots_2.io_out_uop_rob_idx : i7
    %2111 = comb.mux %2085, %slots_3.io_out_uop_imm_packed, %slots_2.io_out_uop_imm_packed : i20
    %2112 = comb.mux %2085, %slots_3.io_out_uop_taken, %slots_2.io_out_uop_taken : i1
    %2113 = comb.mux %2085, %slots_3.io_out_uop_pc_lob, %slots_2.io_out_uop_pc_lob : i6
    %2114 = comb.mux %2085, %slots_3.io_out_uop_edge_inst, %slots_2.io_out_uop_edge_inst : i1
    %2115 = comb.mux %2085, %slots_3.io_out_uop_ftq_idx, %slots_2.io_out_uop_ftq_idx : i6
    %2116 = comb.mux %2085, %slots_3.io_out_uop_br_tag, %slots_2.io_out_uop_br_tag : i5
    %2117 = comb.mux %2085, %slots_3.io_out_uop_br_mask, %slots_2.io_out_uop_br_mask : i20
    %2118 = comb.mux %2085, %slots_3.io_out_uop_is_sfb, %slots_2.io_out_uop_is_sfb : i1
    %2119 = comb.mux %2085, %slots_3.io_out_uop_is_jal, %slots_2.io_out_uop_is_jal : i1
    %2120 = comb.mux %2085, %slots_3.io_out_uop_is_jalr, %slots_2.io_out_uop_is_jalr : i1
    %2121 = comb.mux %2085, %slots_3.io_out_uop_is_br, %slots_2.io_out_uop_is_br : i1
    %2122 = comb.mux %2085, %slots_3.io_out_uop_iw_p2_poisoned, %slots_2.io_out_uop_iw_p2_poisoned : i1
    %2123 = comb.mux %2085, %slots_3.io_out_uop_iw_p1_poisoned, %slots_2.io_out_uop_iw_p1_poisoned : i1
    %2124 = comb.mux %2085, %slots_3.io_out_uop_iw_state, %slots_2.io_out_uop_iw_state : i2
    %2125 = comb.mux %2085, %slots_3.io_out_uop_fu_code, %slots_2.io_out_uop_fu_code : i10
    %2126 = comb.mux %2085, %slots_3.io_out_uop_is_rvc, %slots_2.io_out_uop_is_rvc : i1
    %2127 = comb.mux %2085, %slots_3.io_out_uop_uopc, %slots_2.io_out_uop_uopc : i7
    %2128 = comb.icmp eq %1663, %c4_i4 : i4
    %2129 = comb.mux %2128, %slots_4.io_will_be_valid, %2086 : i1
    %2130 = comb.mux %2128, %slots_4.io_out_uop_fp_val, %2087 : i1
    %2131 = comb.mux %2128, %slots_4.io_out_uop_lrs2_rtype, %2088 : i2
    %2132 = comb.mux %2128, %slots_4.io_out_uop_lrs1_rtype, %2089 : i2
    %2133 = comb.mux %2128, %slots_4.io_out_uop_dst_rtype, %2090 : i2
    %2134 = comb.mux %2128, %slots_4.io_out_uop_ldst_val, %2091 : i1
    %2135 = comb.mux %2128, %slots_4.io_out_uop_uses_stq, %2092 : i1
    %2136 = comb.mux %2128, %slots_4.io_out_uop_uses_ldq, %2093 : i1
    %2137 = comb.mux %2128, %slots_4.io_out_uop_is_amo, %2094 : i1
    %2138 = comb.mux %2128, %slots_4.io_out_uop_is_fence, %2095 : i1
    %2139 = comb.mux %2128, %slots_4.io_out_uop_mem_signed, %2096 : i1
    %2140 = comb.mux %2128, %slots_4.io_out_uop_mem_size, %2097 : i2
    %2141 = comb.mux %2128, %slots_4.io_out_uop_mem_cmd, %2098 : i5
    %2142 = comb.mux %2128, %slots_4.io_out_uop_bypassable, %2099 : i1
    %2143 = comb.mux %2128, %slots_4.io_out_uop_ppred_busy, %2100 : i1
    %2144 = comb.mux %2128, %slots_4.io_out_uop_prs3_busy, %2101 : i1
    %2145 = comb.mux %2128, %slots_4.io_out_uop_prs2_busy, %2102 : i1
    %2146 = comb.mux %2128, %slots_4.io_out_uop_prs1_busy, %2103 : i1
    %2147 = comb.mux %2128, %slots_4.io_out_uop_prs3, %2104 : i7
    %2148 = comb.mux %2128, %slots_4.io_out_uop_prs2, %2105 : i7
    %2149 = comb.mux %2128, %slots_4.io_out_uop_prs1, %2106 : i7
    %2150 = comb.mux %2128, %slots_4.io_out_uop_pdst, %2107 : i7
    %2151 = comb.mux %2128, %slots_4.io_out_uop_stq_idx, %2108 : i5
    %2152 = comb.mux %2128, %slots_4.io_out_uop_ldq_idx, %2109 : i5
    %2153 = comb.mux %2128, %slots_4.io_out_uop_rob_idx, %2110 : i7
    %2154 = comb.mux %2128, %slots_4.io_out_uop_imm_packed, %2111 : i20
    %2155 = comb.mux %2128, %slots_4.io_out_uop_taken, %2112 : i1
    %2156 = comb.mux %2128, %slots_4.io_out_uop_pc_lob, %2113 : i6
    %2157 = comb.mux %2128, %slots_4.io_out_uop_edge_inst, %2114 : i1
    %2158 = comb.mux %2128, %slots_4.io_out_uop_ftq_idx, %2115 : i6
    %2159 = comb.mux %2128, %slots_4.io_out_uop_br_tag, %2116 : i5
    %2160 = comb.mux %2128, %slots_4.io_out_uop_br_mask, %2117 : i20
    %2161 = comb.mux %2128, %slots_4.io_out_uop_is_sfb, %2118 : i1
    %2162 = comb.mux %2128, %slots_4.io_out_uop_is_jal, %2119 : i1
    %2163 = comb.mux %2128, %slots_4.io_out_uop_is_jalr, %2120 : i1
    %2164 = comb.mux %2128, %slots_4.io_out_uop_is_br, %2121 : i1
    %2165 = comb.mux %2128, %slots_4.io_out_uop_iw_p2_poisoned, %2122 : i1
    %2166 = comb.mux %2128, %slots_4.io_out_uop_iw_p1_poisoned, %2123 : i1
    %2167 = comb.mux %2128, %slots_4.io_out_uop_iw_state, %2124 : i2
    %2168 = comb.mux %2128, %slots_4.io_out_uop_fu_code, %2125 : i10
    %2169 = comb.mux %2128, %slots_4.io_out_uop_is_rvc, %2126 : i1
    %2170 = comb.mux %2128, %slots_4.io_out_uop_uopc, %2127 : i7
    %2171 = comb.icmp eq %1671, %c-8_i4 : i4
    %issue_slots_5_will_be_valid = sv.wire sym @issue_slots_5_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_5_will_be_valid, %slots_5.io_will_be_valid : i1
    %2172 = comb.mux %2171, %slots_5.io_will_be_valid, %2129 {sv.namehint = "_issue_slots_1_in_uop_valid"} : i1
    %issue_slots_1_in_uop_valid = sv.wire sym @issue_slots_1_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_1_in_uop_valid, %2172 : i1
    %issue_slots_5_out_uop_fp_val = sv.wire sym @issue_slots_5_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_fp_val, %slots_5.io_out_uop_fp_val : i1
    %issue_slots_5_out_uop_lrs2_rtype = sv.wire sym @issue_slots_5_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_5_out_uop_lrs2_rtype, %slots_5.io_out_uop_lrs2_rtype : i2
    %issue_slots_5_out_uop_lrs1_rtype = sv.wire sym @issue_slots_5_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_5_out_uop_lrs1_rtype, %slots_5.io_out_uop_lrs1_rtype : i2
    %issue_slots_5_out_uop_dst_rtype = sv.wire sym @issue_slots_5_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_5_out_uop_dst_rtype, %slots_5.io_out_uop_dst_rtype : i2
    %issue_slots_5_out_uop_ldst_val = sv.wire sym @issue_slots_5_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_ldst_val, %slots_5.io_out_uop_ldst_val : i1
    %issue_slots_5_out_uop_uses_stq = sv.wire sym @issue_slots_5_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_uses_stq, %slots_5.io_out_uop_uses_stq : i1
    %issue_slots_5_out_uop_uses_ldq = sv.wire sym @issue_slots_5_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_uses_ldq, %slots_5.io_out_uop_uses_ldq : i1
    %issue_slots_5_out_uop_is_amo = sv.wire sym @issue_slots_5_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_is_amo, %slots_5.io_out_uop_is_amo : i1
    %issue_slots_5_out_uop_is_fence = sv.wire sym @issue_slots_5_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_is_fence, %slots_5.io_out_uop_is_fence : i1
    %issue_slots_5_out_uop_mem_signed = sv.wire sym @issue_slots_5_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_mem_signed, %slots_5.io_out_uop_mem_signed : i1
    %issue_slots_5_out_uop_mem_size = sv.wire sym @issue_slots_5_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_5_out_uop_mem_size, %slots_5.io_out_uop_mem_size : i2
    %issue_slots_5_out_uop_mem_cmd = sv.wire sym @issue_slots_5_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_5_out_uop_mem_cmd, %slots_5.io_out_uop_mem_cmd : i5
    %issue_slots_5_out_uop_bypassable = sv.wire sym @issue_slots_5_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_bypassable, %slots_5.io_out_uop_bypassable : i1
    %issue_slots_5_out_uop_ppred_busy = sv.wire sym @issue_slots_5_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_ppred_busy, %slots_5.io_out_uop_ppred_busy : i1
    %issue_slots_5_out_uop_prs3_busy = sv.wire sym @issue_slots_5_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_prs3_busy, %slots_5.io_out_uop_prs3_busy : i1
    %issue_slots_5_out_uop_prs2_busy = sv.wire sym @issue_slots_5_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_prs2_busy, %slots_5.io_out_uop_prs2_busy : i1
    %issue_slots_5_out_uop_prs1_busy = sv.wire sym @issue_slots_5_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_prs1_busy, %slots_5.io_out_uop_prs1_busy : i1
    %issue_slots_5_out_uop_prs3 = sv.wire sym @issue_slots_5_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_5_out_uop_prs3, %slots_5.io_out_uop_prs3 : i7
    %issue_slots_5_out_uop_prs2 = sv.wire sym @issue_slots_5_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_5_out_uop_prs2, %slots_5.io_out_uop_prs2 : i7
    %issue_slots_5_out_uop_prs1 = sv.wire sym @issue_slots_5_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_5_out_uop_prs1, %slots_5.io_out_uop_prs1 : i7
    %issue_slots_5_out_uop_pdst = sv.wire sym @issue_slots_5_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_5_out_uop_pdst, %slots_5.io_out_uop_pdst : i7
    %issue_slots_5_out_uop_stq_idx = sv.wire sym @issue_slots_5_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_5_out_uop_stq_idx, %slots_5.io_out_uop_stq_idx : i5
    %issue_slots_5_out_uop_ldq_idx = sv.wire sym @issue_slots_5_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_5_out_uop_ldq_idx, %slots_5.io_out_uop_ldq_idx : i5
    %issue_slots_5_out_uop_rob_idx = sv.wire sym @issue_slots_5_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_5_out_uop_rob_idx, %slots_5.io_out_uop_rob_idx : i7
    %issue_slots_5_out_uop_imm_packed = sv.wire sym @issue_slots_5_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_5_out_uop_imm_packed, %slots_5.io_out_uop_imm_packed : i20
    %issue_slots_5_out_uop_taken = sv.wire sym @issue_slots_5_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_taken, %slots_5.io_out_uop_taken : i1
    %issue_slots_5_out_uop_pc_lob = sv.wire sym @issue_slots_5_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_5_out_uop_pc_lob, %slots_5.io_out_uop_pc_lob : i6
    %issue_slots_5_out_uop_edge_inst = sv.wire sym @issue_slots_5_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_edge_inst, %slots_5.io_out_uop_edge_inst : i1
    %issue_slots_5_out_uop_ftq_idx = sv.wire sym @issue_slots_5_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_5_out_uop_ftq_idx, %slots_5.io_out_uop_ftq_idx : i6
    %issue_slots_5_out_uop_br_tag = sv.wire sym @issue_slots_5_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_5_out_uop_br_tag, %slots_5.io_out_uop_br_tag : i5
    %issue_slots_5_out_uop_br_mask = sv.wire sym @issue_slots_5_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_5_out_uop_br_mask, %slots_5.io_out_uop_br_mask : i20
    %issue_slots_5_out_uop_is_sfb = sv.wire sym @issue_slots_5_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_is_sfb, %slots_5.io_out_uop_is_sfb : i1
    %issue_slots_5_out_uop_is_jal = sv.wire sym @issue_slots_5_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_is_jal, %slots_5.io_out_uop_is_jal : i1
    %issue_slots_5_out_uop_is_jalr = sv.wire sym @issue_slots_5_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_is_jalr, %slots_5.io_out_uop_is_jalr : i1
    %issue_slots_5_out_uop_is_br = sv.wire sym @issue_slots_5_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_is_br, %slots_5.io_out_uop_is_br : i1
    %issue_slots_5_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_5_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_iw_p2_poisoned, %slots_5.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_5_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_5_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_iw_p1_poisoned, %slots_5.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_5_out_uop_iw_state = sv.wire sym @issue_slots_5_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_5_out_uop_iw_state, %slots_5.io_out_uop_iw_state : i2
    %issue_slots_5_out_uop_fu_code = sv.wire sym @issue_slots_5_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_5_out_uop_fu_code, %slots_5.io_out_uop_fu_code : i10
    %issue_slots_5_out_uop_is_rvc = sv.wire sym @issue_slots_5_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_5_out_uop_is_rvc, %slots_5.io_out_uop_is_rvc : i1
    %issue_slots_5_out_uop_uopc = sv.wire sym @issue_slots_5_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_5_out_uop_uopc, %slots_5.io_out_uop_uopc : i7
    %issue_slots_1_clear = sv.wire sym @issue_slots_1_clear  : !hw.inout<i1>
    sv.assign %issue_slots_1_clear, %1600 : i1
    %2173 = comb.icmp eq %1655, %c1_i4 : i4
    %2174 = comb.and %2173, %slots_3.io_will_be_valid : i1
    %2175 = comb.icmp eq %1663, %c2_i4 : i4
    %2176 = comb.mux %2175, %slots_4.io_will_be_valid, %2174 : i1
    %2177 = comb.mux %2175, %slots_4.io_out_uop_fp_val, %slots_3.io_out_uop_fp_val : i1
    %2178 = comb.mux %2175, %slots_4.io_out_uop_lrs2_rtype, %slots_3.io_out_uop_lrs2_rtype : i2
    %2179 = comb.mux %2175, %slots_4.io_out_uop_lrs1_rtype, %slots_3.io_out_uop_lrs1_rtype : i2
    %2180 = comb.mux %2175, %slots_4.io_out_uop_dst_rtype, %slots_3.io_out_uop_dst_rtype : i2
    %2181 = comb.mux %2175, %slots_4.io_out_uop_ldst_val, %slots_3.io_out_uop_ldst_val : i1
    %2182 = comb.mux %2175, %slots_4.io_out_uop_uses_stq, %slots_3.io_out_uop_uses_stq : i1
    %2183 = comb.mux %2175, %slots_4.io_out_uop_uses_ldq, %slots_3.io_out_uop_uses_ldq : i1
    %2184 = comb.mux %2175, %slots_4.io_out_uop_is_amo, %slots_3.io_out_uop_is_amo : i1
    %2185 = comb.mux %2175, %slots_4.io_out_uop_is_fence, %slots_3.io_out_uop_is_fence : i1
    %2186 = comb.mux %2175, %slots_4.io_out_uop_mem_signed, %slots_3.io_out_uop_mem_signed : i1
    %2187 = comb.mux %2175, %slots_4.io_out_uop_mem_size, %slots_3.io_out_uop_mem_size : i2
    %2188 = comb.mux %2175, %slots_4.io_out_uop_mem_cmd, %slots_3.io_out_uop_mem_cmd : i5
    %2189 = comb.mux %2175, %slots_4.io_out_uop_bypassable, %slots_3.io_out_uop_bypassable : i1
    %2190 = comb.mux %2175, %slots_4.io_out_uop_ppred_busy, %slots_3.io_out_uop_ppred_busy : i1
    %2191 = comb.mux %2175, %slots_4.io_out_uop_prs3_busy, %slots_3.io_out_uop_prs3_busy : i1
    %2192 = comb.mux %2175, %slots_4.io_out_uop_prs2_busy, %slots_3.io_out_uop_prs2_busy : i1
    %2193 = comb.mux %2175, %slots_4.io_out_uop_prs1_busy, %slots_3.io_out_uop_prs1_busy : i1
    %2194 = comb.mux %2175, %slots_4.io_out_uop_prs3, %slots_3.io_out_uop_prs3 : i7
    %2195 = comb.mux %2175, %slots_4.io_out_uop_prs2, %slots_3.io_out_uop_prs2 : i7
    %2196 = comb.mux %2175, %slots_4.io_out_uop_prs1, %slots_3.io_out_uop_prs1 : i7
    %2197 = comb.mux %2175, %slots_4.io_out_uop_pdst, %slots_3.io_out_uop_pdst : i7
    %2198 = comb.mux %2175, %slots_4.io_out_uop_stq_idx, %slots_3.io_out_uop_stq_idx : i5
    %2199 = comb.mux %2175, %slots_4.io_out_uop_ldq_idx, %slots_3.io_out_uop_ldq_idx : i5
    %2200 = comb.mux %2175, %slots_4.io_out_uop_rob_idx, %slots_3.io_out_uop_rob_idx : i7
    %2201 = comb.mux %2175, %slots_4.io_out_uop_imm_packed, %slots_3.io_out_uop_imm_packed : i20
    %2202 = comb.mux %2175, %slots_4.io_out_uop_taken, %slots_3.io_out_uop_taken : i1
    %2203 = comb.mux %2175, %slots_4.io_out_uop_pc_lob, %slots_3.io_out_uop_pc_lob : i6
    %2204 = comb.mux %2175, %slots_4.io_out_uop_edge_inst, %slots_3.io_out_uop_edge_inst : i1
    %2205 = comb.mux %2175, %slots_4.io_out_uop_ftq_idx, %slots_3.io_out_uop_ftq_idx : i6
    %2206 = comb.mux %2175, %slots_4.io_out_uop_br_tag, %slots_3.io_out_uop_br_tag : i5
    %2207 = comb.mux %2175, %slots_4.io_out_uop_br_mask, %slots_3.io_out_uop_br_mask : i20
    %2208 = comb.mux %2175, %slots_4.io_out_uop_is_sfb, %slots_3.io_out_uop_is_sfb : i1
    %2209 = comb.mux %2175, %slots_4.io_out_uop_is_jal, %slots_3.io_out_uop_is_jal : i1
    %2210 = comb.mux %2175, %slots_4.io_out_uop_is_jalr, %slots_3.io_out_uop_is_jalr : i1
    %2211 = comb.mux %2175, %slots_4.io_out_uop_is_br, %slots_3.io_out_uop_is_br : i1
    %2212 = comb.mux %2175, %slots_4.io_out_uop_iw_p2_poisoned, %slots_3.io_out_uop_iw_p2_poisoned : i1
    %2213 = comb.mux %2175, %slots_4.io_out_uop_iw_p1_poisoned, %slots_3.io_out_uop_iw_p1_poisoned : i1
    %2214 = comb.mux %2175, %slots_4.io_out_uop_iw_state, %slots_3.io_out_uop_iw_state : i2
    %2215 = comb.mux %2175, %slots_4.io_out_uop_fu_code, %slots_3.io_out_uop_fu_code : i10
    %2216 = comb.mux %2175, %slots_4.io_out_uop_is_rvc, %slots_3.io_out_uop_is_rvc : i1
    %2217 = comb.mux %2175, %slots_4.io_out_uop_uopc, %slots_3.io_out_uop_uopc : i7
    %2218 = comb.icmp eq %1671, %c4_i4 : i4
    %2219 = comb.mux %2218, %slots_5.io_will_be_valid, %2176 : i1
    %2220 = comb.mux %2218, %slots_5.io_out_uop_fp_val, %2177 : i1
    %2221 = comb.mux %2218, %slots_5.io_out_uop_lrs2_rtype, %2178 : i2
    %2222 = comb.mux %2218, %slots_5.io_out_uop_lrs1_rtype, %2179 : i2
    %2223 = comb.mux %2218, %slots_5.io_out_uop_dst_rtype, %2180 : i2
    %2224 = comb.mux %2218, %slots_5.io_out_uop_ldst_val, %2181 : i1
    %2225 = comb.mux %2218, %slots_5.io_out_uop_uses_stq, %2182 : i1
    %2226 = comb.mux %2218, %slots_5.io_out_uop_uses_ldq, %2183 : i1
    %2227 = comb.mux %2218, %slots_5.io_out_uop_is_amo, %2184 : i1
    %2228 = comb.mux %2218, %slots_5.io_out_uop_is_fence, %2185 : i1
    %2229 = comb.mux %2218, %slots_5.io_out_uop_mem_signed, %2186 : i1
    %2230 = comb.mux %2218, %slots_5.io_out_uop_mem_size, %2187 : i2
    %2231 = comb.mux %2218, %slots_5.io_out_uop_mem_cmd, %2188 : i5
    %2232 = comb.mux %2218, %slots_5.io_out_uop_bypassable, %2189 : i1
    %2233 = comb.mux %2218, %slots_5.io_out_uop_ppred_busy, %2190 : i1
    %2234 = comb.mux %2218, %slots_5.io_out_uop_prs3_busy, %2191 : i1
    %2235 = comb.mux %2218, %slots_5.io_out_uop_prs2_busy, %2192 : i1
    %2236 = comb.mux %2218, %slots_5.io_out_uop_prs1_busy, %2193 : i1
    %2237 = comb.mux %2218, %slots_5.io_out_uop_prs3, %2194 : i7
    %2238 = comb.mux %2218, %slots_5.io_out_uop_prs2, %2195 : i7
    %2239 = comb.mux %2218, %slots_5.io_out_uop_prs1, %2196 : i7
    %2240 = comb.mux %2218, %slots_5.io_out_uop_pdst, %2197 : i7
    %2241 = comb.mux %2218, %slots_5.io_out_uop_stq_idx, %2198 : i5
    %2242 = comb.mux %2218, %slots_5.io_out_uop_ldq_idx, %2199 : i5
    %2243 = comb.mux %2218, %slots_5.io_out_uop_rob_idx, %2200 : i7
    %2244 = comb.mux %2218, %slots_5.io_out_uop_imm_packed, %2201 : i20
    %2245 = comb.mux %2218, %slots_5.io_out_uop_taken, %2202 : i1
    %2246 = comb.mux %2218, %slots_5.io_out_uop_pc_lob, %2203 : i6
    %2247 = comb.mux %2218, %slots_5.io_out_uop_edge_inst, %2204 : i1
    %2248 = comb.mux %2218, %slots_5.io_out_uop_ftq_idx, %2205 : i6
    %2249 = comb.mux %2218, %slots_5.io_out_uop_br_tag, %2206 : i5
    %2250 = comb.mux %2218, %slots_5.io_out_uop_br_mask, %2207 : i20
    %2251 = comb.mux %2218, %slots_5.io_out_uop_is_sfb, %2208 : i1
    %2252 = comb.mux %2218, %slots_5.io_out_uop_is_jal, %2209 : i1
    %2253 = comb.mux %2218, %slots_5.io_out_uop_is_jalr, %2210 : i1
    %2254 = comb.mux %2218, %slots_5.io_out_uop_is_br, %2211 : i1
    %2255 = comb.mux %2218, %slots_5.io_out_uop_iw_p2_poisoned, %2212 : i1
    %2256 = comb.mux %2218, %slots_5.io_out_uop_iw_p1_poisoned, %2213 : i1
    %2257 = comb.mux %2218, %slots_5.io_out_uop_iw_state, %2214 : i2
    %2258 = comb.mux %2218, %slots_5.io_out_uop_fu_code, %2215 : i10
    %2259 = comb.mux %2218, %slots_5.io_out_uop_is_rvc, %2216 : i1
    %2260 = comb.mux %2218, %slots_5.io_out_uop_uopc, %2217 : i7
    %2261 = comb.icmp eq %1679, %c-8_i4 : i4
    %issue_slots_6_will_be_valid = sv.wire sym @issue_slots_6_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_6_will_be_valid, %slots_6.io_will_be_valid : i1
    %2262 = comb.mux %2261, %slots_6.io_will_be_valid, %2219 {sv.namehint = "_issue_slots_2_in_uop_valid"} : i1
    %issue_slots_2_in_uop_valid = sv.wire sym @issue_slots_2_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_2_in_uop_valid, %2262 : i1
    %issue_slots_6_out_uop_fp_val = sv.wire sym @issue_slots_6_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_fp_val, %slots_6.io_out_uop_fp_val : i1
    %issue_slots_6_out_uop_lrs2_rtype = sv.wire sym @issue_slots_6_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_6_out_uop_lrs2_rtype, %slots_6.io_out_uop_lrs2_rtype : i2
    %issue_slots_6_out_uop_lrs1_rtype = sv.wire sym @issue_slots_6_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_6_out_uop_lrs1_rtype, %slots_6.io_out_uop_lrs1_rtype : i2
    %issue_slots_6_out_uop_dst_rtype = sv.wire sym @issue_slots_6_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_6_out_uop_dst_rtype, %slots_6.io_out_uop_dst_rtype : i2
    %issue_slots_6_out_uop_ldst_val = sv.wire sym @issue_slots_6_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_ldst_val, %slots_6.io_out_uop_ldst_val : i1
    %issue_slots_6_out_uop_uses_stq = sv.wire sym @issue_slots_6_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_uses_stq, %slots_6.io_out_uop_uses_stq : i1
    %issue_slots_6_out_uop_uses_ldq = sv.wire sym @issue_slots_6_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_uses_ldq, %slots_6.io_out_uop_uses_ldq : i1
    %issue_slots_6_out_uop_is_amo = sv.wire sym @issue_slots_6_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_is_amo, %slots_6.io_out_uop_is_amo : i1
    %issue_slots_6_out_uop_is_fence = sv.wire sym @issue_slots_6_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_is_fence, %slots_6.io_out_uop_is_fence : i1
    %issue_slots_6_out_uop_mem_signed = sv.wire sym @issue_slots_6_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_mem_signed, %slots_6.io_out_uop_mem_signed : i1
    %issue_slots_6_out_uop_mem_size = sv.wire sym @issue_slots_6_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_6_out_uop_mem_size, %slots_6.io_out_uop_mem_size : i2
    %issue_slots_6_out_uop_mem_cmd = sv.wire sym @issue_slots_6_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_6_out_uop_mem_cmd, %slots_6.io_out_uop_mem_cmd : i5
    %issue_slots_6_out_uop_bypassable = sv.wire sym @issue_slots_6_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_bypassable, %slots_6.io_out_uop_bypassable : i1
    %issue_slots_6_out_uop_ppred_busy = sv.wire sym @issue_slots_6_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_ppred_busy, %slots_6.io_out_uop_ppred_busy : i1
    %issue_slots_6_out_uop_prs3_busy = sv.wire sym @issue_slots_6_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_prs3_busy, %slots_6.io_out_uop_prs3_busy : i1
    %issue_slots_6_out_uop_prs2_busy = sv.wire sym @issue_slots_6_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_prs2_busy, %slots_6.io_out_uop_prs2_busy : i1
    %issue_slots_6_out_uop_prs1_busy = sv.wire sym @issue_slots_6_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_prs1_busy, %slots_6.io_out_uop_prs1_busy : i1
    %issue_slots_6_out_uop_prs3 = sv.wire sym @issue_slots_6_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_6_out_uop_prs3, %slots_6.io_out_uop_prs3 : i7
    %issue_slots_6_out_uop_prs2 = sv.wire sym @issue_slots_6_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_6_out_uop_prs2, %slots_6.io_out_uop_prs2 : i7
    %issue_slots_6_out_uop_prs1 = sv.wire sym @issue_slots_6_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_6_out_uop_prs1, %slots_6.io_out_uop_prs1 : i7
    %issue_slots_6_out_uop_pdst = sv.wire sym @issue_slots_6_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_6_out_uop_pdst, %slots_6.io_out_uop_pdst : i7
    %issue_slots_6_out_uop_stq_idx = sv.wire sym @issue_slots_6_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_6_out_uop_stq_idx, %slots_6.io_out_uop_stq_idx : i5
    %issue_slots_6_out_uop_ldq_idx = sv.wire sym @issue_slots_6_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_6_out_uop_ldq_idx, %slots_6.io_out_uop_ldq_idx : i5
    %issue_slots_6_out_uop_rob_idx = sv.wire sym @issue_slots_6_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_6_out_uop_rob_idx, %slots_6.io_out_uop_rob_idx : i7
    %issue_slots_6_out_uop_imm_packed = sv.wire sym @issue_slots_6_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_6_out_uop_imm_packed, %slots_6.io_out_uop_imm_packed : i20
    %issue_slots_6_out_uop_taken = sv.wire sym @issue_slots_6_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_taken, %slots_6.io_out_uop_taken : i1
    %issue_slots_6_out_uop_pc_lob = sv.wire sym @issue_slots_6_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_6_out_uop_pc_lob, %slots_6.io_out_uop_pc_lob : i6
    %issue_slots_6_out_uop_edge_inst = sv.wire sym @issue_slots_6_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_edge_inst, %slots_6.io_out_uop_edge_inst : i1
    %issue_slots_6_out_uop_ftq_idx = sv.wire sym @issue_slots_6_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_6_out_uop_ftq_idx, %slots_6.io_out_uop_ftq_idx : i6
    %issue_slots_6_out_uop_br_tag = sv.wire sym @issue_slots_6_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_6_out_uop_br_tag, %slots_6.io_out_uop_br_tag : i5
    %issue_slots_6_out_uop_br_mask = sv.wire sym @issue_slots_6_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_6_out_uop_br_mask, %slots_6.io_out_uop_br_mask : i20
    %issue_slots_6_out_uop_is_sfb = sv.wire sym @issue_slots_6_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_is_sfb, %slots_6.io_out_uop_is_sfb : i1
    %issue_slots_6_out_uop_is_jal = sv.wire sym @issue_slots_6_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_is_jal, %slots_6.io_out_uop_is_jal : i1
    %issue_slots_6_out_uop_is_jalr = sv.wire sym @issue_slots_6_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_is_jalr, %slots_6.io_out_uop_is_jalr : i1
    %issue_slots_6_out_uop_is_br = sv.wire sym @issue_slots_6_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_is_br, %slots_6.io_out_uop_is_br : i1
    %issue_slots_6_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_6_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_iw_p2_poisoned, %slots_6.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_6_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_6_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_iw_p1_poisoned, %slots_6.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_6_out_uop_iw_state = sv.wire sym @issue_slots_6_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_6_out_uop_iw_state, %slots_6.io_out_uop_iw_state : i2
    %issue_slots_6_out_uop_fu_code = sv.wire sym @issue_slots_6_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_6_out_uop_fu_code, %slots_6.io_out_uop_fu_code : i10
    %issue_slots_6_out_uop_is_rvc = sv.wire sym @issue_slots_6_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_6_out_uop_is_rvc, %slots_6.io_out_uop_is_rvc : i1
    %issue_slots_6_out_uop_uopc = sv.wire sym @issue_slots_6_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_6_out_uop_uopc, %slots_6.io_out_uop_uopc : i7
    %2263 = comb.extract %1648 from 0 : (i4) -> i2
    %2264 = comb.icmp ne %2263, %c0_i2 : i2
    %issue_slots_2_clear = sv.wire sym @issue_slots_2_clear  : !hw.inout<i1>
    sv.assign %issue_slots_2_clear, %2264 : i1
    %2265 = comb.icmp eq %1663, %c1_i4 : i4
    %2266 = comb.and %2265, %slots_4.io_will_be_valid : i1
    %2267 = comb.icmp eq %1671, %c2_i4 : i4
    %2268 = comb.mux %2267, %slots_5.io_will_be_valid, %2266 : i1
    %2269 = comb.mux %2267, %slots_5.io_out_uop_fp_val, %slots_4.io_out_uop_fp_val : i1
    %2270 = comb.mux %2267, %slots_5.io_out_uop_lrs2_rtype, %slots_4.io_out_uop_lrs2_rtype : i2
    %2271 = comb.mux %2267, %slots_5.io_out_uop_lrs1_rtype, %slots_4.io_out_uop_lrs1_rtype : i2
    %2272 = comb.mux %2267, %slots_5.io_out_uop_dst_rtype, %slots_4.io_out_uop_dst_rtype : i2
    %2273 = comb.mux %2267, %slots_5.io_out_uop_ldst_val, %slots_4.io_out_uop_ldst_val : i1
    %2274 = comb.mux %2267, %slots_5.io_out_uop_uses_stq, %slots_4.io_out_uop_uses_stq : i1
    %2275 = comb.mux %2267, %slots_5.io_out_uop_uses_ldq, %slots_4.io_out_uop_uses_ldq : i1
    %2276 = comb.mux %2267, %slots_5.io_out_uop_is_amo, %slots_4.io_out_uop_is_amo : i1
    %2277 = comb.mux %2267, %slots_5.io_out_uop_is_fence, %slots_4.io_out_uop_is_fence : i1
    %2278 = comb.mux %2267, %slots_5.io_out_uop_mem_signed, %slots_4.io_out_uop_mem_signed : i1
    %2279 = comb.mux %2267, %slots_5.io_out_uop_mem_size, %slots_4.io_out_uop_mem_size : i2
    %2280 = comb.mux %2267, %slots_5.io_out_uop_mem_cmd, %slots_4.io_out_uop_mem_cmd : i5
    %2281 = comb.mux %2267, %slots_5.io_out_uop_bypassable, %slots_4.io_out_uop_bypassable : i1
    %2282 = comb.mux %2267, %slots_5.io_out_uop_ppred_busy, %slots_4.io_out_uop_ppred_busy : i1
    %2283 = comb.mux %2267, %slots_5.io_out_uop_prs3_busy, %slots_4.io_out_uop_prs3_busy : i1
    %2284 = comb.mux %2267, %slots_5.io_out_uop_prs2_busy, %slots_4.io_out_uop_prs2_busy : i1
    %2285 = comb.mux %2267, %slots_5.io_out_uop_prs1_busy, %slots_4.io_out_uop_prs1_busy : i1
    %2286 = comb.mux %2267, %slots_5.io_out_uop_prs3, %slots_4.io_out_uop_prs3 : i7
    %2287 = comb.mux %2267, %slots_5.io_out_uop_prs2, %slots_4.io_out_uop_prs2 : i7
    %2288 = comb.mux %2267, %slots_5.io_out_uop_prs1, %slots_4.io_out_uop_prs1 : i7
    %2289 = comb.mux %2267, %slots_5.io_out_uop_pdst, %slots_4.io_out_uop_pdst : i7
    %2290 = comb.mux %2267, %slots_5.io_out_uop_stq_idx, %slots_4.io_out_uop_stq_idx : i5
    %2291 = comb.mux %2267, %slots_5.io_out_uop_ldq_idx, %slots_4.io_out_uop_ldq_idx : i5
    %2292 = comb.mux %2267, %slots_5.io_out_uop_rob_idx, %slots_4.io_out_uop_rob_idx : i7
    %2293 = comb.mux %2267, %slots_5.io_out_uop_imm_packed, %slots_4.io_out_uop_imm_packed : i20
    %2294 = comb.mux %2267, %slots_5.io_out_uop_taken, %slots_4.io_out_uop_taken : i1
    %2295 = comb.mux %2267, %slots_5.io_out_uop_pc_lob, %slots_4.io_out_uop_pc_lob : i6
    %2296 = comb.mux %2267, %slots_5.io_out_uop_edge_inst, %slots_4.io_out_uop_edge_inst : i1
    %2297 = comb.mux %2267, %slots_5.io_out_uop_ftq_idx, %slots_4.io_out_uop_ftq_idx : i6
    %2298 = comb.mux %2267, %slots_5.io_out_uop_br_tag, %slots_4.io_out_uop_br_tag : i5
    %2299 = comb.mux %2267, %slots_5.io_out_uop_br_mask, %slots_4.io_out_uop_br_mask : i20
    %2300 = comb.mux %2267, %slots_5.io_out_uop_is_sfb, %slots_4.io_out_uop_is_sfb : i1
    %2301 = comb.mux %2267, %slots_5.io_out_uop_is_jal, %slots_4.io_out_uop_is_jal : i1
    %2302 = comb.mux %2267, %slots_5.io_out_uop_is_jalr, %slots_4.io_out_uop_is_jalr : i1
    %2303 = comb.mux %2267, %slots_5.io_out_uop_is_br, %slots_4.io_out_uop_is_br : i1
    %2304 = comb.mux %2267, %slots_5.io_out_uop_iw_p2_poisoned, %slots_4.io_out_uop_iw_p2_poisoned : i1
    %2305 = comb.mux %2267, %slots_5.io_out_uop_iw_p1_poisoned, %slots_4.io_out_uop_iw_p1_poisoned : i1
    %2306 = comb.mux %2267, %slots_5.io_out_uop_iw_state, %slots_4.io_out_uop_iw_state : i2
    %2307 = comb.mux %2267, %slots_5.io_out_uop_fu_code, %slots_4.io_out_uop_fu_code : i10
    %2308 = comb.mux %2267, %slots_5.io_out_uop_is_rvc, %slots_4.io_out_uop_is_rvc : i1
    %2309 = comb.mux %2267, %slots_5.io_out_uop_uopc, %slots_4.io_out_uop_uopc : i7
    %2310 = comb.icmp eq %1679, %c4_i4 : i4
    %2311 = comb.mux %2310, %slots_6.io_will_be_valid, %2268 : i1
    %2312 = comb.mux %2310, %slots_6.io_out_uop_fp_val, %2269 : i1
    %2313 = comb.mux %2310, %slots_6.io_out_uop_lrs2_rtype, %2270 : i2
    %2314 = comb.mux %2310, %slots_6.io_out_uop_lrs1_rtype, %2271 : i2
    %2315 = comb.mux %2310, %slots_6.io_out_uop_dst_rtype, %2272 : i2
    %2316 = comb.mux %2310, %slots_6.io_out_uop_ldst_val, %2273 : i1
    %2317 = comb.mux %2310, %slots_6.io_out_uop_uses_stq, %2274 : i1
    %2318 = comb.mux %2310, %slots_6.io_out_uop_uses_ldq, %2275 : i1
    %2319 = comb.mux %2310, %slots_6.io_out_uop_is_amo, %2276 : i1
    %2320 = comb.mux %2310, %slots_6.io_out_uop_is_fence, %2277 : i1
    %2321 = comb.mux %2310, %slots_6.io_out_uop_mem_signed, %2278 : i1
    %2322 = comb.mux %2310, %slots_6.io_out_uop_mem_size, %2279 : i2
    %2323 = comb.mux %2310, %slots_6.io_out_uop_mem_cmd, %2280 : i5
    %2324 = comb.mux %2310, %slots_6.io_out_uop_bypassable, %2281 : i1
    %2325 = comb.mux %2310, %slots_6.io_out_uop_ppred_busy, %2282 : i1
    %2326 = comb.mux %2310, %slots_6.io_out_uop_prs3_busy, %2283 : i1
    %2327 = comb.mux %2310, %slots_6.io_out_uop_prs2_busy, %2284 : i1
    %2328 = comb.mux %2310, %slots_6.io_out_uop_prs1_busy, %2285 : i1
    %2329 = comb.mux %2310, %slots_6.io_out_uop_prs3, %2286 : i7
    %2330 = comb.mux %2310, %slots_6.io_out_uop_prs2, %2287 : i7
    %2331 = comb.mux %2310, %slots_6.io_out_uop_prs1, %2288 : i7
    %2332 = comb.mux %2310, %slots_6.io_out_uop_pdst, %2289 : i7
    %2333 = comb.mux %2310, %slots_6.io_out_uop_stq_idx, %2290 : i5
    %2334 = comb.mux %2310, %slots_6.io_out_uop_ldq_idx, %2291 : i5
    %2335 = comb.mux %2310, %slots_6.io_out_uop_rob_idx, %2292 : i7
    %2336 = comb.mux %2310, %slots_6.io_out_uop_imm_packed, %2293 : i20
    %2337 = comb.mux %2310, %slots_6.io_out_uop_taken, %2294 : i1
    %2338 = comb.mux %2310, %slots_6.io_out_uop_pc_lob, %2295 : i6
    %2339 = comb.mux %2310, %slots_6.io_out_uop_edge_inst, %2296 : i1
    %2340 = comb.mux %2310, %slots_6.io_out_uop_ftq_idx, %2297 : i6
    %2341 = comb.mux %2310, %slots_6.io_out_uop_br_tag, %2298 : i5
    %2342 = comb.mux %2310, %slots_6.io_out_uop_br_mask, %2299 : i20
    %2343 = comb.mux %2310, %slots_6.io_out_uop_is_sfb, %2300 : i1
    %2344 = comb.mux %2310, %slots_6.io_out_uop_is_jal, %2301 : i1
    %2345 = comb.mux %2310, %slots_6.io_out_uop_is_jalr, %2302 : i1
    %2346 = comb.mux %2310, %slots_6.io_out_uop_is_br, %2303 : i1
    %2347 = comb.mux %2310, %slots_6.io_out_uop_iw_p2_poisoned, %2304 : i1
    %2348 = comb.mux %2310, %slots_6.io_out_uop_iw_p1_poisoned, %2305 : i1
    %2349 = comb.mux %2310, %slots_6.io_out_uop_iw_state, %2306 : i2
    %2350 = comb.mux %2310, %slots_6.io_out_uop_fu_code, %2307 : i10
    %2351 = comb.mux %2310, %slots_6.io_out_uop_is_rvc, %2308 : i1
    %2352 = comb.mux %2310, %slots_6.io_out_uop_uopc, %2309 : i7
    %2353 = comb.icmp eq %1687, %c-8_i4 : i4
    %issue_slots_7_will_be_valid = sv.wire sym @issue_slots_7_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_7_will_be_valid, %slots_7.io_will_be_valid : i1
    %2354 = comb.mux %2353, %slots_7.io_will_be_valid, %2311 {sv.namehint = "_issue_slots_3_in_uop_valid"} : i1
    %issue_slots_3_in_uop_valid = sv.wire sym @issue_slots_3_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_3_in_uop_valid, %2354 : i1
    %issue_slots_7_out_uop_fp_val = sv.wire sym @issue_slots_7_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_fp_val, %slots_7.io_out_uop_fp_val : i1
    %issue_slots_7_out_uop_lrs2_rtype = sv.wire sym @issue_slots_7_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_7_out_uop_lrs2_rtype, %slots_7.io_out_uop_lrs2_rtype : i2
    %issue_slots_7_out_uop_lrs1_rtype = sv.wire sym @issue_slots_7_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_7_out_uop_lrs1_rtype, %slots_7.io_out_uop_lrs1_rtype : i2
    %issue_slots_7_out_uop_dst_rtype = sv.wire sym @issue_slots_7_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_7_out_uop_dst_rtype, %slots_7.io_out_uop_dst_rtype : i2
    %issue_slots_7_out_uop_ldst_val = sv.wire sym @issue_slots_7_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_ldst_val, %slots_7.io_out_uop_ldst_val : i1
    %issue_slots_7_out_uop_uses_stq = sv.wire sym @issue_slots_7_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_uses_stq, %slots_7.io_out_uop_uses_stq : i1
    %issue_slots_7_out_uop_uses_ldq = sv.wire sym @issue_slots_7_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_uses_ldq, %slots_7.io_out_uop_uses_ldq : i1
    %issue_slots_7_out_uop_is_amo = sv.wire sym @issue_slots_7_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_is_amo, %slots_7.io_out_uop_is_amo : i1
    %issue_slots_7_out_uop_is_fence = sv.wire sym @issue_slots_7_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_is_fence, %slots_7.io_out_uop_is_fence : i1
    %issue_slots_7_out_uop_mem_signed = sv.wire sym @issue_slots_7_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_mem_signed, %slots_7.io_out_uop_mem_signed : i1
    %issue_slots_7_out_uop_mem_size = sv.wire sym @issue_slots_7_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_7_out_uop_mem_size, %slots_7.io_out_uop_mem_size : i2
    %issue_slots_7_out_uop_mem_cmd = sv.wire sym @issue_slots_7_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_7_out_uop_mem_cmd, %slots_7.io_out_uop_mem_cmd : i5
    %issue_slots_7_out_uop_bypassable = sv.wire sym @issue_slots_7_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_bypassable, %slots_7.io_out_uop_bypassable : i1
    %issue_slots_7_out_uop_ppred_busy = sv.wire sym @issue_slots_7_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_ppred_busy, %slots_7.io_out_uop_ppred_busy : i1
    %issue_slots_7_out_uop_prs3_busy = sv.wire sym @issue_slots_7_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_prs3_busy, %slots_7.io_out_uop_prs3_busy : i1
    %issue_slots_7_out_uop_prs2_busy = sv.wire sym @issue_slots_7_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_prs2_busy, %slots_7.io_out_uop_prs2_busy : i1
    %issue_slots_7_out_uop_prs1_busy = sv.wire sym @issue_slots_7_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_prs1_busy, %slots_7.io_out_uop_prs1_busy : i1
    %issue_slots_7_out_uop_prs3 = sv.wire sym @issue_slots_7_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_7_out_uop_prs3, %slots_7.io_out_uop_prs3 : i7
    %issue_slots_7_out_uop_prs2 = sv.wire sym @issue_slots_7_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_7_out_uop_prs2, %slots_7.io_out_uop_prs2 : i7
    %issue_slots_7_out_uop_prs1 = sv.wire sym @issue_slots_7_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_7_out_uop_prs1, %slots_7.io_out_uop_prs1 : i7
    %issue_slots_7_out_uop_pdst = sv.wire sym @issue_slots_7_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_7_out_uop_pdst, %slots_7.io_out_uop_pdst : i7
    %issue_slots_7_out_uop_stq_idx = sv.wire sym @issue_slots_7_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_7_out_uop_stq_idx, %slots_7.io_out_uop_stq_idx : i5
    %issue_slots_7_out_uop_ldq_idx = sv.wire sym @issue_slots_7_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_7_out_uop_ldq_idx, %slots_7.io_out_uop_ldq_idx : i5
    %issue_slots_7_out_uop_rob_idx = sv.wire sym @issue_slots_7_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_7_out_uop_rob_idx, %slots_7.io_out_uop_rob_idx : i7
    %issue_slots_7_out_uop_imm_packed = sv.wire sym @issue_slots_7_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_7_out_uop_imm_packed, %slots_7.io_out_uop_imm_packed : i20
    %issue_slots_7_out_uop_taken = sv.wire sym @issue_slots_7_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_taken, %slots_7.io_out_uop_taken : i1
    %issue_slots_7_out_uop_pc_lob = sv.wire sym @issue_slots_7_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_7_out_uop_pc_lob, %slots_7.io_out_uop_pc_lob : i6
    %issue_slots_7_out_uop_edge_inst = sv.wire sym @issue_slots_7_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_edge_inst, %slots_7.io_out_uop_edge_inst : i1
    %issue_slots_7_out_uop_ftq_idx = sv.wire sym @issue_slots_7_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_7_out_uop_ftq_idx, %slots_7.io_out_uop_ftq_idx : i6
    %issue_slots_7_out_uop_br_tag = sv.wire sym @issue_slots_7_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_7_out_uop_br_tag, %slots_7.io_out_uop_br_tag : i5
    %issue_slots_7_out_uop_br_mask = sv.wire sym @issue_slots_7_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_7_out_uop_br_mask, %slots_7.io_out_uop_br_mask : i20
    %issue_slots_7_out_uop_is_sfb = sv.wire sym @issue_slots_7_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_is_sfb, %slots_7.io_out_uop_is_sfb : i1
    %issue_slots_7_out_uop_is_jal = sv.wire sym @issue_slots_7_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_is_jal, %slots_7.io_out_uop_is_jal : i1
    %issue_slots_7_out_uop_is_jalr = sv.wire sym @issue_slots_7_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_is_jalr, %slots_7.io_out_uop_is_jalr : i1
    %issue_slots_7_out_uop_is_br = sv.wire sym @issue_slots_7_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_is_br, %slots_7.io_out_uop_is_br : i1
    %issue_slots_7_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_7_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_iw_p2_poisoned, %slots_7.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_7_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_7_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_iw_p1_poisoned, %slots_7.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_7_out_uop_iw_state = sv.wire sym @issue_slots_7_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_7_out_uop_iw_state, %slots_7.io_out_uop_iw_state : i2
    %issue_slots_7_out_uop_fu_code = sv.wire sym @issue_slots_7_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_7_out_uop_fu_code, %slots_7.io_out_uop_fu_code : i10
    %issue_slots_7_out_uop_is_rvc = sv.wire sym @issue_slots_7_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_7_out_uop_is_rvc, %slots_7.io_out_uop_is_rvc : i1
    %issue_slots_7_out_uop_uopc = sv.wire sym @issue_slots_7_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_7_out_uop_uopc, %slots_7.io_out_uop_uopc : i7
    %2355 = comb.icmp ne %1655, %c0_i4 {sv.namehint = "_issue_slots_3_clear"} : i4
    %issue_slots_3_clear = sv.wire sym @issue_slots_3_clear  : !hw.inout<i1>
    sv.assign %issue_slots_3_clear, %2355 : i1
    %2356 = comb.icmp eq %1671, %c1_i4 : i4
    %2357 = comb.and %2356, %slots_5.io_will_be_valid : i1
    %2358 = comb.icmp eq %1679, %c2_i4 : i4
    %2359 = comb.mux %2358, %slots_6.io_will_be_valid, %2357 : i1
    %2360 = comb.mux %2358, %slots_6.io_out_uop_fp_val, %slots_5.io_out_uop_fp_val : i1
    %2361 = comb.mux %2358, %slots_6.io_out_uop_lrs2_rtype, %slots_5.io_out_uop_lrs2_rtype : i2
    %2362 = comb.mux %2358, %slots_6.io_out_uop_lrs1_rtype, %slots_5.io_out_uop_lrs1_rtype : i2
    %2363 = comb.mux %2358, %slots_6.io_out_uop_dst_rtype, %slots_5.io_out_uop_dst_rtype : i2
    %2364 = comb.mux %2358, %slots_6.io_out_uop_ldst_val, %slots_5.io_out_uop_ldst_val : i1
    %2365 = comb.mux %2358, %slots_6.io_out_uop_uses_stq, %slots_5.io_out_uop_uses_stq : i1
    %2366 = comb.mux %2358, %slots_6.io_out_uop_uses_ldq, %slots_5.io_out_uop_uses_ldq : i1
    %2367 = comb.mux %2358, %slots_6.io_out_uop_is_amo, %slots_5.io_out_uop_is_amo : i1
    %2368 = comb.mux %2358, %slots_6.io_out_uop_is_fence, %slots_5.io_out_uop_is_fence : i1
    %2369 = comb.mux %2358, %slots_6.io_out_uop_mem_signed, %slots_5.io_out_uop_mem_signed : i1
    %2370 = comb.mux %2358, %slots_6.io_out_uop_mem_size, %slots_5.io_out_uop_mem_size : i2
    %2371 = comb.mux %2358, %slots_6.io_out_uop_mem_cmd, %slots_5.io_out_uop_mem_cmd : i5
    %2372 = comb.mux %2358, %slots_6.io_out_uop_bypassable, %slots_5.io_out_uop_bypassable : i1
    %2373 = comb.mux %2358, %slots_6.io_out_uop_ppred_busy, %slots_5.io_out_uop_ppred_busy : i1
    %2374 = comb.mux %2358, %slots_6.io_out_uop_prs3_busy, %slots_5.io_out_uop_prs3_busy : i1
    %2375 = comb.mux %2358, %slots_6.io_out_uop_prs2_busy, %slots_5.io_out_uop_prs2_busy : i1
    %2376 = comb.mux %2358, %slots_6.io_out_uop_prs1_busy, %slots_5.io_out_uop_prs1_busy : i1
    %2377 = comb.mux %2358, %slots_6.io_out_uop_prs3, %slots_5.io_out_uop_prs3 : i7
    %2378 = comb.mux %2358, %slots_6.io_out_uop_prs2, %slots_5.io_out_uop_prs2 : i7
    %2379 = comb.mux %2358, %slots_6.io_out_uop_prs1, %slots_5.io_out_uop_prs1 : i7
    %2380 = comb.mux %2358, %slots_6.io_out_uop_pdst, %slots_5.io_out_uop_pdst : i7
    %2381 = comb.mux %2358, %slots_6.io_out_uop_stq_idx, %slots_5.io_out_uop_stq_idx : i5
    %2382 = comb.mux %2358, %slots_6.io_out_uop_ldq_idx, %slots_5.io_out_uop_ldq_idx : i5
    %2383 = comb.mux %2358, %slots_6.io_out_uop_rob_idx, %slots_5.io_out_uop_rob_idx : i7
    %2384 = comb.mux %2358, %slots_6.io_out_uop_imm_packed, %slots_5.io_out_uop_imm_packed : i20
    %2385 = comb.mux %2358, %slots_6.io_out_uop_taken, %slots_5.io_out_uop_taken : i1
    %2386 = comb.mux %2358, %slots_6.io_out_uop_pc_lob, %slots_5.io_out_uop_pc_lob : i6
    %2387 = comb.mux %2358, %slots_6.io_out_uop_edge_inst, %slots_5.io_out_uop_edge_inst : i1
    %2388 = comb.mux %2358, %slots_6.io_out_uop_ftq_idx, %slots_5.io_out_uop_ftq_idx : i6
    %2389 = comb.mux %2358, %slots_6.io_out_uop_br_tag, %slots_5.io_out_uop_br_tag : i5
    %2390 = comb.mux %2358, %slots_6.io_out_uop_br_mask, %slots_5.io_out_uop_br_mask : i20
    %2391 = comb.mux %2358, %slots_6.io_out_uop_is_sfb, %slots_5.io_out_uop_is_sfb : i1
    %2392 = comb.mux %2358, %slots_6.io_out_uop_is_jal, %slots_5.io_out_uop_is_jal : i1
    %2393 = comb.mux %2358, %slots_6.io_out_uop_is_jalr, %slots_5.io_out_uop_is_jalr : i1
    %2394 = comb.mux %2358, %slots_6.io_out_uop_is_br, %slots_5.io_out_uop_is_br : i1
    %2395 = comb.mux %2358, %slots_6.io_out_uop_iw_p2_poisoned, %slots_5.io_out_uop_iw_p2_poisoned : i1
    %2396 = comb.mux %2358, %slots_6.io_out_uop_iw_p1_poisoned, %slots_5.io_out_uop_iw_p1_poisoned : i1
    %2397 = comb.mux %2358, %slots_6.io_out_uop_iw_state, %slots_5.io_out_uop_iw_state : i2
    %2398 = comb.mux %2358, %slots_6.io_out_uop_fu_code, %slots_5.io_out_uop_fu_code : i10
    %2399 = comb.mux %2358, %slots_6.io_out_uop_is_rvc, %slots_5.io_out_uop_is_rvc : i1
    %2400 = comb.mux %2358, %slots_6.io_out_uop_uopc, %slots_5.io_out_uop_uopc : i7
    %2401 = comb.icmp eq %1687, %c4_i4 : i4
    %2402 = comb.mux %2401, %slots_7.io_will_be_valid, %2359 : i1
    %2403 = comb.mux %2401, %slots_7.io_out_uop_fp_val, %2360 : i1
    %2404 = comb.mux %2401, %slots_7.io_out_uop_lrs2_rtype, %2361 : i2
    %2405 = comb.mux %2401, %slots_7.io_out_uop_lrs1_rtype, %2362 : i2
    %2406 = comb.mux %2401, %slots_7.io_out_uop_dst_rtype, %2363 : i2
    %2407 = comb.mux %2401, %slots_7.io_out_uop_ldst_val, %2364 : i1
    %2408 = comb.mux %2401, %slots_7.io_out_uop_uses_stq, %2365 : i1
    %2409 = comb.mux %2401, %slots_7.io_out_uop_uses_ldq, %2366 : i1
    %2410 = comb.mux %2401, %slots_7.io_out_uop_is_amo, %2367 : i1
    %2411 = comb.mux %2401, %slots_7.io_out_uop_is_fence, %2368 : i1
    %2412 = comb.mux %2401, %slots_7.io_out_uop_mem_signed, %2369 : i1
    %2413 = comb.mux %2401, %slots_7.io_out_uop_mem_size, %2370 : i2
    %2414 = comb.mux %2401, %slots_7.io_out_uop_mem_cmd, %2371 : i5
    %2415 = comb.mux %2401, %slots_7.io_out_uop_bypassable, %2372 : i1
    %2416 = comb.mux %2401, %slots_7.io_out_uop_ppred_busy, %2373 : i1
    %2417 = comb.mux %2401, %slots_7.io_out_uop_prs3_busy, %2374 : i1
    %2418 = comb.mux %2401, %slots_7.io_out_uop_prs2_busy, %2375 : i1
    %2419 = comb.mux %2401, %slots_7.io_out_uop_prs1_busy, %2376 : i1
    %2420 = comb.mux %2401, %slots_7.io_out_uop_prs3, %2377 : i7
    %2421 = comb.mux %2401, %slots_7.io_out_uop_prs2, %2378 : i7
    %2422 = comb.mux %2401, %slots_7.io_out_uop_prs1, %2379 : i7
    %2423 = comb.mux %2401, %slots_7.io_out_uop_pdst, %2380 : i7
    %2424 = comb.mux %2401, %slots_7.io_out_uop_stq_idx, %2381 : i5
    %2425 = comb.mux %2401, %slots_7.io_out_uop_ldq_idx, %2382 : i5
    %2426 = comb.mux %2401, %slots_7.io_out_uop_rob_idx, %2383 : i7
    %2427 = comb.mux %2401, %slots_7.io_out_uop_imm_packed, %2384 : i20
    %2428 = comb.mux %2401, %slots_7.io_out_uop_taken, %2385 : i1
    %2429 = comb.mux %2401, %slots_7.io_out_uop_pc_lob, %2386 : i6
    %2430 = comb.mux %2401, %slots_7.io_out_uop_edge_inst, %2387 : i1
    %2431 = comb.mux %2401, %slots_7.io_out_uop_ftq_idx, %2388 : i6
    %2432 = comb.mux %2401, %slots_7.io_out_uop_br_tag, %2389 : i5
    %2433 = comb.mux %2401, %slots_7.io_out_uop_br_mask, %2390 : i20
    %2434 = comb.mux %2401, %slots_7.io_out_uop_is_sfb, %2391 : i1
    %2435 = comb.mux %2401, %slots_7.io_out_uop_is_jal, %2392 : i1
    %2436 = comb.mux %2401, %slots_7.io_out_uop_is_jalr, %2393 : i1
    %2437 = comb.mux %2401, %slots_7.io_out_uop_is_br, %2394 : i1
    %2438 = comb.mux %2401, %slots_7.io_out_uop_iw_p2_poisoned, %2395 : i1
    %2439 = comb.mux %2401, %slots_7.io_out_uop_iw_p1_poisoned, %2396 : i1
    %2440 = comb.mux %2401, %slots_7.io_out_uop_iw_state, %2397 : i2
    %2441 = comb.mux %2401, %slots_7.io_out_uop_fu_code, %2398 : i10
    %2442 = comb.mux %2401, %slots_7.io_out_uop_is_rvc, %2399 : i1
    %2443 = comb.mux %2401, %slots_7.io_out_uop_uopc, %2400 : i7
    %2444 = comb.icmp eq %1695, %c-8_i4 : i4
    %issue_slots_8_will_be_valid = sv.wire sym @issue_slots_8_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_8_will_be_valid, %slots_8.io_will_be_valid : i1
    %2445 = comb.mux %2444, %slots_8.io_will_be_valid, %2402 {sv.namehint = "_issue_slots_4_in_uop_valid"} : i1
    %issue_slots_4_in_uop_valid = sv.wire sym @issue_slots_4_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_4_in_uop_valid, %2445 : i1
    %issue_slots_8_out_uop_fp_val = sv.wire sym @issue_slots_8_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_fp_val, %slots_8.io_out_uop_fp_val : i1
    %issue_slots_8_out_uop_lrs2_rtype = sv.wire sym @issue_slots_8_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_8_out_uop_lrs2_rtype, %slots_8.io_out_uop_lrs2_rtype : i2
    %issue_slots_8_out_uop_lrs1_rtype = sv.wire sym @issue_slots_8_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_8_out_uop_lrs1_rtype, %slots_8.io_out_uop_lrs1_rtype : i2
    %issue_slots_8_out_uop_dst_rtype = sv.wire sym @issue_slots_8_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_8_out_uop_dst_rtype, %slots_8.io_out_uop_dst_rtype : i2
    %issue_slots_8_out_uop_ldst_val = sv.wire sym @issue_slots_8_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_ldst_val, %slots_8.io_out_uop_ldst_val : i1
    %issue_slots_8_out_uop_uses_stq = sv.wire sym @issue_slots_8_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_uses_stq, %slots_8.io_out_uop_uses_stq : i1
    %issue_slots_8_out_uop_uses_ldq = sv.wire sym @issue_slots_8_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_uses_ldq, %slots_8.io_out_uop_uses_ldq : i1
    %issue_slots_8_out_uop_is_amo = sv.wire sym @issue_slots_8_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_is_amo, %slots_8.io_out_uop_is_amo : i1
    %issue_slots_8_out_uop_is_fence = sv.wire sym @issue_slots_8_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_is_fence, %slots_8.io_out_uop_is_fence : i1
    %issue_slots_8_out_uop_mem_signed = sv.wire sym @issue_slots_8_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_mem_signed, %slots_8.io_out_uop_mem_signed : i1
    %issue_slots_8_out_uop_mem_size = sv.wire sym @issue_slots_8_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_8_out_uop_mem_size, %slots_8.io_out_uop_mem_size : i2
    %issue_slots_8_out_uop_mem_cmd = sv.wire sym @issue_slots_8_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_8_out_uop_mem_cmd, %slots_8.io_out_uop_mem_cmd : i5
    %issue_slots_8_out_uop_bypassable = sv.wire sym @issue_slots_8_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_bypassable, %slots_8.io_out_uop_bypassable : i1
    %issue_slots_8_out_uop_ppred_busy = sv.wire sym @issue_slots_8_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_ppred_busy, %slots_8.io_out_uop_ppred_busy : i1
    %issue_slots_8_out_uop_prs3_busy = sv.wire sym @issue_slots_8_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_prs3_busy, %slots_8.io_out_uop_prs3_busy : i1
    %issue_slots_8_out_uop_prs2_busy = sv.wire sym @issue_slots_8_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_prs2_busy, %slots_8.io_out_uop_prs2_busy : i1
    %issue_slots_8_out_uop_prs1_busy = sv.wire sym @issue_slots_8_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_prs1_busy, %slots_8.io_out_uop_prs1_busy : i1
    %issue_slots_8_out_uop_prs3 = sv.wire sym @issue_slots_8_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_8_out_uop_prs3, %slots_8.io_out_uop_prs3 : i7
    %issue_slots_8_out_uop_prs2 = sv.wire sym @issue_slots_8_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_8_out_uop_prs2, %slots_8.io_out_uop_prs2 : i7
    %issue_slots_8_out_uop_prs1 = sv.wire sym @issue_slots_8_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_8_out_uop_prs1, %slots_8.io_out_uop_prs1 : i7
    %issue_slots_8_out_uop_pdst = sv.wire sym @issue_slots_8_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_8_out_uop_pdst, %slots_8.io_out_uop_pdst : i7
    %issue_slots_8_out_uop_stq_idx = sv.wire sym @issue_slots_8_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_8_out_uop_stq_idx, %slots_8.io_out_uop_stq_idx : i5
    %issue_slots_8_out_uop_ldq_idx = sv.wire sym @issue_slots_8_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_8_out_uop_ldq_idx, %slots_8.io_out_uop_ldq_idx : i5
    %issue_slots_8_out_uop_rob_idx = sv.wire sym @issue_slots_8_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_8_out_uop_rob_idx, %slots_8.io_out_uop_rob_idx : i7
    %issue_slots_8_out_uop_imm_packed = sv.wire sym @issue_slots_8_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_8_out_uop_imm_packed, %slots_8.io_out_uop_imm_packed : i20
    %issue_slots_8_out_uop_taken = sv.wire sym @issue_slots_8_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_taken, %slots_8.io_out_uop_taken : i1
    %issue_slots_8_out_uop_pc_lob = sv.wire sym @issue_slots_8_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_8_out_uop_pc_lob, %slots_8.io_out_uop_pc_lob : i6
    %issue_slots_8_out_uop_edge_inst = sv.wire sym @issue_slots_8_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_edge_inst, %slots_8.io_out_uop_edge_inst : i1
    %issue_slots_8_out_uop_ftq_idx = sv.wire sym @issue_slots_8_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_8_out_uop_ftq_idx, %slots_8.io_out_uop_ftq_idx : i6
    %issue_slots_8_out_uop_br_tag = sv.wire sym @issue_slots_8_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_8_out_uop_br_tag, %slots_8.io_out_uop_br_tag : i5
    %issue_slots_8_out_uop_br_mask = sv.wire sym @issue_slots_8_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_8_out_uop_br_mask, %slots_8.io_out_uop_br_mask : i20
    %issue_slots_8_out_uop_is_sfb = sv.wire sym @issue_slots_8_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_is_sfb, %slots_8.io_out_uop_is_sfb : i1
    %issue_slots_8_out_uop_is_jal = sv.wire sym @issue_slots_8_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_is_jal, %slots_8.io_out_uop_is_jal : i1
    %issue_slots_8_out_uop_is_jalr = sv.wire sym @issue_slots_8_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_is_jalr, %slots_8.io_out_uop_is_jalr : i1
    %issue_slots_8_out_uop_is_br = sv.wire sym @issue_slots_8_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_is_br, %slots_8.io_out_uop_is_br : i1
    %issue_slots_8_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_8_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_iw_p2_poisoned, %slots_8.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_8_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_8_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_iw_p1_poisoned, %slots_8.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_8_out_uop_iw_state = sv.wire sym @issue_slots_8_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_8_out_uop_iw_state, %slots_8.io_out_uop_iw_state : i2
    %issue_slots_8_out_uop_fu_code = sv.wire sym @issue_slots_8_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_8_out_uop_fu_code, %slots_8.io_out_uop_fu_code : i10
    %issue_slots_8_out_uop_is_rvc = sv.wire sym @issue_slots_8_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_8_out_uop_is_rvc, %slots_8.io_out_uop_is_rvc : i1
    %issue_slots_8_out_uop_uopc = sv.wire sym @issue_slots_8_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_8_out_uop_uopc, %slots_8.io_out_uop_uopc : i7
    %2446 = comb.icmp ne %1663, %c0_i4 {sv.namehint = "_issue_slots_4_clear"} : i4
    %issue_slots_4_clear = sv.wire sym @issue_slots_4_clear  : !hw.inout<i1>
    sv.assign %issue_slots_4_clear, %2446 : i1
    %2447 = comb.icmp eq %1679, %c1_i4 : i4
    %2448 = comb.and %2447, %slots_6.io_will_be_valid : i1
    %2449 = comb.icmp eq %1687, %c2_i4 : i4
    %2450 = comb.mux %2449, %slots_7.io_will_be_valid, %2448 : i1
    %2451 = comb.mux %2449, %slots_7.io_out_uop_fp_val, %slots_6.io_out_uop_fp_val : i1
    %2452 = comb.mux %2449, %slots_7.io_out_uop_lrs2_rtype, %slots_6.io_out_uop_lrs2_rtype : i2
    %2453 = comb.mux %2449, %slots_7.io_out_uop_lrs1_rtype, %slots_6.io_out_uop_lrs1_rtype : i2
    %2454 = comb.mux %2449, %slots_7.io_out_uop_dst_rtype, %slots_6.io_out_uop_dst_rtype : i2
    %2455 = comb.mux %2449, %slots_7.io_out_uop_ldst_val, %slots_6.io_out_uop_ldst_val : i1
    %2456 = comb.mux %2449, %slots_7.io_out_uop_uses_stq, %slots_6.io_out_uop_uses_stq : i1
    %2457 = comb.mux %2449, %slots_7.io_out_uop_uses_ldq, %slots_6.io_out_uop_uses_ldq : i1
    %2458 = comb.mux %2449, %slots_7.io_out_uop_is_amo, %slots_6.io_out_uop_is_amo : i1
    %2459 = comb.mux %2449, %slots_7.io_out_uop_is_fence, %slots_6.io_out_uop_is_fence : i1
    %2460 = comb.mux %2449, %slots_7.io_out_uop_mem_signed, %slots_6.io_out_uop_mem_signed : i1
    %2461 = comb.mux %2449, %slots_7.io_out_uop_mem_size, %slots_6.io_out_uop_mem_size : i2
    %2462 = comb.mux %2449, %slots_7.io_out_uop_mem_cmd, %slots_6.io_out_uop_mem_cmd : i5
    %2463 = comb.mux %2449, %slots_7.io_out_uop_bypassable, %slots_6.io_out_uop_bypassable : i1
    %2464 = comb.mux %2449, %slots_7.io_out_uop_ppred_busy, %slots_6.io_out_uop_ppred_busy : i1
    %2465 = comb.mux %2449, %slots_7.io_out_uop_prs3_busy, %slots_6.io_out_uop_prs3_busy : i1
    %2466 = comb.mux %2449, %slots_7.io_out_uop_prs2_busy, %slots_6.io_out_uop_prs2_busy : i1
    %2467 = comb.mux %2449, %slots_7.io_out_uop_prs1_busy, %slots_6.io_out_uop_prs1_busy : i1
    %2468 = comb.mux %2449, %slots_7.io_out_uop_prs3, %slots_6.io_out_uop_prs3 : i7
    %2469 = comb.mux %2449, %slots_7.io_out_uop_prs2, %slots_6.io_out_uop_prs2 : i7
    %2470 = comb.mux %2449, %slots_7.io_out_uop_prs1, %slots_6.io_out_uop_prs1 : i7
    %2471 = comb.mux %2449, %slots_7.io_out_uop_pdst, %slots_6.io_out_uop_pdst : i7
    %2472 = comb.mux %2449, %slots_7.io_out_uop_stq_idx, %slots_6.io_out_uop_stq_idx : i5
    %2473 = comb.mux %2449, %slots_7.io_out_uop_ldq_idx, %slots_6.io_out_uop_ldq_idx : i5
    %2474 = comb.mux %2449, %slots_7.io_out_uop_rob_idx, %slots_6.io_out_uop_rob_idx : i7
    %2475 = comb.mux %2449, %slots_7.io_out_uop_imm_packed, %slots_6.io_out_uop_imm_packed : i20
    %2476 = comb.mux %2449, %slots_7.io_out_uop_taken, %slots_6.io_out_uop_taken : i1
    %2477 = comb.mux %2449, %slots_7.io_out_uop_pc_lob, %slots_6.io_out_uop_pc_lob : i6
    %2478 = comb.mux %2449, %slots_7.io_out_uop_edge_inst, %slots_6.io_out_uop_edge_inst : i1
    %2479 = comb.mux %2449, %slots_7.io_out_uop_ftq_idx, %slots_6.io_out_uop_ftq_idx : i6
    %2480 = comb.mux %2449, %slots_7.io_out_uop_br_tag, %slots_6.io_out_uop_br_tag : i5
    %2481 = comb.mux %2449, %slots_7.io_out_uop_br_mask, %slots_6.io_out_uop_br_mask : i20
    %2482 = comb.mux %2449, %slots_7.io_out_uop_is_sfb, %slots_6.io_out_uop_is_sfb : i1
    %2483 = comb.mux %2449, %slots_7.io_out_uop_is_jal, %slots_6.io_out_uop_is_jal : i1
    %2484 = comb.mux %2449, %slots_7.io_out_uop_is_jalr, %slots_6.io_out_uop_is_jalr : i1
    %2485 = comb.mux %2449, %slots_7.io_out_uop_is_br, %slots_6.io_out_uop_is_br : i1
    %2486 = comb.mux %2449, %slots_7.io_out_uop_iw_p2_poisoned, %slots_6.io_out_uop_iw_p2_poisoned : i1
    %2487 = comb.mux %2449, %slots_7.io_out_uop_iw_p1_poisoned, %slots_6.io_out_uop_iw_p1_poisoned : i1
    %2488 = comb.mux %2449, %slots_7.io_out_uop_iw_state, %slots_6.io_out_uop_iw_state : i2
    %2489 = comb.mux %2449, %slots_7.io_out_uop_fu_code, %slots_6.io_out_uop_fu_code : i10
    %2490 = comb.mux %2449, %slots_7.io_out_uop_is_rvc, %slots_6.io_out_uop_is_rvc : i1
    %2491 = comb.mux %2449, %slots_7.io_out_uop_uopc, %slots_6.io_out_uop_uopc : i7
    %2492 = comb.icmp eq %1695, %c4_i4 : i4
    %2493 = comb.mux %2492, %slots_8.io_will_be_valid, %2450 : i1
    %2494 = comb.mux %2492, %slots_8.io_out_uop_fp_val, %2451 : i1
    %2495 = comb.mux %2492, %slots_8.io_out_uop_lrs2_rtype, %2452 : i2
    %2496 = comb.mux %2492, %slots_8.io_out_uop_lrs1_rtype, %2453 : i2
    %2497 = comb.mux %2492, %slots_8.io_out_uop_dst_rtype, %2454 : i2
    %2498 = comb.mux %2492, %slots_8.io_out_uop_ldst_val, %2455 : i1
    %2499 = comb.mux %2492, %slots_8.io_out_uop_uses_stq, %2456 : i1
    %2500 = comb.mux %2492, %slots_8.io_out_uop_uses_ldq, %2457 : i1
    %2501 = comb.mux %2492, %slots_8.io_out_uop_is_amo, %2458 : i1
    %2502 = comb.mux %2492, %slots_8.io_out_uop_is_fence, %2459 : i1
    %2503 = comb.mux %2492, %slots_8.io_out_uop_mem_signed, %2460 : i1
    %2504 = comb.mux %2492, %slots_8.io_out_uop_mem_size, %2461 : i2
    %2505 = comb.mux %2492, %slots_8.io_out_uop_mem_cmd, %2462 : i5
    %2506 = comb.mux %2492, %slots_8.io_out_uop_bypassable, %2463 : i1
    %2507 = comb.mux %2492, %slots_8.io_out_uop_ppred_busy, %2464 : i1
    %2508 = comb.mux %2492, %slots_8.io_out_uop_prs3_busy, %2465 : i1
    %2509 = comb.mux %2492, %slots_8.io_out_uop_prs2_busy, %2466 : i1
    %2510 = comb.mux %2492, %slots_8.io_out_uop_prs1_busy, %2467 : i1
    %2511 = comb.mux %2492, %slots_8.io_out_uop_prs3, %2468 : i7
    %2512 = comb.mux %2492, %slots_8.io_out_uop_prs2, %2469 : i7
    %2513 = comb.mux %2492, %slots_8.io_out_uop_prs1, %2470 : i7
    %2514 = comb.mux %2492, %slots_8.io_out_uop_pdst, %2471 : i7
    %2515 = comb.mux %2492, %slots_8.io_out_uop_stq_idx, %2472 : i5
    %2516 = comb.mux %2492, %slots_8.io_out_uop_ldq_idx, %2473 : i5
    %2517 = comb.mux %2492, %slots_8.io_out_uop_rob_idx, %2474 : i7
    %2518 = comb.mux %2492, %slots_8.io_out_uop_imm_packed, %2475 : i20
    %2519 = comb.mux %2492, %slots_8.io_out_uop_taken, %2476 : i1
    %2520 = comb.mux %2492, %slots_8.io_out_uop_pc_lob, %2477 : i6
    %2521 = comb.mux %2492, %slots_8.io_out_uop_edge_inst, %2478 : i1
    %2522 = comb.mux %2492, %slots_8.io_out_uop_ftq_idx, %2479 : i6
    %2523 = comb.mux %2492, %slots_8.io_out_uop_br_tag, %2480 : i5
    %2524 = comb.mux %2492, %slots_8.io_out_uop_br_mask, %2481 : i20
    %2525 = comb.mux %2492, %slots_8.io_out_uop_is_sfb, %2482 : i1
    %2526 = comb.mux %2492, %slots_8.io_out_uop_is_jal, %2483 : i1
    %2527 = comb.mux %2492, %slots_8.io_out_uop_is_jalr, %2484 : i1
    %2528 = comb.mux %2492, %slots_8.io_out_uop_is_br, %2485 : i1
    %2529 = comb.mux %2492, %slots_8.io_out_uop_iw_p2_poisoned, %2486 : i1
    %2530 = comb.mux %2492, %slots_8.io_out_uop_iw_p1_poisoned, %2487 : i1
    %2531 = comb.mux %2492, %slots_8.io_out_uop_iw_state, %2488 : i2
    %2532 = comb.mux %2492, %slots_8.io_out_uop_fu_code, %2489 : i10
    %2533 = comb.mux %2492, %slots_8.io_out_uop_is_rvc, %2490 : i1
    %2534 = comb.mux %2492, %slots_8.io_out_uop_uopc, %2491 : i7
    %2535 = comb.icmp eq %1703, %c-8_i4 : i4
    %issue_slots_9_will_be_valid = sv.wire sym @issue_slots_9_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_9_will_be_valid, %slots_9.io_will_be_valid : i1
    %2536 = comb.mux %2535, %slots_9.io_will_be_valid, %2493 {sv.namehint = "_issue_slots_5_in_uop_valid"} : i1
    %issue_slots_5_in_uop_valid = sv.wire sym @issue_slots_5_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_5_in_uop_valid, %2536 : i1
    %issue_slots_9_out_uop_fp_val = sv.wire sym @issue_slots_9_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_fp_val, %slots_9.io_out_uop_fp_val : i1
    %issue_slots_9_out_uop_lrs2_rtype = sv.wire sym @issue_slots_9_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_9_out_uop_lrs2_rtype, %slots_9.io_out_uop_lrs2_rtype : i2
    %issue_slots_9_out_uop_lrs1_rtype = sv.wire sym @issue_slots_9_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_9_out_uop_lrs1_rtype, %slots_9.io_out_uop_lrs1_rtype : i2
    %issue_slots_9_out_uop_dst_rtype = sv.wire sym @issue_slots_9_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_9_out_uop_dst_rtype, %slots_9.io_out_uop_dst_rtype : i2
    %issue_slots_9_out_uop_ldst_val = sv.wire sym @issue_slots_9_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_ldst_val, %slots_9.io_out_uop_ldst_val : i1
    %issue_slots_9_out_uop_uses_stq = sv.wire sym @issue_slots_9_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_uses_stq, %slots_9.io_out_uop_uses_stq : i1
    %issue_slots_9_out_uop_uses_ldq = sv.wire sym @issue_slots_9_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_uses_ldq, %slots_9.io_out_uop_uses_ldq : i1
    %issue_slots_9_out_uop_is_amo = sv.wire sym @issue_slots_9_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_is_amo, %slots_9.io_out_uop_is_amo : i1
    %issue_slots_9_out_uop_is_fence = sv.wire sym @issue_slots_9_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_is_fence, %slots_9.io_out_uop_is_fence : i1
    %issue_slots_9_out_uop_mem_signed = sv.wire sym @issue_slots_9_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_mem_signed, %slots_9.io_out_uop_mem_signed : i1
    %issue_slots_9_out_uop_mem_size = sv.wire sym @issue_slots_9_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_9_out_uop_mem_size, %slots_9.io_out_uop_mem_size : i2
    %issue_slots_9_out_uop_mem_cmd = sv.wire sym @issue_slots_9_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_9_out_uop_mem_cmd, %slots_9.io_out_uop_mem_cmd : i5
    %issue_slots_9_out_uop_bypassable = sv.wire sym @issue_slots_9_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_bypassable, %slots_9.io_out_uop_bypassable : i1
    %issue_slots_9_out_uop_ppred_busy = sv.wire sym @issue_slots_9_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_ppred_busy, %slots_9.io_out_uop_ppred_busy : i1
    %issue_slots_9_out_uop_prs3_busy = sv.wire sym @issue_slots_9_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_prs3_busy, %slots_9.io_out_uop_prs3_busy : i1
    %issue_slots_9_out_uop_prs2_busy = sv.wire sym @issue_slots_9_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_prs2_busy, %slots_9.io_out_uop_prs2_busy : i1
    %issue_slots_9_out_uop_prs1_busy = sv.wire sym @issue_slots_9_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_prs1_busy, %slots_9.io_out_uop_prs1_busy : i1
    %issue_slots_9_out_uop_prs3 = sv.wire sym @issue_slots_9_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_9_out_uop_prs3, %slots_9.io_out_uop_prs3 : i7
    %issue_slots_9_out_uop_prs2 = sv.wire sym @issue_slots_9_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_9_out_uop_prs2, %slots_9.io_out_uop_prs2 : i7
    %issue_slots_9_out_uop_prs1 = sv.wire sym @issue_slots_9_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_9_out_uop_prs1, %slots_9.io_out_uop_prs1 : i7
    %issue_slots_9_out_uop_pdst = sv.wire sym @issue_slots_9_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_9_out_uop_pdst, %slots_9.io_out_uop_pdst : i7
    %issue_slots_9_out_uop_stq_idx = sv.wire sym @issue_slots_9_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_9_out_uop_stq_idx, %slots_9.io_out_uop_stq_idx : i5
    %issue_slots_9_out_uop_ldq_idx = sv.wire sym @issue_slots_9_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_9_out_uop_ldq_idx, %slots_9.io_out_uop_ldq_idx : i5
    %issue_slots_9_out_uop_rob_idx = sv.wire sym @issue_slots_9_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_9_out_uop_rob_idx, %slots_9.io_out_uop_rob_idx : i7
    %issue_slots_9_out_uop_imm_packed = sv.wire sym @issue_slots_9_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_9_out_uop_imm_packed, %slots_9.io_out_uop_imm_packed : i20
    %issue_slots_9_out_uop_taken = sv.wire sym @issue_slots_9_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_taken, %slots_9.io_out_uop_taken : i1
    %issue_slots_9_out_uop_pc_lob = sv.wire sym @issue_slots_9_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_9_out_uop_pc_lob, %slots_9.io_out_uop_pc_lob : i6
    %issue_slots_9_out_uop_edge_inst = sv.wire sym @issue_slots_9_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_edge_inst, %slots_9.io_out_uop_edge_inst : i1
    %issue_slots_9_out_uop_ftq_idx = sv.wire sym @issue_slots_9_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_9_out_uop_ftq_idx, %slots_9.io_out_uop_ftq_idx : i6
    %issue_slots_9_out_uop_br_tag = sv.wire sym @issue_slots_9_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_9_out_uop_br_tag, %slots_9.io_out_uop_br_tag : i5
    %issue_slots_9_out_uop_br_mask = sv.wire sym @issue_slots_9_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_9_out_uop_br_mask, %slots_9.io_out_uop_br_mask : i20
    %issue_slots_9_out_uop_is_sfb = sv.wire sym @issue_slots_9_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_is_sfb, %slots_9.io_out_uop_is_sfb : i1
    %issue_slots_9_out_uop_is_jal = sv.wire sym @issue_slots_9_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_is_jal, %slots_9.io_out_uop_is_jal : i1
    %issue_slots_9_out_uop_is_jalr = sv.wire sym @issue_slots_9_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_is_jalr, %slots_9.io_out_uop_is_jalr : i1
    %issue_slots_9_out_uop_is_br = sv.wire sym @issue_slots_9_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_is_br, %slots_9.io_out_uop_is_br : i1
    %issue_slots_9_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_9_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_iw_p2_poisoned, %slots_9.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_9_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_9_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_iw_p1_poisoned, %slots_9.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_9_out_uop_iw_state = sv.wire sym @issue_slots_9_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_9_out_uop_iw_state, %slots_9.io_out_uop_iw_state : i2
    %issue_slots_9_out_uop_fu_code = sv.wire sym @issue_slots_9_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_9_out_uop_fu_code, %slots_9.io_out_uop_fu_code : i10
    %issue_slots_9_out_uop_is_rvc = sv.wire sym @issue_slots_9_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_9_out_uop_is_rvc, %slots_9.io_out_uop_is_rvc : i1
    %issue_slots_9_out_uop_uopc = sv.wire sym @issue_slots_9_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_9_out_uop_uopc, %slots_9.io_out_uop_uopc : i7
    %2537 = comb.icmp ne %1671, %c0_i4 {sv.namehint = "_issue_slots_5_clear"} : i4
    %issue_slots_5_clear = sv.wire sym @issue_slots_5_clear  : !hw.inout<i1>
    sv.assign %issue_slots_5_clear, %2537 : i1
    %2538 = comb.icmp eq %1687, %c1_i4 : i4
    %2539 = comb.and %2538, %slots_7.io_will_be_valid : i1
    %2540 = comb.icmp eq %1695, %c2_i4 : i4
    %2541 = comb.mux %2540, %slots_8.io_will_be_valid, %2539 : i1
    %2542 = comb.mux %2540, %slots_8.io_out_uop_fp_val, %slots_7.io_out_uop_fp_val : i1
    %2543 = comb.mux %2540, %slots_8.io_out_uop_lrs2_rtype, %slots_7.io_out_uop_lrs2_rtype : i2
    %2544 = comb.mux %2540, %slots_8.io_out_uop_lrs1_rtype, %slots_7.io_out_uop_lrs1_rtype : i2
    %2545 = comb.mux %2540, %slots_8.io_out_uop_dst_rtype, %slots_7.io_out_uop_dst_rtype : i2
    %2546 = comb.mux %2540, %slots_8.io_out_uop_ldst_val, %slots_7.io_out_uop_ldst_val : i1
    %2547 = comb.mux %2540, %slots_8.io_out_uop_uses_stq, %slots_7.io_out_uop_uses_stq : i1
    %2548 = comb.mux %2540, %slots_8.io_out_uop_uses_ldq, %slots_7.io_out_uop_uses_ldq : i1
    %2549 = comb.mux %2540, %slots_8.io_out_uop_is_amo, %slots_7.io_out_uop_is_amo : i1
    %2550 = comb.mux %2540, %slots_8.io_out_uop_is_fence, %slots_7.io_out_uop_is_fence : i1
    %2551 = comb.mux %2540, %slots_8.io_out_uop_mem_signed, %slots_7.io_out_uop_mem_signed : i1
    %2552 = comb.mux %2540, %slots_8.io_out_uop_mem_size, %slots_7.io_out_uop_mem_size : i2
    %2553 = comb.mux %2540, %slots_8.io_out_uop_mem_cmd, %slots_7.io_out_uop_mem_cmd : i5
    %2554 = comb.mux %2540, %slots_8.io_out_uop_bypassable, %slots_7.io_out_uop_bypassable : i1
    %2555 = comb.mux %2540, %slots_8.io_out_uop_ppred_busy, %slots_7.io_out_uop_ppred_busy : i1
    %2556 = comb.mux %2540, %slots_8.io_out_uop_prs3_busy, %slots_7.io_out_uop_prs3_busy : i1
    %2557 = comb.mux %2540, %slots_8.io_out_uop_prs2_busy, %slots_7.io_out_uop_prs2_busy : i1
    %2558 = comb.mux %2540, %slots_8.io_out_uop_prs1_busy, %slots_7.io_out_uop_prs1_busy : i1
    %2559 = comb.mux %2540, %slots_8.io_out_uop_prs3, %slots_7.io_out_uop_prs3 : i7
    %2560 = comb.mux %2540, %slots_8.io_out_uop_prs2, %slots_7.io_out_uop_prs2 : i7
    %2561 = comb.mux %2540, %slots_8.io_out_uop_prs1, %slots_7.io_out_uop_prs1 : i7
    %2562 = comb.mux %2540, %slots_8.io_out_uop_pdst, %slots_7.io_out_uop_pdst : i7
    %2563 = comb.mux %2540, %slots_8.io_out_uop_stq_idx, %slots_7.io_out_uop_stq_idx : i5
    %2564 = comb.mux %2540, %slots_8.io_out_uop_ldq_idx, %slots_7.io_out_uop_ldq_idx : i5
    %2565 = comb.mux %2540, %slots_8.io_out_uop_rob_idx, %slots_7.io_out_uop_rob_idx : i7
    %2566 = comb.mux %2540, %slots_8.io_out_uop_imm_packed, %slots_7.io_out_uop_imm_packed : i20
    %2567 = comb.mux %2540, %slots_8.io_out_uop_taken, %slots_7.io_out_uop_taken : i1
    %2568 = comb.mux %2540, %slots_8.io_out_uop_pc_lob, %slots_7.io_out_uop_pc_lob : i6
    %2569 = comb.mux %2540, %slots_8.io_out_uop_edge_inst, %slots_7.io_out_uop_edge_inst : i1
    %2570 = comb.mux %2540, %slots_8.io_out_uop_ftq_idx, %slots_7.io_out_uop_ftq_idx : i6
    %2571 = comb.mux %2540, %slots_8.io_out_uop_br_tag, %slots_7.io_out_uop_br_tag : i5
    %2572 = comb.mux %2540, %slots_8.io_out_uop_br_mask, %slots_7.io_out_uop_br_mask : i20
    %2573 = comb.mux %2540, %slots_8.io_out_uop_is_sfb, %slots_7.io_out_uop_is_sfb : i1
    %2574 = comb.mux %2540, %slots_8.io_out_uop_is_jal, %slots_7.io_out_uop_is_jal : i1
    %2575 = comb.mux %2540, %slots_8.io_out_uop_is_jalr, %slots_7.io_out_uop_is_jalr : i1
    %2576 = comb.mux %2540, %slots_8.io_out_uop_is_br, %slots_7.io_out_uop_is_br : i1
    %2577 = comb.mux %2540, %slots_8.io_out_uop_iw_p2_poisoned, %slots_7.io_out_uop_iw_p2_poisoned : i1
    %2578 = comb.mux %2540, %slots_8.io_out_uop_iw_p1_poisoned, %slots_7.io_out_uop_iw_p1_poisoned : i1
    %2579 = comb.mux %2540, %slots_8.io_out_uop_iw_state, %slots_7.io_out_uop_iw_state : i2
    %2580 = comb.mux %2540, %slots_8.io_out_uop_fu_code, %slots_7.io_out_uop_fu_code : i10
    %2581 = comb.mux %2540, %slots_8.io_out_uop_is_rvc, %slots_7.io_out_uop_is_rvc : i1
    %2582 = comb.mux %2540, %slots_8.io_out_uop_uopc, %slots_7.io_out_uop_uopc : i7
    %2583 = comb.icmp eq %1703, %c4_i4 : i4
    %2584 = comb.mux %2583, %slots_9.io_will_be_valid, %2541 : i1
    %2585 = comb.mux %2583, %slots_9.io_out_uop_fp_val, %2542 : i1
    %2586 = comb.mux %2583, %slots_9.io_out_uop_lrs2_rtype, %2543 : i2
    %2587 = comb.mux %2583, %slots_9.io_out_uop_lrs1_rtype, %2544 : i2
    %2588 = comb.mux %2583, %slots_9.io_out_uop_dst_rtype, %2545 : i2
    %2589 = comb.mux %2583, %slots_9.io_out_uop_ldst_val, %2546 : i1
    %2590 = comb.mux %2583, %slots_9.io_out_uop_uses_stq, %2547 : i1
    %2591 = comb.mux %2583, %slots_9.io_out_uop_uses_ldq, %2548 : i1
    %2592 = comb.mux %2583, %slots_9.io_out_uop_is_amo, %2549 : i1
    %2593 = comb.mux %2583, %slots_9.io_out_uop_is_fence, %2550 : i1
    %2594 = comb.mux %2583, %slots_9.io_out_uop_mem_signed, %2551 : i1
    %2595 = comb.mux %2583, %slots_9.io_out_uop_mem_size, %2552 : i2
    %2596 = comb.mux %2583, %slots_9.io_out_uop_mem_cmd, %2553 : i5
    %2597 = comb.mux %2583, %slots_9.io_out_uop_bypassable, %2554 : i1
    %2598 = comb.mux %2583, %slots_9.io_out_uop_ppred_busy, %2555 : i1
    %2599 = comb.mux %2583, %slots_9.io_out_uop_prs3_busy, %2556 : i1
    %2600 = comb.mux %2583, %slots_9.io_out_uop_prs2_busy, %2557 : i1
    %2601 = comb.mux %2583, %slots_9.io_out_uop_prs1_busy, %2558 : i1
    %2602 = comb.mux %2583, %slots_9.io_out_uop_prs3, %2559 : i7
    %2603 = comb.mux %2583, %slots_9.io_out_uop_prs2, %2560 : i7
    %2604 = comb.mux %2583, %slots_9.io_out_uop_prs1, %2561 : i7
    %2605 = comb.mux %2583, %slots_9.io_out_uop_pdst, %2562 : i7
    %2606 = comb.mux %2583, %slots_9.io_out_uop_stq_idx, %2563 : i5
    %2607 = comb.mux %2583, %slots_9.io_out_uop_ldq_idx, %2564 : i5
    %2608 = comb.mux %2583, %slots_9.io_out_uop_rob_idx, %2565 : i7
    %2609 = comb.mux %2583, %slots_9.io_out_uop_imm_packed, %2566 : i20
    %2610 = comb.mux %2583, %slots_9.io_out_uop_taken, %2567 : i1
    %2611 = comb.mux %2583, %slots_9.io_out_uop_pc_lob, %2568 : i6
    %2612 = comb.mux %2583, %slots_9.io_out_uop_edge_inst, %2569 : i1
    %2613 = comb.mux %2583, %slots_9.io_out_uop_ftq_idx, %2570 : i6
    %2614 = comb.mux %2583, %slots_9.io_out_uop_br_tag, %2571 : i5
    %2615 = comb.mux %2583, %slots_9.io_out_uop_br_mask, %2572 : i20
    %2616 = comb.mux %2583, %slots_9.io_out_uop_is_sfb, %2573 : i1
    %2617 = comb.mux %2583, %slots_9.io_out_uop_is_jal, %2574 : i1
    %2618 = comb.mux %2583, %slots_9.io_out_uop_is_jalr, %2575 : i1
    %2619 = comb.mux %2583, %slots_9.io_out_uop_is_br, %2576 : i1
    %2620 = comb.mux %2583, %slots_9.io_out_uop_iw_p2_poisoned, %2577 : i1
    %2621 = comb.mux %2583, %slots_9.io_out_uop_iw_p1_poisoned, %2578 : i1
    %2622 = comb.mux %2583, %slots_9.io_out_uop_iw_state, %2579 : i2
    %2623 = comb.mux %2583, %slots_9.io_out_uop_fu_code, %2580 : i10
    %2624 = comb.mux %2583, %slots_9.io_out_uop_is_rvc, %2581 : i1
    %2625 = comb.mux %2583, %slots_9.io_out_uop_uopc, %2582 : i7
    %2626 = comb.icmp eq %1711, %c-8_i4 : i4
    %issue_slots_10_will_be_valid = sv.wire sym @issue_slots_10_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_10_will_be_valid, %slots_10.io_will_be_valid : i1
    %2627 = comb.mux %2626, %slots_10.io_will_be_valid, %2584 {sv.namehint = "_issue_slots_6_in_uop_valid"} : i1
    %issue_slots_6_in_uop_valid = sv.wire sym @issue_slots_6_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_6_in_uop_valid, %2627 : i1
    %issue_slots_10_out_uop_fp_val = sv.wire sym @issue_slots_10_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_fp_val, %slots_10.io_out_uop_fp_val : i1
    %issue_slots_10_out_uop_lrs2_rtype = sv.wire sym @issue_slots_10_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_10_out_uop_lrs2_rtype, %slots_10.io_out_uop_lrs2_rtype : i2
    %issue_slots_10_out_uop_lrs1_rtype = sv.wire sym @issue_slots_10_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_10_out_uop_lrs1_rtype, %slots_10.io_out_uop_lrs1_rtype : i2
    %issue_slots_10_out_uop_dst_rtype = sv.wire sym @issue_slots_10_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_10_out_uop_dst_rtype, %slots_10.io_out_uop_dst_rtype : i2
    %issue_slots_10_out_uop_ldst_val = sv.wire sym @issue_slots_10_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_ldst_val, %slots_10.io_out_uop_ldst_val : i1
    %issue_slots_10_out_uop_uses_stq = sv.wire sym @issue_slots_10_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_uses_stq, %slots_10.io_out_uop_uses_stq : i1
    %issue_slots_10_out_uop_uses_ldq = sv.wire sym @issue_slots_10_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_uses_ldq, %slots_10.io_out_uop_uses_ldq : i1
    %issue_slots_10_out_uop_is_amo = sv.wire sym @issue_slots_10_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_is_amo, %slots_10.io_out_uop_is_amo : i1
    %issue_slots_10_out_uop_is_fence = sv.wire sym @issue_slots_10_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_is_fence, %slots_10.io_out_uop_is_fence : i1
    %issue_slots_10_out_uop_mem_signed = sv.wire sym @issue_slots_10_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_mem_signed, %slots_10.io_out_uop_mem_signed : i1
    %issue_slots_10_out_uop_mem_size = sv.wire sym @issue_slots_10_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_10_out_uop_mem_size, %slots_10.io_out_uop_mem_size : i2
    %issue_slots_10_out_uop_mem_cmd = sv.wire sym @issue_slots_10_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_10_out_uop_mem_cmd, %slots_10.io_out_uop_mem_cmd : i5
    %issue_slots_10_out_uop_bypassable = sv.wire sym @issue_slots_10_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_bypassable, %slots_10.io_out_uop_bypassable : i1
    %issue_slots_10_out_uop_ppred_busy = sv.wire sym @issue_slots_10_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_ppred_busy, %slots_10.io_out_uop_ppred_busy : i1
    %issue_slots_10_out_uop_prs3_busy = sv.wire sym @issue_slots_10_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_prs3_busy, %slots_10.io_out_uop_prs3_busy : i1
    %issue_slots_10_out_uop_prs2_busy = sv.wire sym @issue_slots_10_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_prs2_busy, %slots_10.io_out_uop_prs2_busy : i1
    %issue_slots_10_out_uop_prs1_busy = sv.wire sym @issue_slots_10_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_prs1_busy, %slots_10.io_out_uop_prs1_busy : i1
    %issue_slots_10_out_uop_prs3 = sv.wire sym @issue_slots_10_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_10_out_uop_prs3, %slots_10.io_out_uop_prs3 : i7
    %issue_slots_10_out_uop_prs2 = sv.wire sym @issue_slots_10_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_10_out_uop_prs2, %slots_10.io_out_uop_prs2 : i7
    %issue_slots_10_out_uop_prs1 = sv.wire sym @issue_slots_10_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_10_out_uop_prs1, %slots_10.io_out_uop_prs1 : i7
    %issue_slots_10_out_uop_pdst = sv.wire sym @issue_slots_10_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_10_out_uop_pdst, %slots_10.io_out_uop_pdst : i7
    %issue_slots_10_out_uop_stq_idx = sv.wire sym @issue_slots_10_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_10_out_uop_stq_idx, %slots_10.io_out_uop_stq_idx : i5
    %issue_slots_10_out_uop_ldq_idx = sv.wire sym @issue_slots_10_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_10_out_uop_ldq_idx, %slots_10.io_out_uop_ldq_idx : i5
    %issue_slots_10_out_uop_rob_idx = sv.wire sym @issue_slots_10_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_10_out_uop_rob_idx, %slots_10.io_out_uop_rob_idx : i7
    %issue_slots_10_out_uop_imm_packed = sv.wire sym @issue_slots_10_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_10_out_uop_imm_packed, %slots_10.io_out_uop_imm_packed : i20
    %issue_slots_10_out_uop_taken = sv.wire sym @issue_slots_10_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_taken, %slots_10.io_out_uop_taken : i1
    %issue_slots_10_out_uop_pc_lob = sv.wire sym @issue_slots_10_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_10_out_uop_pc_lob, %slots_10.io_out_uop_pc_lob : i6
    %issue_slots_10_out_uop_edge_inst = sv.wire sym @issue_slots_10_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_edge_inst, %slots_10.io_out_uop_edge_inst : i1
    %issue_slots_10_out_uop_ftq_idx = sv.wire sym @issue_slots_10_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_10_out_uop_ftq_idx, %slots_10.io_out_uop_ftq_idx : i6
    %issue_slots_10_out_uop_br_tag = sv.wire sym @issue_slots_10_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_10_out_uop_br_tag, %slots_10.io_out_uop_br_tag : i5
    %issue_slots_10_out_uop_br_mask = sv.wire sym @issue_slots_10_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_10_out_uop_br_mask, %slots_10.io_out_uop_br_mask : i20
    %issue_slots_10_out_uop_is_sfb = sv.wire sym @issue_slots_10_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_is_sfb, %slots_10.io_out_uop_is_sfb : i1
    %issue_slots_10_out_uop_is_jal = sv.wire sym @issue_slots_10_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_is_jal, %slots_10.io_out_uop_is_jal : i1
    %issue_slots_10_out_uop_is_jalr = sv.wire sym @issue_slots_10_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_is_jalr, %slots_10.io_out_uop_is_jalr : i1
    %issue_slots_10_out_uop_is_br = sv.wire sym @issue_slots_10_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_is_br, %slots_10.io_out_uop_is_br : i1
    %issue_slots_10_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_10_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_iw_p2_poisoned, %slots_10.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_10_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_10_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_iw_p1_poisoned, %slots_10.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_10_out_uop_iw_state = sv.wire sym @issue_slots_10_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_10_out_uop_iw_state, %slots_10.io_out_uop_iw_state : i2
    %issue_slots_10_out_uop_fu_code = sv.wire sym @issue_slots_10_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_10_out_uop_fu_code, %slots_10.io_out_uop_fu_code : i10
    %issue_slots_10_out_uop_is_rvc = sv.wire sym @issue_slots_10_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_10_out_uop_is_rvc, %slots_10.io_out_uop_is_rvc : i1
    %issue_slots_10_out_uop_uopc = sv.wire sym @issue_slots_10_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_10_out_uop_uopc, %slots_10.io_out_uop_uopc : i7
    %2628 = comb.icmp ne %1679, %c0_i4 {sv.namehint = "_issue_slots_6_clear"} : i4
    %issue_slots_6_clear = sv.wire sym @issue_slots_6_clear  : !hw.inout<i1>
    sv.assign %issue_slots_6_clear, %2628 : i1
    %2629 = comb.icmp eq %1695, %c1_i4 : i4
    %2630 = comb.and %2629, %slots_8.io_will_be_valid : i1
    %2631 = comb.icmp eq %1703, %c2_i4 : i4
    %2632 = comb.mux %2631, %slots_9.io_will_be_valid, %2630 : i1
    %2633 = comb.mux %2631, %slots_9.io_out_uop_fp_val, %slots_8.io_out_uop_fp_val : i1
    %2634 = comb.mux %2631, %slots_9.io_out_uop_lrs2_rtype, %slots_8.io_out_uop_lrs2_rtype : i2
    %2635 = comb.mux %2631, %slots_9.io_out_uop_lrs1_rtype, %slots_8.io_out_uop_lrs1_rtype : i2
    %2636 = comb.mux %2631, %slots_9.io_out_uop_dst_rtype, %slots_8.io_out_uop_dst_rtype : i2
    %2637 = comb.mux %2631, %slots_9.io_out_uop_ldst_val, %slots_8.io_out_uop_ldst_val : i1
    %2638 = comb.mux %2631, %slots_9.io_out_uop_uses_stq, %slots_8.io_out_uop_uses_stq : i1
    %2639 = comb.mux %2631, %slots_9.io_out_uop_uses_ldq, %slots_8.io_out_uop_uses_ldq : i1
    %2640 = comb.mux %2631, %slots_9.io_out_uop_is_amo, %slots_8.io_out_uop_is_amo : i1
    %2641 = comb.mux %2631, %slots_9.io_out_uop_is_fence, %slots_8.io_out_uop_is_fence : i1
    %2642 = comb.mux %2631, %slots_9.io_out_uop_mem_signed, %slots_8.io_out_uop_mem_signed : i1
    %2643 = comb.mux %2631, %slots_9.io_out_uop_mem_size, %slots_8.io_out_uop_mem_size : i2
    %2644 = comb.mux %2631, %slots_9.io_out_uop_mem_cmd, %slots_8.io_out_uop_mem_cmd : i5
    %2645 = comb.mux %2631, %slots_9.io_out_uop_bypassable, %slots_8.io_out_uop_bypassable : i1
    %2646 = comb.mux %2631, %slots_9.io_out_uop_ppred_busy, %slots_8.io_out_uop_ppred_busy : i1
    %2647 = comb.mux %2631, %slots_9.io_out_uop_prs3_busy, %slots_8.io_out_uop_prs3_busy : i1
    %2648 = comb.mux %2631, %slots_9.io_out_uop_prs2_busy, %slots_8.io_out_uop_prs2_busy : i1
    %2649 = comb.mux %2631, %slots_9.io_out_uop_prs1_busy, %slots_8.io_out_uop_prs1_busy : i1
    %2650 = comb.mux %2631, %slots_9.io_out_uop_prs3, %slots_8.io_out_uop_prs3 : i7
    %2651 = comb.mux %2631, %slots_9.io_out_uop_prs2, %slots_8.io_out_uop_prs2 : i7
    %2652 = comb.mux %2631, %slots_9.io_out_uop_prs1, %slots_8.io_out_uop_prs1 : i7
    %2653 = comb.mux %2631, %slots_9.io_out_uop_pdst, %slots_8.io_out_uop_pdst : i7
    %2654 = comb.mux %2631, %slots_9.io_out_uop_stq_idx, %slots_8.io_out_uop_stq_idx : i5
    %2655 = comb.mux %2631, %slots_9.io_out_uop_ldq_idx, %slots_8.io_out_uop_ldq_idx : i5
    %2656 = comb.mux %2631, %slots_9.io_out_uop_rob_idx, %slots_8.io_out_uop_rob_idx : i7
    %2657 = comb.mux %2631, %slots_9.io_out_uop_imm_packed, %slots_8.io_out_uop_imm_packed : i20
    %2658 = comb.mux %2631, %slots_9.io_out_uop_taken, %slots_8.io_out_uop_taken : i1
    %2659 = comb.mux %2631, %slots_9.io_out_uop_pc_lob, %slots_8.io_out_uop_pc_lob : i6
    %2660 = comb.mux %2631, %slots_9.io_out_uop_edge_inst, %slots_8.io_out_uop_edge_inst : i1
    %2661 = comb.mux %2631, %slots_9.io_out_uop_ftq_idx, %slots_8.io_out_uop_ftq_idx : i6
    %2662 = comb.mux %2631, %slots_9.io_out_uop_br_tag, %slots_8.io_out_uop_br_tag : i5
    %2663 = comb.mux %2631, %slots_9.io_out_uop_br_mask, %slots_8.io_out_uop_br_mask : i20
    %2664 = comb.mux %2631, %slots_9.io_out_uop_is_sfb, %slots_8.io_out_uop_is_sfb : i1
    %2665 = comb.mux %2631, %slots_9.io_out_uop_is_jal, %slots_8.io_out_uop_is_jal : i1
    %2666 = comb.mux %2631, %slots_9.io_out_uop_is_jalr, %slots_8.io_out_uop_is_jalr : i1
    %2667 = comb.mux %2631, %slots_9.io_out_uop_is_br, %slots_8.io_out_uop_is_br : i1
    %2668 = comb.mux %2631, %slots_9.io_out_uop_iw_p2_poisoned, %slots_8.io_out_uop_iw_p2_poisoned : i1
    %2669 = comb.mux %2631, %slots_9.io_out_uop_iw_p1_poisoned, %slots_8.io_out_uop_iw_p1_poisoned : i1
    %2670 = comb.mux %2631, %slots_9.io_out_uop_iw_state, %slots_8.io_out_uop_iw_state : i2
    %2671 = comb.mux %2631, %slots_9.io_out_uop_fu_code, %slots_8.io_out_uop_fu_code : i10
    %2672 = comb.mux %2631, %slots_9.io_out_uop_is_rvc, %slots_8.io_out_uop_is_rvc : i1
    %2673 = comb.mux %2631, %slots_9.io_out_uop_uopc, %slots_8.io_out_uop_uopc : i7
    %2674 = comb.icmp eq %1711, %c4_i4 : i4
    %2675 = comb.mux %2674, %slots_10.io_will_be_valid, %2632 : i1
    %2676 = comb.mux %2674, %slots_10.io_out_uop_fp_val, %2633 : i1
    %2677 = comb.mux %2674, %slots_10.io_out_uop_lrs2_rtype, %2634 : i2
    %2678 = comb.mux %2674, %slots_10.io_out_uop_lrs1_rtype, %2635 : i2
    %2679 = comb.mux %2674, %slots_10.io_out_uop_dst_rtype, %2636 : i2
    %2680 = comb.mux %2674, %slots_10.io_out_uop_ldst_val, %2637 : i1
    %2681 = comb.mux %2674, %slots_10.io_out_uop_uses_stq, %2638 : i1
    %2682 = comb.mux %2674, %slots_10.io_out_uop_uses_ldq, %2639 : i1
    %2683 = comb.mux %2674, %slots_10.io_out_uop_is_amo, %2640 : i1
    %2684 = comb.mux %2674, %slots_10.io_out_uop_is_fence, %2641 : i1
    %2685 = comb.mux %2674, %slots_10.io_out_uop_mem_signed, %2642 : i1
    %2686 = comb.mux %2674, %slots_10.io_out_uop_mem_size, %2643 : i2
    %2687 = comb.mux %2674, %slots_10.io_out_uop_mem_cmd, %2644 : i5
    %2688 = comb.mux %2674, %slots_10.io_out_uop_bypassable, %2645 : i1
    %2689 = comb.mux %2674, %slots_10.io_out_uop_ppred_busy, %2646 : i1
    %2690 = comb.mux %2674, %slots_10.io_out_uop_prs3_busy, %2647 : i1
    %2691 = comb.mux %2674, %slots_10.io_out_uop_prs2_busy, %2648 : i1
    %2692 = comb.mux %2674, %slots_10.io_out_uop_prs1_busy, %2649 : i1
    %2693 = comb.mux %2674, %slots_10.io_out_uop_prs3, %2650 : i7
    %2694 = comb.mux %2674, %slots_10.io_out_uop_prs2, %2651 : i7
    %2695 = comb.mux %2674, %slots_10.io_out_uop_prs1, %2652 : i7
    %2696 = comb.mux %2674, %slots_10.io_out_uop_pdst, %2653 : i7
    %2697 = comb.mux %2674, %slots_10.io_out_uop_stq_idx, %2654 : i5
    %2698 = comb.mux %2674, %slots_10.io_out_uop_ldq_idx, %2655 : i5
    %2699 = comb.mux %2674, %slots_10.io_out_uop_rob_idx, %2656 : i7
    %2700 = comb.mux %2674, %slots_10.io_out_uop_imm_packed, %2657 : i20
    %2701 = comb.mux %2674, %slots_10.io_out_uop_taken, %2658 : i1
    %2702 = comb.mux %2674, %slots_10.io_out_uop_pc_lob, %2659 : i6
    %2703 = comb.mux %2674, %slots_10.io_out_uop_edge_inst, %2660 : i1
    %2704 = comb.mux %2674, %slots_10.io_out_uop_ftq_idx, %2661 : i6
    %2705 = comb.mux %2674, %slots_10.io_out_uop_br_tag, %2662 : i5
    %2706 = comb.mux %2674, %slots_10.io_out_uop_br_mask, %2663 : i20
    %2707 = comb.mux %2674, %slots_10.io_out_uop_is_sfb, %2664 : i1
    %2708 = comb.mux %2674, %slots_10.io_out_uop_is_jal, %2665 : i1
    %2709 = comb.mux %2674, %slots_10.io_out_uop_is_jalr, %2666 : i1
    %2710 = comb.mux %2674, %slots_10.io_out_uop_is_br, %2667 : i1
    %2711 = comb.mux %2674, %slots_10.io_out_uop_iw_p2_poisoned, %2668 : i1
    %2712 = comb.mux %2674, %slots_10.io_out_uop_iw_p1_poisoned, %2669 : i1
    %2713 = comb.mux %2674, %slots_10.io_out_uop_iw_state, %2670 : i2
    %2714 = comb.mux %2674, %slots_10.io_out_uop_fu_code, %2671 : i10
    %2715 = comb.mux %2674, %slots_10.io_out_uop_is_rvc, %2672 : i1
    %2716 = comb.mux %2674, %slots_10.io_out_uop_uopc, %2673 : i7
    %2717 = comb.icmp eq %1719, %c-8_i4 : i4
    %issue_slots_11_will_be_valid = sv.wire sym @issue_slots_11_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_11_will_be_valid, %slots_11.io_will_be_valid : i1
    %2718 = comb.mux %2717, %slots_11.io_will_be_valid, %2675 {sv.namehint = "_issue_slots_7_in_uop_valid"} : i1
    %issue_slots_7_in_uop_valid = sv.wire sym @issue_slots_7_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_7_in_uop_valid, %2718 : i1
    %issue_slots_11_out_uop_fp_val = sv.wire sym @issue_slots_11_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_fp_val, %slots_11.io_out_uop_fp_val : i1
    %issue_slots_11_out_uop_lrs2_rtype = sv.wire sym @issue_slots_11_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_11_out_uop_lrs2_rtype, %slots_11.io_out_uop_lrs2_rtype : i2
    %issue_slots_11_out_uop_lrs1_rtype = sv.wire sym @issue_slots_11_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_11_out_uop_lrs1_rtype, %slots_11.io_out_uop_lrs1_rtype : i2
    %issue_slots_11_out_uop_dst_rtype = sv.wire sym @issue_slots_11_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_11_out_uop_dst_rtype, %slots_11.io_out_uop_dst_rtype : i2
    %issue_slots_11_out_uop_ldst_val = sv.wire sym @issue_slots_11_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_ldst_val, %slots_11.io_out_uop_ldst_val : i1
    %issue_slots_11_out_uop_uses_stq = sv.wire sym @issue_slots_11_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_uses_stq, %slots_11.io_out_uop_uses_stq : i1
    %issue_slots_11_out_uop_uses_ldq = sv.wire sym @issue_slots_11_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_uses_ldq, %slots_11.io_out_uop_uses_ldq : i1
    %issue_slots_11_out_uop_is_amo = sv.wire sym @issue_slots_11_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_is_amo, %slots_11.io_out_uop_is_amo : i1
    %issue_slots_11_out_uop_is_fence = sv.wire sym @issue_slots_11_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_is_fence, %slots_11.io_out_uop_is_fence : i1
    %issue_slots_11_out_uop_mem_signed = sv.wire sym @issue_slots_11_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_mem_signed, %slots_11.io_out_uop_mem_signed : i1
    %issue_slots_11_out_uop_mem_size = sv.wire sym @issue_slots_11_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_11_out_uop_mem_size, %slots_11.io_out_uop_mem_size : i2
    %issue_slots_11_out_uop_mem_cmd = sv.wire sym @issue_slots_11_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_11_out_uop_mem_cmd, %slots_11.io_out_uop_mem_cmd : i5
    %issue_slots_11_out_uop_bypassable = sv.wire sym @issue_slots_11_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_bypassable, %slots_11.io_out_uop_bypassable : i1
    %issue_slots_11_out_uop_ppred_busy = sv.wire sym @issue_slots_11_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_ppred_busy, %slots_11.io_out_uop_ppred_busy : i1
    %issue_slots_11_out_uop_prs3_busy = sv.wire sym @issue_slots_11_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_prs3_busy, %slots_11.io_out_uop_prs3_busy : i1
    %issue_slots_11_out_uop_prs2_busy = sv.wire sym @issue_slots_11_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_prs2_busy, %slots_11.io_out_uop_prs2_busy : i1
    %issue_slots_11_out_uop_prs1_busy = sv.wire sym @issue_slots_11_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_prs1_busy, %slots_11.io_out_uop_prs1_busy : i1
    %issue_slots_11_out_uop_prs3 = sv.wire sym @issue_slots_11_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_11_out_uop_prs3, %slots_11.io_out_uop_prs3 : i7
    %issue_slots_11_out_uop_prs2 = sv.wire sym @issue_slots_11_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_11_out_uop_prs2, %slots_11.io_out_uop_prs2 : i7
    %issue_slots_11_out_uop_prs1 = sv.wire sym @issue_slots_11_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_11_out_uop_prs1, %slots_11.io_out_uop_prs1 : i7
    %issue_slots_11_out_uop_pdst = sv.wire sym @issue_slots_11_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_11_out_uop_pdst, %slots_11.io_out_uop_pdst : i7
    %issue_slots_11_out_uop_stq_idx = sv.wire sym @issue_slots_11_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_11_out_uop_stq_idx, %slots_11.io_out_uop_stq_idx : i5
    %issue_slots_11_out_uop_ldq_idx = sv.wire sym @issue_slots_11_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_11_out_uop_ldq_idx, %slots_11.io_out_uop_ldq_idx : i5
    %issue_slots_11_out_uop_rob_idx = sv.wire sym @issue_slots_11_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_11_out_uop_rob_idx, %slots_11.io_out_uop_rob_idx : i7
    %issue_slots_11_out_uop_imm_packed = sv.wire sym @issue_slots_11_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_11_out_uop_imm_packed, %slots_11.io_out_uop_imm_packed : i20
    %issue_slots_11_out_uop_taken = sv.wire sym @issue_slots_11_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_taken, %slots_11.io_out_uop_taken : i1
    %issue_slots_11_out_uop_pc_lob = sv.wire sym @issue_slots_11_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_11_out_uop_pc_lob, %slots_11.io_out_uop_pc_lob : i6
    %issue_slots_11_out_uop_edge_inst = sv.wire sym @issue_slots_11_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_edge_inst, %slots_11.io_out_uop_edge_inst : i1
    %issue_slots_11_out_uop_ftq_idx = sv.wire sym @issue_slots_11_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_11_out_uop_ftq_idx, %slots_11.io_out_uop_ftq_idx : i6
    %issue_slots_11_out_uop_br_tag = sv.wire sym @issue_slots_11_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_11_out_uop_br_tag, %slots_11.io_out_uop_br_tag : i5
    %issue_slots_11_out_uop_br_mask = sv.wire sym @issue_slots_11_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_11_out_uop_br_mask, %slots_11.io_out_uop_br_mask : i20
    %issue_slots_11_out_uop_is_sfb = sv.wire sym @issue_slots_11_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_is_sfb, %slots_11.io_out_uop_is_sfb : i1
    %issue_slots_11_out_uop_is_jal = sv.wire sym @issue_slots_11_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_is_jal, %slots_11.io_out_uop_is_jal : i1
    %issue_slots_11_out_uop_is_jalr = sv.wire sym @issue_slots_11_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_is_jalr, %slots_11.io_out_uop_is_jalr : i1
    %issue_slots_11_out_uop_is_br = sv.wire sym @issue_slots_11_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_is_br, %slots_11.io_out_uop_is_br : i1
    %issue_slots_11_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_11_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_iw_p2_poisoned, %slots_11.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_11_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_11_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_iw_p1_poisoned, %slots_11.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_11_out_uop_iw_state = sv.wire sym @issue_slots_11_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_11_out_uop_iw_state, %slots_11.io_out_uop_iw_state : i2
    %issue_slots_11_out_uop_fu_code = sv.wire sym @issue_slots_11_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_11_out_uop_fu_code, %slots_11.io_out_uop_fu_code : i10
    %issue_slots_11_out_uop_is_rvc = sv.wire sym @issue_slots_11_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_11_out_uop_is_rvc, %slots_11.io_out_uop_is_rvc : i1
    %issue_slots_11_out_uop_uopc = sv.wire sym @issue_slots_11_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_11_out_uop_uopc, %slots_11.io_out_uop_uopc : i7
    %2719 = comb.icmp ne %1687, %c0_i4 {sv.namehint = "_issue_slots_7_clear"} : i4
    %issue_slots_7_clear = sv.wire sym @issue_slots_7_clear  : !hw.inout<i1>
    sv.assign %issue_slots_7_clear, %2719 : i1
    %2720 = comb.icmp eq %1703, %c1_i4 : i4
    %2721 = comb.and %2720, %slots_9.io_will_be_valid : i1
    %2722 = comb.icmp eq %1711, %c2_i4 : i4
    %2723 = comb.mux %2722, %slots_10.io_will_be_valid, %2721 : i1
    %2724 = comb.mux %2722, %slots_10.io_out_uop_fp_val, %slots_9.io_out_uop_fp_val : i1
    %2725 = comb.mux %2722, %slots_10.io_out_uop_lrs2_rtype, %slots_9.io_out_uop_lrs2_rtype : i2
    %2726 = comb.mux %2722, %slots_10.io_out_uop_lrs1_rtype, %slots_9.io_out_uop_lrs1_rtype : i2
    %2727 = comb.mux %2722, %slots_10.io_out_uop_dst_rtype, %slots_9.io_out_uop_dst_rtype : i2
    %2728 = comb.mux %2722, %slots_10.io_out_uop_ldst_val, %slots_9.io_out_uop_ldst_val : i1
    %2729 = comb.mux %2722, %slots_10.io_out_uop_uses_stq, %slots_9.io_out_uop_uses_stq : i1
    %2730 = comb.mux %2722, %slots_10.io_out_uop_uses_ldq, %slots_9.io_out_uop_uses_ldq : i1
    %2731 = comb.mux %2722, %slots_10.io_out_uop_is_amo, %slots_9.io_out_uop_is_amo : i1
    %2732 = comb.mux %2722, %slots_10.io_out_uop_is_fence, %slots_9.io_out_uop_is_fence : i1
    %2733 = comb.mux %2722, %slots_10.io_out_uop_mem_signed, %slots_9.io_out_uop_mem_signed : i1
    %2734 = comb.mux %2722, %slots_10.io_out_uop_mem_size, %slots_9.io_out_uop_mem_size : i2
    %2735 = comb.mux %2722, %slots_10.io_out_uop_mem_cmd, %slots_9.io_out_uop_mem_cmd : i5
    %2736 = comb.mux %2722, %slots_10.io_out_uop_bypassable, %slots_9.io_out_uop_bypassable : i1
    %2737 = comb.mux %2722, %slots_10.io_out_uop_ppred_busy, %slots_9.io_out_uop_ppred_busy : i1
    %2738 = comb.mux %2722, %slots_10.io_out_uop_prs3_busy, %slots_9.io_out_uop_prs3_busy : i1
    %2739 = comb.mux %2722, %slots_10.io_out_uop_prs2_busy, %slots_9.io_out_uop_prs2_busy : i1
    %2740 = comb.mux %2722, %slots_10.io_out_uop_prs1_busy, %slots_9.io_out_uop_prs1_busy : i1
    %2741 = comb.mux %2722, %slots_10.io_out_uop_prs3, %slots_9.io_out_uop_prs3 : i7
    %2742 = comb.mux %2722, %slots_10.io_out_uop_prs2, %slots_9.io_out_uop_prs2 : i7
    %2743 = comb.mux %2722, %slots_10.io_out_uop_prs1, %slots_9.io_out_uop_prs1 : i7
    %2744 = comb.mux %2722, %slots_10.io_out_uop_pdst, %slots_9.io_out_uop_pdst : i7
    %2745 = comb.mux %2722, %slots_10.io_out_uop_stq_idx, %slots_9.io_out_uop_stq_idx : i5
    %2746 = comb.mux %2722, %slots_10.io_out_uop_ldq_idx, %slots_9.io_out_uop_ldq_idx : i5
    %2747 = comb.mux %2722, %slots_10.io_out_uop_rob_idx, %slots_9.io_out_uop_rob_idx : i7
    %2748 = comb.mux %2722, %slots_10.io_out_uop_imm_packed, %slots_9.io_out_uop_imm_packed : i20
    %2749 = comb.mux %2722, %slots_10.io_out_uop_taken, %slots_9.io_out_uop_taken : i1
    %2750 = comb.mux %2722, %slots_10.io_out_uop_pc_lob, %slots_9.io_out_uop_pc_lob : i6
    %2751 = comb.mux %2722, %slots_10.io_out_uop_edge_inst, %slots_9.io_out_uop_edge_inst : i1
    %2752 = comb.mux %2722, %slots_10.io_out_uop_ftq_idx, %slots_9.io_out_uop_ftq_idx : i6
    %2753 = comb.mux %2722, %slots_10.io_out_uop_br_tag, %slots_9.io_out_uop_br_tag : i5
    %2754 = comb.mux %2722, %slots_10.io_out_uop_br_mask, %slots_9.io_out_uop_br_mask : i20
    %2755 = comb.mux %2722, %slots_10.io_out_uop_is_sfb, %slots_9.io_out_uop_is_sfb : i1
    %2756 = comb.mux %2722, %slots_10.io_out_uop_is_jal, %slots_9.io_out_uop_is_jal : i1
    %2757 = comb.mux %2722, %slots_10.io_out_uop_is_jalr, %slots_9.io_out_uop_is_jalr : i1
    %2758 = comb.mux %2722, %slots_10.io_out_uop_is_br, %slots_9.io_out_uop_is_br : i1
    %2759 = comb.mux %2722, %slots_10.io_out_uop_iw_p2_poisoned, %slots_9.io_out_uop_iw_p2_poisoned : i1
    %2760 = comb.mux %2722, %slots_10.io_out_uop_iw_p1_poisoned, %slots_9.io_out_uop_iw_p1_poisoned : i1
    %2761 = comb.mux %2722, %slots_10.io_out_uop_iw_state, %slots_9.io_out_uop_iw_state : i2
    %2762 = comb.mux %2722, %slots_10.io_out_uop_fu_code, %slots_9.io_out_uop_fu_code : i10
    %2763 = comb.mux %2722, %slots_10.io_out_uop_is_rvc, %slots_9.io_out_uop_is_rvc : i1
    %2764 = comb.mux %2722, %slots_10.io_out_uop_uopc, %slots_9.io_out_uop_uopc : i7
    %2765 = comb.icmp eq %1719, %c4_i4 : i4
    %2766 = comb.mux %2765, %slots_11.io_will_be_valid, %2723 : i1
    %2767 = comb.mux %2765, %slots_11.io_out_uop_fp_val, %2724 : i1
    %2768 = comb.mux %2765, %slots_11.io_out_uop_lrs2_rtype, %2725 : i2
    %2769 = comb.mux %2765, %slots_11.io_out_uop_lrs1_rtype, %2726 : i2
    %2770 = comb.mux %2765, %slots_11.io_out_uop_dst_rtype, %2727 : i2
    %2771 = comb.mux %2765, %slots_11.io_out_uop_ldst_val, %2728 : i1
    %2772 = comb.mux %2765, %slots_11.io_out_uop_uses_stq, %2729 : i1
    %2773 = comb.mux %2765, %slots_11.io_out_uop_uses_ldq, %2730 : i1
    %2774 = comb.mux %2765, %slots_11.io_out_uop_is_amo, %2731 : i1
    %2775 = comb.mux %2765, %slots_11.io_out_uop_is_fence, %2732 : i1
    %2776 = comb.mux %2765, %slots_11.io_out_uop_mem_signed, %2733 : i1
    %2777 = comb.mux %2765, %slots_11.io_out_uop_mem_size, %2734 : i2
    %2778 = comb.mux %2765, %slots_11.io_out_uop_mem_cmd, %2735 : i5
    %2779 = comb.mux %2765, %slots_11.io_out_uop_bypassable, %2736 : i1
    %2780 = comb.mux %2765, %slots_11.io_out_uop_ppred_busy, %2737 : i1
    %2781 = comb.mux %2765, %slots_11.io_out_uop_prs3_busy, %2738 : i1
    %2782 = comb.mux %2765, %slots_11.io_out_uop_prs2_busy, %2739 : i1
    %2783 = comb.mux %2765, %slots_11.io_out_uop_prs1_busy, %2740 : i1
    %2784 = comb.mux %2765, %slots_11.io_out_uop_prs3, %2741 : i7
    %2785 = comb.mux %2765, %slots_11.io_out_uop_prs2, %2742 : i7
    %2786 = comb.mux %2765, %slots_11.io_out_uop_prs1, %2743 : i7
    %2787 = comb.mux %2765, %slots_11.io_out_uop_pdst, %2744 : i7
    %2788 = comb.mux %2765, %slots_11.io_out_uop_stq_idx, %2745 : i5
    %2789 = comb.mux %2765, %slots_11.io_out_uop_ldq_idx, %2746 : i5
    %2790 = comb.mux %2765, %slots_11.io_out_uop_rob_idx, %2747 : i7
    %2791 = comb.mux %2765, %slots_11.io_out_uop_imm_packed, %2748 : i20
    %2792 = comb.mux %2765, %slots_11.io_out_uop_taken, %2749 : i1
    %2793 = comb.mux %2765, %slots_11.io_out_uop_pc_lob, %2750 : i6
    %2794 = comb.mux %2765, %slots_11.io_out_uop_edge_inst, %2751 : i1
    %2795 = comb.mux %2765, %slots_11.io_out_uop_ftq_idx, %2752 : i6
    %2796 = comb.mux %2765, %slots_11.io_out_uop_br_tag, %2753 : i5
    %2797 = comb.mux %2765, %slots_11.io_out_uop_br_mask, %2754 : i20
    %2798 = comb.mux %2765, %slots_11.io_out_uop_is_sfb, %2755 : i1
    %2799 = comb.mux %2765, %slots_11.io_out_uop_is_jal, %2756 : i1
    %2800 = comb.mux %2765, %slots_11.io_out_uop_is_jalr, %2757 : i1
    %2801 = comb.mux %2765, %slots_11.io_out_uop_is_br, %2758 : i1
    %2802 = comb.mux %2765, %slots_11.io_out_uop_iw_p2_poisoned, %2759 : i1
    %2803 = comb.mux %2765, %slots_11.io_out_uop_iw_p1_poisoned, %2760 : i1
    %2804 = comb.mux %2765, %slots_11.io_out_uop_iw_state, %2761 : i2
    %2805 = comb.mux %2765, %slots_11.io_out_uop_fu_code, %2762 : i10
    %2806 = comb.mux %2765, %slots_11.io_out_uop_is_rvc, %2763 : i1
    %2807 = comb.mux %2765, %slots_11.io_out_uop_uopc, %2764 : i7
    %2808 = comb.icmp eq %1727, %c-8_i4 : i4
    %issue_slots_12_will_be_valid = sv.wire sym @issue_slots_12_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_12_will_be_valid, %slots_12.io_will_be_valid : i1
    %2809 = comb.mux %2808, %slots_12.io_will_be_valid, %2766 {sv.namehint = "_issue_slots_8_in_uop_valid"} : i1
    %issue_slots_8_in_uop_valid = sv.wire sym @issue_slots_8_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_8_in_uop_valid, %2809 : i1
    %issue_slots_12_out_uop_fp_val = sv.wire sym @issue_slots_12_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_fp_val, %slots_12.io_out_uop_fp_val : i1
    %issue_slots_12_out_uop_lrs2_rtype = sv.wire sym @issue_slots_12_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_12_out_uop_lrs2_rtype, %slots_12.io_out_uop_lrs2_rtype : i2
    %issue_slots_12_out_uop_lrs1_rtype = sv.wire sym @issue_slots_12_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_12_out_uop_lrs1_rtype, %slots_12.io_out_uop_lrs1_rtype : i2
    %issue_slots_12_out_uop_dst_rtype = sv.wire sym @issue_slots_12_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_12_out_uop_dst_rtype, %slots_12.io_out_uop_dst_rtype : i2
    %issue_slots_12_out_uop_ldst_val = sv.wire sym @issue_slots_12_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_ldst_val, %slots_12.io_out_uop_ldst_val : i1
    %issue_slots_12_out_uop_uses_stq = sv.wire sym @issue_slots_12_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_uses_stq, %slots_12.io_out_uop_uses_stq : i1
    %issue_slots_12_out_uop_uses_ldq = sv.wire sym @issue_slots_12_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_uses_ldq, %slots_12.io_out_uop_uses_ldq : i1
    %issue_slots_12_out_uop_is_amo = sv.wire sym @issue_slots_12_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_is_amo, %slots_12.io_out_uop_is_amo : i1
    %issue_slots_12_out_uop_is_fence = sv.wire sym @issue_slots_12_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_is_fence, %slots_12.io_out_uop_is_fence : i1
    %issue_slots_12_out_uop_mem_signed = sv.wire sym @issue_slots_12_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_mem_signed, %slots_12.io_out_uop_mem_signed : i1
    %issue_slots_12_out_uop_mem_size = sv.wire sym @issue_slots_12_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_12_out_uop_mem_size, %slots_12.io_out_uop_mem_size : i2
    %issue_slots_12_out_uop_mem_cmd = sv.wire sym @issue_slots_12_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_12_out_uop_mem_cmd, %slots_12.io_out_uop_mem_cmd : i5
    %issue_slots_12_out_uop_bypassable = sv.wire sym @issue_slots_12_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_bypassable, %slots_12.io_out_uop_bypassable : i1
    %issue_slots_12_out_uop_ppred_busy = sv.wire sym @issue_slots_12_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_ppred_busy, %slots_12.io_out_uop_ppred_busy : i1
    %issue_slots_12_out_uop_prs3_busy = sv.wire sym @issue_slots_12_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_prs3_busy, %slots_12.io_out_uop_prs3_busy : i1
    %issue_slots_12_out_uop_prs2_busy = sv.wire sym @issue_slots_12_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_prs2_busy, %slots_12.io_out_uop_prs2_busy : i1
    %issue_slots_12_out_uop_prs1_busy = sv.wire sym @issue_slots_12_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_prs1_busy, %slots_12.io_out_uop_prs1_busy : i1
    %issue_slots_12_out_uop_prs3 = sv.wire sym @issue_slots_12_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_12_out_uop_prs3, %slots_12.io_out_uop_prs3 : i7
    %issue_slots_12_out_uop_prs2 = sv.wire sym @issue_slots_12_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_12_out_uop_prs2, %slots_12.io_out_uop_prs2 : i7
    %issue_slots_12_out_uop_prs1 = sv.wire sym @issue_slots_12_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_12_out_uop_prs1, %slots_12.io_out_uop_prs1 : i7
    %issue_slots_12_out_uop_pdst = sv.wire sym @issue_slots_12_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_12_out_uop_pdst, %slots_12.io_out_uop_pdst : i7
    %issue_slots_12_out_uop_stq_idx = sv.wire sym @issue_slots_12_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_12_out_uop_stq_idx, %slots_12.io_out_uop_stq_idx : i5
    %issue_slots_12_out_uop_ldq_idx = sv.wire sym @issue_slots_12_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_12_out_uop_ldq_idx, %slots_12.io_out_uop_ldq_idx : i5
    %issue_slots_12_out_uop_rob_idx = sv.wire sym @issue_slots_12_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_12_out_uop_rob_idx, %slots_12.io_out_uop_rob_idx : i7
    %issue_slots_12_out_uop_imm_packed = sv.wire sym @issue_slots_12_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_12_out_uop_imm_packed, %slots_12.io_out_uop_imm_packed : i20
    %issue_slots_12_out_uop_taken = sv.wire sym @issue_slots_12_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_taken, %slots_12.io_out_uop_taken : i1
    %issue_slots_12_out_uop_pc_lob = sv.wire sym @issue_slots_12_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_12_out_uop_pc_lob, %slots_12.io_out_uop_pc_lob : i6
    %issue_slots_12_out_uop_edge_inst = sv.wire sym @issue_slots_12_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_edge_inst, %slots_12.io_out_uop_edge_inst : i1
    %issue_slots_12_out_uop_ftq_idx = sv.wire sym @issue_slots_12_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_12_out_uop_ftq_idx, %slots_12.io_out_uop_ftq_idx : i6
    %issue_slots_12_out_uop_br_tag = sv.wire sym @issue_slots_12_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_12_out_uop_br_tag, %slots_12.io_out_uop_br_tag : i5
    %issue_slots_12_out_uop_br_mask = sv.wire sym @issue_slots_12_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_12_out_uop_br_mask, %slots_12.io_out_uop_br_mask : i20
    %issue_slots_12_out_uop_is_sfb = sv.wire sym @issue_slots_12_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_is_sfb, %slots_12.io_out_uop_is_sfb : i1
    %issue_slots_12_out_uop_is_jal = sv.wire sym @issue_slots_12_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_is_jal, %slots_12.io_out_uop_is_jal : i1
    %issue_slots_12_out_uop_is_jalr = sv.wire sym @issue_slots_12_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_is_jalr, %slots_12.io_out_uop_is_jalr : i1
    %issue_slots_12_out_uop_is_br = sv.wire sym @issue_slots_12_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_is_br, %slots_12.io_out_uop_is_br : i1
    %issue_slots_12_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_12_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_iw_p2_poisoned, %slots_12.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_12_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_12_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_iw_p1_poisoned, %slots_12.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_12_out_uop_iw_state = sv.wire sym @issue_slots_12_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_12_out_uop_iw_state, %slots_12.io_out_uop_iw_state : i2
    %issue_slots_12_out_uop_fu_code = sv.wire sym @issue_slots_12_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_12_out_uop_fu_code, %slots_12.io_out_uop_fu_code : i10
    %issue_slots_12_out_uop_is_rvc = sv.wire sym @issue_slots_12_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_12_out_uop_is_rvc, %slots_12.io_out_uop_is_rvc : i1
    %issue_slots_12_out_uop_uopc = sv.wire sym @issue_slots_12_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_12_out_uop_uopc, %slots_12.io_out_uop_uopc : i7
    %2810 = comb.icmp ne %1695, %c0_i4 {sv.namehint = "_issue_slots_8_clear"} : i4
    %issue_slots_8_clear = sv.wire sym @issue_slots_8_clear  : !hw.inout<i1>
    sv.assign %issue_slots_8_clear, %2810 : i1
    %2811 = comb.icmp eq %1711, %c1_i4 : i4
    %2812 = comb.and %2811, %slots_10.io_will_be_valid : i1
    %2813 = comb.icmp eq %1719, %c2_i4 : i4
    %2814 = comb.mux %2813, %slots_11.io_will_be_valid, %2812 : i1
    %2815 = comb.mux %2813, %slots_11.io_out_uop_fp_val, %slots_10.io_out_uop_fp_val : i1
    %2816 = comb.mux %2813, %slots_11.io_out_uop_lrs2_rtype, %slots_10.io_out_uop_lrs2_rtype : i2
    %2817 = comb.mux %2813, %slots_11.io_out_uop_lrs1_rtype, %slots_10.io_out_uop_lrs1_rtype : i2
    %2818 = comb.mux %2813, %slots_11.io_out_uop_dst_rtype, %slots_10.io_out_uop_dst_rtype : i2
    %2819 = comb.mux %2813, %slots_11.io_out_uop_ldst_val, %slots_10.io_out_uop_ldst_val : i1
    %2820 = comb.mux %2813, %slots_11.io_out_uop_uses_stq, %slots_10.io_out_uop_uses_stq : i1
    %2821 = comb.mux %2813, %slots_11.io_out_uop_uses_ldq, %slots_10.io_out_uop_uses_ldq : i1
    %2822 = comb.mux %2813, %slots_11.io_out_uop_is_amo, %slots_10.io_out_uop_is_amo : i1
    %2823 = comb.mux %2813, %slots_11.io_out_uop_is_fence, %slots_10.io_out_uop_is_fence : i1
    %2824 = comb.mux %2813, %slots_11.io_out_uop_mem_signed, %slots_10.io_out_uop_mem_signed : i1
    %2825 = comb.mux %2813, %slots_11.io_out_uop_mem_size, %slots_10.io_out_uop_mem_size : i2
    %2826 = comb.mux %2813, %slots_11.io_out_uop_mem_cmd, %slots_10.io_out_uop_mem_cmd : i5
    %2827 = comb.mux %2813, %slots_11.io_out_uop_bypassable, %slots_10.io_out_uop_bypassable : i1
    %2828 = comb.mux %2813, %slots_11.io_out_uop_ppred_busy, %slots_10.io_out_uop_ppred_busy : i1
    %2829 = comb.mux %2813, %slots_11.io_out_uop_prs3_busy, %slots_10.io_out_uop_prs3_busy : i1
    %2830 = comb.mux %2813, %slots_11.io_out_uop_prs2_busy, %slots_10.io_out_uop_prs2_busy : i1
    %2831 = comb.mux %2813, %slots_11.io_out_uop_prs1_busy, %slots_10.io_out_uop_prs1_busy : i1
    %2832 = comb.mux %2813, %slots_11.io_out_uop_prs3, %slots_10.io_out_uop_prs3 : i7
    %2833 = comb.mux %2813, %slots_11.io_out_uop_prs2, %slots_10.io_out_uop_prs2 : i7
    %2834 = comb.mux %2813, %slots_11.io_out_uop_prs1, %slots_10.io_out_uop_prs1 : i7
    %2835 = comb.mux %2813, %slots_11.io_out_uop_pdst, %slots_10.io_out_uop_pdst : i7
    %2836 = comb.mux %2813, %slots_11.io_out_uop_stq_idx, %slots_10.io_out_uop_stq_idx : i5
    %2837 = comb.mux %2813, %slots_11.io_out_uop_ldq_idx, %slots_10.io_out_uop_ldq_idx : i5
    %2838 = comb.mux %2813, %slots_11.io_out_uop_rob_idx, %slots_10.io_out_uop_rob_idx : i7
    %2839 = comb.mux %2813, %slots_11.io_out_uop_imm_packed, %slots_10.io_out_uop_imm_packed : i20
    %2840 = comb.mux %2813, %slots_11.io_out_uop_taken, %slots_10.io_out_uop_taken : i1
    %2841 = comb.mux %2813, %slots_11.io_out_uop_pc_lob, %slots_10.io_out_uop_pc_lob : i6
    %2842 = comb.mux %2813, %slots_11.io_out_uop_edge_inst, %slots_10.io_out_uop_edge_inst : i1
    %2843 = comb.mux %2813, %slots_11.io_out_uop_ftq_idx, %slots_10.io_out_uop_ftq_idx : i6
    %2844 = comb.mux %2813, %slots_11.io_out_uop_br_tag, %slots_10.io_out_uop_br_tag : i5
    %2845 = comb.mux %2813, %slots_11.io_out_uop_br_mask, %slots_10.io_out_uop_br_mask : i20
    %2846 = comb.mux %2813, %slots_11.io_out_uop_is_sfb, %slots_10.io_out_uop_is_sfb : i1
    %2847 = comb.mux %2813, %slots_11.io_out_uop_is_jal, %slots_10.io_out_uop_is_jal : i1
    %2848 = comb.mux %2813, %slots_11.io_out_uop_is_jalr, %slots_10.io_out_uop_is_jalr : i1
    %2849 = comb.mux %2813, %slots_11.io_out_uop_is_br, %slots_10.io_out_uop_is_br : i1
    %2850 = comb.mux %2813, %slots_11.io_out_uop_iw_p2_poisoned, %slots_10.io_out_uop_iw_p2_poisoned : i1
    %2851 = comb.mux %2813, %slots_11.io_out_uop_iw_p1_poisoned, %slots_10.io_out_uop_iw_p1_poisoned : i1
    %2852 = comb.mux %2813, %slots_11.io_out_uop_iw_state, %slots_10.io_out_uop_iw_state : i2
    %2853 = comb.mux %2813, %slots_11.io_out_uop_fu_code, %slots_10.io_out_uop_fu_code : i10
    %2854 = comb.mux %2813, %slots_11.io_out_uop_is_rvc, %slots_10.io_out_uop_is_rvc : i1
    %2855 = comb.mux %2813, %slots_11.io_out_uop_uopc, %slots_10.io_out_uop_uopc : i7
    %2856 = comb.icmp eq %1727, %c4_i4 : i4
    %2857 = comb.mux %2856, %slots_12.io_will_be_valid, %2814 : i1
    %2858 = comb.mux %2856, %slots_12.io_out_uop_fp_val, %2815 : i1
    %2859 = comb.mux %2856, %slots_12.io_out_uop_lrs2_rtype, %2816 : i2
    %2860 = comb.mux %2856, %slots_12.io_out_uop_lrs1_rtype, %2817 : i2
    %2861 = comb.mux %2856, %slots_12.io_out_uop_dst_rtype, %2818 : i2
    %2862 = comb.mux %2856, %slots_12.io_out_uop_ldst_val, %2819 : i1
    %2863 = comb.mux %2856, %slots_12.io_out_uop_uses_stq, %2820 : i1
    %2864 = comb.mux %2856, %slots_12.io_out_uop_uses_ldq, %2821 : i1
    %2865 = comb.mux %2856, %slots_12.io_out_uop_is_amo, %2822 : i1
    %2866 = comb.mux %2856, %slots_12.io_out_uop_is_fence, %2823 : i1
    %2867 = comb.mux %2856, %slots_12.io_out_uop_mem_signed, %2824 : i1
    %2868 = comb.mux %2856, %slots_12.io_out_uop_mem_size, %2825 : i2
    %2869 = comb.mux %2856, %slots_12.io_out_uop_mem_cmd, %2826 : i5
    %2870 = comb.mux %2856, %slots_12.io_out_uop_bypassable, %2827 : i1
    %2871 = comb.mux %2856, %slots_12.io_out_uop_ppred_busy, %2828 : i1
    %2872 = comb.mux %2856, %slots_12.io_out_uop_prs3_busy, %2829 : i1
    %2873 = comb.mux %2856, %slots_12.io_out_uop_prs2_busy, %2830 : i1
    %2874 = comb.mux %2856, %slots_12.io_out_uop_prs1_busy, %2831 : i1
    %2875 = comb.mux %2856, %slots_12.io_out_uop_prs3, %2832 : i7
    %2876 = comb.mux %2856, %slots_12.io_out_uop_prs2, %2833 : i7
    %2877 = comb.mux %2856, %slots_12.io_out_uop_prs1, %2834 : i7
    %2878 = comb.mux %2856, %slots_12.io_out_uop_pdst, %2835 : i7
    %2879 = comb.mux %2856, %slots_12.io_out_uop_stq_idx, %2836 : i5
    %2880 = comb.mux %2856, %slots_12.io_out_uop_ldq_idx, %2837 : i5
    %2881 = comb.mux %2856, %slots_12.io_out_uop_rob_idx, %2838 : i7
    %2882 = comb.mux %2856, %slots_12.io_out_uop_imm_packed, %2839 : i20
    %2883 = comb.mux %2856, %slots_12.io_out_uop_taken, %2840 : i1
    %2884 = comb.mux %2856, %slots_12.io_out_uop_pc_lob, %2841 : i6
    %2885 = comb.mux %2856, %slots_12.io_out_uop_edge_inst, %2842 : i1
    %2886 = comb.mux %2856, %slots_12.io_out_uop_ftq_idx, %2843 : i6
    %2887 = comb.mux %2856, %slots_12.io_out_uop_br_tag, %2844 : i5
    %2888 = comb.mux %2856, %slots_12.io_out_uop_br_mask, %2845 : i20
    %2889 = comb.mux %2856, %slots_12.io_out_uop_is_sfb, %2846 : i1
    %2890 = comb.mux %2856, %slots_12.io_out_uop_is_jal, %2847 : i1
    %2891 = comb.mux %2856, %slots_12.io_out_uop_is_jalr, %2848 : i1
    %2892 = comb.mux %2856, %slots_12.io_out_uop_is_br, %2849 : i1
    %2893 = comb.mux %2856, %slots_12.io_out_uop_iw_p2_poisoned, %2850 : i1
    %2894 = comb.mux %2856, %slots_12.io_out_uop_iw_p1_poisoned, %2851 : i1
    %2895 = comb.mux %2856, %slots_12.io_out_uop_iw_state, %2852 : i2
    %2896 = comb.mux %2856, %slots_12.io_out_uop_fu_code, %2853 : i10
    %2897 = comb.mux %2856, %slots_12.io_out_uop_is_rvc, %2854 : i1
    %2898 = comb.mux %2856, %slots_12.io_out_uop_uopc, %2855 : i7
    %2899 = comb.icmp eq %1735, %c-8_i4 : i4
    %issue_slots_13_will_be_valid = sv.wire sym @issue_slots_13_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_13_will_be_valid, %slots_13.io_will_be_valid : i1
    %2900 = comb.mux %2899, %slots_13.io_will_be_valid, %2857 {sv.namehint = "_issue_slots_9_in_uop_valid"} : i1
    %issue_slots_9_in_uop_valid = sv.wire sym @issue_slots_9_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_9_in_uop_valid, %2900 : i1
    %issue_slots_13_out_uop_fp_val = sv.wire sym @issue_slots_13_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_fp_val, %slots_13.io_out_uop_fp_val : i1
    %issue_slots_13_out_uop_lrs2_rtype = sv.wire sym @issue_slots_13_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_13_out_uop_lrs2_rtype, %slots_13.io_out_uop_lrs2_rtype : i2
    %issue_slots_13_out_uop_lrs1_rtype = sv.wire sym @issue_slots_13_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_13_out_uop_lrs1_rtype, %slots_13.io_out_uop_lrs1_rtype : i2
    %issue_slots_13_out_uop_dst_rtype = sv.wire sym @issue_slots_13_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_13_out_uop_dst_rtype, %slots_13.io_out_uop_dst_rtype : i2
    %issue_slots_13_out_uop_ldst_val = sv.wire sym @issue_slots_13_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_ldst_val, %slots_13.io_out_uop_ldst_val : i1
    %issue_slots_13_out_uop_uses_stq = sv.wire sym @issue_slots_13_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_uses_stq, %slots_13.io_out_uop_uses_stq : i1
    %issue_slots_13_out_uop_uses_ldq = sv.wire sym @issue_slots_13_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_uses_ldq, %slots_13.io_out_uop_uses_ldq : i1
    %issue_slots_13_out_uop_is_amo = sv.wire sym @issue_slots_13_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_is_amo, %slots_13.io_out_uop_is_amo : i1
    %issue_slots_13_out_uop_is_fence = sv.wire sym @issue_slots_13_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_is_fence, %slots_13.io_out_uop_is_fence : i1
    %issue_slots_13_out_uop_mem_signed = sv.wire sym @issue_slots_13_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_mem_signed, %slots_13.io_out_uop_mem_signed : i1
    %issue_slots_13_out_uop_mem_size = sv.wire sym @issue_slots_13_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_13_out_uop_mem_size, %slots_13.io_out_uop_mem_size : i2
    %issue_slots_13_out_uop_mem_cmd = sv.wire sym @issue_slots_13_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_13_out_uop_mem_cmd, %slots_13.io_out_uop_mem_cmd : i5
    %issue_slots_13_out_uop_bypassable = sv.wire sym @issue_slots_13_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_bypassable, %slots_13.io_out_uop_bypassable : i1
    %issue_slots_13_out_uop_ppred_busy = sv.wire sym @issue_slots_13_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_ppred_busy, %slots_13.io_out_uop_ppred_busy : i1
    %issue_slots_13_out_uop_prs3_busy = sv.wire sym @issue_slots_13_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_prs3_busy, %slots_13.io_out_uop_prs3_busy : i1
    %issue_slots_13_out_uop_prs2_busy = sv.wire sym @issue_slots_13_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_prs2_busy, %slots_13.io_out_uop_prs2_busy : i1
    %issue_slots_13_out_uop_prs1_busy = sv.wire sym @issue_slots_13_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_prs1_busy, %slots_13.io_out_uop_prs1_busy : i1
    %issue_slots_13_out_uop_prs3 = sv.wire sym @issue_slots_13_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_13_out_uop_prs3, %slots_13.io_out_uop_prs3 : i7
    %issue_slots_13_out_uop_prs2 = sv.wire sym @issue_slots_13_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_13_out_uop_prs2, %slots_13.io_out_uop_prs2 : i7
    %issue_slots_13_out_uop_prs1 = sv.wire sym @issue_slots_13_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_13_out_uop_prs1, %slots_13.io_out_uop_prs1 : i7
    %issue_slots_13_out_uop_pdst = sv.wire sym @issue_slots_13_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_13_out_uop_pdst, %slots_13.io_out_uop_pdst : i7
    %issue_slots_13_out_uop_stq_idx = sv.wire sym @issue_slots_13_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_13_out_uop_stq_idx, %slots_13.io_out_uop_stq_idx : i5
    %issue_slots_13_out_uop_ldq_idx = sv.wire sym @issue_slots_13_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_13_out_uop_ldq_idx, %slots_13.io_out_uop_ldq_idx : i5
    %issue_slots_13_out_uop_rob_idx = sv.wire sym @issue_slots_13_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_13_out_uop_rob_idx, %slots_13.io_out_uop_rob_idx : i7
    %issue_slots_13_out_uop_imm_packed = sv.wire sym @issue_slots_13_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_13_out_uop_imm_packed, %slots_13.io_out_uop_imm_packed : i20
    %issue_slots_13_out_uop_taken = sv.wire sym @issue_slots_13_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_taken, %slots_13.io_out_uop_taken : i1
    %issue_slots_13_out_uop_pc_lob = sv.wire sym @issue_slots_13_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_13_out_uop_pc_lob, %slots_13.io_out_uop_pc_lob : i6
    %issue_slots_13_out_uop_edge_inst = sv.wire sym @issue_slots_13_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_edge_inst, %slots_13.io_out_uop_edge_inst : i1
    %issue_slots_13_out_uop_ftq_idx = sv.wire sym @issue_slots_13_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_13_out_uop_ftq_idx, %slots_13.io_out_uop_ftq_idx : i6
    %issue_slots_13_out_uop_br_tag = sv.wire sym @issue_slots_13_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_13_out_uop_br_tag, %slots_13.io_out_uop_br_tag : i5
    %issue_slots_13_out_uop_br_mask = sv.wire sym @issue_slots_13_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_13_out_uop_br_mask, %slots_13.io_out_uop_br_mask : i20
    %issue_slots_13_out_uop_is_sfb = sv.wire sym @issue_slots_13_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_is_sfb, %slots_13.io_out_uop_is_sfb : i1
    %issue_slots_13_out_uop_is_jal = sv.wire sym @issue_slots_13_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_is_jal, %slots_13.io_out_uop_is_jal : i1
    %issue_slots_13_out_uop_is_jalr = sv.wire sym @issue_slots_13_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_is_jalr, %slots_13.io_out_uop_is_jalr : i1
    %issue_slots_13_out_uop_is_br = sv.wire sym @issue_slots_13_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_is_br, %slots_13.io_out_uop_is_br : i1
    %issue_slots_13_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_13_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_iw_p2_poisoned, %slots_13.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_13_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_13_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_iw_p1_poisoned, %slots_13.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_13_out_uop_iw_state = sv.wire sym @issue_slots_13_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_13_out_uop_iw_state, %slots_13.io_out_uop_iw_state : i2
    %issue_slots_13_out_uop_fu_code = sv.wire sym @issue_slots_13_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_13_out_uop_fu_code, %slots_13.io_out_uop_fu_code : i10
    %issue_slots_13_out_uop_is_rvc = sv.wire sym @issue_slots_13_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_13_out_uop_is_rvc, %slots_13.io_out_uop_is_rvc : i1
    %issue_slots_13_out_uop_uopc = sv.wire sym @issue_slots_13_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_13_out_uop_uopc, %slots_13.io_out_uop_uopc : i7
    %2901 = comb.icmp ne %1703, %c0_i4 {sv.namehint = "_issue_slots_9_clear"} : i4
    %issue_slots_9_clear = sv.wire sym @issue_slots_9_clear  : !hw.inout<i1>
    sv.assign %issue_slots_9_clear, %2901 : i1
    %2902 = comb.icmp eq %1719, %c1_i4 : i4
    %2903 = comb.and %2902, %slots_11.io_will_be_valid : i1
    %2904 = comb.icmp eq %1727, %c2_i4 : i4
    %2905 = comb.mux %2904, %slots_12.io_will_be_valid, %2903 : i1
    %2906 = comb.mux %2904, %slots_12.io_out_uop_fp_val, %slots_11.io_out_uop_fp_val : i1
    %2907 = comb.mux %2904, %slots_12.io_out_uop_lrs2_rtype, %slots_11.io_out_uop_lrs2_rtype : i2
    %2908 = comb.mux %2904, %slots_12.io_out_uop_lrs1_rtype, %slots_11.io_out_uop_lrs1_rtype : i2
    %2909 = comb.mux %2904, %slots_12.io_out_uop_dst_rtype, %slots_11.io_out_uop_dst_rtype : i2
    %2910 = comb.mux %2904, %slots_12.io_out_uop_ldst_val, %slots_11.io_out_uop_ldst_val : i1
    %2911 = comb.mux %2904, %slots_12.io_out_uop_uses_stq, %slots_11.io_out_uop_uses_stq : i1
    %2912 = comb.mux %2904, %slots_12.io_out_uop_uses_ldq, %slots_11.io_out_uop_uses_ldq : i1
    %2913 = comb.mux %2904, %slots_12.io_out_uop_is_amo, %slots_11.io_out_uop_is_amo : i1
    %2914 = comb.mux %2904, %slots_12.io_out_uop_is_fence, %slots_11.io_out_uop_is_fence : i1
    %2915 = comb.mux %2904, %slots_12.io_out_uop_mem_signed, %slots_11.io_out_uop_mem_signed : i1
    %2916 = comb.mux %2904, %slots_12.io_out_uop_mem_size, %slots_11.io_out_uop_mem_size : i2
    %2917 = comb.mux %2904, %slots_12.io_out_uop_mem_cmd, %slots_11.io_out_uop_mem_cmd : i5
    %2918 = comb.mux %2904, %slots_12.io_out_uop_bypassable, %slots_11.io_out_uop_bypassable : i1
    %2919 = comb.mux %2904, %slots_12.io_out_uop_ppred_busy, %slots_11.io_out_uop_ppred_busy : i1
    %2920 = comb.mux %2904, %slots_12.io_out_uop_prs3_busy, %slots_11.io_out_uop_prs3_busy : i1
    %2921 = comb.mux %2904, %slots_12.io_out_uop_prs2_busy, %slots_11.io_out_uop_prs2_busy : i1
    %2922 = comb.mux %2904, %slots_12.io_out_uop_prs1_busy, %slots_11.io_out_uop_prs1_busy : i1
    %2923 = comb.mux %2904, %slots_12.io_out_uop_prs3, %slots_11.io_out_uop_prs3 : i7
    %2924 = comb.mux %2904, %slots_12.io_out_uop_prs2, %slots_11.io_out_uop_prs2 : i7
    %2925 = comb.mux %2904, %slots_12.io_out_uop_prs1, %slots_11.io_out_uop_prs1 : i7
    %2926 = comb.mux %2904, %slots_12.io_out_uop_pdst, %slots_11.io_out_uop_pdst : i7
    %2927 = comb.mux %2904, %slots_12.io_out_uop_stq_idx, %slots_11.io_out_uop_stq_idx : i5
    %2928 = comb.mux %2904, %slots_12.io_out_uop_ldq_idx, %slots_11.io_out_uop_ldq_idx : i5
    %2929 = comb.mux %2904, %slots_12.io_out_uop_rob_idx, %slots_11.io_out_uop_rob_idx : i7
    %2930 = comb.mux %2904, %slots_12.io_out_uop_imm_packed, %slots_11.io_out_uop_imm_packed : i20
    %2931 = comb.mux %2904, %slots_12.io_out_uop_taken, %slots_11.io_out_uop_taken : i1
    %2932 = comb.mux %2904, %slots_12.io_out_uop_pc_lob, %slots_11.io_out_uop_pc_lob : i6
    %2933 = comb.mux %2904, %slots_12.io_out_uop_edge_inst, %slots_11.io_out_uop_edge_inst : i1
    %2934 = comb.mux %2904, %slots_12.io_out_uop_ftq_idx, %slots_11.io_out_uop_ftq_idx : i6
    %2935 = comb.mux %2904, %slots_12.io_out_uop_br_tag, %slots_11.io_out_uop_br_tag : i5
    %2936 = comb.mux %2904, %slots_12.io_out_uop_br_mask, %slots_11.io_out_uop_br_mask : i20
    %2937 = comb.mux %2904, %slots_12.io_out_uop_is_sfb, %slots_11.io_out_uop_is_sfb : i1
    %2938 = comb.mux %2904, %slots_12.io_out_uop_is_jal, %slots_11.io_out_uop_is_jal : i1
    %2939 = comb.mux %2904, %slots_12.io_out_uop_is_jalr, %slots_11.io_out_uop_is_jalr : i1
    %2940 = comb.mux %2904, %slots_12.io_out_uop_is_br, %slots_11.io_out_uop_is_br : i1
    %2941 = comb.mux %2904, %slots_12.io_out_uop_iw_p2_poisoned, %slots_11.io_out_uop_iw_p2_poisoned : i1
    %2942 = comb.mux %2904, %slots_12.io_out_uop_iw_p1_poisoned, %slots_11.io_out_uop_iw_p1_poisoned : i1
    %2943 = comb.mux %2904, %slots_12.io_out_uop_iw_state, %slots_11.io_out_uop_iw_state : i2
    %2944 = comb.mux %2904, %slots_12.io_out_uop_fu_code, %slots_11.io_out_uop_fu_code : i10
    %2945 = comb.mux %2904, %slots_12.io_out_uop_is_rvc, %slots_11.io_out_uop_is_rvc : i1
    %2946 = comb.mux %2904, %slots_12.io_out_uop_uopc, %slots_11.io_out_uop_uopc : i7
    %2947 = comb.icmp eq %1735, %c4_i4 : i4
    %2948 = comb.mux %2947, %slots_13.io_will_be_valid, %2905 : i1
    %2949 = comb.mux %2947, %slots_13.io_out_uop_fp_val, %2906 : i1
    %2950 = comb.mux %2947, %slots_13.io_out_uop_lrs2_rtype, %2907 : i2
    %2951 = comb.mux %2947, %slots_13.io_out_uop_lrs1_rtype, %2908 : i2
    %2952 = comb.mux %2947, %slots_13.io_out_uop_dst_rtype, %2909 : i2
    %2953 = comb.mux %2947, %slots_13.io_out_uop_ldst_val, %2910 : i1
    %2954 = comb.mux %2947, %slots_13.io_out_uop_uses_stq, %2911 : i1
    %2955 = comb.mux %2947, %slots_13.io_out_uop_uses_ldq, %2912 : i1
    %2956 = comb.mux %2947, %slots_13.io_out_uop_is_amo, %2913 : i1
    %2957 = comb.mux %2947, %slots_13.io_out_uop_is_fence, %2914 : i1
    %2958 = comb.mux %2947, %slots_13.io_out_uop_mem_signed, %2915 : i1
    %2959 = comb.mux %2947, %slots_13.io_out_uop_mem_size, %2916 : i2
    %2960 = comb.mux %2947, %slots_13.io_out_uop_mem_cmd, %2917 : i5
    %2961 = comb.mux %2947, %slots_13.io_out_uop_bypassable, %2918 : i1
    %2962 = comb.mux %2947, %slots_13.io_out_uop_ppred_busy, %2919 : i1
    %2963 = comb.mux %2947, %slots_13.io_out_uop_prs3_busy, %2920 : i1
    %2964 = comb.mux %2947, %slots_13.io_out_uop_prs2_busy, %2921 : i1
    %2965 = comb.mux %2947, %slots_13.io_out_uop_prs1_busy, %2922 : i1
    %2966 = comb.mux %2947, %slots_13.io_out_uop_prs3, %2923 : i7
    %2967 = comb.mux %2947, %slots_13.io_out_uop_prs2, %2924 : i7
    %2968 = comb.mux %2947, %slots_13.io_out_uop_prs1, %2925 : i7
    %2969 = comb.mux %2947, %slots_13.io_out_uop_pdst, %2926 : i7
    %2970 = comb.mux %2947, %slots_13.io_out_uop_stq_idx, %2927 : i5
    %2971 = comb.mux %2947, %slots_13.io_out_uop_ldq_idx, %2928 : i5
    %2972 = comb.mux %2947, %slots_13.io_out_uop_rob_idx, %2929 : i7
    %2973 = comb.mux %2947, %slots_13.io_out_uop_imm_packed, %2930 : i20
    %2974 = comb.mux %2947, %slots_13.io_out_uop_taken, %2931 : i1
    %2975 = comb.mux %2947, %slots_13.io_out_uop_pc_lob, %2932 : i6
    %2976 = comb.mux %2947, %slots_13.io_out_uop_edge_inst, %2933 : i1
    %2977 = comb.mux %2947, %slots_13.io_out_uop_ftq_idx, %2934 : i6
    %2978 = comb.mux %2947, %slots_13.io_out_uop_br_tag, %2935 : i5
    %2979 = comb.mux %2947, %slots_13.io_out_uop_br_mask, %2936 : i20
    %2980 = comb.mux %2947, %slots_13.io_out_uop_is_sfb, %2937 : i1
    %2981 = comb.mux %2947, %slots_13.io_out_uop_is_jal, %2938 : i1
    %2982 = comb.mux %2947, %slots_13.io_out_uop_is_jalr, %2939 : i1
    %2983 = comb.mux %2947, %slots_13.io_out_uop_is_br, %2940 : i1
    %2984 = comb.mux %2947, %slots_13.io_out_uop_iw_p2_poisoned, %2941 : i1
    %2985 = comb.mux %2947, %slots_13.io_out_uop_iw_p1_poisoned, %2942 : i1
    %2986 = comb.mux %2947, %slots_13.io_out_uop_iw_state, %2943 : i2
    %2987 = comb.mux %2947, %slots_13.io_out_uop_fu_code, %2944 : i10
    %2988 = comb.mux %2947, %slots_13.io_out_uop_is_rvc, %2945 : i1
    %2989 = comb.mux %2947, %slots_13.io_out_uop_uopc, %2946 : i7
    %2990 = comb.icmp eq %1743, %c-8_i4 : i4
    %issue_slots_14_will_be_valid = sv.wire sym @issue_slots_14_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_14_will_be_valid, %slots_14.io_will_be_valid : i1
    %2991 = comb.mux %2990, %slots_14.io_will_be_valid, %2948 {sv.namehint = "_issue_slots_10_in_uop_valid"} : i1
    %issue_slots_10_in_uop_valid = sv.wire sym @issue_slots_10_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_10_in_uop_valid, %2991 : i1
    %issue_slots_14_out_uop_fp_val = sv.wire sym @issue_slots_14_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_fp_val, %slots_14.io_out_uop_fp_val : i1
    %issue_slots_14_out_uop_lrs2_rtype = sv.wire sym @issue_slots_14_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_14_out_uop_lrs2_rtype, %slots_14.io_out_uop_lrs2_rtype : i2
    %issue_slots_14_out_uop_lrs1_rtype = sv.wire sym @issue_slots_14_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_14_out_uop_lrs1_rtype, %slots_14.io_out_uop_lrs1_rtype : i2
    %issue_slots_14_out_uop_dst_rtype = sv.wire sym @issue_slots_14_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_14_out_uop_dst_rtype, %slots_14.io_out_uop_dst_rtype : i2
    %issue_slots_14_out_uop_ldst_val = sv.wire sym @issue_slots_14_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_ldst_val, %slots_14.io_out_uop_ldst_val : i1
    %issue_slots_14_out_uop_uses_stq = sv.wire sym @issue_slots_14_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_uses_stq, %slots_14.io_out_uop_uses_stq : i1
    %issue_slots_14_out_uop_uses_ldq = sv.wire sym @issue_slots_14_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_uses_ldq, %slots_14.io_out_uop_uses_ldq : i1
    %issue_slots_14_out_uop_is_amo = sv.wire sym @issue_slots_14_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_is_amo, %slots_14.io_out_uop_is_amo : i1
    %issue_slots_14_out_uop_is_fence = sv.wire sym @issue_slots_14_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_is_fence, %slots_14.io_out_uop_is_fence : i1
    %issue_slots_14_out_uop_mem_signed = sv.wire sym @issue_slots_14_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_mem_signed, %slots_14.io_out_uop_mem_signed : i1
    %issue_slots_14_out_uop_mem_size = sv.wire sym @issue_slots_14_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_14_out_uop_mem_size, %slots_14.io_out_uop_mem_size : i2
    %issue_slots_14_out_uop_mem_cmd = sv.wire sym @issue_slots_14_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_14_out_uop_mem_cmd, %slots_14.io_out_uop_mem_cmd : i5
    %issue_slots_14_out_uop_bypassable = sv.wire sym @issue_slots_14_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_bypassable, %slots_14.io_out_uop_bypassable : i1
    %issue_slots_14_out_uop_ppred_busy = sv.wire sym @issue_slots_14_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_ppred_busy, %slots_14.io_out_uop_ppred_busy : i1
    %issue_slots_14_out_uop_prs3_busy = sv.wire sym @issue_slots_14_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_prs3_busy, %slots_14.io_out_uop_prs3_busy : i1
    %issue_slots_14_out_uop_prs2_busy = sv.wire sym @issue_slots_14_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_prs2_busy, %slots_14.io_out_uop_prs2_busy : i1
    %issue_slots_14_out_uop_prs1_busy = sv.wire sym @issue_slots_14_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_prs1_busy, %slots_14.io_out_uop_prs1_busy : i1
    %issue_slots_14_out_uop_prs3 = sv.wire sym @issue_slots_14_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_14_out_uop_prs3, %slots_14.io_out_uop_prs3 : i7
    %issue_slots_14_out_uop_prs2 = sv.wire sym @issue_slots_14_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_14_out_uop_prs2, %slots_14.io_out_uop_prs2 : i7
    %issue_slots_14_out_uop_prs1 = sv.wire sym @issue_slots_14_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_14_out_uop_prs1, %slots_14.io_out_uop_prs1 : i7
    %issue_slots_14_out_uop_pdst = sv.wire sym @issue_slots_14_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_14_out_uop_pdst, %slots_14.io_out_uop_pdst : i7
    %issue_slots_14_out_uop_stq_idx = sv.wire sym @issue_slots_14_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_14_out_uop_stq_idx, %slots_14.io_out_uop_stq_idx : i5
    %issue_slots_14_out_uop_ldq_idx = sv.wire sym @issue_slots_14_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_14_out_uop_ldq_idx, %slots_14.io_out_uop_ldq_idx : i5
    %issue_slots_14_out_uop_rob_idx = sv.wire sym @issue_slots_14_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_14_out_uop_rob_idx, %slots_14.io_out_uop_rob_idx : i7
    %issue_slots_14_out_uop_imm_packed = sv.wire sym @issue_slots_14_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_14_out_uop_imm_packed, %slots_14.io_out_uop_imm_packed : i20
    %issue_slots_14_out_uop_taken = sv.wire sym @issue_slots_14_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_taken, %slots_14.io_out_uop_taken : i1
    %issue_slots_14_out_uop_pc_lob = sv.wire sym @issue_slots_14_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_14_out_uop_pc_lob, %slots_14.io_out_uop_pc_lob : i6
    %issue_slots_14_out_uop_edge_inst = sv.wire sym @issue_slots_14_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_edge_inst, %slots_14.io_out_uop_edge_inst : i1
    %issue_slots_14_out_uop_ftq_idx = sv.wire sym @issue_slots_14_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_14_out_uop_ftq_idx, %slots_14.io_out_uop_ftq_idx : i6
    %issue_slots_14_out_uop_br_tag = sv.wire sym @issue_slots_14_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_14_out_uop_br_tag, %slots_14.io_out_uop_br_tag : i5
    %issue_slots_14_out_uop_br_mask = sv.wire sym @issue_slots_14_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_14_out_uop_br_mask, %slots_14.io_out_uop_br_mask : i20
    %issue_slots_14_out_uop_is_sfb = sv.wire sym @issue_slots_14_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_is_sfb, %slots_14.io_out_uop_is_sfb : i1
    %issue_slots_14_out_uop_is_jal = sv.wire sym @issue_slots_14_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_is_jal, %slots_14.io_out_uop_is_jal : i1
    %issue_slots_14_out_uop_is_jalr = sv.wire sym @issue_slots_14_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_is_jalr, %slots_14.io_out_uop_is_jalr : i1
    %issue_slots_14_out_uop_is_br = sv.wire sym @issue_slots_14_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_is_br, %slots_14.io_out_uop_is_br : i1
    %issue_slots_14_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_14_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_iw_p2_poisoned, %slots_14.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_14_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_14_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_iw_p1_poisoned, %slots_14.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_14_out_uop_iw_state = sv.wire sym @issue_slots_14_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_14_out_uop_iw_state, %slots_14.io_out_uop_iw_state : i2
    %issue_slots_14_out_uop_fu_code = sv.wire sym @issue_slots_14_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_14_out_uop_fu_code, %slots_14.io_out_uop_fu_code : i10
    %issue_slots_14_out_uop_is_rvc = sv.wire sym @issue_slots_14_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_14_out_uop_is_rvc, %slots_14.io_out_uop_is_rvc : i1
    %issue_slots_14_out_uop_uopc = sv.wire sym @issue_slots_14_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_14_out_uop_uopc, %slots_14.io_out_uop_uopc : i7
    %2992 = comb.icmp ne %1711, %c0_i4 {sv.namehint = "_issue_slots_10_clear"} : i4
    %issue_slots_10_clear = sv.wire sym @issue_slots_10_clear  : !hw.inout<i1>
    sv.assign %issue_slots_10_clear, %2992 : i1
    %2993 = comb.icmp eq %1727, %c1_i4 : i4
    %2994 = comb.and %2993, %slots_12.io_will_be_valid : i1
    %2995 = comb.icmp eq %1735, %c2_i4 : i4
    %2996 = comb.mux %2995, %slots_13.io_will_be_valid, %2994 : i1
    %2997 = comb.mux %2995, %slots_13.io_out_uop_fp_val, %slots_12.io_out_uop_fp_val : i1
    %2998 = comb.mux %2995, %slots_13.io_out_uop_lrs2_rtype, %slots_12.io_out_uop_lrs2_rtype : i2
    %2999 = comb.mux %2995, %slots_13.io_out_uop_lrs1_rtype, %slots_12.io_out_uop_lrs1_rtype : i2
    %3000 = comb.mux %2995, %slots_13.io_out_uop_dst_rtype, %slots_12.io_out_uop_dst_rtype : i2
    %3001 = comb.mux %2995, %slots_13.io_out_uop_ldst_val, %slots_12.io_out_uop_ldst_val : i1
    %3002 = comb.mux %2995, %slots_13.io_out_uop_uses_stq, %slots_12.io_out_uop_uses_stq : i1
    %3003 = comb.mux %2995, %slots_13.io_out_uop_uses_ldq, %slots_12.io_out_uop_uses_ldq : i1
    %3004 = comb.mux %2995, %slots_13.io_out_uop_is_amo, %slots_12.io_out_uop_is_amo : i1
    %3005 = comb.mux %2995, %slots_13.io_out_uop_is_fence, %slots_12.io_out_uop_is_fence : i1
    %3006 = comb.mux %2995, %slots_13.io_out_uop_mem_signed, %slots_12.io_out_uop_mem_signed : i1
    %3007 = comb.mux %2995, %slots_13.io_out_uop_mem_size, %slots_12.io_out_uop_mem_size : i2
    %3008 = comb.mux %2995, %slots_13.io_out_uop_mem_cmd, %slots_12.io_out_uop_mem_cmd : i5
    %3009 = comb.mux %2995, %slots_13.io_out_uop_bypassable, %slots_12.io_out_uop_bypassable : i1
    %3010 = comb.mux %2995, %slots_13.io_out_uop_ppred_busy, %slots_12.io_out_uop_ppred_busy : i1
    %3011 = comb.mux %2995, %slots_13.io_out_uop_prs3_busy, %slots_12.io_out_uop_prs3_busy : i1
    %3012 = comb.mux %2995, %slots_13.io_out_uop_prs2_busy, %slots_12.io_out_uop_prs2_busy : i1
    %3013 = comb.mux %2995, %slots_13.io_out_uop_prs1_busy, %slots_12.io_out_uop_prs1_busy : i1
    %3014 = comb.mux %2995, %slots_13.io_out_uop_prs3, %slots_12.io_out_uop_prs3 : i7
    %3015 = comb.mux %2995, %slots_13.io_out_uop_prs2, %slots_12.io_out_uop_prs2 : i7
    %3016 = comb.mux %2995, %slots_13.io_out_uop_prs1, %slots_12.io_out_uop_prs1 : i7
    %3017 = comb.mux %2995, %slots_13.io_out_uop_pdst, %slots_12.io_out_uop_pdst : i7
    %3018 = comb.mux %2995, %slots_13.io_out_uop_stq_idx, %slots_12.io_out_uop_stq_idx : i5
    %3019 = comb.mux %2995, %slots_13.io_out_uop_ldq_idx, %slots_12.io_out_uop_ldq_idx : i5
    %3020 = comb.mux %2995, %slots_13.io_out_uop_rob_idx, %slots_12.io_out_uop_rob_idx : i7
    %3021 = comb.mux %2995, %slots_13.io_out_uop_imm_packed, %slots_12.io_out_uop_imm_packed : i20
    %3022 = comb.mux %2995, %slots_13.io_out_uop_taken, %slots_12.io_out_uop_taken : i1
    %3023 = comb.mux %2995, %slots_13.io_out_uop_pc_lob, %slots_12.io_out_uop_pc_lob : i6
    %3024 = comb.mux %2995, %slots_13.io_out_uop_edge_inst, %slots_12.io_out_uop_edge_inst : i1
    %3025 = comb.mux %2995, %slots_13.io_out_uop_ftq_idx, %slots_12.io_out_uop_ftq_idx : i6
    %3026 = comb.mux %2995, %slots_13.io_out_uop_br_tag, %slots_12.io_out_uop_br_tag : i5
    %3027 = comb.mux %2995, %slots_13.io_out_uop_br_mask, %slots_12.io_out_uop_br_mask : i20
    %3028 = comb.mux %2995, %slots_13.io_out_uop_is_sfb, %slots_12.io_out_uop_is_sfb : i1
    %3029 = comb.mux %2995, %slots_13.io_out_uop_is_jal, %slots_12.io_out_uop_is_jal : i1
    %3030 = comb.mux %2995, %slots_13.io_out_uop_is_jalr, %slots_12.io_out_uop_is_jalr : i1
    %3031 = comb.mux %2995, %slots_13.io_out_uop_is_br, %slots_12.io_out_uop_is_br : i1
    %3032 = comb.mux %2995, %slots_13.io_out_uop_iw_p2_poisoned, %slots_12.io_out_uop_iw_p2_poisoned : i1
    %3033 = comb.mux %2995, %slots_13.io_out_uop_iw_p1_poisoned, %slots_12.io_out_uop_iw_p1_poisoned : i1
    %3034 = comb.mux %2995, %slots_13.io_out_uop_iw_state, %slots_12.io_out_uop_iw_state : i2
    %3035 = comb.mux %2995, %slots_13.io_out_uop_fu_code, %slots_12.io_out_uop_fu_code : i10
    %3036 = comb.mux %2995, %slots_13.io_out_uop_is_rvc, %slots_12.io_out_uop_is_rvc : i1
    %3037 = comb.mux %2995, %slots_13.io_out_uop_uopc, %slots_12.io_out_uop_uopc : i7
    %3038 = comb.icmp eq %1743, %c4_i4 : i4
    %3039 = comb.mux %3038, %slots_14.io_will_be_valid, %2996 : i1
    %3040 = comb.mux %3038, %slots_14.io_out_uop_fp_val, %2997 : i1
    %3041 = comb.mux %3038, %slots_14.io_out_uop_lrs2_rtype, %2998 : i2
    %3042 = comb.mux %3038, %slots_14.io_out_uop_lrs1_rtype, %2999 : i2
    %3043 = comb.mux %3038, %slots_14.io_out_uop_dst_rtype, %3000 : i2
    %3044 = comb.mux %3038, %slots_14.io_out_uop_ldst_val, %3001 : i1
    %3045 = comb.mux %3038, %slots_14.io_out_uop_uses_stq, %3002 : i1
    %3046 = comb.mux %3038, %slots_14.io_out_uop_uses_ldq, %3003 : i1
    %3047 = comb.mux %3038, %slots_14.io_out_uop_is_amo, %3004 : i1
    %3048 = comb.mux %3038, %slots_14.io_out_uop_is_fence, %3005 : i1
    %3049 = comb.mux %3038, %slots_14.io_out_uop_mem_signed, %3006 : i1
    %3050 = comb.mux %3038, %slots_14.io_out_uop_mem_size, %3007 : i2
    %3051 = comb.mux %3038, %slots_14.io_out_uop_mem_cmd, %3008 : i5
    %3052 = comb.mux %3038, %slots_14.io_out_uop_bypassable, %3009 : i1
    %3053 = comb.mux %3038, %slots_14.io_out_uop_ppred_busy, %3010 : i1
    %3054 = comb.mux %3038, %slots_14.io_out_uop_prs3_busy, %3011 : i1
    %3055 = comb.mux %3038, %slots_14.io_out_uop_prs2_busy, %3012 : i1
    %3056 = comb.mux %3038, %slots_14.io_out_uop_prs1_busy, %3013 : i1
    %3057 = comb.mux %3038, %slots_14.io_out_uop_prs3, %3014 : i7
    %3058 = comb.mux %3038, %slots_14.io_out_uop_prs2, %3015 : i7
    %3059 = comb.mux %3038, %slots_14.io_out_uop_prs1, %3016 : i7
    %3060 = comb.mux %3038, %slots_14.io_out_uop_pdst, %3017 : i7
    %3061 = comb.mux %3038, %slots_14.io_out_uop_stq_idx, %3018 : i5
    %3062 = comb.mux %3038, %slots_14.io_out_uop_ldq_idx, %3019 : i5
    %3063 = comb.mux %3038, %slots_14.io_out_uop_rob_idx, %3020 : i7
    %3064 = comb.mux %3038, %slots_14.io_out_uop_imm_packed, %3021 : i20
    %3065 = comb.mux %3038, %slots_14.io_out_uop_taken, %3022 : i1
    %3066 = comb.mux %3038, %slots_14.io_out_uop_pc_lob, %3023 : i6
    %3067 = comb.mux %3038, %slots_14.io_out_uop_edge_inst, %3024 : i1
    %3068 = comb.mux %3038, %slots_14.io_out_uop_ftq_idx, %3025 : i6
    %3069 = comb.mux %3038, %slots_14.io_out_uop_br_tag, %3026 : i5
    %3070 = comb.mux %3038, %slots_14.io_out_uop_br_mask, %3027 : i20
    %3071 = comb.mux %3038, %slots_14.io_out_uop_is_sfb, %3028 : i1
    %3072 = comb.mux %3038, %slots_14.io_out_uop_is_jal, %3029 : i1
    %3073 = comb.mux %3038, %slots_14.io_out_uop_is_jalr, %3030 : i1
    %3074 = comb.mux %3038, %slots_14.io_out_uop_is_br, %3031 : i1
    %3075 = comb.mux %3038, %slots_14.io_out_uop_iw_p2_poisoned, %3032 : i1
    %3076 = comb.mux %3038, %slots_14.io_out_uop_iw_p1_poisoned, %3033 : i1
    %3077 = comb.mux %3038, %slots_14.io_out_uop_iw_state, %3034 : i2
    %3078 = comb.mux %3038, %slots_14.io_out_uop_fu_code, %3035 : i10
    %3079 = comb.mux %3038, %slots_14.io_out_uop_is_rvc, %3036 : i1
    %3080 = comb.mux %3038, %slots_14.io_out_uop_uopc, %3037 : i7
    %3081 = comb.icmp eq %1751, %c-8_i4 : i4
    %issue_slots_15_will_be_valid = sv.wire sym @issue_slots_15_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_15_will_be_valid, %slots_15.io_will_be_valid : i1
    %3082 = comb.mux %3081, %slots_15.io_will_be_valid, %3039 {sv.namehint = "_issue_slots_11_in_uop_valid"} : i1
    %issue_slots_11_in_uop_valid = sv.wire sym @issue_slots_11_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_11_in_uop_valid, %3082 : i1
    %issue_slots_15_out_uop_fp_val = sv.wire sym @issue_slots_15_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_fp_val, %slots_15.io_out_uop_fp_val : i1
    %issue_slots_15_out_uop_lrs2_rtype = sv.wire sym @issue_slots_15_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_15_out_uop_lrs2_rtype, %slots_15.io_out_uop_lrs2_rtype : i2
    %issue_slots_15_out_uop_lrs1_rtype = sv.wire sym @issue_slots_15_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_15_out_uop_lrs1_rtype, %slots_15.io_out_uop_lrs1_rtype : i2
    %issue_slots_15_out_uop_dst_rtype = sv.wire sym @issue_slots_15_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_15_out_uop_dst_rtype, %slots_15.io_out_uop_dst_rtype : i2
    %issue_slots_15_out_uop_ldst_val = sv.wire sym @issue_slots_15_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_ldst_val, %slots_15.io_out_uop_ldst_val : i1
    %issue_slots_15_out_uop_uses_stq = sv.wire sym @issue_slots_15_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_uses_stq, %slots_15.io_out_uop_uses_stq : i1
    %issue_slots_15_out_uop_uses_ldq = sv.wire sym @issue_slots_15_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_uses_ldq, %slots_15.io_out_uop_uses_ldq : i1
    %issue_slots_15_out_uop_is_amo = sv.wire sym @issue_slots_15_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_is_amo, %slots_15.io_out_uop_is_amo : i1
    %issue_slots_15_out_uop_is_fence = sv.wire sym @issue_slots_15_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_is_fence, %slots_15.io_out_uop_is_fence : i1
    %issue_slots_15_out_uop_mem_signed = sv.wire sym @issue_slots_15_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_mem_signed, %slots_15.io_out_uop_mem_signed : i1
    %issue_slots_15_out_uop_mem_size = sv.wire sym @issue_slots_15_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_15_out_uop_mem_size, %slots_15.io_out_uop_mem_size : i2
    %issue_slots_15_out_uop_mem_cmd = sv.wire sym @issue_slots_15_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_15_out_uop_mem_cmd, %slots_15.io_out_uop_mem_cmd : i5
    %issue_slots_15_out_uop_bypassable = sv.wire sym @issue_slots_15_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_bypassable, %slots_15.io_out_uop_bypassable : i1
    %issue_slots_15_out_uop_ppred_busy = sv.wire sym @issue_slots_15_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_ppred_busy, %slots_15.io_out_uop_ppred_busy : i1
    %issue_slots_15_out_uop_prs3_busy = sv.wire sym @issue_slots_15_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_prs3_busy, %slots_15.io_out_uop_prs3_busy : i1
    %issue_slots_15_out_uop_prs2_busy = sv.wire sym @issue_slots_15_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_prs2_busy, %slots_15.io_out_uop_prs2_busy : i1
    %issue_slots_15_out_uop_prs1_busy = sv.wire sym @issue_slots_15_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_prs1_busy, %slots_15.io_out_uop_prs1_busy : i1
    %issue_slots_15_out_uop_prs3 = sv.wire sym @issue_slots_15_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_15_out_uop_prs3, %slots_15.io_out_uop_prs3 : i7
    %issue_slots_15_out_uop_prs2 = sv.wire sym @issue_slots_15_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_15_out_uop_prs2, %slots_15.io_out_uop_prs2 : i7
    %issue_slots_15_out_uop_prs1 = sv.wire sym @issue_slots_15_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_15_out_uop_prs1, %slots_15.io_out_uop_prs1 : i7
    %issue_slots_15_out_uop_pdst = sv.wire sym @issue_slots_15_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_15_out_uop_pdst, %slots_15.io_out_uop_pdst : i7
    %issue_slots_15_out_uop_stq_idx = sv.wire sym @issue_slots_15_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_15_out_uop_stq_idx, %slots_15.io_out_uop_stq_idx : i5
    %issue_slots_15_out_uop_ldq_idx = sv.wire sym @issue_slots_15_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_15_out_uop_ldq_idx, %slots_15.io_out_uop_ldq_idx : i5
    %issue_slots_15_out_uop_rob_idx = sv.wire sym @issue_slots_15_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_15_out_uop_rob_idx, %slots_15.io_out_uop_rob_idx : i7
    %issue_slots_15_out_uop_imm_packed = sv.wire sym @issue_slots_15_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_15_out_uop_imm_packed, %slots_15.io_out_uop_imm_packed : i20
    %issue_slots_15_out_uop_taken = sv.wire sym @issue_slots_15_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_taken, %slots_15.io_out_uop_taken : i1
    %issue_slots_15_out_uop_pc_lob = sv.wire sym @issue_slots_15_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_15_out_uop_pc_lob, %slots_15.io_out_uop_pc_lob : i6
    %issue_slots_15_out_uop_edge_inst = sv.wire sym @issue_slots_15_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_edge_inst, %slots_15.io_out_uop_edge_inst : i1
    %issue_slots_15_out_uop_ftq_idx = sv.wire sym @issue_slots_15_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_15_out_uop_ftq_idx, %slots_15.io_out_uop_ftq_idx : i6
    %issue_slots_15_out_uop_br_tag = sv.wire sym @issue_slots_15_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_15_out_uop_br_tag, %slots_15.io_out_uop_br_tag : i5
    %issue_slots_15_out_uop_br_mask = sv.wire sym @issue_slots_15_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_15_out_uop_br_mask, %slots_15.io_out_uop_br_mask : i20
    %issue_slots_15_out_uop_is_sfb = sv.wire sym @issue_slots_15_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_is_sfb, %slots_15.io_out_uop_is_sfb : i1
    %issue_slots_15_out_uop_is_jal = sv.wire sym @issue_slots_15_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_is_jal, %slots_15.io_out_uop_is_jal : i1
    %issue_slots_15_out_uop_is_jalr = sv.wire sym @issue_slots_15_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_is_jalr, %slots_15.io_out_uop_is_jalr : i1
    %issue_slots_15_out_uop_is_br = sv.wire sym @issue_slots_15_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_is_br, %slots_15.io_out_uop_is_br : i1
    %issue_slots_15_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_15_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_iw_p2_poisoned, %slots_15.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_15_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_15_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_iw_p1_poisoned, %slots_15.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_15_out_uop_iw_state = sv.wire sym @issue_slots_15_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_15_out_uop_iw_state, %slots_15.io_out_uop_iw_state : i2
    %issue_slots_15_out_uop_fu_code = sv.wire sym @issue_slots_15_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_15_out_uop_fu_code, %slots_15.io_out_uop_fu_code : i10
    %issue_slots_15_out_uop_is_rvc = sv.wire sym @issue_slots_15_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_15_out_uop_is_rvc, %slots_15.io_out_uop_is_rvc : i1
    %issue_slots_15_out_uop_uopc = sv.wire sym @issue_slots_15_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_15_out_uop_uopc, %slots_15.io_out_uop_uopc : i7
    %3083 = comb.icmp ne %1719, %c0_i4 {sv.namehint = "_issue_slots_11_clear"} : i4
    %issue_slots_11_clear = sv.wire sym @issue_slots_11_clear  : !hw.inout<i1>
    sv.assign %issue_slots_11_clear, %3083 : i1
    %3084 = comb.icmp eq %1735, %c1_i4 : i4
    %3085 = comb.and %3084, %slots_13.io_will_be_valid : i1
    %3086 = comb.icmp eq %1743, %c2_i4 : i4
    %3087 = comb.mux %3086, %slots_14.io_will_be_valid, %3085 : i1
    %3088 = comb.mux %3086, %slots_14.io_out_uop_fp_val, %slots_13.io_out_uop_fp_val : i1
    %3089 = comb.mux %3086, %slots_14.io_out_uop_lrs2_rtype, %slots_13.io_out_uop_lrs2_rtype : i2
    %3090 = comb.mux %3086, %slots_14.io_out_uop_lrs1_rtype, %slots_13.io_out_uop_lrs1_rtype : i2
    %3091 = comb.mux %3086, %slots_14.io_out_uop_dst_rtype, %slots_13.io_out_uop_dst_rtype : i2
    %3092 = comb.mux %3086, %slots_14.io_out_uop_ldst_val, %slots_13.io_out_uop_ldst_val : i1
    %3093 = comb.mux %3086, %slots_14.io_out_uop_uses_stq, %slots_13.io_out_uop_uses_stq : i1
    %3094 = comb.mux %3086, %slots_14.io_out_uop_uses_ldq, %slots_13.io_out_uop_uses_ldq : i1
    %3095 = comb.mux %3086, %slots_14.io_out_uop_is_amo, %slots_13.io_out_uop_is_amo : i1
    %3096 = comb.mux %3086, %slots_14.io_out_uop_is_fence, %slots_13.io_out_uop_is_fence : i1
    %3097 = comb.mux %3086, %slots_14.io_out_uop_mem_signed, %slots_13.io_out_uop_mem_signed : i1
    %3098 = comb.mux %3086, %slots_14.io_out_uop_mem_size, %slots_13.io_out_uop_mem_size : i2
    %3099 = comb.mux %3086, %slots_14.io_out_uop_mem_cmd, %slots_13.io_out_uop_mem_cmd : i5
    %3100 = comb.mux %3086, %slots_14.io_out_uop_bypassable, %slots_13.io_out_uop_bypassable : i1
    %3101 = comb.mux %3086, %slots_14.io_out_uop_ppred_busy, %slots_13.io_out_uop_ppred_busy : i1
    %3102 = comb.mux %3086, %slots_14.io_out_uop_prs3_busy, %slots_13.io_out_uop_prs3_busy : i1
    %3103 = comb.mux %3086, %slots_14.io_out_uop_prs2_busy, %slots_13.io_out_uop_prs2_busy : i1
    %3104 = comb.mux %3086, %slots_14.io_out_uop_prs1_busy, %slots_13.io_out_uop_prs1_busy : i1
    %3105 = comb.mux %3086, %slots_14.io_out_uop_prs3, %slots_13.io_out_uop_prs3 : i7
    %3106 = comb.mux %3086, %slots_14.io_out_uop_prs2, %slots_13.io_out_uop_prs2 : i7
    %3107 = comb.mux %3086, %slots_14.io_out_uop_prs1, %slots_13.io_out_uop_prs1 : i7
    %3108 = comb.mux %3086, %slots_14.io_out_uop_pdst, %slots_13.io_out_uop_pdst : i7
    %3109 = comb.mux %3086, %slots_14.io_out_uop_stq_idx, %slots_13.io_out_uop_stq_idx : i5
    %3110 = comb.mux %3086, %slots_14.io_out_uop_ldq_idx, %slots_13.io_out_uop_ldq_idx : i5
    %3111 = comb.mux %3086, %slots_14.io_out_uop_rob_idx, %slots_13.io_out_uop_rob_idx : i7
    %3112 = comb.mux %3086, %slots_14.io_out_uop_imm_packed, %slots_13.io_out_uop_imm_packed : i20
    %3113 = comb.mux %3086, %slots_14.io_out_uop_taken, %slots_13.io_out_uop_taken : i1
    %3114 = comb.mux %3086, %slots_14.io_out_uop_pc_lob, %slots_13.io_out_uop_pc_lob : i6
    %3115 = comb.mux %3086, %slots_14.io_out_uop_edge_inst, %slots_13.io_out_uop_edge_inst : i1
    %3116 = comb.mux %3086, %slots_14.io_out_uop_ftq_idx, %slots_13.io_out_uop_ftq_idx : i6
    %3117 = comb.mux %3086, %slots_14.io_out_uop_br_tag, %slots_13.io_out_uop_br_tag : i5
    %3118 = comb.mux %3086, %slots_14.io_out_uop_br_mask, %slots_13.io_out_uop_br_mask : i20
    %3119 = comb.mux %3086, %slots_14.io_out_uop_is_sfb, %slots_13.io_out_uop_is_sfb : i1
    %3120 = comb.mux %3086, %slots_14.io_out_uop_is_jal, %slots_13.io_out_uop_is_jal : i1
    %3121 = comb.mux %3086, %slots_14.io_out_uop_is_jalr, %slots_13.io_out_uop_is_jalr : i1
    %3122 = comb.mux %3086, %slots_14.io_out_uop_is_br, %slots_13.io_out_uop_is_br : i1
    %3123 = comb.mux %3086, %slots_14.io_out_uop_iw_p2_poisoned, %slots_13.io_out_uop_iw_p2_poisoned : i1
    %3124 = comb.mux %3086, %slots_14.io_out_uop_iw_p1_poisoned, %slots_13.io_out_uop_iw_p1_poisoned : i1
    %3125 = comb.mux %3086, %slots_14.io_out_uop_iw_state, %slots_13.io_out_uop_iw_state : i2
    %3126 = comb.mux %3086, %slots_14.io_out_uop_fu_code, %slots_13.io_out_uop_fu_code : i10
    %3127 = comb.mux %3086, %slots_14.io_out_uop_is_rvc, %slots_13.io_out_uop_is_rvc : i1
    %3128 = comb.mux %3086, %slots_14.io_out_uop_uopc, %slots_13.io_out_uop_uopc : i7
    %3129 = comb.icmp eq %1751, %c4_i4 : i4
    %3130 = comb.mux %3129, %slots_15.io_will_be_valid, %3087 : i1
    %3131 = comb.mux %3129, %slots_15.io_out_uop_fp_val, %3088 : i1
    %3132 = comb.mux %3129, %slots_15.io_out_uop_lrs2_rtype, %3089 : i2
    %3133 = comb.mux %3129, %slots_15.io_out_uop_lrs1_rtype, %3090 : i2
    %3134 = comb.mux %3129, %slots_15.io_out_uop_dst_rtype, %3091 : i2
    %3135 = comb.mux %3129, %slots_15.io_out_uop_ldst_val, %3092 : i1
    %3136 = comb.mux %3129, %slots_15.io_out_uop_uses_stq, %3093 : i1
    %3137 = comb.mux %3129, %slots_15.io_out_uop_uses_ldq, %3094 : i1
    %3138 = comb.mux %3129, %slots_15.io_out_uop_is_amo, %3095 : i1
    %3139 = comb.mux %3129, %slots_15.io_out_uop_is_fence, %3096 : i1
    %3140 = comb.mux %3129, %slots_15.io_out_uop_mem_signed, %3097 : i1
    %3141 = comb.mux %3129, %slots_15.io_out_uop_mem_size, %3098 : i2
    %3142 = comb.mux %3129, %slots_15.io_out_uop_mem_cmd, %3099 : i5
    %3143 = comb.mux %3129, %slots_15.io_out_uop_bypassable, %3100 : i1
    %3144 = comb.mux %3129, %slots_15.io_out_uop_ppred_busy, %3101 : i1
    %3145 = comb.mux %3129, %slots_15.io_out_uop_prs3_busy, %3102 : i1
    %3146 = comb.mux %3129, %slots_15.io_out_uop_prs2_busy, %3103 : i1
    %3147 = comb.mux %3129, %slots_15.io_out_uop_prs1_busy, %3104 : i1
    %3148 = comb.mux %3129, %slots_15.io_out_uop_prs3, %3105 : i7
    %3149 = comb.mux %3129, %slots_15.io_out_uop_prs2, %3106 : i7
    %3150 = comb.mux %3129, %slots_15.io_out_uop_prs1, %3107 : i7
    %3151 = comb.mux %3129, %slots_15.io_out_uop_pdst, %3108 : i7
    %3152 = comb.mux %3129, %slots_15.io_out_uop_stq_idx, %3109 : i5
    %3153 = comb.mux %3129, %slots_15.io_out_uop_ldq_idx, %3110 : i5
    %3154 = comb.mux %3129, %slots_15.io_out_uop_rob_idx, %3111 : i7
    %3155 = comb.mux %3129, %slots_15.io_out_uop_imm_packed, %3112 : i20
    %3156 = comb.mux %3129, %slots_15.io_out_uop_taken, %3113 : i1
    %3157 = comb.mux %3129, %slots_15.io_out_uop_pc_lob, %3114 : i6
    %3158 = comb.mux %3129, %slots_15.io_out_uop_edge_inst, %3115 : i1
    %3159 = comb.mux %3129, %slots_15.io_out_uop_ftq_idx, %3116 : i6
    %3160 = comb.mux %3129, %slots_15.io_out_uop_br_tag, %3117 : i5
    %3161 = comb.mux %3129, %slots_15.io_out_uop_br_mask, %3118 : i20
    %3162 = comb.mux %3129, %slots_15.io_out_uop_is_sfb, %3119 : i1
    %3163 = comb.mux %3129, %slots_15.io_out_uop_is_jal, %3120 : i1
    %3164 = comb.mux %3129, %slots_15.io_out_uop_is_jalr, %3121 : i1
    %3165 = comb.mux %3129, %slots_15.io_out_uop_is_br, %3122 : i1
    %3166 = comb.mux %3129, %slots_15.io_out_uop_iw_p2_poisoned, %3123 : i1
    %3167 = comb.mux %3129, %slots_15.io_out_uop_iw_p1_poisoned, %3124 : i1
    %3168 = comb.mux %3129, %slots_15.io_out_uop_iw_state, %3125 : i2
    %3169 = comb.mux %3129, %slots_15.io_out_uop_fu_code, %3126 : i10
    %3170 = comb.mux %3129, %slots_15.io_out_uop_is_rvc, %3127 : i1
    %3171 = comb.mux %3129, %slots_15.io_out_uop_uopc, %3128 : i7
    %3172 = comb.icmp eq %1759, %c-8_i4 : i4
    %issue_slots_16_will_be_valid = sv.wire sym @issue_slots_16_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_16_will_be_valid, %slots_16.io_will_be_valid : i1
    %3173 = comb.mux %3172, %slots_16.io_will_be_valid, %3130 {sv.namehint = "_issue_slots_12_in_uop_valid"} : i1
    %issue_slots_12_in_uop_valid = sv.wire sym @issue_slots_12_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_12_in_uop_valid, %3173 : i1
    %issue_slots_16_out_uop_fp_val = sv.wire sym @issue_slots_16_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_fp_val, %slots_16.io_out_uop_fp_val : i1
    %issue_slots_16_out_uop_lrs2_rtype = sv.wire sym @issue_slots_16_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_16_out_uop_lrs2_rtype, %slots_16.io_out_uop_lrs2_rtype : i2
    %issue_slots_16_out_uop_lrs1_rtype = sv.wire sym @issue_slots_16_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_16_out_uop_lrs1_rtype, %slots_16.io_out_uop_lrs1_rtype : i2
    %issue_slots_16_out_uop_dst_rtype = sv.wire sym @issue_slots_16_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_16_out_uop_dst_rtype, %slots_16.io_out_uop_dst_rtype : i2
    %issue_slots_16_out_uop_ldst_val = sv.wire sym @issue_slots_16_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_ldst_val, %slots_16.io_out_uop_ldst_val : i1
    %issue_slots_16_out_uop_uses_stq = sv.wire sym @issue_slots_16_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_uses_stq, %slots_16.io_out_uop_uses_stq : i1
    %issue_slots_16_out_uop_uses_ldq = sv.wire sym @issue_slots_16_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_uses_ldq, %slots_16.io_out_uop_uses_ldq : i1
    %issue_slots_16_out_uop_is_amo = sv.wire sym @issue_slots_16_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_is_amo, %slots_16.io_out_uop_is_amo : i1
    %issue_slots_16_out_uop_is_fence = sv.wire sym @issue_slots_16_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_is_fence, %slots_16.io_out_uop_is_fence : i1
    %issue_slots_16_out_uop_mem_signed = sv.wire sym @issue_slots_16_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_mem_signed, %slots_16.io_out_uop_mem_signed : i1
    %issue_slots_16_out_uop_mem_size = sv.wire sym @issue_slots_16_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_16_out_uop_mem_size, %slots_16.io_out_uop_mem_size : i2
    %issue_slots_16_out_uop_mem_cmd = sv.wire sym @issue_slots_16_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_16_out_uop_mem_cmd, %slots_16.io_out_uop_mem_cmd : i5
    %issue_slots_16_out_uop_bypassable = sv.wire sym @issue_slots_16_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_bypassable, %slots_16.io_out_uop_bypassable : i1
    %issue_slots_16_out_uop_ppred_busy = sv.wire sym @issue_slots_16_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_ppred_busy, %slots_16.io_out_uop_ppred_busy : i1
    %issue_slots_16_out_uop_prs3_busy = sv.wire sym @issue_slots_16_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_prs3_busy, %slots_16.io_out_uop_prs3_busy : i1
    %issue_slots_16_out_uop_prs2_busy = sv.wire sym @issue_slots_16_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_prs2_busy, %slots_16.io_out_uop_prs2_busy : i1
    %issue_slots_16_out_uop_prs1_busy = sv.wire sym @issue_slots_16_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_prs1_busy, %slots_16.io_out_uop_prs1_busy : i1
    %issue_slots_16_out_uop_prs3 = sv.wire sym @issue_slots_16_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_16_out_uop_prs3, %slots_16.io_out_uop_prs3 : i7
    %issue_slots_16_out_uop_prs2 = sv.wire sym @issue_slots_16_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_16_out_uop_prs2, %slots_16.io_out_uop_prs2 : i7
    %issue_slots_16_out_uop_prs1 = sv.wire sym @issue_slots_16_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_16_out_uop_prs1, %slots_16.io_out_uop_prs1 : i7
    %issue_slots_16_out_uop_pdst = sv.wire sym @issue_slots_16_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_16_out_uop_pdst, %slots_16.io_out_uop_pdst : i7
    %issue_slots_16_out_uop_stq_idx = sv.wire sym @issue_slots_16_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_16_out_uop_stq_idx, %slots_16.io_out_uop_stq_idx : i5
    %issue_slots_16_out_uop_ldq_idx = sv.wire sym @issue_slots_16_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_16_out_uop_ldq_idx, %slots_16.io_out_uop_ldq_idx : i5
    %issue_slots_16_out_uop_rob_idx = sv.wire sym @issue_slots_16_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_16_out_uop_rob_idx, %slots_16.io_out_uop_rob_idx : i7
    %issue_slots_16_out_uop_imm_packed = sv.wire sym @issue_slots_16_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_16_out_uop_imm_packed, %slots_16.io_out_uop_imm_packed : i20
    %issue_slots_16_out_uop_taken = sv.wire sym @issue_slots_16_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_taken, %slots_16.io_out_uop_taken : i1
    %issue_slots_16_out_uop_pc_lob = sv.wire sym @issue_slots_16_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_16_out_uop_pc_lob, %slots_16.io_out_uop_pc_lob : i6
    %issue_slots_16_out_uop_edge_inst = sv.wire sym @issue_slots_16_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_edge_inst, %slots_16.io_out_uop_edge_inst : i1
    %issue_slots_16_out_uop_ftq_idx = sv.wire sym @issue_slots_16_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_16_out_uop_ftq_idx, %slots_16.io_out_uop_ftq_idx : i6
    %issue_slots_16_out_uop_br_tag = sv.wire sym @issue_slots_16_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_16_out_uop_br_tag, %slots_16.io_out_uop_br_tag : i5
    %issue_slots_16_out_uop_br_mask = sv.wire sym @issue_slots_16_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_16_out_uop_br_mask, %slots_16.io_out_uop_br_mask : i20
    %issue_slots_16_out_uop_is_sfb = sv.wire sym @issue_slots_16_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_is_sfb, %slots_16.io_out_uop_is_sfb : i1
    %issue_slots_16_out_uop_is_jal = sv.wire sym @issue_slots_16_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_is_jal, %slots_16.io_out_uop_is_jal : i1
    %issue_slots_16_out_uop_is_jalr = sv.wire sym @issue_slots_16_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_is_jalr, %slots_16.io_out_uop_is_jalr : i1
    %issue_slots_16_out_uop_is_br = sv.wire sym @issue_slots_16_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_is_br, %slots_16.io_out_uop_is_br : i1
    %issue_slots_16_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_16_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_iw_p2_poisoned, %slots_16.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_16_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_16_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_iw_p1_poisoned, %slots_16.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_16_out_uop_iw_state = sv.wire sym @issue_slots_16_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_16_out_uop_iw_state, %slots_16.io_out_uop_iw_state : i2
    %issue_slots_16_out_uop_fu_code = sv.wire sym @issue_slots_16_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_16_out_uop_fu_code, %slots_16.io_out_uop_fu_code : i10
    %issue_slots_16_out_uop_is_rvc = sv.wire sym @issue_slots_16_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_16_out_uop_is_rvc, %slots_16.io_out_uop_is_rvc : i1
    %issue_slots_16_out_uop_uopc = sv.wire sym @issue_slots_16_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_16_out_uop_uopc, %slots_16.io_out_uop_uopc : i7
    %3174 = comb.icmp ne %1727, %c0_i4 {sv.namehint = "_issue_slots_12_clear"} : i4
    %issue_slots_12_clear = sv.wire sym @issue_slots_12_clear  : !hw.inout<i1>
    sv.assign %issue_slots_12_clear, %3174 : i1
    %3175 = comb.icmp eq %1743, %c1_i4 : i4
    %3176 = comb.and %3175, %slots_14.io_will_be_valid : i1
    %3177 = comb.icmp eq %1751, %c2_i4 : i4
    %3178 = comb.mux %3177, %slots_15.io_will_be_valid, %3176 : i1
    %3179 = comb.mux %3177, %slots_15.io_out_uop_fp_val, %slots_14.io_out_uop_fp_val : i1
    %3180 = comb.mux %3177, %slots_15.io_out_uop_lrs2_rtype, %slots_14.io_out_uop_lrs2_rtype : i2
    %3181 = comb.mux %3177, %slots_15.io_out_uop_lrs1_rtype, %slots_14.io_out_uop_lrs1_rtype : i2
    %3182 = comb.mux %3177, %slots_15.io_out_uop_dst_rtype, %slots_14.io_out_uop_dst_rtype : i2
    %3183 = comb.mux %3177, %slots_15.io_out_uop_ldst_val, %slots_14.io_out_uop_ldst_val : i1
    %3184 = comb.mux %3177, %slots_15.io_out_uop_uses_stq, %slots_14.io_out_uop_uses_stq : i1
    %3185 = comb.mux %3177, %slots_15.io_out_uop_uses_ldq, %slots_14.io_out_uop_uses_ldq : i1
    %3186 = comb.mux %3177, %slots_15.io_out_uop_is_amo, %slots_14.io_out_uop_is_amo : i1
    %3187 = comb.mux %3177, %slots_15.io_out_uop_is_fence, %slots_14.io_out_uop_is_fence : i1
    %3188 = comb.mux %3177, %slots_15.io_out_uop_mem_signed, %slots_14.io_out_uop_mem_signed : i1
    %3189 = comb.mux %3177, %slots_15.io_out_uop_mem_size, %slots_14.io_out_uop_mem_size : i2
    %3190 = comb.mux %3177, %slots_15.io_out_uop_mem_cmd, %slots_14.io_out_uop_mem_cmd : i5
    %3191 = comb.mux %3177, %slots_15.io_out_uop_bypassable, %slots_14.io_out_uop_bypassable : i1
    %3192 = comb.mux %3177, %slots_15.io_out_uop_ppred_busy, %slots_14.io_out_uop_ppred_busy : i1
    %3193 = comb.mux %3177, %slots_15.io_out_uop_prs3_busy, %slots_14.io_out_uop_prs3_busy : i1
    %3194 = comb.mux %3177, %slots_15.io_out_uop_prs2_busy, %slots_14.io_out_uop_prs2_busy : i1
    %3195 = comb.mux %3177, %slots_15.io_out_uop_prs1_busy, %slots_14.io_out_uop_prs1_busy : i1
    %3196 = comb.mux %3177, %slots_15.io_out_uop_prs3, %slots_14.io_out_uop_prs3 : i7
    %3197 = comb.mux %3177, %slots_15.io_out_uop_prs2, %slots_14.io_out_uop_prs2 : i7
    %3198 = comb.mux %3177, %slots_15.io_out_uop_prs1, %slots_14.io_out_uop_prs1 : i7
    %3199 = comb.mux %3177, %slots_15.io_out_uop_pdst, %slots_14.io_out_uop_pdst : i7
    %3200 = comb.mux %3177, %slots_15.io_out_uop_stq_idx, %slots_14.io_out_uop_stq_idx : i5
    %3201 = comb.mux %3177, %slots_15.io_out_uop_ldq_idx, %slots_14.io_out_uop_ldq_idx : i5
    %3202 = comb.mux %3177, %slots_15.io_out_uop_rob_idx, %slots_14.io_out_uop_rob_idx : i7
    %3203 = comb.mux %3177, %slots_15.io_out_uop_imm_packed, %slots_14.io_out_uop_imm_packed : i20
    %3204 = comb.mux %3177, %slots_15.io_out_uop_taken, %slots_14.io_out_uop_taken : i1
    %3205 = comb.mux %3177, %slots_15.io_out_uop_pc_lob, %slots_14.io_out_uop_pc_lob : i6
    %3206 = comb.mux %3177, %slots_15.io_out_uop_edge_inst, %slots_14.io_out_uop_edge_inst : i1
    %3207 = comb.mux %3177, %slots_15.io_out_uop_ftq_idx, %slots_14.io_out_uop_ftq_idx : i6
    %3208 = comb.mux %3177, %slots_15.io_out_uop_br_tag, %slots_14.io_out_uop_br_tag : i5
    %3209 = comb.mux %3177, %slots_15.io_out_uop_br_mask, %slots_14.io_out_uop_br_mask : i20
    %3210 = comb.mux %3177, %slots_15.io_out_uop_is_sfb, %slots_14.io_out_uop_is_sfb : i1
    %3211 = comb.mux %3177, %slots_15.io_out_uop_is_jal, %slots_14.io_out_uop_is_jal : i1
    %3212 = comb.mux %3177, %slots_15.io_out_uop_is_jalr, %slots_14.io_out_uop_is_jalr : i1
    %3213 = comb.mux %3177, %slots_15.io_out_uop_is_br, %slots_14.io_out_uop_is_br : i1
    %3214 = comb.mux %3177, %slots_15.io_out_uop_iw_p2_poisoned, %slots_14.io_out_uop_iw_p2_poisoned : i1
    %3215 = comb.mux %3177, %slots_15.io_out_uop_iw_p1_poisoned, %slots_14.io_out_uop_iw_p1_poisoned : i1
    %3216 = comb.mux %3177, %slots_15.io_out_uop_iw_state, %slots_14.io_out_uop_iw_state : i2
    %3217 = comb.mux %3177, %slots_15.io_out_uop_fu_code, %slots_14.io_out_uop_fu_code : i10
    %3218 = comb.mux %3177, %slots_15.io_out_uop_is_rvc, %slots_14.io_out_uop_is_rvc : i1
    %3219 = comb.mux %3177, %slots_15.io_out_uop_uopc, %slots_14.io_out_uop_uopc : i7
    %3220 = comb.icmp eq %1759, %c4_i4 : i4
    %3221 = comb.mux %3220, %slots_16.io_will_be_valid, %3178 : i1
    %3222 = comb.mux %3220, %slots_16.io_out_uop_fp_val, %3179 : i1
    %3223 = comb.mux %3220, %slots_16.io_out_uop_lrs2_rtype, %3180 : i2
    %3224 = comb.mux %3220, %slots_16.io_out_uop_lrs1_rtype, %3181 : i2
    %3225 = comb.mux %3220, %slots_16.io_out_uop_dst_rtype, %3182 : i2
    %3226 = comb.mux %3220, %slots_16.io_out_uop_ldst_val, %3183 : i1
    %3227 = comb.mux %3220, %slots_16.io_out_uop_uses_stq, %3184 : i1
    %3228 = comb.mux %3220, %slots_16.io_out_uop_uses_ldq, %3185 : i1
    %3229 = comb.mux %3220, %slots_16.io_out_uop_is_amo, %3186 : i1
    %3230 = comb.mux %3220, %slots_16.io_out_uop_is_fence, %3187 : i1
    %3231 = comb.mux %3220, %slots_16.io_out_uop_mem_signed, %3188 : i1
    %3232 = comb.mux %3220, %slots_16.io_out_uop_mem_size, %3189 : i2
    %3233 = comb.mux %3220, %slots_16.io_out_uop_mem_cmd, %3190 : i5
    %3234 = comb.mux %3220, %slots_16.io_out_uop_bypassable, %3191 : i1
    %3235 = comb.mux %3220, %slots_16.io_out_uop_ppred_busy, %3192 : i1
    %3236 = comb.mux %3220, %slots_16.io_out_uop_prs3_busy, %3193 : i1
    %3237 = comb.mux %3220, %slots_16.io_out_uop_prs2_busy, %3194 : i1
    %3238 = comb.mux %3220, %slots_16.io_out_uop_prs1_busy, %3195 : i1
    %3239 = comb.mux %3220, %slots_16.io_out_uop_prs3, %3196 : i7
    %3240 = comb.mux %3220, %slots_16.io_out_uop_prs2, %3197 : i7
    %3241 = comb.mux %3220, %slots_16.io_out_uop_prs1, %3198 : i7
    %3242 = comb.mux %3220, %slots_16.io_out_uop_pdst, %3199 : i7
    %3243 = comb.mux %3220, %slots_16.io_out_uop_stq_idx, %3200 : i5
    %3244 = comb.mux %3220, %slots_16.io_out_uop_ldq_idx, %3201 : i5
    %3245 = comb.mux %3220, %slots_16.io_out_uop_rob_idx, %3202 : i7
    %3246 = comb.mux %3220, %slots_16.io_out_uop_imm_packed, %3203 : i20
    %3247 = comb.mux %3220, %slots_16.io_out_uop_taken, %3204 : i1
    %3248 = comb.mux %3220, %slots_16.io_out_uop_pc_lob, %3205 : i6
    %3249 = comb.mux %3220, %slots_16.io_out_uop_edge_inst, %3206 : i1
    %3250 = comb.mux %3220, %slots_16.io_out_uop_ftq_idx, %3207 : i6
    %3251 = comb.mux %3220, %slots_16.io_out_uop_br_tag, %3208 : i5
    %3252 = comb.mux %3220, %slots_16.io_out_uop_br_mask, %3209 : i20
    %3253 = comb.mux %3220, %slots_16.io_out_uop_is_sfb, %3210 : i1
    %3254 = comb.mux %3220, %slots_16.io_out_uop_is_jal, %3211 : i1
    %3255 = comb.mux %3220, %slots_16.io_out_uop_is_jalr, %3212 : i1
    %3256 = comb.mux %3220, %slots_16.io_out_uop_is_br, %3213 : i1
    %3257 = comb.mux %3220, %slots_16.io_out_uop_iw_p2_poisoned, %3214 : i1
    %3258 = comb.mux %3220, %slots_16.io_out_uop_iw_p1_poisoned, %3215 : i1
    %3259 = comb.mux %3220, %slots_16.io_out_uop_iw_state, %3216 : i2
    %3260 = comb.mux %3220, %slots_16.io_out_uop_fu_code, %3217 : i10
    %3261 = comb.mux %3220, %slots_16.io_out_uop_is_rvc, %3218 : i1
    %3262 = comb.mux %3220, %slots_16.io_out_uop_uopc, %3219 : i7
    %3263 = comb.icmp eq %1767, %c-8_i4 : i4
    %issue_slots_17_will_be_valid = sv.wire sym @issue_slots_17_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_17_will_be_valid, %slots_17.io_will_be_valid : i1
    %3264 = comb.mux %3263, %slots_17.io_will_be_valid, %3221 {sv.namehint = "_issue_slots_13_in_uop_valid"} : i1
    %issue_slots_13_in_uop_valid = sv.wire sym @issue_slots_13_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_13_in_uop_valid, %3264 : i1
    %issue_slots_17_out_uop_fp_val = sv.wire sym @issue_slots_17_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_fp_val, %slots_17.io_out_uop_fp_val : i1
    %issue_slots_17_out_uop_lrs2_rtype = sv.wire sym @issue_slots_17_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_17_out_uop_lrs2_rtype, %slots_17.io_out_uop_lrs2_rtype : i2
    %issue_slots_17_out_uop_lrs1_rtype = sv.wire sym @issue_slots_17_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_17_out_uop_lrs1_rtype, %slots_17.io_out_uop_lrs1_rtype : i2
    %issue_slots_17_out_uop_dst_rtype = sv.wire sym @issue_slots_17_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_17_out_uop_dst_rtype, %slots_17.io_out_uop_dst_rtype : i2
    %issue_slots_17_out_uop_ldst_val = sv.wire sym @issue_slots_17_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_ldst_val, %slots_17.io_out_uop_ldst_val : i1
    %issue_slots_17_out_uop_uses_stq = sv.wire sym @issue_slots_17_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_uses_stq, %slots_17.io_out_uop_uses_stq : i1
    %issue_slots_17_out_uop_uses_ldq = sv.wire sym @issue_slots_17_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_uses_ldq, %slots_17.io_out_uop_uses_ldq : i1
    %issue_slots_17_out_uop_is_amo = sv.wire sym @issue_slots_17_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_is_amo, %slots_17.io_out_uop_is_amo : i1
    %issue_slots_17_out_uop_is_fence = sv.wire sym @issue_slots_17_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_is_fence, %slots_17.io_out_uop_is_fence : i1
    %issue_slots_17_out_uop_mem_signed = sv.wire sym @issue_slots_17_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_mem_signed, %slots_17.io_out_uop_mem_signed : i1
    %issue_slots_17_out_uop_mem_size = sv.wire sym @issue_slots_17_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_17_out_uop_mem_size, %slots_17.io_out_uop_mem_size : i2
    %issue_slots_17_out_uop_mem_cmd = sv.wire sym @issue_slots_17_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_17_out_uop_mem_cmd, %slots_17.io_out_uop_mem_cmd : i5
    %issue_slots_17_out_uop_bypassable = sv.wire sym @issue_slots_17_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_bypassable, %slots_17.io_out_uop_bypassable : i1
    %issue_slots_17_out_uop_ppred_busy = sv.wire sym @issue_slots_17_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_ppred_busy, %slots_17.io_out_uop_ppred_busy : i1
    %issue_slots_17_out_uop_prs3_busy = sv.wire sym @issue_slots_17_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_prs3_busy, %slots_17.io_out_uop_prs3_busy : i1
    %issue_slots_17_out_uop_prs2_busy = sv.wire sym @issue_slots_17_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_prs2_busy, %slots_17.io_out_uop_prs2_busy : i1
    %issue_slots_17_out_uop_prs1_busy = sv.wire sym @issue_slots_17_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_prs1_busy, %slots_17.io_out_uop_prs1_busy : i1
    %issue_slots_17_out_uop_prs3 = sv.wire sym @issue_slots_17_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_17_out_uop_prs3, %slots_17.io_out_uop_prs3 : i7
    %issue_slots_17_out_uop_prs2 = sv.wire sym @issue_slots_17_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_17_out_uop_prs2, %slots_17.io_out_uop_prs2 : i7
    %issue_slots_17_out_uop_prs1 = sv.wire sym @issue_slots_17_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_17_out_uop_prs1, %slots_17.io_out_uop_prs1 : i7
    %issue_slots_17_out_uop_pdst = sv.wire sym @issue_slots_17_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_17_out_uop_pdst, %slots_17.io_out_uop_pdst : i7
    %issue_slots_17_out_uop_stq_idx = sv.wire sym @issue_slots_17_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_17_out_uop_stq_idx, %slots_17.io_out_uop_stq_idx : i5
    %issue_slots_17_out_uop_ldq_idx = sv.wire sym @issue_slots_17_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_17_out_uop_ldq_idx, %slots_17.io_out_uop_ldq_idx : i5
    %issue_slots_17_out_uop_rob_idx = sv.wire sym @issue_slots_17_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_17_out_uop_rob_idx, %slots_17.io_out_uop_rob_idx : i7
    %issue_slots_17_out_uop_imm_packed = sv.wire sym @issue_slots_17_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_17_out_uop_imm_packed, %slots_17.io_out_uop_imm_packed : i20
    %issue_slots_17_out_uop_taken = sv.wire sym @issue_slots_17_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_taken, %slots_17.io_out_uop_taken : i1
    %issue_slots_17_out_uop_pc_lob = sv.wire sym @issue_slots_17_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_17_out_uop_pc_lob, %slots_17.io_out_uop_pc_lob : i6
    %issue_slots_17_out_uop_edge_inst = sv.wire sym @issue_slots_17_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_edge_inst, %slots_17.io_out_uop_edge_inst : i1
    %issue_slots_17_out_uop_ftq_idx = sv.wire sym @issue_slots_17_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_17_out_uop_ftq_idx, %slots_17.io_out_uop_ftq_idx : i6
    %issue_slots_17_out_uop_br_tag = sv.wire sym @issue_slots_17_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_17_out_uop_br_tag, %slots_17.io_out_uop_br_tag : i5
    %issue_slots_17_out_uop_br_mask = sv.wire sym @issue_slots_17_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_17_out_uop_br_mask, %slots_17.io_out_uop_br_mask : i20
    %issue_slots_17_out_uop_is_sfb = sv.wire sym @issue_slots_17_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_is_sfb, %slots_17.io_out_uop_is_sfb : i1
    %issue_slots_17_out_uop_is_jal = sv.wire sym @issue_slots_17_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_is_jal, %slots_17.io_out_uop_is_jal : i1
    %issue_slots_17_out_uop_is_jalr = sv.wire sym @issue_slots_17_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_is_jalr, %slots_17.io_out_uop_is_jalr : i1
    %issue_slots_17_out_uop_is_br = sv.wire sym @issue_slots_17_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_is_br, %slots_17.io_out_uop_is_br : i1
    %issue_slots_17_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_17_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_iw_p2_poisoned, %slots_17.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_17_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_17_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_iw_p1_poisoned, %slots_17.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_17_out_uop_iw_state = sv.wire sym @issue_slots_17_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_17_out_uop_iw_state, %slots_17.io_out_uop_iw_state : i2
    %issue_slots_17_out_uop_fu_code = sv.wire sym @issue_slots_17_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_17_out_uop_fu_code, %slots_17.io_out_uop_fu_code : i10
    %issue_slots_17_out_uop_is_rvc = sv.wire sym @issue_slots_17_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_17_out_uop_is_rvc, %slots_17.io_out_uop_is_rvc : i1
    %issue_slots_17_out_uop_uopc = sv.wire sym @issue_slots_17_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_17_out_uop_uopc, %slots_17.io_out_uop_uopc : i7
    %3265 = comb.icmp ne %1735, %c0_i4 {sv.namehint = "_issue_slots_13_clear"} : i4
    %issue_slots_13_clear = sv.wire sym @issue_slots_13_clear  : !hw.inout<i1>
    sv.assign %issue_slots_13_clear, %3265 : i1
    %3266 = comb.icmp eq %1751, %c1_i4 : i4
    %3267 = comb.and %3266, %slots_15.io_will_be_valid : i1
    %3268 = comb.icmp eq %1759, %c2_i4 : i4
    %3269 = comb.mux %3268, %slots_16.io_will_be_valid, %3267 : i1
    %3270 = comb.mux %3268, %slots_16.io_out_uop_fp_val, %slots_15.io_out_uop_fp_val : i1
    %3271 = comb.mux %3268, %slots_16.io_out_uop_lrs2_rtype, %slots_15.io_out_uop_lrs2_rtype : i2
    %3272 = comb.mux %3268, %slots_16.io_out_uop_lrs1_rtype, %slots_15.io_out_uop_lrs1_rtype : i2
    %3273 = comb.mux %3268, %slots_16.io_out_uop_dst_rtype, %slots_15.io_out_uop_dst_rtype : i2
    %3274 = comb.mux %3268, %slots_16.io_out_uop_ldst_val, %slots_15.io_out_uop_ldst_val : i1
    %3275 = comb.mux %3268, %slots_16.io_out_uop_uses_stq, %slots_15.io_out_uop_uses_stq : i1
    %3276 = comb.mux %3268, %slots_16.io_out_uop_uses_ldq, %slots_15.io_out_uop_uses_ldq : i1
    %3277 = comb.mux %3268, %slots_16.io_out_uop_is_amo, %slots_15.io_out_uop_is_amo : i1
    %3278 = comb.mux %3268, %slots_16.io_out_uop_is_fence, %slots_15.io_out_uop_is_fence : i1
    %3279 = comb.mux %3268, %slots_16.io_out_uop_mem_signed, %slots_15.io_out_uop_mem_signed : i1
    %3280 = comb.mux %3268, %slots_16.io_out_uop_mem_size, %slots_15.io_out_uop_mem_size : i2
    %3281 = comb.mux %3268, %slots_16.io_out_uop_mem_cmd, %slots_15.io_out_uop_mem_cmd : i5
    %3282 = comb.mux %3268, %slots_16.io_out_uop_bypassable, %slots_15.io_out_uop_bypassable : i1
    %3283 = comb.mux %3268, %slots_16.io_out_uop_ppred_busy, %slots_15.io_out_uop_ppred_busy : i1
    %3284 = comb.mux %3268, %slots_16.io_out_uop_prs3_busy, %slots_15.io_out_uop_prs3_busy : i1
    %3285 = comb.mux %3268, %slots_16.io_out_uop_prs2_busy, %slots_15.io_out_uop_prs2_busy : i1
    %3286 = comb.mux %3268, %slots_16.io_out_uop_prs1_busy, %slots_15.io_out_uop_prs1_busy : i1
    %3287 = comb.mux %3268, %slots_16.io_out_uop_prs3, %slots_15.io_out_uop_prs3 : i7
    %3288 = comb.mux %3268, %slots_16.io_out_uop_prs2, %slots_15.io_out_uop_prs2 : i7
    %3289 = comb.mux %3268, %slots_16.io_out_uop_prs1, %slots_15.io_out_uop_prs1 : i7
    %3290 = comb.mux %3268, %slots_16.io_out_uop_pdst, %slots_15.io_out_uop_pdst : i7
    %3291 = comb.mux %3268, %slots_16.io_out_uop_stq_idx, %slots_15.io_out_uop_stq_idx : i5
    %3292 = comb.mux %3268, %slots_16.io_out_uop_ldq_idx, %slots_15.io_out_uop_ldq_idx : i5
    %3293 = comb.mux %3268, %slots_16.io_out_uop_rob_idx, %slots_15.io_out_uop_rob_idx : i7
    %3294 = comb.mux %3268, %slots_16.io_out_uop_imm_packed, %slots_15.io_out_uop_imm_packed : i20
    %3295 = comb.mux %3268, %slots_16.io_out_uop_taken, %slots_15.io_out_uop_taken : i1
    %3296 = comb.mux %3268, %slots_16.io_out_uop_pc_lob, %slots_15.io_out_uop_pc_lob : i6
    %3297 = comb.mux %3268, %slots_16.io_out_uop_edge_inst, %slots_15.io_out_uop_edge_inst : i1
    %3298 = comb.mux %3268, %slots_16.io_out_uop_ftq_idx, %slots_15.io_out_uop_ftq_idx : i6
    %3299 = comb.mux %3268, %slots_16.io_out_uop_br_tag, %slots_15.io_out_uop_br_tag : i5
    %3300 = comb.mux %3268, %slots_16.io_out_uop_br_mask, %slots_15.io_out_uop_br_mask : i20
    %3301 = comb.mux %3268, %slots_16.io_out_uop_is_sfb, %slots_15.io_out_uop_is_sfb : i1
    %3302 = comb.mux %3268, %slots_16.io_out_uop_is_jal, %slots_15.io_out_uop_is_jal : i1
    %3303 = comb.mux %3268, %slots_16.io_out_uop_is_jalr, %slots_15.io_out_uop_is_jalr : i1
    %3304 = comb.mux %3268, %slots_16.io_out_uop_is_br, %slots_15.io_out_uop_is_br : i1
    %3305 = comb.mux %3268, %slots_16.io_out_uop_iw_p2_poisoned, %slots_15.io_out_uop_iw_p2_poisoned : i1
    %3306 = comb.mux %3268, %slots_16.io_out_uop_iw_p1_poisoned, %slots_15.io_out_uop_iw_p1_poisoned : i1
    %3307 = comb.mux %3268, %slots_16.io_out_uop_iw_state, %slots_15.io_out_uop_iw_state : i2
    %3308 = comb.mux %3268, %slots_16.io_out_uop_fu_code, %slots_15.io_out_uop_fu_code : i10
    %3309 = comb.mux %3268, %slots_16.io_out_uop_is_rvc, %slots_15.io_out_uop_is_rvc : i1
    %3310 = comb.mux %3268, %slots_16.io_out_uop_uopc, %slots_15.io_out_uop_uopc : i7
    %3311 = comb.icmp eq %1767, %c4_i4 : i4
    %3312 = comb.mux %3311, %slots_17.io_will_be_valid, %3269 : i1
    %3313 = comb.mux %3311, %slots_17.io_out_uop_fp_val, %3270 : i1
    %3314 = comb.mux %3311, %slots_17.io_out_uop_lrs2_rtype, %3271 : i2
    %3315 = comb.mux %3311, %slots_17.io_out_uop_lrs1_rtype, %3272 : i2
    %3316 = comb.mux %3311, %slots_17.io_out_uop_dst_rtype, %3273 : i2
    %3317 = comb.mux %3311, %slots_17.io_out_uop_ldst_val, %3274 : i1
    %3318 = comb.mux %3311, %slots_17.io_out_uop_uses_stq, %3275 : i1
    %3319 = comb.mux %3311, %slots_17.io_out_uop_uses_ldq, %3276 : i1
    %3320 = comb.mux %3311, %slots_17.io_out_uop_is_amo, %3277 : i1
    %3321 = comb.mux %3311, %slots_17.io_out_uop_is_fence, %3278 : i1
    %3322 = comb.mux %3311, %slots_17.io_out_uop_mem_signed, %3279 : i1
    %3323 = comb.mux %3311, %slots_17.io_out_uop_mem_size, %3280 : i2
    %3324 = comb.mux %3311, %slots_17.io_out_uop_mem_cmd, %3281 : i5
    %3325 = comb.mux %3311, %slots_17.io_out_uop_bypassable, %3282 : i1
    %3326 = comb.mux %3311, %slots_17.io_out_uop_ppred_busy, %3283 : i1
    %3327 = comb.mux %3311, %slots_17.io_out_uop_prs3_busy, %3284 : i1
    %3328 = comb.mux %3311, %slots_17.io_out_uop_prs2_busy, %3285 : i1
    %3329 = comb.mux %3311, %slots_17.io_out_uop_prs1_busy, %3286 : i1
    %3330 = comb.mux %3311, %slots_17.io_out_uop_prs3, %3287 : i7
    %3331 = comb.mux %3311, %slots_17.io_out_uop_prs2, %3288 : i7
    %3332 = comb.mux %3311, %slots_17.io_out_uop_prs1, %3289 : i7
    %3333 = comb.mux %3311, %slots_17.io_out_uop_pdst, %3290 : i7
    %3334 = comb.mux %3311, %slots_17.io_out_uop_stq_idx, %3291 : i5
    %3335 = comb.mux %3311, %slots_17.io_out_uop_ldq_idx, %3292 : i5
    %3336 = comb.mux %3311, %slots_17.io_out_uop_rob_idx, %3293 : i7
    %3337 = comb.mux %3311, %slots_17.io_out_uop_imm_packed, %3294 : i20
    %3338 = comb.mux %3311, %slots_17.io_out_uop_taken, %3295 : i1
    %3339 = comb.mux %3311, %slots_17.io_out_uop_pc_lob, %3296 : i6
    %3340 = comb.mux %3311, %slots_17.io_out_uop_edge_inst, %3297 : i1
    %3341 = comb.mux %3311, %slots_17.io_out_uop_ftq_idx, %3298 : i6
    %3342 = comb.mux %3311, %slots_17.io_out_uop_br_tag, %3299 : i5
    %3343 = comb.mux %3311, %slots_17.io_out_uop_br_mask, %3300 : i20
    %3344 = comb.mux %3311, %slots_17.io_out_uop_is_sfb, %3301 : i1
    %3345 = comb.mux %3311, %slots_17.io_out_uop_is_jal, %3302 : i1
    %3346 = comb.mux %3311, %slots_17.io_out_uop_is_jalr, %3303 : i1
    %3347 = comb.mux %3311, %slots_17.io_out_uop_is_br, %3304 : i1
    %3348 = comb.mux %3311, %slots_17.io_out_uop_iw_p2_poisoned, %3305 : i1
    %3349 = comb.mux %3311, %slots_17.io_out_uop_iw_p1_poisoned, %3306 : i1
    %3350 = comb.mux %3311, %slots_17.io_out_uop_iw_state, %3307 : i2
    %3351 = comb.mux %3311, %slots_17.io_out_uop_fu_code, %3308 : i10
    %3352 = comb.mux %3311, %slots_17.io_out_uop_is_rvc, %3309 : i1
    %3353 = comb.mux %3311, %slots_17.io_out_uop_uopc, %3310 : i7
    %3354 = comb.icmp eq %1775, %c-8_i4 : i4
    %issue_slots_18_will_be_valid = sv.wire sym @issue_slots_18_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_18_will_be_valid, %slots_18.io_will_be_valid : i1
    %3355 = comb.mux %3354, %slots_18.io_will_be_valid, %3312 {sv.namehint = "_issue_slots_14_in_uop_valid"} : i1
    %issue_slots_14_in_uop_valid = sv.wire sym @issue_slots_14_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_14_in_uop_valid, %3355 : i1
    %issue_slots_18_out_uop_fp_val = sv.wire sym @issue_slots_18_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_fp_val, %slots_18.io_out_uop_fp_val : i1
    %issue_slots_18_out_uop_lrs2_rtype = sv.wire sym @issue_slots_18_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_18_out_uop_lrs2_rtype, %slots_18.io_out_uop_lrs2_rtype : i2
    %issue_slots_18_out_uop_lrs1_rtype = sv.wire sym @issue_slots_18_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_18_out_uop_lrs1_rtype, %slots_18.io_out_uop_lrs1_rtype : i2
    %issue_slots_18_out_uop_dst_rtype = sv.wire sym @issue_slots_18_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_18_out_uop_dst_rtype, %slots_18.io_out_uop_dst_rtype : i2
    %issue_slots_18_out_uop_ldst_val = sv.wire sym @issue_slots_18_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_ldst_val, %slots_18.io_out_uop_ldst_val : i1
    %issue_slots_18_out_uop_uses_stq = sv.wire sym @issue_slots_18_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_uses_stq, %slots_18.io_out_uop_uses_stq : i1
    %issue_slots_18_out_uop_uses_ldq = sv.wire sym @issue_slots_18_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_uses_ldq, %slots_18.io_out_uop_uses_ldq : i1
    %issue_slots_18_out_uop_is_amo = sv.wire sym @issue_slots_18_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_is_amo, %slots_18.io_out_uop_is_amo : i1
    %issue_slots_18_out_uop_is_fence = sv.wire sym @issue_slots_18_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_is_fence, %slots_18.io_out_uop_is_fence : i1
    %issue_slots_18_out_uop_mem_signed = sv.wire sym @issue_slots_18_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_mem_signed, %slots_18.io_out_uop_mem_signed : i1
    %issue_slots_18_out_uop_mem_size = sv.wire sym @issue_slots_18_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_18_out_uop_mem_size, %slots_18.io_out_uop_mem_size : i2
    %issue_slots_18_out_uop_mem_cmd = sv.wire sym @issue_slots_18_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_18_out_uop_mem_cmd, %slots_18.io_out_uop_mem_cmd : i5
    %issue_slots_18_out_uop_bypassable = sv.wire sym @issue_slots_18_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_bypassable, %slots_18.io_out_uop_bypassable : i1
    %issue_slots_18_out_uop_ppred_busy = sv.wire sym @issue_slots_18_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_ppred_busy, %slots_18.io_out_uop_ppred_busy : i1
    %issue_slots_18_out_uop_prs3_busy = sv.wire sym @issue_slots_18_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_prs3_busy, %slots_18.io_out_uop_prs3_busy : i1
    %issue_slots_18_out_uop_prs2_busy = sv.wire sym @issue_slots_18_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_prs2_busy, %slots_18.io_out_uop_prs2_busy : i1
    %issue_slots_18_out_uop_prs1_busy = sv.wire sym @issue_slots_18_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_prs1_busy, %slots_18.io_out_uop_prs1_busy : i1
    %issue_slots_18_out_uop_prs3 = sv.wire sym @issue_slots_18_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_18_out_uop_prs3, %slots_18.io_out_uop_prs3 : i7
    %issue_slots_18_out_uop_prs2 = sv.wire sym @issue_slots_18_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_18_out_uop_prs2, %slots_18.io_out_uop_prs2 : i7
    %issue_slots_18_out_uop_prs1 = sv.wire sym @issue_slots_18_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_18_out_uop_prs1, %slots_18.io_out_uop_prs1 : i7
    %issue_slots_18_out_uop_pdst = sv.wire sym @issue_slots_18_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_18_out_uop_pdst, %slots_18.io_out_uop_pdst : i7
    %issue_slots_18_out_uop_stq_idx = sv.wire sym @issue_slots_18_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_18_out_uop_stq_idx, %slots_18.io_out_uop_stq_idx : i5
    %issue_slots_18_out_uop_ldq_idx = sv.wire sym @issue_slots_18_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_18_out_uop_ldq_idx, %slots_18.io_out_uop_ldq_idx : i5
    %issue_slots_18_out_uop_rob_idx = sv.wire sym @issue_slots_18_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_18_out_uop_rob_idx, %slots_18.io_out_uop_rob_idx : i7
    %issue_slots_18_out_uop_imm_packed = sv.wire sym @issue_slots_18_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_18_out_uop_imm_packed, %slots_18.io_out_uop_imm_packed : i20
    %issue_slots_18_out_uop_taken = sv.wire sym @issue_slots_18_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_taken, %slots_18.io_out_uop_taken : i1
    %issue_slots_18_out_uop_pc_lob = sv.wire sym @issue_slots_18_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_18_out_uop_pc_lob, %slots_18.io_out_uop_pc_lob : i6
    %issue_slots_18_out_uop_edge_inst = sv.wire sym @issue_slots_18_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_edge_inst, %slots_18.io_out_uop_edge_inst : i1
    %issue_slots_18_out_uop_ftq_idx = sv.wire sym @issue_slots_18_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_18_out_uop_ftq_idx, %slots_18.io_out_uop_ftq_idx : i6
    %issue_slots_18_out_uop_br_tag = sv.wire sym @issue_slots_18_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_18_out_uop_br_tag, %slots_18.io_out_uop_br_tag : i5
    %issue_slots_18_out_uop_br_mask = sv.wire sym @issue_slots_18_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_18_out_uop_br_mask, %slots_18.io_out_uop_br_mask : i20
    %issue_slots_18_out_uop_is_sfb = sv.wire sym @issue_slots_18_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_is_sfb, %slots_18.io_out_uop_is_sfb : i1
    %issue_slots_18_out_uop_is_jal = sv.wire sym @issue_slots_18_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_is_jal, %slots_18.io_out_uop_is_jal : i1
    %issue_slots_18_out_uop_is_jalr = sv.wire sym @issue_slots_18_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_is_jalr, %slots_18.io_out_uop_is_jalr : i1
    %issue_slots_18_out_uop_is_br = sv.wire sym @issue_slots_18_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_is_br, %slots_18.io_out_uop_is_br : i1
    %issue_slots_18_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_18_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_iw_p2_poisoned, %slots_18.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_18_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_18_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_iw_p1_poisoned, %slots_18.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_18_out_uop_iw_state = sv.wire sym @issue_slots_18_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_18_out_uop_iw_state, %slots_18.io_out_uop_iw_state : i2
    %issue_slots_18_out_uop_fu_code = sv.wire sym @issue_slots_18_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_18_out_uop_fu_code, %slots_18.io_out_uop_fu_code : i10
    %issue_slots_18_out_uop_is_rvc = sv.wire sym @issue_slots_18_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_18_out_uop_is_rvc, %slots_18.io_out_uop_is_rvc : i1
    %issue_slots_18_out_uop_uopc = sv.wire sym @issue_slots_18_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_18_out_uop_uopc, %slots_18.io_out_uop_uopc : i7
    %3356 = comb.icmp ne %1743, %c0_i4 {sv.namehint = "_issue_slots_14_clear"} : i4
    %issue_slots_14_clear = sv.wire sym @issue_slots_14_clear  : !hw.inout<i1>
    sv.assign %issue_slots_14_clear, %3356 : i1
    %3357 = comb.icmp eq %1759, %c1_i4 : i4
    %3358 = comb.and %3357, %slots_16.io_will_be_valid : i1
    %3359 = comb.icmp eq %1767, %c2_i4 : i4
    %3360 = comb.mux %3359, %slots_17.io_will_be_valid, %3358 : i1
    %3361 = comb.mux %3359, %slots_17.io_out_uop_fp_val, %slots_16.io_out_uop_fp_val : i1
    %3362 = comb.mux %3359, %slots_17.io_out_uop_lrs2_rtype, %slots_16.io_out_uop_lrs2_rtype : i2
    %3363 = comb.mux %3359, %slots_17.io_out_uop_lrs1_rtype, %slots_16.io_out_uop_lrs1_rtype : i2
    %3364 = comb.mux %3359, %slots_17.io_out_uop_dst_rtype, %slots_16.io_out_uop_dst_rtype : i2
    %3365 = comb.mux %3359, %slots_17.io_out_uop_ldst_val, %slots_16.io_out_uop_ldst_val : i1
    %3366 = comb.mux %3359, %slots_17.io_out_uop_uses_stq, %slots_16.io_out_uop_uses_stq : i1
    %3367 = comb.mux %3359, %slots_17.io_out_uop_uses_ldq, %slots_16.io_out_uop_uses_ldq : i1
    %3368 = comb.mux %3359, %slots_17.io_out_uop_is_amo, %slots_16.io_out_uop_is_amo : i1
    %3369 = comb.mux %3359, %slots_17.io_out_uop_is_fence, %slots_16.io_out_uop_is_fence : i1
    %3370 = comb.mux %3359, %slots_17.io_out_uop_mem_signed, %slots_16.io_out_uop_mem_signed : i1
    %3371 = comb.mux %3359, %slots_17.io_out_uop_mem_size, %slots_16.io_out_uop_mem_size : i2
    %3372 = comb.mux %3359, %slots_17.io_out_uop_mem_cmd, %slots_16.io_out_uop_mem_cmd : i5
    %3373 = comb.mux %3359, %slots_17.io_out_uop_bypassable, %slots_16.io_out_uop_bypassable : i1
    %3374 = comb.mux %3359, %slots_17.io_out_uop_ppred_busy, %slots_16.io_out_uop_ppred_busy : i1
    %3375 = comb.mux %3359, %slots_17.io_out_uop_prs3_busy, %slots_16.io_out_uop_prs3_busy : i1
    %3376 = comb.mux %3359, %slots_17.io_out_uop_prs2_busy, %slots_16.io_out_uop_prs2_busy : i1
    %3377 = comb.mux %3359, %slots_17.io_out_uop_prs1_busy, %slots_16.io_out_uop_prs1_busy : i1
    %3378 = comb.mux %3359, %slots_17.io_out_uop_prs3, %slots_16.io_out_uop_prs3 : i7
    %3379 = comb.mux %3359, %slots_17.io_out_uop_prs2, %slots_16.io_out_uop_prs2 : i7
    %3380 = comb.mux %3359, %slots_17.io_out_uop_prs1, %slots_16.io_out_uop_prs1 : i7
    %3381 = comb.mux %3359, %slots_17.io_out_uop_pdst, %slots_16.io_out_uop_pdst : i7
    %3382 = comb.mux %3359, %slots_17.io_out_uop_stq_idx, %slots_16.io_out_uop_stq_idx : i5
    %3383 = comb.mux %3359, %slots_17.io_out_uop_ldq_idx, %slots_16.io_out_uop_ldq_idx : i5
    %3384 = comb.mux %3359, %slots_17.io_out_uop_rob_idx, %slots_16.io_out_uop_rob_idx : i7
    %3385 = comb.mux %3359, %slots_17.io_out_uop_imm_packed, %slots_16.io_out_uop_imm_packed : i20
    %3386 = comb.mux %3359, %slots_17.io_out_uop_taken, %slots_16.io_out_uop_taken : i1
    %3387 = comb.mux %3359, %slots_17.io_out_uop_pc_lob, %slots_16.io_out_uop_pc_lob : i6
    %3388 = comb.mux %3359, %slots_17.io_out_uop_edge_inst, %slots_16.io_out_uop_edge_inst : i1
    %3389 = comb.mux %3359, %slots_17.io_out_uop_ftq_idx, %slots_16.io_out_uop_ftq_idx : i6
    %3390 = comb.mux %3359, %slots_17.io_out_uop_br_tag, %slots_16.io_out_uop_br_tag : i5
    %3391 = comb.mux %3359, %slots_17.io_out_uop_br_mask, %slots_16.io_out_uop_br_mask : i20
    %3392 = comb.mux %3359, %slots_17.io_out_uop_is_sfb, %slots_16.io_out_uop_is_sfb : i1
    %3393 = comb.mux %3359, %slots_17.io_out_uop_is_jal, %slots_16.io_out_uop_is_jal : i1
    %3394 = comb.mux %3359, %slots_17.io_out_uop_is_jalr, %slots_16.io_out_uop_is_jalr : i1
    %3395 = comb.mux %3359, %slots_17.io_out_uop_is_br, %slots_16.io_out_uop_is_br : i1
    %3396 = comb.mux %3359, %slots_17.io_out_uop_iw_p2_poisoned, %slots_16.io_out_uop_iw_p2_poisoned : i1
    %3397 = comb.mux %3359, %slots_17.io_out_uop_iw_p1_poisoned, %slots_16.io_out_uop_iw_p1_poisoned : i1
    %3398 = comb.mux %3359, %slots_17.io_out_uop_iw_state, %slots_16.io_out_uop_iw_state : i2
    %3399 = comb.mux %3359, %slots_17.io_out_uop_fu_code, %slots_16.io_out_uop_fu_code : i10
    %3400 = comb.mux %3359, %slots_17.io_out_uop_is_rvc, %slots_16.io_out_uop_is_rvc : i1
    %3401 = comb.mux %3359, %slots_17.io_out_uop_uopc, %slots_16.io_out_uop_uopc : i7
    %3402 = comb.icmp eq %1775, %c4_i4 : i4
    %3403 = comb.mux %3402, %slots_18.io_will_be_valid, %3360 : i1
    %3404 = comb.mux %3402, %slots_18.io_out_uop_fp_val, %3361 : i1
    %3405 = comb.mux %3402, %slots_18.io_out_uop_lrs2_rtype, %3362 : i2
    %3406 = comb.mux %3402, %slots_18.io_out_uop_lrs1_rtype, %3363 : i2
    %3407 = comb.mux %3402, %slots_18.io_out_uop_dst_rtype, %3364 : i2
    %3408 = comb.mux %3402, %slots_18.io_out_uop_ldst_val, %3365 : i1
    %3409 = comb.mux %3402, %slots_18.io_out_uop_uses_stq, %3366 : i1
    %3410 = comb.mux %3402, %slots_18.io_out_uop_uses_ldq, %3367 : i1
    %3411 = comb.mux %3402, %slots_18.io_out_uop_is_amo, %3368 : i1
    %3412 = comb.mux %3402, %slots_18.io_out_uop_is_fence, %3369 : i1
    %3413 = comb.mux %3402, %slots_18.io_out_uop_mem_signed, %3370 : i1
    %3414 = comb.mux %3402, %slots_18.io_out_uop_mem_size, %3371 : i2
    %3415 = comb.mux %3402, %slots_18.io_out_uop_mem_cmd, %3372 : i5
    %3416 = comb.mux %3402, %slots_18.io_out_uop_bypassable, %3373 : i1
    %3417 = comb.mux %3402, %slots_18.io_out_uop_ppred_busy, %3374 : i1
    %3418 = comb.mux %3402, %slots_18.io_out_uop_prs3_busy, %3375 : i1
    %3419 = comb.mux %3402, %slots_18.io_out_uop_prs2_busy, %3376 : i1
    %3420 = comb.mux %3402, %slots_18.io_out_uop_prs1_busy, %3377 : i1
    %3421 = comb.mux %3402, %slots_18.io_out_uop_prs3, %3378 : i7
    %3422 = comb.mux %3402, %slots_18.io_out_uop_prs2, %3379 : i7
    %3423 = comb.mux %3402, %slots_18.io_out_uop_prs1, %3380 : i7
    %3424 = comb.mux %3402, %slots_18.io_out_uop_pdst, %3381 : i7
    %3425 = comb.mux %3402, %slots_18.io_out_uop_stq_idx, %3382 : i5
    %3426 = comb.mux %3402, %slots_18.io_out_uop_ldq_idx, %3383 : i5
    %3427 = comb.mux %3402, %slots_18.io_out_uop_rob_idx, %3384 : i7
    %3428 = comb.mux %3402, %slots_18.io_out_uop_imm_packed, %3385 : i20
    %3429 = comb.mux %3402, %slots_18.io_out_uop_taken, %3386 : i1
    %3430 = comb.mux %3402, %slots_18.io_out_uop_pc_lob, %3387 : i6
    %3431 = comb.mux %3402, %slots_18.io_out_uop_edge_inst, %3388 : i1
    %3432 = comb.mux %3402, %slots_18.io_out_uop_ftq_idx, %3389 : i6
    %3433 = comb.mux %3402, %slots_18.io_out_uop_br_tag, %3390 : i5
    %3434 = comb.mux %3402, %slots_18.io_out_uop_br_mask, %3391 : i20
    %3435 = comb.mux %3402, %slots_18.io_out_uop_is_sfb, %3392 : i1
    %3436 = comb.mux %3402, %slots_18.io_out_uop_is_jal, %3393 : i1
    %3437 = comb.mux %3402, %slots_18.io_out_uop_is_jalr, %3394 : i1
    %3438 = comb.mux %3402, %slots_18.io_out_uop_is_br, %3395 : i1
    %3439 = comb.mux %3402, %slots_18.io_out_uop_iw_p2_poisoned, %3396 : i1
    %3440 = comb.mux %3402, %slots_18.io_out_uop_iw_p1_poisoned, %3397 : i1
    %3441 = comb.mux %3402, %slots_18.io_out_uop_iw_state, %3398 : i2
    %3442 = comb.mux %3402, %slots_18.io_out_uop_fu_code, %3399 : i10
    %3443 = comb.mux %3402, %slots_18.io_out_uop_is_rvc, %3400 : i1
    %3444 = comb.mux %3402, %slots_18.io_out_uop_uopc, %3401 : i7
    %3445 = comb.icmp eq %1783, %c-8_i4 : i4
    %issue_slots_19_will_be_valid = sv.wire sym @issue_slots_19_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_19_will_be_valid, %slots_19.io_will_be_valid : i1
    %3446 = comb.mux %3445, %slots_19.io_will_be_valid, %3403 {sv.namehint = "_issue_slots_15_in_uop_valid"} : i1
    %issue_slots_15_in_uop_valid = sv.wire sym @issue_slots_15_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_15_in_uop_valid, %3446 : i1
    %issue_slots_19_out_uop_fp_val = sv.wire sym @issue_slots_19_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_fp_val, %slots_19.io_out_uop_fp_val : i1
    %issue_slots_19_out_uop_lrs2_rtype = sv.wire sym @issue_slots_19_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_19_out_uop_lrs2_rtype, %slots_19.io_out_uop_lrs2_rtype : i2
    %issue_slots_19_out_uop_lrs1_rtype = sv.wire sym @issue_slots_19_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_19_out_uop_lrs1_rtype, %slots_19.io_out_uop_lrs1_rtype : i2
    %issue_slots_19_out_uop_dst_rtype = sv.wire sym @issue_slots_19_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_19_out_uop_dst_rtype, %slots_19.io_out_uop_dst_rtype : i2
    %issue_slots_19_out_uop_ldst_val = sv.wire sym @issue_slots_19_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_ldst_val, %slots_19.io_out_uop_ldst_val : i1
    %issue_slots_19_out_uop_uses_stq = sv.wire sym @issue_slots_19_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_uses_stq, %slots_19.io_out_uop_uses_stq : i1
    %issue_slots_19_out_uop_uses_ldq = sv.wire sym @issue_slots_19_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_uses_ldq, %slots_19.io_out_uop_uses_ldq : i1
    %issue_slots_19_out_uop_is_amo = sv.wire sym @issue_slots_19_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_is_amo, %slots_19.io_out_uop_is_amo : i1
    %issue_slots_19_out_uop_is_fence = sv.wire sym @issue_slots_19_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_is_fence, %slots_19.io_out_uop_is_fence : i1
    %issue_slots_19_out_uop_mem_signed = sv.wire sym @issue_slots_19_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_mem_signed, %slots_19.io_out_uop_mem_signed : i1
    %issue_slots_19_out_uop_mem_size = sv.wire sym @issue_slots_19_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_19_out_uop_mem_size, %slots_19.io_out_uop_mem_size : i2
    %issue_slots_19_out_uop_mem_cmd = sv.wire sym @issue_slots_19_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_19_out_uop_mem_cmd, %slots_19.io_out_uop_mem_cmd : i5
    %issue_slots_19_out_uop_bypassable = sv.wire sym @issue_slots_19_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_bypassable, %slots_19.io_out_uop_bypassable : i1
    %issue_slots_19_out_uop_ppred_busy = sv.wire sym @issue_slots_19_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_ppred_busy, %slots_19.io_out_uop_ppred_busy : i1
    %issue_slots_19_out_uop_prs3_busy = sv.wire sym @issue_slots_19_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_prs3_busy, %slots_19.io_out_uop_prs3_busy : i1
    %issue_slots_19_out_uop_prs2_busy = sv.wire sym @issue_slots_19_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_prs2_busy, %slots_19.io_out_uop_prs2_busy : i1
    %issue_slots_19_out_uop_prs1_busy = sv.wire sym @issue_slots_19_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_prs1_busy, %slots_19.io_out_uop_prs1_busy : i1
    %issue_slots_19_out_uop_prs3 = sv.wire sym @issue_slots_19_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_19_out_uop_prs3, %slots_19.io_out_uop_prs3 : i7
    %issue_slots_19_out_uop_prs2 = sv.wire sym @issue_slots_19_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_19_out_uop_prs2, %slots_19.io_out_uop_prs2 : i7
    %issue_slots_19_out_uop_prs1 = sv.wire sym @issue_slots_19_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_19_out_uop_prs1, %slots_19.io_out_uop_prs1 : i7
    %issue_slots_19_out_uop_pdst = sv.wire sym @issue_slots_19_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_19_out_uop_pdst, %slots_19.io_out_uop_pdst : i7
    %issue_slots_19_out_uop_stq_idx = sv.wire sym @issue_slots_19_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_19_out_uop_stq_idx, %slots_19.io_out_uop_stq_idx : i5
    %issue_slots_19_out_uop_ldq_idx = sv.wire sym @issue_slots_19_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_19_out_uop_ldq_idx, %slots_19.io_out_uop_ldq_idx : i5
    %issue_slots_19_out_uop_rob_idx = sv.wire sym @issue_slots_19_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_19_out_uop_rob_idx, %slots_19.io_out_uop_rob_idx : i7
    %issue_slots_19_out_uop_imm_packed = sv.wire sym @issue_slots_19_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_19_out_uop_imm_packed, %slots_19.io_out_uop_imm_packed : i20
    %issue_slots_19_out_uop_taken = sv.wire sym @issue_slots_19_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_taken, %slots_19.io_out_uop_taken : i1
    %issue_slots_19_out_uop_pc_lob = sv.wire sym @issue_slots_19_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_19_out_uop_pc_lob, %slots_19.io_out_uop_pc_lob : i6
    %issue_slots_19_out_uop_edge_inst = sv.wire sym @issue_slots_19_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_edge_inst, %slots_19.io_out_uop_edge_inst : i1
    %issue_slots_19_out_uop_ftq_idx = sv.wire sym @issue_slots_19_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_19_out_uop_ftq_idx, %slots_19.io_out_uop_ftq_idx : i6
    %issue_slots_19_out_uop_br_tag = sv.wire sym @issue_slots_19_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_19_out_uop_br_tag, %slots_19.io_out_uop_br_tag : i5
    %issue_slots_19_out_uop_br_mask = sv.wire sym @issue_slots_19_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_19_out_uop_br_mask, %slots_19.io_out_uop_br_mask : i20
    %issue_slots_19_out_uop_is_sfb = sv.wire sym @issue_slots_19_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_is_sfb, %slots_19.io_out_uop_is_sfb : i1
    %issue_slots_19_out_uop_is_jal = sv.wire sym @issue_slots_19_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_is_jal, %slots_19.io_out_uop_is_jal : i1
    %issue_slots_19_out_uop_is_jalr = sv.wire sym @issue_slots_19_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_is_jalr, %slots_19.io_out_uop_is_jalr : i1
    %issue_slots_19_out_uop_is_br = sv.wire sym @issue_slots_19_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_is_br, %slots_19.io_out_uop_is_br : i1
    %issue_slots_19_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_19_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_iw_p2_poisoned, %slots_19.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_19_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_19_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_iw_p1_poisoned, %slots_19.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_19_out_uop_iw_state = sv.wire sym @issue_slots_19_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_19_out_uop_iw_state, %slots_19.io_out_uop_iw_state : i2
    %issue_slots_19_out_uop_fu_code = sv.wire sym @issue_slots_19_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_19_out_uop_fu_code, %slots_19.io_out_uop_fu_code : i10
    %issue_slots_19_out_uop_is_rvc = sv.wire sym @issue_slots_19_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_19_out_uop_is_rvc, %slots_19.io_out_uop_is_rvc : i1
    %issue_slots_19_out_uop_uopc = sv.wire sym @issue_slots_19_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_19_out_uop_uopc, %slots_19.io_out_uop_uopc : i7
    %3447 = comb.icmp ne %1751, %c0_i4 {sv.namehint = "_issue_slots_15_clear"} : i4
    %issue_slots_15_clear = sv.wire sym @issue_slots_15_clear  : !hw.inout<i1>
    sv.assign %issue_slots_15_clear, %3447 : i1
    %3448 = comb.icmp eq %1767, %c1_i4 : i4
    %3449 = comb.and %3448, %slots_17.io_will_be_valid : i1
    %3450 = comb.icmp eq %1775, %c2_i4 : i4
    %3451 = comb.mux %3450, %slots_18.io_will_be_valid, %3449 : i1
    %3452 = comb.mux %3450, %slots_18.io_out_uop_fp_val, %slots_17.io_out_uop_fp_val : i1
    %3453 = comb.mux %3450, %slots_18.io_out_uop_lrs2_rtype, %slots_17.io_out_uop_lrs2_rtype : i2
    %3454 = comb.mux %3450, %slots_18.io_out_uop_lrs1_rtype, %slots_17.io_out_uop_lrs1_rtype : i2
    %3455 = comb.mux %3450, %slots_18.io_out_uop_dst_rtype, %slots_17.io_out_uop_dst_rtype : i2
    %3456 = comb.mux %3450, %slots_18.io_out_uop_ldst_val, %slots_17.io_out_uop_ldst_val : i1
    %3457 = comb.mux %3450, %slots_18.io_out_uop_uses_stq, %slots_17.io_out_uop_uses_stq : i1
    %3458 = comb.mux %3450, %slots_18.io_out_uop_uses_ldq, %slots_17.io_out_uop_uses_ldq : i1
    %3459 = comb.mux %3450, %slots_18.io_out_uop_is_amo, %slots_17.io_out_uop_is_amo : i1
    %3460 = comb.mux %3450, %slots_18.io_out_uop_is_fence, %slots_17.io_out_uop_is_fence : i1
    %3461 = comb.mux %3450, %slots_18.io_out_uop_mem_signed, %slots_17.io_out_uop_mem_signed : i1
    %3462 = comb.mux %3450, %slots_18.io_out_uop_mem_size, %slots_17.io_out_uop_mem_size : i2
    %3463 = comb.mux %3450, %slots_18.io_out_uop_mem_cmd, %slots_17.io_out_uop_mem_cmd : i5
    %3464 = comb.mux %3450, %slots_18.io_out_uop_bypassable, %slots_17.io_out_uop_bypassable : i1
    %3465 = comb.mux %3450, %slots_18.io_out_uop_ppred_busy, %slots_17.io_out_uop_ppred_busy : i1
    %3466 = comb.mux %3450, %slots_18.io_out_uop_prs3_busy, %slots_17.io_out_uop_prs3_busy : i1
    %3467 = comb.mux %3450, %slots_18.io_out_uop_prs2_busy, %slots_17.io_out_uop_prs2_busy : i1
    %3468 = comb.mux %3450, %slots_18.io_out_uop_prs1_busy, %slots_17.io_out_uop_prs1_busy : i1
    %3469 = comb.mux %3450, %slots_18.io_out_uop_prs3, %slots_17.io_out_uop_prs3 : i7
    %3470 = comb.mux %3450, %slots_18.io_out_uop_prs2, %slots_17.io_out_uop_prs2 : i7
    %3471 = comb.mux %3450, %slots_18.io_out_uop_prs1, %slots_17.io_out_uop_prs1 : i7
    %3472 = comb.mux %3450, %slots_18.io_out_uop_pdst, %slots_17.io_out_uop_pdst : i7
    %3473 = comb.mux %3450, %slots_18.io_out_uop_stq_idx, %slots_17.io_out_uop_stq_idx : i5
    %3474 = comb.mux %3450, %slots_18.io_out_uop_ldq_idx, %slots_17.io_out_uop_ldq_idx : i5
    %3475 = comb.mux %3450, %slots_18.io_out_uop_rob_idx, %slots_17.io_out_uop_rob_idx : i7
    %3476 = comb.mux %3450, %slots_18.io_out_uop_imm_packed, %slots_17.io_out_uop_imm_packed : i20
    %3477 = comb.mux %3450, %slots_18.io_out_uop_taken, %slots_17.io_out_uop_taken : i1
    %3478 = comb.mux %3450, %slots_18.io_out_uop_pc_lob, %slots_17.io_out_uop_pc_lob : i6
    %3479 = comb.mux %3450, %slots_18.io_out_uop_edge_inst, %slots_17.io_out_uop_edge_inst : i1
    %3480 = comb.mux %3450, %slots_18.io_out_uop_ftq_idx, %slots_17.io_out_uop_ftq_idx : i6
    %3481 = comb.mux %3450, %slots_18.io_out_uop_br_tag, %slots_17.io_out_uop_br_tag : i5
    %3482 = comb.mux %3450, %slots_18.io_out_uop_br_mask, %slots_17.io_out_uop_br_mask : i20
    %3483 = comb.mux %3450, %slots_18.io_out_uop_is_sfb, %slots_17.io_out_uop_is_sfb : i1
    %3484 = comb.mux %3450, %slots_18.io_out_uop_is_jal, %slots_17.io_out_uop_is_jal : i1
    %3485 = comb.mux %3450, %slots_18.io_out_uop_is_jalr, %slots_17.io_out_uop_is_jalr : i1
    %3486 = comb.mux %3450, %slots_18.io_out_uop_is_br, %slots_17.io_out_uop_is_br : i1
    %3487 = comb.mux %3450, %slots_18.io_out_uop_iw_p2_poisoned, %slots_17.io_out_uop_iw_p2_poisoned : i1
    %3488 = comb.mux %3450, %slots_18.io_out_uop_iw_p1_poisoned, %slots_17.io_out_uop_iw_p1_poisoned : i1
    %3489 = comb.mux %3450, %slots_18.io_out_uop_iw_state, %slots_17.io_out_uop_iw_state : i2
    %3490 = comb.mux %3450, %slots_18.io_out_uop_fu_code, %slots_17.io_out_uop_fu_code : i10
    %3491 = comb.mux %3450, %slots_18.io_out_uop_is_rvc, %slots_17.io_out_uop_is_rvc : i1
    %3492 = comb.mux %3450, %slots_18.io_out_uop_uopc, %slots_17.io_out_uop_uopc : i7
    %3493 = comb.icmp eq %1783, %c4_i4 : i4
    %3494 = comb.mux %3493, %slots_19.io_will_be_valid, %3451 : i1
    %3495 = comb.mux %3493, %slots_19.io_out_uop_fp_val, %3452 : i1
    %3496 = comb.mux %3493, %slots_19.io_out_uop_lrs2_rtype, %3453 : i2
    %3497 = comb.mux %3493, %slots_19.io_out_uop_lrs1_rtype, %3454 : i2
    %3498 = comb.mux %3493, %slots_19.io_out_uop_dst_rtype, %3455 : i2
    %3499 = comb.mux %3493, %slots_19.io_out_uop_ldst_val, %3456 : i1
    %3500 = comb.mux %3493, %slots_19.io_out_uop_uses_stq, %3457 : i1
    %3501 = comb.mux %3493, %slots_19.io_out_uop_uses_ldq, %3458 : i1
    %3502 = comb.mux %3493, %slots_19.io_out_uop_is_amo, %3459 : i1
    %3503 = comb.mux %3493, %slots_19.io_out_uop_is_fence, %3460 : i1
    %3504 = comb.mux %3493, %slots_19.io_out_uop_mem_signed, %3461 : i1
    %3505 = comb.mux %3493, %slots_19.io_out_uop_mem_size, %3462 : i2
    %3506 = comb.mux %3493, %slots_19.io_out_uop_mem_cmd, %3463 : i5
    %3507 = comb.mux %3493, %slots_19.io_out_uop_bypassable, %3464 : i1
    %3508 = comb.mux %3493, %slots_19.io_out_uop_ppred_busy, %3465 : i1
    %3509 = comb.mux %3493, %slots_19.io_out_uop_prs3_busy, %3466 : i1
    %3510 = comb.mux %3493, %slots_19.io_out_uop_prs2_busy, %3467 : i1
    %3511 = comb.mux %3493, %slots_19.io_out_uop_prs1_busy, %3468 : i1
    %3512 = comb.mux %3493, %slots_19.io_out_uop_prs3, %3469 : i7
    %3513 = comb.mux %3493, %slots_19.io_out_uop_prs2, %3470 : i7
    %3514 = comb.mux %3493, %slots_19.io_out_uop_prs1, %3471 : i7
    %3515 = comb.mux %3493, %slots_19.io_out_uop_pdst, %3472 : i7
    %3516 = comb.mux %3493, %slots_19.io_out_uop_stq_idx, %3473 : i5
    %3517 = comb.mux %3493, %slots_19.io_out_uop_ldq_idx, %3474 : i5
    %3518 = comb.mux %3493, %slots_19.io_out_uop_rob_idx, %3475 : i7
    %3519 = comb.mux %3493, %slots_19.io_out_uop_imm_packed, %3476 : i20
    %3520 = comb.mux %3493, %slots_19.io_out_uop_taken, %3477 : i1
    %3521 = comb.mux %3493, %slots_19.io_out_uop_pc_lob, %3478 : i6
    %3522 = comb.mux %3493, %slots_19.io_out_uop_edge_inst, %3479 : i1
    %3523 = comb.mux %3493, %slots_19.io_out_uop_ftq_idx, %3480 : i6
    %3524 = comb.mux %3493, %slots_19.io_out_uop_br_tag, %3481 : i5
    %3525 = comb.mux %3493, %slots_19.io_out_uop_br_mask, %3482 : i20
    %3526 = comb.mux %3493, %slots_19.io_out_uop_is_sfb, %3483 : i1
    %3527 = comb.mux %3493, %slots_19.io_out_uop_is_jal, %3484 : i1
    %3528 = comb.mux %3493, %slots_19.io_out_uop_is_jalr, %3485 : i1
    %3529 = comb.mux %3493, %slots_19.io_out_uop_is_br, %3486 : i1
    %3530 = comb.mux %3493, %slots_19.io_out_uop_iw_p2_poisoned, %3487 : i1
    %3531 = comb.mux %3493, %slots_19.io_out_uop_iw_p1_poisoned, %3488 : i1
    %3532 = comb.mux %3493, %slots_19.io_out_uop_iw_state, %3489 : i2
    %3533 = comb.mux %3493, %slots_19.io_out_uop_fu_code, %3490 : i10
    %3534 = comb.mux %3493, %slots_19.io_out_uop_is_rvc, %3491 : i1
    %3535 = comb.mux %3493, %slots_19.io_out_uop_uopc, %3492 : i7
    %3536 = comb.icmp eq %1791, %c-8_i4 : i4
    %issue_slots_20_will_be_valid = sv.wire sym @issue_slots_20_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_20_will_be_valid, %slots_20.io_will_be_valid : i1
    %3537 = comb.mux %3536, %slots_20.io_will_be_valid, %3494 {sv.namehint = "_issue_slots_16_in_uop_valid"} : i1
    %issue_slots_16_in_uop_valid = sv.wire sym @issue_slots_16_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_16_in_uop_valid, %3537 : i1
    %issue_slots_20_out_uop_fp_val = sv.wire sym @issue_slots_20_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_fp_val, %slots_20.io_out_uop_fp_val : i1
    %issue_slots_20_out_uop_lrs2_rtype = sv.wire sym @issue_slots_20_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_20_out_uop_lrs2_rtype, %slots_20.io_out_uop_lrs2_rtype : i2
    %issue_slots_20_out_uop_lrs1_rtype = sv.wire sym @issue_slots_20_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_20_out_uop_lrs1_rtype, %slots_20.io_out_uop_lrs1_rtype : i2
    %issue_slots_20_out_uop_dst_rtype = sv.wire sym @issue_slots_20_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_20_out_uop_dst_rtype, %slots_20.io_out_uop_dst_rtype : i2
    %issue_slots_20_out_uop_ldst_val = sv.wire sym @issue_slots_20_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_ldst_val, %slots_20.io_out_uop_ldst_val : i1
    %issue_slots_20_out_uop_uses_stq = sv.wire sym @issue_slots_20_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_uses_stq, %slots_20.io_out_uop_uses_stq : i1
    %issue_slots_20_out_uop_uses_ldq = sv.wire sym @issue_slots_20_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_uses_ldq, %slots_20.io_out_uop_uses_ldq : i1
    %issue_slots_20_out_uop_is_amo = sv.wire sym @issue_slots_20_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_is_amo, %slots_20.io_out_uop_is_amo : i1
    %issue_slots_20_out_uop_is_fence = sv.wire sym @issue_slots_20_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_is_fence, %slots_20.io_out_uop_is_fence : i1
    %issue_slots_20_out_uop_mem_signed = sv.wire sym @issue_slots_20_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_mem_signed, %slots_20.io_out_uop_mem_signed : i1
    %issue_slots_20_out_uop_mem_size = sv.wire sym @issue_slots_20_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_20_out_uop_mem_size, %slots_20.io_out_uop_mem_size : i2
    %issue_slots_20_out_uop_mem_cmd = sv.wire sym @issue_slots_20_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_20_out_uop_mem_cmd, %slots_20.io_out_uop_mem_cmd : i5
    %issue_slots_20_out_uop_bypassable = sv.wire sym @issue_slots_20_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_bypassable, %slots_20.io_out_uop_bypassable : i1
    %issue_slots_20_out_uop_ppred_busy = sv.wire sym @issue_slots_20_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_ppred_busy, %slots_20.io_out_uop_ppred_busy : i1
    %issue_slots_20_out_uop_prs3_busy = sv.wire sym @issue_slots_20_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_prs3_busy, %slots_20.io_out_uop_prs3_busy : i1
    %issue_slots_20_out_uop_prs2_busy = sv.wire sym @issue_slots_20_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_prs2_busy, %slots_20.io_out_uop_prs2_busy : i1
    %issue_slots_20_out_uop_prs1_busy = sv.wire sym @issue_slots_20_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_prs1_busy, %slots_20.io_out_uop_prs1_busy : i1
    %issue_slots_20_out_uop_prs3 = sv.wire sym @issue_slots_20_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_20_out_uop_prs3, %slots_20.io_out_uop_prs3 : i7
    %issue_slots_20_out_uop_prs2 = sv.wire sym @issue_slots_20_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_20_out_uop_prs2, %slots_20.io_out_uop_prs2 : i7
    %issue_slots_20_out_uop_prs1 = sv.wire sym @issue_slots_20_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_20_out_uop_prs1, %slots_20.io_out_uop_prs1 : i7
    %issue_slots_20_out_uop_pdst = sv.wire sym @issue_slots_20_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_20_out_uop_pdst, %slots_20.io_out_uop_pdst : i7
    %issue_slots_20_out_uop_stq_idx = sv.wire sym @issue_slots_20_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_20_out_uop_stq_idx, %slots_20.io_out_uop_stq_idx : i5
    %issue_slots_20_out_uop_ldq_idx = sv.wire sym @issue_slots_20_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_20_out_uop_ldq_idx, %slots_20.io_out_uop_ldq_idx : i5
    %issue_slots_20_out_uop_rob_idx = sv.wire sym @issue_slots_20_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_20_out_uop_rob_idx, %slots_20.io_out_uop_rob_idx : i7
    %issue_slots_20_out_uop_imm_packed = sv.wire sym @issue_slots_20_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_20_out_uop_imm_packed, %slots_20.io_out_uop_imm_packed : i20
    %issue_slots_20_out_uop_taken = sv.wire sym @issue_slots_20_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_taken, %slots_20.io_out_uop_taken : i1
    %issue_slots_20_out_uop_pc_lob = sv.wire sym @issue_slots_20_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_20_out_uop_pc_lob, %slots_20.io_out_uop_pc_lob : i6
    %issue_slots_20_out_uop_edge_inst = sv.wire sym @issue_slots_20_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_edge_inst, %slots_20.io_out_uop_edge_inst : i1
    %issue_slots_20_out_uop_ftq_idx = sv.wire sym @issue_slots_20_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_20_out_uop_ftq_idx, %slots_20.io_out_uop_ftq_idx : i6
    %issue_slots_20_out_uop_br_tag = sv.wire sym @issue_slots_20_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_20_out_uop_br_tag, %slots_20.io_out_uop_br_tag : i5
    %issue_slots_20_out_uop_br_mask = sv.wire sym @issue_slots_20_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_20_out_uop_br_mask, %slots_20.io_out_uop_br_mask : i20
    %issue_slots_20_out_uop_is_sfb = sv.wire sym @issue_slots_20_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_is_sfb, %slots_20.io_out_uop_is_sfb : i1
    %issue_slots_20_out_uop_is_jal = sv.wire sym @issue_slots_20_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_is_jal, %slots_20.io_out_uop_is_jal : i1
    %issue_slots_20_out_uop_is_jalr = sv.wire sym @issue_slots_20_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_is_jalr, %slots_20.io_out_uop_is_jalr : i1
    %issue_slots_20_out_uop_is_br = sv.wire sym @issue_slots_20_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_is_br, %slots_20.io_out_uop_is_br : i1
    %issue_slots_20_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_20_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_iw_p2_poisoned, %slots_20.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_20_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_20_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_iw_p1_poisoned, %slots_20.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_20_out_uop_iw_state = sv.wire sym @issue_slots_20_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_20_out_uop_iw_state, %slots_20.io_out_uop_iw_state : i2
    %issue_slots_20_out_uop_fu_code = sv.wire sym @issue_slots_20_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_20_out_uop_fu_code, %slots_20.io_out_uop_fu_code : i10
    %issue_slots_20_out_uop_is_rvc = sv.wire sym @issue_slots_20_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_20_out_uop_is_rvc, %slots_20.io_out_uop_is_rvc : i1
    %issue_slots_20_out_uop_uopc = sv.wire sym @issue_slots_20_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_20_out_uop_uopc, %slots_20.io_out_uop_uopc : i7
    %3538 = comb.icmp ne %1759, %c0_i4 {sv.namehint = "_issue_slots_16_clear"} : i4
    %issue_slots_16_clear = sv.wire sym @issue_slots_16_clear  : !hw.inout<i1>
    sv.assign %issue_slots_16_clear, %3538 : i1
    %3539 = comb.icmp eq %1775, %c1_i4 : i4
    %3540 = comb.and %3539, %slots_18.io_will_be_valid : i1
    %3541 = comb.icmp eq %1783, %c2_i4 : i4
    %3542 = comb.mux %3541, %slots_19.io_will_be_valid, %3540 : i1
    %3543 = comb.mux %3541, %slots_19.io_out_uop_fp_val, %slots_18.io_out_uop_fp_val : i1
    %3544 = comb.mux %3541, %slots_19.io_out_uop_lrs2_rtype, %slots_18.io_out_uop_lrs2_rtype : i2
    %3545 = comb.mux %3541, %slots_19.io_out_uop_lrs1_rtype, %slots_18.io_out_uop_lrs1_rtype : i2
    %3546 = comb.mux %3541, %slots_19.io_out_uop_dst_rtype, %slots_18.io_out_uop_dst_rtype : i2
    %3547 = comb.mux %3541, %slots_19.io_out_uop_ldst_val, %slots_18.io_out_uop_ldst_val : i1
    %3548 = comb.mux %3541, %slots_19.io_out_uop_uses_stq, %slots_18.io_out_uop_uses_stq : i1
    %3549 = comb.mux %3541, %slots_19.io_out_uop_uses_ldq, %slots_18.io_out_uop_uses_ldq : i1
    %3550 = comb.mux %3541, %slots_19.io_out_uop_is_amo, %slots_18.io_out_uop_is_amo : i1
    %3551 = comb.mux %3541, %slots_19.io_out_uop_is_fence, %slots_18.io_out_uop_is_fence : i1
    %3552 = comb.mux %3541, %slots_19.io_out_uop_mem_signed, %slots_18.io_out_uop_mem_signed : i1
    %3553 = comb.mux %3541, %slots_19.io_out_uop_mem_size, %slots_18.io_out_uop_mem_size : i2
    %3554 = comb.mux %3541, %slots_19.io_out_uop_mem_cmd, %slots_18.io_out_uop_mem_cmd : i5
    %3555 = comb.mux %3541, %slots_19.io_out_uop_bypassable, %slots_18.io_out_uop_bypassable : i1
    %3556 = comb.mux %3541, %slots_19.io_out_uop_ppred_busy, %slots_18.io_out_uop_ppred_busy : i1
    %3557 = comb.mux %3541, %slots_19.io_out_uop_prs3_busy, %slots_18.io_out_uop_prs3_busy : i1
    %3558 = comb.mux %3541, %slots_19.io_out_uop_prs2_busy, %slots_18.io_out_uop_prs2_busy : i1
    %3559 = comb.mux %3541, %slots_19.io_out_uop_prs1_busy, %slots_18.io_out_uop_prs1_busy : i1
    %3560 = comb.mux %3541, %slots_19.io_out_uop_prs3, %slots_18.io_out_uop_prs3 : i7
    %3561 = comb.mux %3541, %slots_19.io_out_uop_prs2, %slots_18.io_out_uop_prs2 : i7
    %3562 = comb.mux %3541, %slots_19.io_out_uop_prs1, %slots_18.io_out_uop_prs1 : i7
    %3563 = comb.mux %3541, %slots_19.io_out_uop_pdst, %slots_18.io_out_uop_pdst : i7
    %3564 = comb.mux %3541, %slots_19.io_out_uop_stq_idx, %slots_18.io_out_uop_stq_idx : i5
    %3565 = comb.mux %3541, %slots_19.io_out_uop_ldq_idx, %slots_18.io_out_uop_ldq_idx : i5
    %3566 = comb.mux %3541, %slots_19.io_out_uop_rob_idx, %slots_18.io_out_uop_rob_idx : i7
    %3567 = comb.mux %3541, %slots_19.io_out_uop_imm_packed, %slots_18.io_out_uop_imm_packed : i20
    %3568 = comb.mux %3541, %slots_19.io_out_uop_taken, %slots_18.io_out_uop_taken : i1
    %3569 = comb.mux %3541, %slots_19.io_out_uop_pc_lob, %slots_18.io_out_uop_pc_lob : i6
    %3570 = comb.mux %3541, %slots_19.io_out_uop_edge_inst, %slots_18.io_out_uop_edge_inst : i1
    %3571 = comb.mux %3541, %slots_19.io_out_uop_ftq_idx, %slots_18.io_out_uop_ftq_idx : i6
    %3572 = comb.mux %3541, %slots_19.io_out_uop_br_tag, %slots_18.io_out_uop_br_tag : i5
    %3573 = comb.mux %3541, %slots_19.io_out_uop_br_mask, %slots_18.io_out_uop_br_mask : i20
    %3574 = comb.mux %3541, %slots_19.io_out_uop_is_sfb, %slots_18.io_out_uop_is_sfb : i1
    %3575 = comb.mux %3541, %slots_19.io_out_uop_is_jal, %slots_18.io_out_uop_is_jal : i1
    %3576 = comb.mux %3541, %slots_19.io_out_uop_is_jalr, %slots_18.io_out_uop_is_jalr : i1
    %3577 = comb.mux %3541, %slots_19.io_out_uop_is_br, %slots_18.io_out_uop_is_br : i1
    %3578 = comb.mux %3541, %slots_19.io_out_uop_iw_p2_poisoned, %slots_18.io_out_uop_iw_p2_poisoned : i1
    %3579 = comb.mux %3541, %slots_19.io_out_uop_iw_p1_poisoned, %slots_18.io_out_uop_iw_p1_poisoned : i1
    %3580 = comb.mux %3541, %slots_19.io_out_uop_iw_state, %slots_18.io_out_uop_iw_state : i2
    %3581 = comb.mux %3541, %slots_19.io_out_uop_fu_code, %slots_18.io_out_uop_fu_code : i10
    %3582 = comb.mux %3541, %slots_19.io_out_uop_is_rvc, %slots_18.io_out_uop_is_rvc : i1
    %3583 = comb.mux %3541, %slots_19.io_out_uop_uopc, %slots_18.io_out_uop_uopc : i7
    %3584 = comb.icmp eq %1791, %c4_i4 : i4
    %3585 = comb.mux %3584, %slots_20.io_will_be_valid, %3542 : i1
    %3586 = comb.mux %3584, %slots_20.io_out_uop_fp_val, %3543 : i1
    %3587 = comb.mux %3584, %slots_20.io_out_uop_lrs2_rtype, %3544 : i2
    %3588 = comb.mux %3584, %slots_20.io_out_uop_lrs1_rtype, %3545 : i2
    %3589 = comb.mux %3584, %slots_20.io_out_uop_dst_rtype, %3546 : i2
    %3590 = comb.mux %3584, %slots_20.io_out_uop_ldst_val, %3547 : i1
    %3591 = comb.mux %3584, %slots_20.io_out_uop_uses_stq, %3548 : i1
    %3592 = comb.mux %3584, %slots_20.io_out_uop_uses_ldq, %3549 : i1
    %3593 = comb.mux %3584, %slots_20.io_out_uop_is_amo, %3550 : i1
    %3594 = comb.mux %3584, %slots_20.io_out_uop_is_fence, %3551 : i1
    %3595 = comb.mux %3584, %slots_20.io_out_uop_mem_signed, %3552 : i1
    %3596 = comb.mux %3584, %slots_20.io_out_uop_mem_size, %3553 : i2
    %3597 = comb.mux %3584, %slots_20.io_out_uop_mem_cmd, %3554 : i5
    %3598 = comb.mux %3584, %slots_20.io_out_uop_bypassable, %3555 : i1
    %3599 = comb.mux %3584, %slots_20.io_out_uop_ppred_busy, %3556 : i1
    %3600 = comb.mux %3584, %slots_20.io_out_uop_prs3_busy, %3557 : i1
    %3601 = comb.mux %3584, %slots_20.io_out_uop_prs2_busy, %3558 : i1
    %3602 = comb.mux %3584, %slots_20.io_out_uop_prs1_busy, %3559 : i1
    %3603 = comb.mux %3584, %slots_20.io_out_uop_prs3, %3560 : i7
    %3604 = comb.mux %3584, %slots_20.io_out_uop_prs2, %3561 : i7
    %3605 = comb.mux %3584, %slots_20.io_out_uop_prs1, %3562 : i7
    %3606 = comb.mux %3584, %slots_20.io_out_uop_pdst, %3563 : i7
    %3607 = comb.mux %3584, %slots_20.io_out_uop_stq_idx, %3564 : i5
    %3608 = comb.mux %3584, %slots_20.io_out_uop_ldq_idx, %3565 : i5
    %3609 = comb.mux %3584, %slots_20.io_out_uop_rob_idx, %3566 : i7
    %3610 = comb.mux %3584, %slots_20.io_out_uop_imm_packed, %3567 : i20
    %3611 = comb.mux %3584, %slots_20.io_out_uop_taken, %3568 : i1
    %3612 = comb.mux %3584, %slots_20.io_out_uop_pc_lob, %3569 : i6
    %3613 = comb.mux %3584, %slots_20.io_out_uop_edge_inst, %3570 : i1
    %3614 = comb.mux %3584, %slots_20.io_out_uop_ftq_idx, %3571 : i6
    %3615 = comb.mux %3584, %slots_20.io_out_uop_br_tag, %3572 : i5
    %3616 = comb.mux %3584, %slots_20.io_out_uop_br_mask, %3573 : i20
    %3617 = comb.mux %3584, %slots_20.io_out_uop_is_sfb, %3574 : i1
    %3618 = comb.mux %3584, %slots_20.io_out_uop_is_jal, %3575 : i1
    %3619 = comb.mux %3584, %slots_20.io_out_uop_is_jalr, %3576 : i1
    %3620 = comb.mux %3584, %slots_20.io_out_uop_is_br, %3577 : i1
    %3621 = comb.mux %3584, %slots_20.io_out_uop_iw_p2_poisoned, %3578 : i1
    %3622 = comb.mux %3584, %slots_20.io_out_uop_iw_p1_poisoned, %3579 : i1
    %3623 = comb.mux %3584, %slots_20.io_out_uop_iw_state, %3580 : i2
    %3624 = comb.mux %3584, %slots_20.io_out_uop_fu_code, %3581 : i10
    %3625 = comb.mux %3584, %slots_20.io_out_uop_is_rvc, %3582 : i1
    %3626 = comb.mux %3584, %slots_20.io_out_uop_uopc, %3583 : i7
    %3627 = comb.icmp eq %1799, %c-8_i4 : i4
    %issue_slots_21_will_be_valid = sv.wire sym @issue_slots_21_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_21_will_be_valid, %slots_21.io_will_be_valid : i1
    %3628 = comb.mux %3627, %slots_21.io_will_be_valid, %3585 {sv.namehint = "_issue_slots_17_in_uop_valid"} : i1
    %issue_slots_17_in_uop_valid = sv.wire sym @issue_slots_17_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_17_in_uop_valid, %3628 : i1
    %issue_slots_21_out_uop_fp_val = sv.wire sym @issue_slots_21_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_fp_val, %slots_21.io_out_uop_fp_val : i1
    %issue_slots_21_out_uop_lrs2_rtype = sv.wire sym @issue_slots_21_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_21_out_uop_lrs2_rtype, %slots_21.io_out_uop_lrs2_rtype : i2
    %issue_slots_21_out_uop_lrs1_rtype = sv.wire sym @issue_slots_21_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_21_out_uop_lrs1_rtype, %slots_21.io_out_uop_lrs1_rtype : i2
    %issue_slots_21_out_uop_dst_rtype = sv.wire sym @issue_slots_21_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_21_out_uop_dst_rtype, %slots_21.io_out_uop_dst_rtype : i2
    %issue_slots_21_out_uop_ldst_val = sv.wire sym @issue_slots_21_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_ldst_val, %slots_21.io_out_uop_ldst_val : i1
    %issue_slots_21_out_uop_uses_stq = sv.wire sym @issue_slots_21_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_uses_stq, %slots_21.io_out_uop_uses_stq : i1
    %issue_slots_21_out_uop_uses_ldq = sv.wire sym @issue_slots_21_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_uses_ldq, %slots_21.io_out_uop_uses_ldq : i1
    %issue_slots_21_out_uop_is_amo = sv.wire sym @issue_slots_21_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_is_amo, %slots_21.io_out_uop_is_amo : i1
    %issue_slots_21_out_uop_is_fence = sv.wire sym @issue_slots_21_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_is_fence, %slots_21.io_out_uop_is_fence : i1
    %issue_slots_21_out_uop_mem_signed = sv.wire sym @issue_slots_21_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_mem_signed, %slots_21.io_out_uop_mem_signed : i1
    %issue_slots_21_out_uop_mem_size = sv.wire sym @issue_slots_21_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_21_out_uop_mem_size, %slots_21.io_out_uop_mem_size : i2
    %issue_slots_21_out_uop_mem_cmd = sv.wire sym @issue_slots_21_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_21_out_uop_mem_cmd, %slots_21.io_out_uop_mem_cmd : i5
    %issue_slots_21_out_uop_bypassable = sv.wire sym @issue_slots_21_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_bypassable, %slots_21.io_out_uop_bypassable : i1
    %issue_slots_21_out_uop_ppred_busy = sv.wire sym @issue_slots_21_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_ppred_busy, %slots_21.io_out_uop_ppred_busy : i1
    %issue_slots_21_out_uop_prs3_busy = sv.wire sym @issue_slots_21_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_prs3_busy, %slots_21.io_out_uop_prs3_busy : i1
    %issue_slots_21_out_uop_prs2_busy = sv.wire sym @issue_slots_21_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_prs2_busy, %slots_21.io_out_uop_prs2_busy : i1
    %issue_slots_21_out_uop_prs1_busy = sv.wire sym @issue_slots_21_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_prs1_busy, %slots_21.io_out_uop_prs1_busy : i1
    %issue_slots_21_out_uop_prs3 = sv.wire sym @issue_slots_21_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_21_out_uop_prs3, %slots_21.io_out_uop_prs3 : i7
    %issue_slots_21_out_uop_prs2 = sv.wire sym @issue_slots_21_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_21_out_uop_prs2, %slots_21.io_out_uop_prs2 : i7
    %issue_slots_21_out_uop_prs1 = sv.wire sym @issue_slots_21_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_21_out_uop_prs1, %slots_21.io_out_uop_prs1 : i7
    %issue_slots_21_out_uop_pdst = sv.wire sym @issue_slots_21_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_21_out_uop_pdst, %slots_21.io_out_uop_pdst : i7
    %issue_slots_21_out_uop_stq_idx = sv.wire sym @issue_slots_21_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_21_out_uop_stq_idx, %slots_21.io_out_uop_stq_idx : i5
    %issue_slots_21_out_uop_ldq_idx = sv.wire sym @issue_slots_21_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_21_out_uop_ldq_idx, %slots_21.io_out_uop_ldq_idx : i5
    %issue_slots_21_out_uop_rob_idx = sv.wire sym @issue_slots_21_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_21_out_uop_rob_idx, %slots_21.io_out_uop_rob_idx : i7
    %issue_slots_21_out_uop_imm_packed = sv.wire sym @issue_slots_21_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_21_out_uop_imm_packed, %slots_21.io_out_uop_imm_packed : i20
    %issue_slots_21_out_uop_taken = sv.wire sym @issue_slots_21_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_taken, %slots_21.io_out_uop_taken : i1
    %issue_slots_21_out_uop_pc_lob = sv.wire sym @issue_slots_21_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_21_out_uop_pc_lob, %slots_21.io_out_uop_pc_lob : i6
    %issue_slots_21_out_uop_edge_inst = sv.wire sym @issue_slots_21_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_edge_inst, %slots_21.io_out_uop_edge_inst : i1
    %issue_slots_21_out_uop_ftq_idx = sv.wire sym @issue_slots_21_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_21_out_uop_ftq_idx, %slots_21.io_out_uop_ftq_idx : i6
    %issue_slots_21_out_uop_br_tag = sv.wire sym @issue_slots_21_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_21_out_uop_br_tag, %slots_21.io_out_uop_br_tag : i5
    %issue_slots_21_out_uop_br_mask = sv.wire sym @issue_slots_21_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_21_out_uop_br_mask, %slots_21.io_out_uop_br_mask : i20
    %issue_slots_21_out_uop_is_sfb = sv.wire sym @issue_slots_21_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_is_sfb, %slots_21.io_out_uop_is_sfb : i1
    %issue_slots_21_out_uop_is_jal = sv.wire sym @issue_slots_21_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_is_jal, %slots_21.io_out_uop_is_jal : i1
    %issue_slots_21_out_uop_is_jalr = sv.wire sym @issue_slots_21_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_is_jalr, %slots_21.io_out_uop_is_jalr : i1
    %issue_slots_21_out_uop_is_br = sv.wire sym @issue_slots_21_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_is_br, %slots_21.io_out_uop_is_br : i1
    %issue_slots_21_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_21_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_iw_p2_poisoned, %slots_21.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_21_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_21_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_iw_p1_poisoned, %slots_21.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_21_out_uop_iw_state = sv.wire sym @issue_slots_21_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_21_out_uop_iw_state, %slots_21.io_out_uop_iw_state : i2
    %issue_slots_21_out_uop_fu_code = sv.wire sym @issue_slots_21_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_21_out_uop_fu_code, %slots_21.io_out_uop_fu_code : i10
    %issue_slots_21_out_uop_is_rvc = sv.wire sym @issue_slots_21_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_21_out_uop_is_rvc, %slots_21.io_out_uop_is_rvc : i1
    %issue_slots_21_out_uop_uopc = sv.wire sym @issue_slots_21_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_21_out_uop_uopc, %slots_21.io_out_uop_uopc : i7
    %3629 = comb.icmp ne %1767, %c0_i4 {sv.namehint = "_issue_slots_17_clear"} : i4
    %issue_slots_17_clear = sv.wire sym @issue_slots_17_clear  : !hw.inout<i1>
    sv.assign %issue_slots_17_clear, %3629 : i1
    %3630 = comb.icmp eq %1783, %c1_i4 : i4
    %3631 = comb.and %3630, %slots_19.io_will_be_valid : i1
    %3632 = comb.icmp eq %1791, %c2_i4 : i4
    %3633 = comb.mux %3632, %slots_20.io_will_be_valid, %3631 : i1
    %3634 = comb.mux %3632, %slots_20.io_out_uop_fp_val, %slots_19.io_out_uop_fp_val : i1
    %3635 = comb.mux %3632, %slots_20.io_out_uop_lrs2_rtype, %slots_19.io_out_uop_lrs2_rtype : i2
    %3636 = comb.mux %3632, %slots_20.io_out_uop_lrs1_rtype, %slots_19.io_out_uop_lrs1_rtype : i2
    %3637 = comb.mux %3632, %slots_20.io_out_uop_dst_rtype, %slots_19.io_out_uop_dst_rtype : i2
    %3638 = comb.mux %3632, %slots_20.io_out_uop_ldst_val, %slots_19.io_out_uop_ldst_val : i1
    %3639 = comb.mux %3632, %slots_20.io_out_uop_uses_stq, %slots_19.io_out_uop_uses_stq : i1
    %3640 = comb.mux %3632, %slots_20.io_out_uop_uses_ldq, %slots_19.io_out_uop_uses_ldq : i1
    %3641 = comb.mux %3632, %slots_20.io_out_uop_is_amo, %slots_19.io_out_uop_is_amo : i1
    %3642 = comb.mux %3632, %slots_20.io_out_uop_is_fence, %slots_19.io_out_uop_is_fence : i1
    %3643 = comb.mux %3632, %slots_20.io_out_uop_mem_signed, %slots_19.io_out_uop_mem_signed : i1
    %3644 = comb.mux %3632, %slots_20.io_out_uop_mem_size, %slots_19.io_out_uop_mem_size : i2
    %3645 = comb.mux %3632, %slots_20.io_out_uop_mem_cmd, %slots_19.io_out_uop_mem_cmd : i5
    %3646 = comb.mux %3632, %slots_20.io_out_uop_bypassable, %slots_19.io_out_uop_bypassable : i1
    %3647 = comb.mux %3632, %slots_20.io_out_uop_ppred_busy, %slots_19.io_out_uop_ppred_busy : i1
    %3648 = comb.mux %3632, %slots_20.io_out_uop_prs3_busy, %slots_19.io_out_uop_prs3_busy : i1
    %3649 = comb.mux %3632, %slots_20.io_out_uop_prs2_busy, %slots_19.io_out_uop_prs2_busy : i1
    %3650 = comb.mux %3632, %slots_20.io_out_uop_prs1_busy, %slots_19.io_out_uop_prs1_busy : i1
    %3651 = comb.mux %3632, %slots_20.io_out_uop_prs3, %slots_19.io_out_uop_prs3 : i7
    %3652 = comb.mux %3632, %slots_20.io_out_uop_prs2, %slots_19.io_out_uop_prs2 : i7
    %3653 = comb.mux %3632, %slots_20.io_out_uop_prs1, %slots_19.io_out_uop_prs1 : i7
    %3654 = comb.mux %3632, %slots_20.io_out_uop_pdst, %slots_19.io_out_uop_pdst : i7
    %3655 = comb.mux %3632, %slots_20.io_out_uop_stq_idx, %slots_19.io_out_uop_stq_idx : i5
    %3656 = comb.mux %3632, %slots_20.io_out_uop_ldq_idx, %slots_19.io_out_uop_ldq_idx : i5
    %3657 = comb.mux %3632, %slots_20.io_out_uop_rob_idx, %slots_19.io_out_uop_rob_idx : i7
    %3658 = comb.mux %3632, %slots_20.io_out_uop_imm_packed, %slots_19.io_out_uop_imm_packed : i20
    %3659 = comb.mux %3632, %slots_20.io_out_uop_taken, %slots_19.io_out_uop_taken : i1
    %3660 = comb.mux %3632, %slots_20.io_out_uop_pc_lob, %slots_19.io_out_uop_pc_lob : i6
    %3661 = comb.mux %3632, %slots_20.io_out_uop_edge_inst, %slots_19.io_out_uop_edge_inst : i1
    %3662 = comb.mux %3632, %slots_20.io_out_uop_ftq_idx, %slots_19.io_out_uop_ftq_idx : i6
    %3663 = comb.mux %3632, %slots_20.io_out_uop_br_tag, %slots_19.io_out_uop_br_tag : i5
    %3664 = comb.mux %3632, %slots_20.io_out_uop_br_mask, %slots_19.io_out_uop_br_mask : i20
    %3665 = comb.mux %3632, %slots_20.io_out_uop_is_sfb, %slots_19.io_out_uop_is_sfb : i1
    %3666 = comb.mux %3632, %slots_20.io_out_uop_is_jal, %slots_19.io_out_uop_is_jal : i1
    %3667 = comb.mux %3632, %slots_20.io_out_uop_is_jalr, %slots_19.io_out_uop_is_jalr : i1
    %3668 = comb.mux %3632, %slots_20.io_out_uop_is_br, %slots_19.io_out_uop_is_br : i1
    %3669 = comb.mux %3632, %slots_20.io_out_uop_iw_p2_poisoned, %slots_19.io_out_uop_iw_p2_poisoned : i1
    %3670 = comb.mux %3632, %slots_20.io_out_uop_iw_p1_poisoned, %slots_19.io_out_uop_iw_p1_poisoned : i1
    %3671 = comb.mux %3632, %slots_20.io_out_uop_iw_state, %slots_19.io_out_uop_iw_state : i2
    %3672 = comb.mux %3632, %slots_20.io_out_uop_fu_code, %slots_19.io_out_uop_fu_code : i10
    %3673 = comb.mux %3632, %slots_20.io_out_uop_is_rvc, %slots_19.io_out_uop_is_rvc : i1
    %3674 = comb.mux %3632, %slots_20.io_out_uop_uopc, %slots_19.io_out_uop_uopc : i7
    %3675 = comb.icmp eq %1799, %c4_i4 : i4
    %3676 = comb.mux %3675, %slots_21.io_will_be_valid, %3633 : i1
    %3677 = comb.mux %3675, %slots_21.io_out_uop_fp_val, %3634 : i1
    %3678 = comb.mux %3675, %slots_21.io_out_uop_lrs2_rtype, %3635 : i2
    %3679 = comb.mux %3675, %slots_21.io_out_uop_lrs1_rtype, %3636 : i2
    %3680 = comb.mux %3675, %slots_21.io_out_uop_dst_rtype, %3637 : i2
    %3681 = comb.mux %3675, %slots_21.io_out_uop_ldst_val, %3638 : i1
    %3682 = comb.mux %3675, %slots_21.io_out_uop_uses_stq, %3639 : i1
    %3683 = comb.mux %3675, %slots_21.io_out_uop_uses_ldq, %3640 : i1
    %3684 = comb.mux %3675, %slots_21.io_out_uop_is_amo, %3641 : i1
    %3685 = comb.mux %3675, %slots_21.io_out_uop_is_fence, %3642 : i1
    %3686 = comb.mux %3675, %slots_21.io_out_uop_mem_signed, %3643 : i1
    %3687 = comb.mux %3675, %slots_21.io_out_uop_mem_size, %3644 : i2
    %3688 = comb.mux %3675, %slots_21.io_out_uop_mem_cmd, %3645 : i5
    %3689 = comb.mux %3675, %slots_21.io_out_uop_bypassable, %3646 : i1
    %3690 = comb.mux %3675, %slots_21.io_out_uop_ppred_busy, %3647 : i1
    %3691 = comb.mux %3675, %slots_21.io_out_uop_prs3_busy, %3648 : i1
    %3692 = comb.mux %3675, %slots_21.io_out_uop_prs2_busy, %3649 : i1
    %3693 = comb.mux %3675, %slots_21.io_out_uop_prs1_busy, %3650 : i1
    %3694 = comb.mux %3675, %slots_21.io_out_uop_prs3, %3651 : i7
    %3695 = comb.mux %3675, %slots_21.io_out_uop_prs2, %3652 : i7
    %3696 = comb.mux %3675, %slots_21.io_out_uop_prs1, %3653 : i7
    %3697 = comb.mux %3675, %slots_21.io_out_uop_pdst, %3654 : i7
    %3698 = comb.mux %3675, %slots_21.io_out_uop_stq_idx, %3655 : i5
    %3699 = comb.mux %3675, %slots_21.io_out_uop_ldq_idx, %3656 : i5
    %3700 = comb.mux %3675, %slots_21.io_out_uop_rob_idx, %3657 : i7
    %3701 = comb.mux %3675, %slots_21.io_out_uop_imm_packed, %3658 : i20
    %3702 = comb.mux %3675, %slots_21.io_out_uop_taken, %3659 : i1
    %3703 = comb.mux %3675, %slots_21.io_out_uop_pc_lob, %3660 : i6
    %3704 = comb.mux %3675, %slots_21.io_out_uop_edge_inst, %3661 : i1
    %3705 = comb.mux %3675, %slots_21.io_out_uop_ftq_idx, %3662 : i6
    %3706 = comb.mux %3675, %slots_21.io_out_uop_br_tag, %3663 : i5
    %3707 = comb.mux %3675, %slots_21.io_out_uop_br_mask, %3664 : i20
    %3708 = comb.mux %3675, %slots_21.io_out_uop_is_sfb, %3665 : i1
    %3709 = comb.mux %3675, %slots_21.io_out_uop_is_jal, %3666 : i1
    %3710 = comb.mux %3675, %slots_21.io_out_uop_is_jalr, %3667 : i1
    %3711 = comb.mux %3675, %slots_21.io_out_uop_is_br, %3668 : i1
    %3712 = comb.mux %3675, %slots_21.io_out_uop_iw_p2_poisoned, %3669 : i1
    %3713 = comb.mux %3675, %slots_21.io_out_uop_iw_p1_poisoned, %3670 : i1
    %3714 = comb.mux %3675, %slots_21.io_out_uop_iw_state, %3671 : i2
    %3715 = comb.mux %3675, %slots_21.io_out_uop_fu_code, %3672 : i10
    %3716 = comb.mux %3675, %slots_21.io_out_uop_is_rvc, %3673 : i1
    %3717 = comb.mux %3675, %slots_21.io_out_uop_uopc, %3674 : i7
    %3718 = comb.icmp eq %1807, %c-8_i4 : i4
    %issue_slots_22_will_be_valid = sv.wire sym @issue_slots_22_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_22_will_be_valid, %slots_22.io_will_be_valid : i1
    %3719 = comb.mux %3718, %slots_22.io_will_be_valid, %3676 {sv.namehint = "_issue_slots_18_in_uop_valid"} : i1
    %issue_slots_18_in_uop_valid = sv.wire sym @issue_slots_18_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_18_in_uop_valid, %3719 : i1
    %issue_slots_22_out_uop_fp_val = sv.wire sym @issue_slots_22_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_fp_val, %slots_22.io_out_uop_fp_val : i1
    %issue_slots_22_out_uop_lrs2_rtype = sv.wire sym @issue_slots_22_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_22_out_uop_lrs2_rtype, %slots_22.io_out_uop_lrs2_rtype : i2
    %issue_slots_22_out_uop_lrs1_rtype = sv.wire sym @issue_slots_22_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_22_out_uop_lrs1_rtype, %slots_22.io_out_uop_lrs1_rtype : i2
    %issue_slots_22_out_uop_dst_rtype = sv.wire sym @issue_slots_22_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_22_out_uop_dst_rtype, %slots_22.io_out_uop_dst_rtype : i2
    %issue_slots_22_out_uop_ldst_val = sv.wire sym @issue_slots_22_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_ldst_val, %slots_22.io_out_uop_ldst_val : i1
    %issue_slots_22_out_uop_uses_stq = sv.wire sym @issue_slots_22_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_uses_stq, %slots_22.io_out_uop_uses_stq : i1
    %issue_slots_22_out_uop_uses_ldq = sv.wire sym @issue_slots_22_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_uses_ldq, %slots_22.io_out_uop_uses_ldq : i1
    %issue_slots_22_out_uop_is_amo = sv.wire sym @issue_slots_22_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_is_amo, %slots_22.io_out_uop_is_amo : i1
    %issue_slots_22_out_uop_is_fence = sv.wire sym @issue_slots_22_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_is_fence, %slots_22.io_out_uop_is_fence : i1
    %issue_slots_22_out_uop_mem_signed = sv.wire sym @issue_slots_22_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_mem_signed, %slots_22.io_out_uop_mem_signed : i1
    %issue_slots_22_out_uop_mem_size = sv.wire sym @issue_slots_22_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_22_out_uop_mem_size, %slots_22.io_out_uop_mem_size : i2
    %issue_slots_22_out_uop_mem_cmd = sv.wire sym @issue_slots_22_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_22_out_uop_mem_cmd, %slots_22.io_out_uop_mem_cmd : i5
    %issue_slots_22_out_uop_bypassable = sv.wire sym @issue_slots_22_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_bypassable, %slots_22.io_out_uop_bypassable : i1
    %issue_slots_22_out_uop_ppred_busy = sv.wire sym @issue_slots_22_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_ppred_busy, %slots_22.io_out_uop_ppred_busy : i1
    %issue_slots_22_out_uop_prs3_busy = sv.wire sym @issue_slots_22_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_prs3_busy, %slots_22.io_out_uop_prs3_busy : i1
    %issue_slots_22_out_uop_prs2_busy = sv.wire sym @issue_slots_22_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_prs2_busy, %slots_22.io_out_uop_prs2_busy : i1
    %issue_slots_22_out_uop_prs1_busy = sv.wire sym @issue_slots_22_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_prs1_busy, %slots_22.io_out_uop_prs1_busy : i1
    %issue_slots_22_out_uop_prs3 = sv.wire sym @issue_slots_22_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_22_out_uop_prs3, %slots_22.io_out_uop_prs3 : i7
    %issue_slots_22_out_uop_prs2 = sv.wire sym @issue_slots_22_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_22_out_uop_prs2, %slots_22.io_out_uop_prs2 : i7
    %issue_slots_22_out_uop_prs1 = sv.wire sym @issue_slots_22_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_22_out_uop_prs1, %slots_22.io_out_uop_prs1 : i7
    %issue_slots_22_out_uop_pdst = sv.wire sym @issue_slots_22_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_22_out_uop_pdst, %slots_22.io_out_uop_pdst : i7
    %issue_slots_22_out_uop_stq_idx = sv.wire sym @issue_slots_22_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_22_out_uop_stq_idx, %slots_22.io_out_uop_stq_idx : i5
    %issue_slots_22_out_uop_ldq_idx = sv.wire sym @issue_slots_22_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_22_out_uop_ldq_idx, %slots_22.io_out_uop_ldq_idx : i5
    %issue_slots_22_out_uop_rob_idx = sv.wire sym @issue_slots_22_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_22_out_uop_rob_idx, %slots_22.io_out_uop_rob_idx : i7
    %issue_slots_22_out_uop_imm_packed = sv.wire sym @issue_slots_22_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_22_out_uop_imm_packed, %slots_22.io_out_uop_imm_packed : i20
    %issue_slots_22_out_uop_taken = sv.wire sym @issue_slots_22_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_taken, %slots_22.io_out_uop_taken : i1
    %issue_slots_22_out_uop_pc_lob = sv.wire sym @issue_slots_22_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_22_out_uop_pc_lob, %slots_22.io_out_uop_pc_lob : i6
    %issue_slots_22_out_uop_edge_inst = sv.wire sym @issue_slots_22_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_edge_inst, %slots_22.io_out_uop_edge_inst : i1
    %issue_slots_22_out_uop_ftq_idx = sv.wire sym @issue_slots_22_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_22_out_uop_ftq_idx, %slots_22.io_out_uop_ftq_idx : i6
    %issue_slots_22_out_uop_br_tag = sv.wire sym @issue_slots_22_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_22_out_uop_br_tag, %slots_22.io_out_uop_br_tag : i5
    %issue_slots_22_out_uop_br_mask = sv.wire sym @issue_slots_22_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_22_out_uop_br_mask, %slots_22.io_out_uop_br_mask : i20
    %issue_slots_22_out_uop_is_sfb = sv.wire sym @issue_slots_22_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_is_sfb, %slots_22.io_out_uop_is_sfb : i1
    %issue_slots_22_out_uop_is_jal = sv.wire sym @issue_slots_22_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_is_jal, %slots_22.io_out_uop_is_jal : i1
    %issue_slots_22_out_uop_is_jalr = sv.wire sym @issue_slots_22_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_is_jalr, %slots_22.io_out_uop_is_jalr : i1
    %issue_slots_22_out_uop_is_br = sv.wire sym @issue_slots_22_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_is_br, %slots_22.io_out_uop_is_br : i1
    %issue_slots_22_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_22_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_iw_p2_poisoned, %slots_22.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_22_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_22_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_iw_p1_poisoned, %slots_22.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_22_out_uop_iw_state = sv.wire sym @issue_slots_22_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_22_out_uop_iw_state, %slots_22.io_out_uop_iw_state : i2
    %issue_slots_22_out_uop_fu_code = sv.wire sym @issue_slots_22_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_22_out_uop_fu_code, %slots_22.io_out_uop_fu_code : i10
    %issue_slots_22_out_uop_is_rvc = sv.wire sym @issue_slots_22_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_22_out_uop_is_rvc, %slots_22.io_out_uop_is_rvc : i1
    %issue_slots_22_out_uop_uopc = sv.wire sym @issue_slots_22_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_22_out_uop_uopc, %slots_22.io_out_uop_uopc : i7
    %3720 = comb.icmp ne %1775, %c0_i4 {sv.namehint = "_issue_slots_18_clear"} : i4
    %issue_slots_18_clear = sv.wire sym @issue_slots_18_clear  : !hw.inout<i1>
    sv.assign %issue_slots_18_clear, %3720 : i1
    %3721 = comb.icmp eq %1791, %c1_i4 : i4
    %3722 = comb.and %3721, %slots_20.io_will_be_valid : i1
    %3723 = comb.icmp eq %1799, %c2_i4 : i4
    %3724 = comb.mux %3723, %slots_21.io_will_be_valid, %3722 : i1
    %3725 = comb.mux %3723, %slots_21.io_out_uop_fp_val, %slots_20.io_out_uop_fp_val : i1
    %3726 = comb.mux %3723, %slots_21.io_out_uop_lrs2_rtype, %slots_20.io_out_uop_lrs2_rtype : i2
    %3727 = comb.mux %3723, %slots_21.io_out_uop_lrs1_rtype, %slots_20.io_out_uop_lrs1_rtype : i2
    %3728 = comb.mux %3723, %slots_21.io_out_uop_dst_rtype, %slots_20.io_out_uop_dst_rtype : i2
    %3729 = comb.mux %3723, %slots_21.io_out_uop_ldst_val, %slots_20.io_out_uop_ldst_val : i1
    %3730 = comb.mux %3723, %slots_21.io_out_uop_uses_stq, %slots_20.io_out_uop_uses_stq : i1
    %3731 = comb.mux %3723, %slots_21.io_out_uop_uses_ldq, %slots_20.io_out_uop_uses_ldq : i1
    %3732 = comb.mux %3723, %slots_21.io_out_uop_is_amo, %slots_20.io_out_uop_is_amo : i1
    %3733 = comb.mux %3723, %slots_21.io_out_uop_is_fence, %slots_20.io_out_uop_is_fence : i1
    %3734 = comb.mux %3723, %slots_21.io_out_uop_mem_signed, %slots_20.io_out_uop_mem_signed : i1
    %3735 = comb.mux %3723, %slots_21.io_out_uop_mem_size, %slots_20.io_out_uop_mem_size : i2
    %3736 = comb.mux %3723, %slots_21.io_out_uop_mem_cmd, %slots_20.io_out_uop_mem_cmd : i5
    %3737 = comb.mux %3723, %slots_21.io_out_uop_bypassable, %slots_20.io_out_uop_bypassable : i1
    %3738 = comb.mux %3723, %slots_21.io_out_uop_ppred_busy, %slots_20.io_out_uop_ppred_busy : i1
    %3739 = comb.mux %3723, %slots_21.io_out_uop_prs3_busy, %slots_20.io_out_uop_prs3_busy : i1
    %3740 = comb.mux %3723, %slots_21.io_out_uop_prs2_busy, %slots_20.io_out_uop_prs2_busy : i1
    %3741 = comb.mux %3723, %slots_21.io_out_uop_prs1_busy, %slots_20.io_out_uop_prs1_busy : i1
    %3742 = comb.mux %3723, %slots_21.io_out_uop_prs3, %slots_20.io_out_uop_prs3 : i7
    %3743 = comb.mux %3723, %slots_21.io_out_uop_prs2, %slots_20.io_out_uop_prs2 : i7
    %3744 = comb.mux %3723, %slots_21.io_out_uop_prs1, %slots_20.io_out_uop_prs1 : i7
    %3745 = comb.mux %3723, %slots_21.io_out_uop_pdst, %slots_20.io_out_uop_pdst : i7
    %3746 = comb.mux %3723, %slots_21.io_out_uop_stq_idx, %slots_20.io_out_uop_stq_idx : i5
    %3747 = comb.mux %3723, %slots_21.io_out_uop_ldq_idx, %slots_20.io_out_uop_ldq_idx : i5
    %3748 = comb.mux %3723, %slots_21.io_out_uop_rob_idx, %slots_20.io_out_uop_rob_idx : i7
    %3749 = comb.mux %3723, %slots_21.io_out_uop_imm_packed, %slots_20.io_out_uop_imm_packed : i20
    %3750 = comb.mux %3723, %slots_21.io_out_uop_taken, %slots_20.io_out_uop_taken : i1
    %3751 = comb.mux %3723, %slots_21.io_out_uop_pc_lob, %slots_20.io_out_uop_pc_lob : i6
    %3752 = comb.mux %3723, %slots_21.io_out_uop_edge_inst, %slots_20.io_out_uop_edge_inst : i1
    %3753 = comb.mux %3723, %slots_21.io_out_uop_ftq_idx, %slots_20.io_out_uop_ftq_idx : i6
    %3754 = comb.mux %3723, %slots_21.io_out_uop_br_tag, %slots_20.io_out_uop_br_tag : i5
    %3755 = comb.mux %3723, %slots_21.io_out_uop_br_mask, %slots_20.io_out_uop_br_mask : i20
    %3756 = comb.mux %3723, %slots_21.io_out_uop_is_sfb, %slots_20.io_out_uop_is_sfb : i1
    %3757 = comb.mux %3723, %slots_21.io_out_uop_is_jal, %slots_20.io_out_uop_is_jal : i1
    %3758 = comb.mux %3723, %slots_21.io_out_uop_is_jalr, %slots_20.io_out_uop_is_jalr : i1
    %3759 = comb.mux %3723, %slots_21.io_out_uop_is_br, %slots_20.io_out_uop_is_br : i1
    %3760 = comb.mux %3723, %slots_21.io_out_uop_iw_p2_poisoned, %slots_20.io_out_uop_iw_p2_poisoned : i1
    %3761 = comb.mux %3723, %slots_21.io_out_uop_iw_p1_poisoned, %slots_20.io_out_uop_iw_p1_poisoned : i1
    %3762 = comb.mux %3723, %slots_21.io_out_uop_iw_state, %slots_20.io_out_uop_iw_state : i2
    %3763 = comb.mux %3723, %slots_21.io_out_uop_fu_code, %slots_20.io_out_uop_fu_code : i10
    %3764 = comb.mux %3723, %slots_21.io_out_uop_is_rvc, %slots_20.io_out_uop_is_rvc : i1
    %3765 = comb.mux %3723, %slots_21.io_out_uop_uopc, %slots_20.io_out_uop_uopc : i7
    %3766 = comb.icmp eq %1807, %c4_i4 : i4
    %3767 = comb.mux %3766, %slots_22.io_will_be_valid, %3724 : i1
    %3768 = comb.mux %3766, %slots_22.io_out_uop_fp_val, %3725 : i1
    %3769 = comb.mux %3766, %slots_22.io_out_uop_lrs2_rtype, %3726 : i2
    %3770 = comb.mux %3766, %slots_22.io_out_uop_lrs1_rtype, %3727 : i2
    %3771 = comb.mux %3766, %slots_22.io_out_uop_dst_rtype, %3728 : i2
    %3772 = comb.mux %3766, %slots_22.io_out_uop_ldst_val, %3729 : i1
    %3773 = comb.mux %3766, %slots_22.io_out_uop_uses_stq, %3730 : i1
    %3774 = comb.mux %3766, %slots_22.io_out_uop_uses_ldq, %3731 : i1
    %3775 = comb.mux %3766, %slots_22.io_out_uop_is_amo, %3732 : i1
    %3776 = comb.mux %3766, %slots_22.io_out_uop_is_fence, %3733 : i1
    %3777 = comb.mux %3766, %slots_22.io_out_uop_mem_signed, %3734 : i1
    %3778 = comb.mux %3766, %slots_22.io_out_uop_mem_size, %3735 : i2
    %3779 = comb.mux %3766, %slots_22.io_out_uop_mem_cmd, %3736 : i5
    %3780 = comb.mux %3766, %slots_22.io_out_uop_bypassable, %3737 : i1
    %3781 = comb.mux %3766, %slots_22.io_out_uop_ppred_busy, %3738 : i1
    %3782 = comb.mux %3766, %slots_22.io_out_uop_prs3_busy, %3739 : i1
    %3783 = comb.mux %3766, %slots_22.io_out_uop_prs2_busy, %3740 : i1
    %3784 = comb.mux %3766, %slots_22.io_out_uop_prs1_busy, %3741 : i1
    %3785 = comb.mux %3766, %slots_22.io_out_uop_prs3, %3742 : i7
    %3786 = comb.mux %3766, %slots_22.io_out_uop_prs2, %3743 : i7
    %3787 = comb.mux %3766, %slots_22.io_out_uop_prs1, %3744 : i7
    %3788 = comb.mux %3766, %slots_22.io_out_uop_pdst, %3745 : i7
    %3789 = comb.mux %3766, %slots_22.io_out_uop_stq_idx, %3746 : i5
    %3790 = comb.mux %3766, %slots_22.io_out_uop_ldq_idx, %3747 : i5
    %3791 = comb.mux %3766, %slots_22.io_out_uop_rob_idx, %3748 : i7
    %3792 = comb.mux %3766, %slots_22.io_out_uop_imm_packed, %3749 : i20
    %3793 = comb.mux %3766, %slots_22.io_out_uop_taken, %3750 : i1
    %3794 = comb.mux %3766, %slots_22.io_out_uop_pc_lob, %3751 : i6
    %3795 = comb.mux %3766, %slots_22.io_out_uop_edge_inst, %3752 : i1
    %3796 = comb.mux %3766, %slots_22.io_out_uop_ftq_idx, %3753 : i6
    %3797 = comb.mux %3766, %slots_22.io_out_uop_br_tag, %3754 : i5
    %3798 = comb.mux %3766, %slots_22.io_out_uop_br_mask, %3755 : i20
    %3799 = comb.mux %3766, %slots_22.io_out_uop_is_sfb, %3756 : i1
    %3800 = comb.mux %3766, %slots_22.io_out_uop_is_jal, %3757 : i1
    %3801 = comb.mux %3766, %slots_22.io_out_uop_is_jalr, %3758 : i1
    %3802 = comb.mux %3766, %slots_22.io_out_uop_is_br, %3759 : i1
    %3803 = comb.mux %3766, %slots_22.io_out_uop_iw_p2_poisoned, %3760 : i1
    %3804 = comb.mux %3766, %slots_22.io_out_uop_iw_p1_poisoned, %3761 : i1
    %3805 = comb.mux %3766, %slots_22.io_out_uop_iw_state, %3762 : i2
    %3806 = comb.mux %3766, %slots_22.io_out_uop_fu_code, %3763 : i10
    %3807 = comb.mux %3766, %slots_22.io_out_uop_is_rvc, %3764 : i1
    %3808 = comb.mux %3766, %slots_22.io_out_uop_uopc, %3765 : i7
    %3809 = comb.icmp eq %1815, %c-8_i4 : i4
    %issue_slots_23_will_be_valid = sv.wire sym @issue_slots_23_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_23_will_be_valid, %slots_23.io_will_be_valid : i1
    %3810 = comb.mux %3809, %slots_23.io_will_be_valid, %3767 {sv.namehint = "_issue_slots_19_in_uop_valid"} : i1
    %issue_slots_19_in_uop_valid = sv.wire sym @issue_slots_19_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_19_in_uop_valid, %3810 : i1
    %issue_slots_23_out_uop_fp_val = sv.wire sym @issue_slots_23_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_fp_val, %slots_23.io_out_uop_fp_val : i1
    %issue_slots_23_out_uop_lrs2_rtype = sv.wire sym @issue_slots_23_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_23_out_uop_lrs2_rtype, %slots_23.io_out_uop_lrs2_rtype : i2
    %issue_slots_23_out_uop_lrs1_rtype = sv.wire sym @issue_slots_23_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_23_out_uop_lrs1_rtype, %slots_23.io_out_uop_lrs1_rtype : i2
    %issue_slots_23_out_uop_dst_rtype = sv.wire sym @issue_slots_23_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_23_out_uop_dst_rtype, %slots_23.io_out_uop_dst_rtype : i2
    %issue_slots_23_out_uop_ldst_val = sv.wire sym @issue_slots_23_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_ldst_val, %slots_23.io_out_uop_ldst_val : i1
    %issue_slots_23_out_uop_uses_stq = sv.wire sym @issue_slots_23_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_uses_stq, %slots_23.io_out_uop_uses_stq : i1
    %issue_slots_23_out_uop_uses_ldq = sv.wire sym @issue_slots_23_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_uses_ldq, %slots_23.io_out_uop_uses_ldq : i1
    %issue_slots_23_out_uop_is_amo = sv.wire sym @issue_slots_23_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_is_amo, %slots_23.io_out_uop_is_amo : i1
    %issue_slots_23_out_uop_is_fence = sv.wire sym @issue_slots_23_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_is_fence, %slots_23.io_out_uop_is_fence : i1
    %issue_slots_23_out_uop_mem_signed = sv.wire sym @issue_slots_23_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_mem_signed, %slots_23.io_out_uop_mem_signed : i1
    %issue_slots_23_out_uop_mem_size = sv.wire sym @issue_slots_23_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_23_out_uop_mem_size, %slots_23.io_out_uop_mem_size : i2
    %issue_slots_23_out_uop_mem_cmd = sv.wire sym @issue_slots_23_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_23_out_uop_mem_cmd, %slots_23.io_out_uop_mem_cmd : i5
    %issue_slots_23_out_uop_bypassable = sv.wire sym @issue_slots_23_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_bypassable, %slots_23.io_out_uop_bypassable : i1
    %issue_slots_23_out_uop_ppred_busy = sv.wire sym @issue_slots_23_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_ppred_busy, %slots_23.io_out_uop_ppred_busy : i1
    %issue_slots_23_out_uop_prs3_busy = sv.wire sym @issue_slots_23_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_prs3_busy, %slots_23.io_out_uop_prs3_busy : i1
    %issue_slots_23_out_uop_prs2_busy = sv.wire sym @issue_slots_23_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_prs2_busy, %slots_23.io_out_uop_prs2_busy : i1
    %issue_slots_23_out_uop_prs1_busy = sv.wire sym @issue_slots_23_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_prs1_busy, %slots_23.io_out_uop_prs1_busy : i1
    %issue_slots_23_out_uop_prs3 = sv.wire sym @issue_slots_23_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_23_out_uop_prs3, %slots_23.io_out_uop_prs3 : i7
    %issue_slots_23_out_uop_prs2 = sv.wire sym @issue_slots_23_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_23_out_uop_prs2, %slots_23.io_out_uop_prs2 : i7
    %issue_slots_23_out_uop_prs1 = sv.wire sym @issue_slots_23_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_23_out_uop_prs1, %slots_23.io_out_uop_prs1 : i7
    %issue_slots_23_out_uop_pdst = sv.wire sym @issue_slots_23_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_23_out_uop_pdst, %slots_23.io_out_uop_pdst : i7
    %issue_slots_23_out_uop_stq_idx = sv.wire sym @issue_slots_23_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_23_out_uop_stq_idx, %slots_23.io_out_uop_stq_idx : i5
    %issue_slots_23_out_uop_ldq_idx = sv.wire sym @issue_slots_23_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_23_out_uop_ldq_idx, %slots_23.io_out_uop_ldq_idx : i5
    %issue_slots_23_out_uop_rob_idx = sv.wire sym @issue_slots_23_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_23_out_uop_rob_idx, %slots_23.io_out_uop_rob_idx : i7
    %issue_slots_23_out_uop_imm_packed = sv.wire sym @issue_slots_23_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_23_out_uop_imm_packed, %slots_23.io_out_uop_imm_packed : i20
    %issue_slots_23_out_uop_taken = sv.wire sym @issue_slots_23_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_taken, %slots_23.io_out_uop_taken : i1
    %issue_slots_23_out_uop_pc_lob = sv.wire sym @issue_slots_23_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_23_out_uop_pc_lob, %slots_23.io_out_uop_pc_lob : i6
    %issue_slots_23_out_uop_edge_inst = sv.wire sym @issue_slots_23_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_edge_inst, %slots_23.io_out_uop_edge_inst : i1
    %issue_slots_23_out_uop_ftq_idx = sv.wire sym @issue_slots_23_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_23_out_uop_ftq_idx, %slots_23.io_out_uop_ftq_idx : i6
    %issue_slots_23_out_uop_br_tag = sv.wire sym @issue_slots_23_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_23_out_uop_br_tag, %slots_23.io_out_uop_br_tag : i5
    %issue_slots_23_out_uop_br_mask = sv.wire sym @issue_slots_23_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_23_out_uop_br_mask, %slots_23.io_out_uop_br_mask : i20
    %issue_slots_23_out_uop_is_sfb = sv.wire sym @issue_slots_23_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_is_sfb, %slots_23.io_out_uop_is_sfb : i1
    %issue_slots_23_out_uop_is_jal = sv.wire sym @issue_slots_23_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_is_jal, %slots_23.io_out_uop_is_jal : i1
    %issue_slots_23_out_uop_is_jalr = sv.wire sym @issue_slots_23_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_is_jalr, %slots_23.io_out_uop_is_jalr : i1
    %issue_slots_23_out_uop_is_br = sv.wire sym @issue_slots_23_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_is_br, %slots_23.io_out_uop_is_br : i1
    %issue_slots_23_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_23_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_iw_p2_poisoned, %slots_23.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_23_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_23_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_iw_p1_poisoned, %slots_23.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_23_out_uop_iw_state = sv.wire sym @issue_slots_23_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_23_out_uop_iw_state, %slots_23.io_out_uop_iw_state : i2
    %issue_slots_23_out_uop_fu_code = sv.wire sym @issue_slots_23_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_23_out_uop_fu_code, %slots_23.io_out_uop_fu_code : i10
    %issue_slots_23_out_uop_is_rvc = sv.wire sym @issue_slots_23_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_23_out_uop_is_rvc, %slots_23.io_out_uop_is_rvc : i1
    %issue_slots_23_out_uop_uopc = sv.wire sym @issue_slots_23_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_23_out_uop_uopc, %slots_23.io_out_uop_uopc : i7
    %3811 = comb.icmp ne %1783, %c0_i4 {sv.namehint = "_issue_slots_19_clear"} : i4
    %issue_slots_19_clear = sv.wire sym @issue_slots_19_clear  : !hw.inout<i1>
    sv.assign %issue_slots_19_clear, %3811 : i1
    %3812 = comb.icmp eq %1799, %c1_i4 : i4
    %3813 = comb.and %3812, %slots_21.io_will_be_valid : i1
    %3814 = comb.icmp eq %1807, %c2_i4 : i4
    %3815 = comb.mux %3814, %slots_22.io_will_be_valid, %3813 : i1
    %3816 = comb.mux %3814, %slots_22.io_out_uop_fp_val, %slots_21.io_out_uop_fp_val : i1
    %3817 = comb.mux %3814, %slots_22.io_out_uop_lrs2_rtype, %slots_21.io_out_uop_lrs2_rtype : i2
    %3818 = comb.mux %3814, %slots_22.io_out_uop_lrs1_rtype, %slots_21.io_out_uop_lrs1_rtype : i2
    %3819 = comb.mux %3814, %slots_22.io_out_uop_dst_rtype, %slots_21.io_out_uop_dst_rtype : i2
    %3820 = comb.mux %3814, %slots_22.io_out_uop_ldst_val, %slots_21.io_out_uop_ldst_val : i1
    %3821 = comb.mux %3814, %slots_22.io_out_uop_uses_stq, %slots_21.io_out_uop_uses_stq : i1
    %3822 = comb.mux %3814, %slots_22.io_out_uop_uses_ldq, %slots_21.io_out_uop_uses_ldq : i1
    %3823 = comb.mux %3814, %slots_22.io_out_uop_is_amo, %slots_21.io_out_uop_is_amo : i1
    %3824 = comb.mux %3814, %slots_22.io_out_uop_is_fence, %slots_21.io_out_uop_is_fence : i1
    %3825 = comb.mux %3814, %slots_22.io_out_uop_mem_signed, %slots_21.io_out_uop_mem_signed : i1
    %3826 = comb.mux %3814, %slots_22.io_out_uop_mem_size, %slots_21.io_out_uop_mem_size : i2
    %3827 = comb.mux %3814, %slots_22.io_out_uop_mem_cmd, %slots_21.io_out_uop_mem_cmd : i5
    %3828 = comb.mux %3814, %slots_22.io_out_uop_bypassable, %slots_21.io_out_uop_bypassable : i1
    %3829 = comb.mux %3814, %slots_22.io_out_uop_ppred_busy, %slots_21.io_out_uop_ppred_busy : i1
    %3830 = comb.mux %3814, %slots_22.io_out_uop_prs3_busy, %slots_21.io_out_uop_prs3_busy : i1
    %3831 = comb.mux %3814, %slots_22.io_out_uop_prs2_busy, %slots_21.io_out_uop_prs2_busy : i1
    %3832 = comb.mux %3814, %slots_22.io_out_uop_prs1_busy, %slots_21.io_out_uop_prs1_busy : i1
    %3833 = comb.mux %3814, %slots_22.io_out_uop_prs3, %slots_21.io_out_uop_prs3 : i7
    %3834 = comb.mux %3814, %slots_22.io_out_uop_prs2, %slots_21.io_out_uop_prs2 : i7
    %3835 = comb.mux %3814, %slots_22.io_out_uop_prs1, %slots_21.io_out_uop_prs1 : i7
    %3836 = comb.mux %3814, %slots_22.io_out_uop_pdst, %slots_21.io_out_uop_pdst : i7
    %3837 = comb.mux %3814, %slots_22.io_out_uop_stq_idx, %slots_21.io_out_uop_stq_idx : i5
    %3838 = comb.mux %3814, %slots_22.io_out_uop_ldq_idx, %slots_21.io_out_uop_ldq_idx : i5
    %3839 = comb.mux %3814, %slots_22.io_out_uop_rob_idx, %slots_21.io_out_uop_rob_idx : i7
    %3840 = comb.mux %3814, %slots_22.io_out_uop_imm_packed, %slots_21.io_out_uop_imm_packed : i20
    %3841 = comb.mux %3814, %slots_22.io_out_uop_taken, %slots_21.io_out_uop_taken : i1
    %3842 = comb.mux %3814, %slots_22.io_out_uop_pc_lob, %slots_21.io_out_uop_pc_lob : i6
    %3843 = comb.mux %3814, %slots_22.io_out_uop_edge_inst, %slots_21.io_out_uop_edge_inst : i1
    %3844 = comb.mux %3814, %slots_22.io_out_uop_ftq_idx, %slots_21.io_out_uop_ftq_idx : i6
    %3845 = comb.mux %3814, %slots_22.io_out_uop_br_tag, %slots_21.io_out_uop_br_tag : i5
    %3846 = comb.mux %3814, %slots_22.io_out_uop_br_mask, %slots_21.io_out_uop_br_mask : i20
    %3847 = comb.mux %3814, %slots_22.io_out_uop_is_sfb, %slots_21.io_out_uop_is_sfb : i1
    %3848 = comb.mux %3814, %slots_22.io_out_uop_is_jal, %slots_21.io_out_uop_is_jal : i1
    %3849 = comb.mux %3814, %slots_22.io_out_uop_is_jalr, %slots_21.io_out_uop_is_jalr : i1
    %3850 = comb.mux %3814, %slots_22.io_out_uop_is_br, %slots_21.io_out_uop_is_br : i1
    %3851 = comb.mux %3814, %slots_22.io_out_uop_iw_p2_poisoned, %slots_21.io_out_uop_iw_p2_poisoned : i1
    %3852 = comb.mux %3814, %slots_22.io_out_uop_iw_p1_poisoned, %slots_21.io_out_uop_iw_p1_poisoned : i1
    %3853 = comb.mux %3814, %slots_22.io_out_uop_iw_state, %slots_21.io_out_uop_iw_state : i2
    %3854 = comb.mux %3814, %slots_22.io_out_uop_fu_code, %slots_21.io_out_uop_fu_code : i10
    %3855 = comb.mux %3814, %slots_22.io_out_uop_is_rvc, %slots_21.io_out_uop_is_rvc : i1
    %3856 = comb.mux %3814, %slots_22.io_out_uop_uopc, %slots_21.io_out_uop_uopc : i7
    %3857 = comb.icmp eq %1815, %c4_i4 : i4
    %3858 = comb.mux %3857, %slots_23.io_will_be_valid, %3815 : i1
    %3859 = comb.mux %3857, %slots_23.io_out_uop_fp_val, %3816 : i1
    %3860 = comb.mux %3857, %slots_23.io_out_uop_lrs2_rtype, %3817 : i2
    %3861 = comb.mux %3857, %slots_23.io_out_uop_lrs1_rtype, %3818 : i2
    %3862 = comb.mux %3857, %slots_23.io_out_uop_dst_rtype, %3819 : i2
    %3863 = comb.mux %3857, %slots_23.io_out_uop_ldst_val, %3820 : i1
    %3864 = comb.mux %3857, %slots_23.io_out_uop_uses_stq, %3821 : i1
    %3865 = comb.mux %3857, %slots_23.io_out_uop_uses_ldq, %3822 : i1
    %3866 = comb.mux %3857, %slots_23.io_out_uop_is_amo, %3823 : i1
    %3867 = comb.mux %3857, %slots_23.io_out_uop_is_fence, %3824 : i1
    %3868 = comb.mux %3857, %slots_23.io_out_uop_mem_signed, %3825 : i1
    %3869 = comb.mux %3857, %slots_23.io_out_uop_mem_size, %3826 : i2
    %3870 = comb.mux %3857, %slots_23.io_out_uop_mem_cmd, %3827 : i5
    %3871 = comb.mux %3857, %slots_23.io_out_uop_bypassable, %3828 : i1
    %3872 = comb.mux %3857, %slots_23.io_out_uop_ppred_busy, %3829 : i1
    %3873 = comb.mux %3857, %slots_23.io_out_uop_prs3_busy, %3830 : i1
    %3874 = comb.mux %3857, %slots_23.io_out_uop_prs2_busy, %3831 : i1
    %3875 = comb.mux %3857, %slots_23.io_out_uop_prs1_busy, %3832 : i1
    %3876 = comb.mux %3857, %slots_23.io_out_uop_prs3, %3833 : i7
    %3877 = comb.mux %3857, %slots_23.io_out_uop_prs2, %3834 : i7
    %3878 = comb.mux %3857, %slots_23.io_out_uop_prs1, %3835 : i7
    %3879 = comb.mux %3857, %slots_23.io_out_uop_pdst, %3836 : i7
    %3880 = comb.mux %3857, %slots_23.io_out_uop_stq_idx, %3837 : i5
    %3881 = comb.mux %3857, %slots_23.io_out_uop_ldq_idx, %3838 : i5
    %3882 = comb.mux %3857, %slots_23.io_out_uop_rob_idx, %3839 : i7
    %3883 = comb.mux %3857, %slots_23.io_out_uop_imm_packed, %3840 : i20
    %3884 = comb.mux %3857, %slots_23.io_out_uop_taken, %3841 : i1
    %3885 = comb.mux %3857, %slots_23.io_out_uop_pc_lob, %3842 : i6
    %3886 = comb.mux %3857, %slots_23.io_out_uop_edge_inst, %3843 : i1
    %3887 = comb.mux %3857, %slots_23.io_out_uop_ftq_idx, %3844 : i6
    %3888 = comb.mux %3857, %slots_23.io_out_uop_br_tag, %3845 : i5
    %3889 = comb.mux %3857, %slots_23.io_out_uop_br_mask, %3846 : i20
    %3890 = comb.mux %3857, %slots_23.io_out_uop_is_sfb, %3847 : i1
    %3891 = comb.mux %3857, %slots_23.io_out_uop_is_jal, %3848 : i1
    %3892 = comb.mux %3857, %slots_23.io_out_uop_is_jalr, %3849 : i1
    %3893 = comb.mux %3857, %slots_23.io_out_uop_is_br, %3850 : i1
    %3894 = comb.mux %3857, %slots_23.io_out_uop_iw_p2_poisoned, %3851 : i1
    %3895 = comb.mux %3857, %slots_23.io_out_uop_iw_p1_poisoned, %3852 : i1
    %3896 = comb.mux %3857, %slots_23.io_out_uop_iw_state, %3853 : i2
    %3897 = comb.mux %3857, %slots_23.io_out_uop_fu_code, %3854 : i10
    %3898 = comb.mux %3857, %slots_23.io_out_uop_is_rvc, %3855 : i1
    %3899 = comb.mux %3857, %slots_23.io_out_uop_uopc, %3856 : i7
    %3900 = comb.icmp eq %1823, %c-8_i4 : i4
    %issue_slots_24_will_be_valid = sv.wire sym @issue_slots_24_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_24_will_be_valid, %slots_24.io_will_be_valid : i1
    %3901 = comb.mux %3900, %slots_24.io_will_be_valid, %3858 {sv.namehint = "_issue_slots_20_in_uop_valid"} : i1
    %issue_slots_20_in_uop_valid = sv.wire sym @issue_slots_20_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_20_in_uop_valid, %3901 : i1
    %issue_slots_24_out_uop_fp_val = sv.wire sym @issue_slots_24_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_fp_val, %slots_24.io_out_uop_fp_val : i1
    %issue_slots_24_out_uop_lrs2_rtype = sv.wire sym @issue_slots_24_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_24_out_uop_lrs2_rtype, %slots_24.io_out_uop_lrs2_rtype : i2
    %issue_slots_24_out_uop_lrs1_rtype = sv.wire sym @issue_slots_24_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_24_out_uop_lrs1_rtype, %slots_24.io_out_uop_lrs1_rtype : i2
    %issue_slots_24_out_uop_dst_rtype = sv.wire sym @issue_slots_24_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_24_out_uop_dst_rtype, %slots_24.io_out_uop_dst_rtype : i2
    %issue_slots_24_out_uop_ldst_val = sv.wire sym @issue_slots_24_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_ldst_val, %slots_24.io_out_uop_ldst_val : i1
    %issue_slots_24_out_uop_uses_stq = sv.wire sym @issue_slots_24_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_uses_stq, %slots_24.io_out_uop_uses_stq : i1
    %issue_slots_24_out_uop_uses_ldq = sv.wire sym @issue_slots_24_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_uses_ldq, %slots_24.io_out_uop_uses_ldq : i1
    %issue_slots_24_out_uop_is_amo = sv.wire sym @issue_slots_24_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_is_amo, %slots_24.io_out_uop_is_amo : i1
    %issue_slots_24_out_uop_is_fence = sv.wire sym @issue_slots_24_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_is_fence, %slots_24.io_out_uop_is_fence : i1
    %issue_slots_24_out_uop_mem_signed = sv.wire sym @issue_slots_24_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_mem_signed, %slots_24.io_out_uop_mem_signed : i1
    %issue_slots_24_out_uop_mem_size = sv.wire sym @issue_slots_24_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_24_out_uop_mem_size, %slots_24.io_out_uop_mem_size : i2
    %issue_slots_24_out_uop_mem_cmd = sv.wire sym @issue_slots_24_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_24_out_uop_mem_cmd, %slots_24.io_out_uop_mem_cmd : i5
    %issue_slots_24_out_uop_bypassable = sv.wire sym @issue_slots_24_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_bypassable, %slots_24.io_out_uop_bypassable : i1
    %issue_slots_24_out_uop_ppred_busy = sv.wire sym @issue_slots_24_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_ppred_busy, %slots_24.io_out_uop_ppred_busy : i1
    %issue_slots_24_out_uop_prs3_busy = sv.wire sym @issue_slots_24_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_prs3_busy, %slots_24.io_out_uop_prs3_busy : i1
    %issue_slots_24_out_uop_prs2_busy = sv.wire sym @issue_slots_24_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_prs2_busy, %slots_24.io_out_uop_prs2_busy : i1
    %issue_slots_24_out_uop_prs1_busy = sv.wire sym @issue_slots_24_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_prs1_busy, %slots_24.io_out_uop_prs1_busy : i1
    %issue_slots_24_out_uop_prs3 = sv.wire sym @issue_slots_24_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_24_out_uop_prs3, %slots_24.io_out_uop_prs3 : i7
    %issue_slots_24_out_uop_prs2 = sv.wire sym @issue_slots_24_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_24_out_uop_prs2, %slots_24.io_out_uop_prs2 : i7
    %issue_slots_24_out_uop_prs1 = sv.wire sym @issue_slots_24_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_24_out_uop_prs1, %slots_24.io_out_uop_prs1 : i7
    %issue_slots_24_out_uop_pdst = sv.wire sym @issue_slots_24_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_24_out_uop_pdst, %slots_24.io_out_uop_pdst : i7
    %issue_slots_24_out_uop_stq_idx = sv.wire sym @issue_slots_24_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_24_out_uop_stq_idx, %slots_24.io_out_uop_stq_idx : i5
    %issue_slots_24_out_uop_ldq_idx = sv.wire sym @issue_slots_24_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_24_out_uop_ldq_idx, %slots_24.io_out_uop_ldq_idx : i5
    %issue_slots_24_out_uop_rob_idx = sv.wire sym @issue_slots_24_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_24_out_uop_rob_idx, %slots_24.io_out_uop_rob_idx : i7
    %issue_slots_24_out_uop_imm_packed = sv.wire sym @issue_slots_24_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_24_out_uop_imm_packed, %slots_24.io_out_uop_imm_packed : i20
    %issue_slots_24_out_uop_taken = sv.wire sym @issue_slots_24_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_taken, %slots_24.io_out_uop_taken : i1
    %issue_slots_24_out_uop_pc_lob = sv.wire sym @issue_slots_24_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_24_out_uop_pc_lob, %slots_24.io_out_uop_pc_lob : i6
    %issue_slots_24_out_uop_edge_inst = sv.wire sym @issue_slots_24_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_edge_inst, %slots_24.io_out_uop_edge_inst : i1
    %issue_slots_24_out_uop_ftq_idx = sv.wire sym @issue_slots_24_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_24_out_uop_ftq_idx, %slots_24.io_out_uop_ftq_idx : i6
    %issue_slots_24_out_uop_br_tag = sv.wire sym @issue_slots_24_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_24_out_uop_br_tag, %slots_24.io_out_uop_br_tag : i5
    %issue_slots_24_out_uop_br_mask = sv.wire sym @issue_slots_24_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_24_out_uop_br_mask, %slots_24.io_out_uop_br_mask : i20
    %issue_slots_24_out_uop_is_sfb = sv.wire sym @issue_slots_24_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_is_sfb, %slots_24.io_out_uop_is_sfb : i1
    %issue_slots_24_out_uop_is_jal = sv.wire sym @issue_slots_24_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_is_jal, %slots_24.io_out_uop_is_jal : i1
    %issue_slots_24_out_uop_is_jalr = sv.wire sym @issue_slots_24_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_is_jalr, %slots_24.io_out_uop_is_jalr : i1
    %issue_slots_24_out_uop_is_br = sv.wire sym @issue_slots_24_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_is_br, %slots_24.io_out_uop_is_br : i1
    %issue_slots_24_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_24_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_iw_p2_poisoned, %slots_24.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_24_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_24_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_iw_p1_poisoned, %slots_24.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_24_out_uop_iw_state = sv.wire sym @issue_slots_24_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_24_out_uop_iw_state, %slots_24.io_out_uop_iw_state : i2
    %issue_slots_24_out_uop_fu_code = sv.wire sym @issue_slots_24_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_24_out_uop_fu_code, %slots_24.io_out_uop_fu_code : i10
    %issue_slots_24_out_uop_is_rvc = sv.wire sym @issue_slots_24_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_24_out_uop_is_rvc, %slots_24.io_out_uop_is_rvc : i1
    %issue_slots_24_out_uop_uopc = sv.wire sym @issue_slots_24_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_24_out_uop_uopc, %slots_24.io_out_uop_uopc : i7
    %3902 = comb.icmp ne %1791, %c0_i4 {sv.namehint = "_issue_slots_20_clear"} : i4
    %issue_slots_20_clear = sv.wire sym @issue_slots_20_clear  : !hw.inout<i1>
    sv.assign %issue_slots_20_clear, %3902 : i1
    %3903 = comb.icmp eq %1807, %c1_i4 : i4
    %3904 = comb.and %3903, %slots_22.io_will_be_valid : i1
    %3905 = comb.icmp eq %1815, %c2_i4 : i4
    %3906 = comb.mux %3905, %slots_23.io_will_be_valid, %3904 : i1
    %3907 = comb.mux %3905, %slots_23.io_out_uop_fp_val, %slots_22.io_out_uop_fp_val : i1
    %3908 = comb.mux %3905, %slots_23.io_out_uop_lrs2_rtype, %slots_22.io_out_uop_lrs2_rtype : i2
    %3909 = comb.mux %3905, %slots_23.io_out_uop_lrs1_rtype, %slots_22.io_out_uop_lrs1_rtype : i2
    %3910 = comb.mux %3905, %slots_23.io_out_uop_dst_rtype, %slots_22.io_out_uop_dst_rtype : i2
    %3911 = comb.mux %3905, %slots_23.io_out_uop_ldst_val, %slots_22.io_out_uop_ldst_val : i1
    %3912 = comb.mux %3905, %slots_23.io_out_uop_uses_stq, %slots_22.io_out_uop_uses_stq : i1
    %3913 = comb.mux %3905, %slots_23.io_out_uop_uses_ldq, %slots_22.io_out_uop_uses_ldq : i1
    %3914 = comb.mux %3905, %slots_23.io_out_uop_is_amo, %slots_22.io_out_uop_is_amo : i1
    %3915 = comb.mux %3905, %slots_23.io_out_uop_is_fence, %slots_22.io_out_uop_is_fence : i1
    %3916 = comb.mux %3905, %slots_23.io_out_uop_mem_signed, %slots_22.io_out_uop_mem_signed : i1
    %3917 = comb.mux %3905, %slots_23.io_out_uop_mem_size, %slots_22.io_out_uop_mem_size : i2
    %3918 = comb.mux %3905, %slots_23.io_out_uop_mem_cmd, %slots_22.io_out_uop_mem_cmd : i5
    %3919 = comb.mux %3905, %slots_23.io_out_uop_bypassable, %slots_22.io_out_uop_bypassable : i1
    %3920 = comb.mux %3905, %slots_23.io_out_uop_ppred_busy, %slots_22.io_out_uop_ppred_busy : i1
    %3921 = comb.mux %3905, %slots_23.io_out_uop_prs3_busy, %slots_22.io_out_uop_prs3_busy : i1
    %3922 = comb.mux %3905, %slots_23.io_out_uop_prs2_busy, %slots_22.io_out_uop_prs2_busy : i1
    %3923 = comb.mux %3905, %slots_23.io_out_uop_prs1_busy, %slots_22.io_out_uop_prs1_busy : i1
    %3924 = comb.mux %3905, %slots_23.io_out_uop_prs3, %slots_22.io_out_uop_prs3 : i7
    %3925 = comb.mux %3905, %slots_23.io_out_uop_prs2, %slots_22.io_out_uop_prs2 : i7
    %3926 = comb.mux %3905, %slots_23.io_out_uop_prs1, %slots_22.io_out_uop_prs1 : i7
    %3927 = comb.mux %3905, %slots_23.io_out_uop_pdst, %slots_22.io_out_uop_pdst : i7
    %3928 = comb.mux %3905, %slots_23.io_out_uop_stq_idx, %slots_22.io_out_uop_stq_idx : i5
    %3929 = comb.mux %3905, %slots_23.io_out_uop_ldq_idx, %slots_22.io_out_uop_ldq_idx : i5
    %3930 = comb.mux %3905, %slots_23.io_out_uop_rob_idx, %slots_22.io_out_uop_rob_idx : i7
    %3931 = comb.mux %3905, %slots_23.io_out_uop_imm_packed, %slots_22.io_out_uop_imm_packed : i20
    %3932 = comb.mux %3905, %slots_23.io_out_uop_taken, %slots_22.io_out_uop_taken : i1
    %3933 = comb.mux %3905, %slots_23.io_out_uop_pc_lob, %slots_22.io_out_uop_pc_lob : i6
    %3934 = comb.mux %3905, %slots_23.io_out_uop_edge_inst, %slots_22.io_out_uop_edge_inst : i1
    %3935 = comb.mux %3905, %slots_23.io_out_uop_ftq_idx, %slots_22.io_out_uop_ftq_idx : i6
    %3936 = comb.mux %3905, %slots_23.io_out_uop_br_tag, %slots_22.io_out_uop_br_tag : i5
    %3937 = comb.mux %3905, %slots_23.io_out_uop_br_mask, %slots_22.io_out_uop_br_mask : i20
    %3938 = comb.mux %3905, %slots_23.io_out_uop_is_sfb, %slots_22.io_out_uop_is_sfb : i1
    %3939 = comb.mux %3905, %slots_23.io_out_uop_is_jal, %slots_22.io_out_uop_is_jal : i1
    %3940 = comb.mux %3905, %slots_23.io_out_uop_is_jalr, %slots_22.io_out_uop_is_jalr : i1
    %3941 = comb.mux %3905, %slots_23.io_out_uop_is_br, %slots_22.io_out_uop_is_br : i1
    %3942 = comb.mux %3905, %slots_23.io_out_uop_iw_p2_poisoned, %slots_22.io_out_uop_iw_p2_poisoned : i1
    %3943 = comb.mux %3905, %slots_23.io_out_uop_iw_p1_poisoned, %slots_22.io_out_uop_iw_p1_poisoned : i1
    %3944 = comb.mux %3905, %slots_23.io_out_uop_iw_state, %slots_22.io_out_uop_iw_state : i2
    %3945 = comb.mux %3905, %slots_23.io_out_uop_fu_code, %slots_22.io_out_uop_fu_code : i10
    %3946 = comb.mux %3905, %slots_23.io_out_uop_is_rvc, %slots_22.io_out_uop_is_rvc : i1
    %3947 = comb.mux %3905, %slots_23.io_out_uop_uopc, %slots_22.io_out_uop_uopc : i7
    %3948 = comb.icmp eq %1823, %c4_i4 : i4
    %3949 = comb.mux %3948, %slots_24.io_will_be_valid, %3906 : i1
    %3950 = comb.mux %3948, %slots_24.io_out_uop_fp_val, %3907 : i1
    %3951 = comb.mux %3948, %slots_24.io_out_uop_lrs2_rtype, %3908 : i2
    %3952 = comb.mux %3948, %slots_24.io_out_uop_lrs1_rtype, %3909 : i2
    %3953 = comb.mux %3948, %slots_24.io_out_uop_dst_rtype, %3910 : i2
    %3954 = comb.mux %3948, %slots_24.io_out_uop_ldst_val, %3911 : i1
    %3955 = comb.mux %3948, %slots_24.io_out_uop_uses_stq, %3912 : i1
    %3956 = comb.mux %3948, %slots_24.io_out_uop_uses_ldq, %3913 : i1
    %3957 = comb.mux %3948, %slots_24.io_out_uop_is_amo, %3914 : i1
    %3958 = comb.mux %3948, %slots_24.io_out_uop_is_fence, %3915 : i1
    %3959 = comb.mux %3948, %slots_24.io_out_uop_mem_signed, %3916 : i1
    %3960 = comb.mux %3948, %slots_24.io_out_uop_mem_size, %3917 : i2
    %3961 = comb.mux %3948, %slots_24.io_out_uop_mem_cmd, %3918 : i5
    %3962 = comb.mux %3948, %slots_24.io_out_uop_bypassable, %3919 : i1
    %3963 = comb.mux %3948, %slots_24.io_out_uop_ppred_busy, %3920 : i1
    %3964 = comb.mux %3948, %slots_24.io_out_uop_prs3_busy, %3921 : i1
    %3965 = comb.mux %3948, %slots_24.io_out_uop_prs2_busy, %3922 : i1
    %3966 = comb.mux %3948, %slots_24.io_out_uop_prs1_busy, %3923 : i1
    %3967 = comb.mux %3948, %slots_24.io_out_uop_prs3, %3924 : i7
    %3968 = comb.mux %3948, %slots_24.io_out_uop_prs2, %3925 : i7
    %3969 = comb.mux %3948, %slots_24.io_out_uop_prs1, %3926 : i7
    %3970 = comb.mux %3948, %slots_24.io_out_uop_pdst, %3927 : i7
    %3971 = comb.mux %3948, %slots_24.io_out_uop_stq_idx, %3928 : i5
    %3972 = comb.mux %3948, %slots_24.io_out_uop_ldq_idx, %3929 : i5
    %3973 = comb.mux %3948, %slots_24.io_out_uop_rob_idx, %3930 : i7
    %3974 = comb.mux %3948, %slots_24.io_out_uop_imm_packed, %3931 : i20
    %3975 = comb.mux %3948, %slots_24.io_out_uop_taken, %3932 : i1
    %3976 = comb.mux %3948, %slots_24.io_out_uop_pc_lob, %3933 : i6
    %3977 = comb.mux %3948, %slots_24.io_out_uop_edge_inst, %3934 : i1
    %3978 = comb.mux %3948, %slots_24.io_out_uop_ftq_idx, %3935 : i6
    %3979 = comb.mux %3948, %slots_24.io_out_uop_br_tag, %3936 : i5
    %3980 = comb.mux %3948, %slots_24.io_out_uop_br_mask, %3937 : i20
    %3981 = comb.mux %3948, %slots_24.io_out_uop_is_sfb, %3938 : i1
    %3982 = comb.mux %3948, %slots_24.io_out_uop_is_jal, %3939 : i1
    %3983 = comb.mux %3948, %slots_24.io_out_uop_is_jalr, %3940 : i1
    %3984 = comb.mux %3948, %slots_24.io_out_uop_is_br, %3941 : i1
    %3985 = comb.mux %3948, %slots_24.io_out_uop_iw_p2_poisoned, %3942 : i1
    %3986 = comb.mux %3948, %slots_24.io_out_uop_iw_p1_poisoned, %3943 : i1
    %3987 = comb.mux %3948, %slots_24.io_out_uop_iw_state, %3944 : i2
    %3988 = comb.mux %3948, %slots_24.io_out_uop_fu_code, %3945 : i10
    %3989 = comb.mux %3948, %slots_24.io_out_uop_is_rvc, %3946 : i1
    %3990 = comb.mux %3948, %slots_24.io_out_uop_uopc, %3947 : i7
    %3991 = comb.icmp eq %1831, %c-8_i4 : i4
    %issue_slots_25_will_be_valid = sv.wire sym @issue_slots_25_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_25_will_be_valid, %slots_25.io_will_be_valid : i1
    %3992 = comb.mux %3991, %slots_25.io_will_be_valid, %3949 {sv.namehint = "_issue_slots_21_in_uop_valid"} : i1
    %issue_slots_21_in_uop_valid = sv.wire sym @issue_slots_21_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_21_in_uop_valid, %3992 : i1
    %issue_slots_25_out_uop_fp_val = sv.wire sym @issue_slots_25_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_fp_val, %slots_25.io_out_uop_fp_val : i1
    %issue_slots_25_out_uop_lrs2_rtype = sv.wire sym @issue_slots_25_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_25_out_uop_lrs2_rtype, %slots_25.io_out_uop_lrs2_rtype : i2
    %issue_slots_25_out_uop_lrs1_rtype = sv.wire sym @issue_slots_25_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_25_out_uop_lrs1_rtype, %slots_25.io_out_uop_lrs1_rtype : i2
    %issue_slots_25_out_uop_dst_rtype = sv.wire sym @issue_slots_25_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_25_out_uop_dst_rtype, %slots_25.io_out_uop_dst_rtype : i2
    %issue_slots_25_out_uop_ldst_val = sv.wire sym @issue_slots_25_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_ldst_val, %slots_25.io_out_uop_ldst_val : i1
    %issue_slots_25_out_uop_uses_stq = sv.wire sym @issue_slots_25_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_uses_stq, %slots_25.io_out_uop_uses_stq : i1
    %issue_slots_25_out_uop_uses_ldq = sv.wire sym @issue_slots_25_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_uses_ldq, %slots_25.io_out_uop_uses_ldq : i1
    %issue_slots_25_out_uop_is_amo = sv.wire sym @issue_slots_25_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_is_amo, %slots_25.io_out_uop_is_amo : i1
    %issue_slots_25_out_uop_is_fence = sv.wire sym @issue_slots_25_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_is_fence, %slots_25.io_out_uop_is_fence : i1
    %issue_slots_25_out_uop_mem_signed = sv.wire sym @issue_slots_25_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_mem_signed, %slots_25.io_out_uop_mem_signed : i1
    %issue_slots_25_out_uop_mem_size = sv.wire sym @issue_slots_25_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_25_out_uop_mem_size, %slots_25.io_out_uop_mem_size : i2
    %issue_slots_25_out_uop_mem_cmd = sv.wire sym @issue_slots_25_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_25_out_uop_mem_cmd, %slots_25.io_out_uop_mem_cmd : i5
    %issue_slots_25_out_uop_bypassable = sv.wire sym @issue_slots_25_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_bypassable, %slots_25.io_out_uop_bypassable : i1
    %issue_slots_25_out_uop_ppred_busy = sv.wire sym @issue_slots_25_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_ppred_busy, %slots_25.io_out_uop_ppred_busy : i1
    %issue_slots_25_out_uop_prs3_busy = sv.wire sym @issue_slots_25_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_prs3_busy, %slots_25.io_out_uop_prs3_busy : i1
    %issue_slots_25_out_uop_prs2_busy = sv.wire sym @issue_slots_25_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_prs2_busy, %slots_25.io_out_uop_prs2_busy : i1
    %issue_slots_25_out_uop_prs1_busy = sv.wire sym @issue_slots_25_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_prs1_busy, %slots_25.io_out_uop_prs1_busy : i1
    %issue_slots_25_out_uop_prs3 = sv.wire sym @issue_slots_25_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_25_out_uop_prs3, %slots_25.io_out_uop_prs3 : i7
    %issue_slots_25_out_uop_prs2 = sv.wire sym @issue_slots_25_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_25_out_uop_prs2, %slots_25.io_out_uop_prs2 : i7
    %issue_slots_25_out_uop_prs1 = sv.wire sym @issue_slots_25_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_25_out_uop_prs1, %slots_25.io_out_uop_prs1 : i7
    %issue_slots_25_out_uop_pdst = sv.wire sym @issue_slots_25_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_25_out_uop_pdst, %slots_25.io_out_uop_pdst : i7
    %issue_slots_25_out_uop_stq_idx = sv.wire sym @issue_slots_25_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_25_out_uop_stq_idx, %slots_25.io_out_uop_stq_idx : i5
    %issue_slots_25_out_uop_ldq_idx = sv.wire sym @issue_slots_25_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_25_out_uop_ldq_idx, %slots_25.io_out_uop_ldq_idx : i5
    %issue_slots_25_out_uop_rob_idx = sv.wire sym @issue_slots_25_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_25_out_uop_rob_idx, %slots_25.io_out_uop_rob_idx : i7
    %issue_slots_25_out_uop_imm_packed = sv.wire sym @issue_slots_25_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_25_out_uop_imm_packed, %slots_25.io_out_uop_imm_packed : i20
    %issue_slots_25_out_uop_taken = sv.wire sym @issue_slots_25_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_taken, %slots_25.io_out_uop_taken : i1
    %issue_slots_25_out_uop_pc_lob = sv.wire sym @issue_slots_25_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_25_out_uop_pc_lob, %slots_25.io_out_uop_pc_lob : i6
    %issue_slots_25_out_uop_edge_inst = sv.wire sym @issue_slots_25_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_edge_inst, %slots_25.io_out_uop_edge_inst : i1
    %issue_slots_25_out_uop_ftq_idx = sv.wire sym @issue_slots_25_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_25_out_uop_ftq_idx, %slots_25.io_out_uop_ftq_idx : i6
    %issue_slots_25_out_uop_br_tag = sv.wire sym @issue_slots_25_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_25_out_uop_br_tag, %slots_25.io_out_uop_br_tag : i5
    %issue_slots_25_out_uop_br_mask = sv.wire sym @issue_slots_25_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_25_out_uop_br_mask, %slots_25.io_out_uop_br_mask : i20
    %issue_slots_25_out_uop_is_sfb = sv.wire sym @issue_slots_25_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_is_sfb, %slots_25.io_out_uop_is_sfb : i1
    %issue_slots_25_out_uop_is_jal = sv.wire sym @issue_slots_25_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_is_jal, %slots_25.io_out_uop_is_jal : i1
    %issue_slots_25_out_uop_is_jalr = sv.wire sym @issue_slots_25_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_is_jalr, %slots_25.io_out_uop_is_jalr : i1
    %issue_slots_25_out_uop_is_br = sv.wire sym @issue_slots_25_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_is_br, %slots_25.io_out_uop_is_br : i1
    %issue_slots_25_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_25_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_iw_p2_poisoned, %slots_25.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_25_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_25_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_iw_p1_poisoned, %slots_25.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_25_out_uop_iw_state = sv.wire sym @issue_slots_25_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_25_out_uop_iw_state, %slots_25.io_out_uop_iw_state : i2
    %issue_slots_25_out_uop_fu_code = sv.wire sym @issue_slots_25_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_25_out_uop_fu_code, %slots_25.io_out_uop_fu_code : i10
    %issue_slots_25_out_uop_is_rvc = sv.wire sym @issue_slots_25_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_25_out_uop_is_rvc, %slots_25.io_out_uop_is_rvc : i1
    %issue_slots_25_out_uop_uopc = sv.wire sym @issue_slots_25_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_25_out_uop_uopc, %slots_25.io_out_uop_uopc : i7
    %3993 = comb.icmp ne %1799, %c0_i4 {sv.namehint = "_issue_slots_21_clear"} : i4
    %issue_slots_21_clear = sv.wire sym @issue_slots_21_clear  : !hw.inout<i1>
    sv.assign %issue_slots_21_clear, %3993 : i1
    %3994 = comb.icmp eq %1815, %c1_i4 : i4
    %3995 = comb.and %3994, %slots_23.io_will_be_valid : i1
    %3996 = comb.icmp eq %1823, %c2_i4 : i4
    %3997 = comb.mux %3996, %slots_24.io_will_be_valid, %3995 : i1
    %3998 = comb.mux %3996, %slots_24.io_out_uop_fp_val, %slots_23.io_out_uop_fp_val : i1
    %3999 = comb.mux %3996, %slots_24.io_out_uop_lrs2_rtype, %slots_23.io_out_uop_lrs2_rtype : i2
    %4000 = comb.mux %3996, %slots_24.io_out_uop_lrs1_rtype, %slots_23.io_out_uop_lrs1_rtype : i2
    %4001 = comb.mux %3996, %slots_24.io_out_uop_dst_rtype, %slots_23.io_out_uop_dst_rtype : i2
    %4002 = comb.mux %3996, %slots_24.io_out_uop_ldst_val, %slots_23.io_out_uop_ldst_val : i1
    %4003 = comb.mux %3996, %slots_24.io_out_uop_uses_stq, %slots_23.io_out_uop_uses_stq : i1
    %4004 = comb.mux %3996, %slots_24.io_out_uop_uses_ldq, %slots_23.io_out_uop_uses_ldq : i1
    %4005 = comb.mux %3996, %slots_24.io_out_uop_is_amo, %slots_23.io_out_uop_is_amo : i1
    %4006 = comb.mux %3996, %slots_24.io_out_uop_is_fence, %slots_23.io_out_uop_is_fence : i1
    %4007 = comb.mux %3996, %slots_24.io_out_uop_mem_signed, %slots_23.io_out_uop_mem_signed : i1
    %4008 = comb.mux %3996, %slots_24.io_out_uop_mem_size, %slots_23.io_out_uop_mem_size : i2
    %4009 = comb.mux %3996, %slots_24.io_out_uop_mem_cmd, %slots_23.io_out_uop_mem_cmd : i5
    %4010 = comb.mux %3996, %slots_24.io_out_uop_bypassable, %slots_23.io_out_uop_bypassable : i1
    %4011 = comb.mux %3996, %slots_24.io_out_uop_ppred_busy, %slots_23.io_out_uop_ppred_busy : i1
    %4012 = comb.mux %3996, %slots_24.io_out_uop_prs3_busy, %slots_23.io_out_uop_prs3_busy : i1
    %4013 = comb.mux %3996, %slots_24.io_out_uop_prs2_busy, %slots_23.io_out_uop_prs2_busy : i1
    %4014 = comb.mux %3996, %slots_24.io_out_uop_prs1_busy, %slots_23.io_out_uop_prs1_busy : i1
    %4015 = comb.mux %3996, %slots_24.io_out_uop_prs3, %slots_23.io_out_uop_prs3 : i7
    %4016 = comb.mux %3996, %slots_24.io_out_uop_prs2, %slots_23.io_out_uop_prs2 : i7
    %4017 = comb.mux %3996, %slots_24.io_out_uop_prs1, %slots_23.io_out_uop_prs1 : i7
    %4018 = comb.mux %3996, %slots_24.io_out_uop_pdst, %slots_23.io_out_uop_pdst : i7
    %4019 = comb.mux %3996, %slots_24.io_out_uop_stq_idx, %slots_23.io_out_uop_stq_idx : i5
    %4020 = comb.mux %3996, %slots_24.io_out_uop_ldq_idx, %slots_23.io_out_uop_ldq_idx : i5
    %4021 = comb.mux %3996, %slots_24.io_out_uop_rob_idx, %slots_23.io_out_uop_rob_idx : i7
    %4022 = comb.mux %3996, %slots_24.io_out_uop_imm_packed, %slots_23.io_out_uop_imm_packed : i20
    %4023 = comb.mux %3996, %slots_24.io_out_uop_taken, %slots_23.io_out_uop_taken : i1
    %4024 = comb.mux %3996, %slots_24.io_out_uop_pc_lob, %slots_23.io_out_uop_pc_lob : i6
    %4025 = comb.mux %3996, %slots_24.io_out_uop_edge_inst, %slots_23.io_out_uop_edge_inst : i1
    %4026 = comb.mux %3996, %slots_24.io_out_uop_ftq_idx, %slots_23.io_out_uop_ftq_idx : i6
    %4027 = comb.mux %3996, %slots_24.io_out_uop_br_tag, %slots_23.io_out_uop_br_tag : i5
    %4028 = comb.mux %3996, %slots_24.io_out_uop_br_mask, %slots_23.io_out_uop_br_mask : i20
    %4029 = comb.mux %3996, %slots_24.io_out_uop_is_sfb, %slots_23.io_out_uop_is_sfb : i1
    %4030 = comb.mux %3996, %slots_24.io_out_uop_is_jal, %slots_23.io_out_uop_is_jal : i1
    %4031 = comb.mux %3996, %slots_24.io_out_uop_is_jalr, %slots_23.io_out_uop_is_jalr : i1
    %4032 = comb.mux %3996, %slots_24.io_out_uop_is_br, %slots_23.io_out_uop_is_br : i1
    %4033 = comb.mux %3996, %slots_24.io_out_uop_iw_p2_poisoned, %slots_23.io_out_uop_iw_p2_poisoned : i1
    %4034 = comb.mux %3996, %slots_24.io_out_uop_iw_p1_poisoned, %slots_23.io_out_uop_iw_p1_poisoned : i1
    %4035 = comb.mux %3996, %slots_24.io_out_uop_iw_state, %slots_23.io_out_uop_iw_state : i2
    %4036 = comb.mux %3996, %slots_24.io_out_uop_fu_code, %slots_23.io_out_uop_fu_code : i10
    %4037 = comb.mux %3996, %slots_24.io_out_uop_is_rvc, %slots_23.io_out_uop_is_rvc : i1
    %4038 = comb.mux %3996, %slots_24.io_out_uop_uopc, %slots_23.io_out_uop_uopc : i7
    %4039 = comb.icmp eq %1831, %c4_i4 : i4
    %4040 = comb.mux %4039, %slots_25.io_will_be_valid, %3997 : i1
    %4041 = comb.mux %4039, %slots_25.io_out_uop_fp_val, %3998 : i1
    %4042 = comb.mux %4039, %slots_25.io_out_uop_lrs2_rtype, %3999 : i2
    %4043 = comb.mux %4039, %slots_25.io_out_uop_lrs1_rtype, %4000 : i2
    %4044 = comb.mux %4039, %slots_25.io_out_uop_dst_rtype, %4001 : i2
    %4045 = comb.mux %4039, %slots_25.io_out_uop_ldst_val, %4002 : i1
    %4046 = comb.mux %4039, %slots_25.io_out_uop_uses_stq, %4003 : i1
    %4047 = comb.mux %4039, %slots_25.io_out_uop_uses_ldq, %4004 : i1
    %4048 = comb.mux %4039, %slots_25.io_out_uop_is_amo, %4005 : i1
    %4049 = comb.mux %4039, %slots_25.io_out_uop_is_fence, %4006 : i1
    %4050 = comb.mux %4039, %slots_25.io_out_uop_mem_signed, %4007 : i1
    %4051 = comb.mux %4039, %slots_25.io_out_uop_mem_size, %4008 : i2
    %4052 = comb.mux %4039, %slots_25.io_out_uop_mem_cmd, %4009 : i5
    %4053 = comb.mux %4039, %slots_25.io_out_uop_bypassable, %4010 : i1
    %4054 = comb.mux %4039, %slots_25.io_out_uop_ppred_busy, %4011 : i1
    %4055 = comb.mux %4039, %slots_25.io_out_uop_prs3_busy, %4012 : i1
    %4056 = comb.mux %4039, %slots_25.io_out_uop_prs2_busy, %4013 : i1
    %4057 = comb.mux %4039, %slots_25.io_out_uop_prs1_busy, %4014 : i1
    %4058 = comb.mux %4039, %slots_25.io_out_uop_prs3, %4015 : i7
    %4059 = comb.mux %4039, %slots_25.io_out_uop_prs2, %4016 : i7
    %4060 = comb.mux %4039, %slots_25.io_out_uop_prs1, %4017 : i7
    %4061 = comb.mux %4039, %slots_25.io_out_uop_pdst, %4018 : i7
    %4062 = comb.mux %4039, %slots_25.io_out_uop_stq_idx, %4019 : i5
    %4063 = comb.mux %4039, %slots_25.io_out_uop_ldq_idx, %4020 : i5
    %4064 = comb.mux %4039, %slots_25.io_out_uop_rob_idx, %4021 : i7
    %4065 = comb.mux %4039, %slots_25.io_out_uop_imm_packed, %4022 : i20
    %4066 = comb.mux %4039, %slots_25.io_out_uop_taken, %4023 : i1
    %4067 = comb.mux %4039, %slots_25.io_out_uop_pc_lob, %4024 : i6
    %4068 = comb.mux %4039, %slots_25.io_out_uop_edge_inst, %4025 : i1
    %4069 = comb.mux %4039, %slots_25.io_out_uop_ftq_idx, %4026 : i6
    %4070 = comb.mux %4039, %slots_25.io_out_uop_br_tag, %4027 : i5
    %4071 = comb.mux %4039, %slots_25.io_out_uop_br_mask, %4028 : i20
    %4072 = comb.mux %4039, %slots_25.io_out_uop_is_sfb, %4029 : i1
    %4073 = comb.mux %4039, %slots_25.io_out_uop_is_jal, %4030 : i1
    %4074 = comb.mux %4039, %slots_25.io_out_uop_is_jalr, %4031 : i1
    %4075 = comb.mux %4039, %slots_25.io_out_uop_is_br, %4032 : i1
    %4076 = comb.mux %4039, %slots_25.io_out_uop_iw_p2_poisoned, %4033 : i1
    %4077 = comb.mux %4039, %slots_25.io_out_uop_iw_p1_poisoned, %4034 : i1
    %4078 = comb.mux %4039, %slots_25.io_out_uop_iw_state, %4035 : i2
    %4079 = comb.mux %4039, %slots_25.io_out_uop_fu_code, %4036 : i10
    %4080 = comb.mux %4039, %slots_25.io_out_uop_is_rvc, %4037 : i1
    %4081 = comb.mux %4039, %slots_25.io_out_uop_uopc, %4038 : i7
    %4082 = comb.icmp eq %1839, %c-8_i4 : i4
    %issue_slots_26_will_be_valid = sv.wire sym @issue_slots_26_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_26_will_be_valid, %slots_26.io_will_be_valid : i1
    %4083 = comb.mux %4082, %slots_26.io_will_be_valid, %4040 {sv.namehint = "_issue_slots_22_in_uop_valid"} : i1
    %issue_slots_22_in_uop_valid = sv.wire sym @issue_slots_22_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_22_in_uop_valid, %4083 : i1
    %issue_slots_26_out_uop_fp_val = sv.wire sym @issue_slots_26_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_fp_val, %slots_26.io_out_uop_fp_val : i1
    %issue_slots_26_out_uop_lrs2_rtype = sv.wire sym @issue_slots_26_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_26_out_uop_lrs2_rtype, %slots_26.io_out_uop_lrs2_rtype : i2
    %issue_slots_26_out_uop_lrs1_rtype = sv.wire sym @issue_slots_26_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_26_out_uop_lrs1_rtype, %slots_26.io_out_uop_lrs1_rtype : i2
    %issue_slots_26_out_uop_dst_rtype = sv.wire sym @issue_slots_26_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_26_out_uop_dst_rtype, %slots_26.io_out_uop_dst_rtype : i2
    %issue_slots_26_out_uop_ldst_val = sv.wire sym @issue_slots_26_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_ldst_val, %slots_26.io_out_uop_ldst_val : i1
    %issue_slots_26_out_uop_uses_stq = sv.wire sym @issue_slots_26_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_uses_stq, %slots_26.io_out_uop_uses_stq : i1
    %issue_slots_26_out_uop_uses_ldq = sv.wire sym @issue_slots_26_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_uses_ldq, %slots_26.io_out_uop_uses_ldq : i1
    %issue_slots_26_out_uop_is_amo = sv.wire sym @issue_slots_26_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_is_amo, %slots_26.io_out_uop_is_amo : i1
    %issue_slots_26_out_uop_is_fence = sv.wire sym @issue_slots_26_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_is_fence, %slots_26.io_out_uop_is_fence : i1
    %issue_slots_26_out_uop_mem_signed = sv.wire sym @issue_slots_26_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_mem_signed, %slots_26.io_out_uop_mem_signed : i1
    %issue_slots_26_out_uop_mem_size = sv.wire sym @issue_slots_26_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_26_out_uop_mem_size, %slots_26.io_out_uop_mem_size : i2
    %issue_slots_26_out_uop_mem_cmd = sv.wire sym @issue_slots_26_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_26_out_uop_mem_cmd, %slots_26.io_out_uop_mem_cmd : i5
    %issue_slots_26_out_uop_bypassable = sv.wire sym @issue_slots_26_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_bypassable, %slots_26.io_out_uop_bypassable : i1
    %issue_slots_26_out_uop_ppred_busy = sv.wire sym @issue_slots_26_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_ppred_busy, %slots_26.io_out_uop_ppred_busy : i1
    %issue_slots_26_out_uop_prs3_busy = sv.wire sym @issue_slots_26_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_prs3_busy, %slots_26.io_out_uop_prs3_busy : i1
    %issue_slots_26_out_uop_prs2_busy = sv.wire sym @issue_slots_26_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_prs2_busy, %slots_26.io_out_uop_prs2_busy : i1
    %issue_slots_26_out_uop_prs1_busy = sv.wire sym @issue_slots_26_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_prs1_busy, %slots_26.io_out_uop_prs1_busy : i1
    %issue_slots_26_out_uop_prs3 = sv.wire sym @issue_slots_26_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_26_out_uop_prs3, %slots_26.io_out_uop_prs3 : i7
    %issue_slots_26_out_uop_prs2 = sv.wire sym @issue_slots_26_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_26_out_uop_prs2, %slots_26.io_out_uop_prs2 : i7
    %issue_slots_26_out_uop_prs1 = sv.wire sym @issue_slots_26_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_26_out_uop_prs1, %slots_26.io_out_uop_prs1 : i7
    %issue_slots_26_out_uop_pdst = sv.wire sym @issue_slots_26_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_26_out_uop_pdst, %slots_26.io_out_uop_pdst : i7
    %issue_slots_26_out_uop_stq_idx = sv.wire sym @issue_slots_26_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_26_out_uop_stq_idx, %slots_26.io_out_uop_stq_idx : i5
    %issue_slots_26_out_uop_ldq_idx = sv.wire sym @issue_slots_26_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_26_out_uop_ldq_idx, %slots_26.io_out_uop_ldq_idx : i5
    %issue_slots_26_out_uop_rob_idx = sv.wire sym @issue_slots_26_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_26_out_uop_rob_idx, %slots_26.io_out_uop_rob_idx : i7
    %issue_slots_26_out_uop_imm_packed = sv.wire sym @issue_slots_26_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_26_out_uop_imm_packed, %slots_26.io_out_uop_imm_packed : i20
    %issue_slots_26_out_uop_taken = sv.wire sym @issue_slots_26_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_taken, %slots_26.io_out_uop_taken : i1
    %issue_slots_26_out_uop_pc_lob = sv.wire sym @issue_slots_26_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_26_out_uop_pc_lob, %slots_26.io_out_uop_pc_lob : i6
    %issue_slots_26_out_uop_edge_inst = sv.wire sym @issue_slots_26_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_edge_inst, %slots_26.io_out_uop_edge_inst : i1
    %issue_slots_26_out_uop_ftq_idx = sv.wire sym @issue_slots_26_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_26_out_uop_ftq_idx, %slots_26.io_out_uop_ftq_idx : i6
    %issue_slots_26_out_uop_br_tag = sv.wire sym @issue_slots_26_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_26_out_uop_br_tag, %slots_26.io_out_uop_br_tag : i5
    %issue_slots_26_out_uop_br_mask = sv.wire sym @issue_slots_26_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_26_out_uop_br_mask, %slots_26.io_out_uop_br_mask : i20
    %issue_slots_26_out_uop_is_sfb = sv.wire sym @issue_slots_26_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_is_sfb, %slots_26.io_out_uop_is_sfb : i1
    %issue_slots_26_out_uop_is_jal = sv.wire sym @issue_slots_26_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_is_jal, %slots_26.io_out_uop_is_jal : i1
    %issue_slots_26_out_uop_is_jalr = sv.wire sym @issue_slots_26_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_is_jalr, %slots_26.io_out_uop_is_jalr : i1
    %issue_slots_26_out_uop_is_br = sv.wire sym @issue_slots_26_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_is_br, %slots_26.io_out_uop_is_br : i1
    %issue_slots_26_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_26_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_iw_p2_poisoned, %slots_26.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_26_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_26_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_iw_p1_poisoned, %slots_26.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_26_out_uop_iw_state = sv.wire sym @issue_slots_26_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_26_out_uop_iw_state, %slots_26.io_out_uop_iw_state : i2
    %issue_slots_26_out_uop_fu_code = sv.wire sym @issue_slots_26_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_26_out_uop_fu_code, %slots_26.io_out_uop_fu_code : i10
    %issue_slots_26_out_uop_is_rvc = sv.wire sym @issue_slots_26_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_26_out_uop_is_rvc, %slots_26.io_out_uop_is_rvc : i1
    %issue_slots_26_out_uop_uopc = sv.wire sym @issue_slots_26_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_26_out_uop_uopc, %slots_26.io_out_uop_uopc : i7
    %4084 = comb.icmp ne %1807, %c0_i4 {sv.namehint = "_issue_slots_22_clear"} : i4
    %issue_slots_22_clear = sv.wire sym @issue_slots_22_clear  : !hw.inout<i1>
    sv.assign %issue_slots_22_clear, %4084 : i1
    %4085 = comb.icmp eq %1823, %c1_i4 : i4
    %4086 = comb.and %4085, %slots_24.io_will_be_valid : i1
    %4087 = comb.icmp eq %1831, %c2_i4 : i4
    %4088 = comb.mux %4087, %slots_25.io_will_be_valid, %4086 : i1
    %4089 = comb.mux %4087, %slots_25.io_out_uop_fp_val, %slots_24.io_out_uop_fp_val : i1
    %4090 = comb.mux %4087, %slots_25.io_out_uop_lrs2_rtype, %slots_24.io_out_uop_lrs2_rtype : i2
    %4091 = comb.mux %4087, %slots_25.io_out_uop_lrs1_rtype, %slots_24.io_out_uop_lrs1_rtype : i2
    %4092 = comb.mux %4087, %slots_25.io_out_uop_dst_rtype, %slots_24.io_out_uop_dst_rtype : i2
    %4093 = comb.mux %4087, %slots_25.io_out_uop_ldst_val, %slots_24.io_out_uop_ldst_val : i1
    %4094 = comb.mux %4087, %slots_25.io_out_uop_uses_stq, %slots_24.io_out_uop_uses_stq : i1
    %4095 = comb.mux %4087, %slots_25.io_out_uop_uses_ldq, %slots_24.io_out_uop_uses_ldq : i1
    %4096 = comb.mux %4087, %slots_25.io_out_uop_is_amo, %slots_24.io_out_uop_is_amo : i1
    %4097 = comb.mux %4087, %slots_25.io_out_uop_is_fence, %slots_24.io_out_uop_is_fence : i1
    %4098 = comb.mux %4087, %slots_25.io_out_uop_mem_signed, %slots_24.io_out_uop_mem_signed : i1
    %4099 = comb.mux %4087, %slots_25.io_out_uop_mem_size, %slots_24.io_out_uop_mem_size : i2
    %4100 = comb.mux %4087, %slots_25.io_out_uop_mem_cmd, %slots_24.io_out_uop_mem_cmd : i5
    %4101 = comb.mux %4087, %slots_25.io_out_uop_bypassable, %slots_24.io_out_uop_bypassable : i1
    %4102 = comb.mux %4087, %slots_25.io_out_uop_ppred_busy, %slots_24.io_out_uop_ppred_busy : i1
    %4103 = comb.mux %4087, %slots_25.io_out_uop_prs3_busy, %slots_24.io_out_uop_prs3_busy : i1
    %4104 = comb.mux %4087, %slots_25.io_out_uop_prs2_busy, %slots_24.io_out_uop_prs2_busy : i1
    %4105 = comb.mux %4087, %slots_25.io_out_uop_prs1_busy, %slots_24.io_out_uop_prs1_busy : i1
    %4106 = comb.mux %4087, %slots_25.io_out_uop_prs3, %slots_24.io_out_uop_prs3 : i7
    %4107 = comb.mux %4087, %slots_25.io_out_uop_prs2, %slots_24.io_out_uop_prs2 : i7
    %4108 = comb.mux %4087, %slots_25.io_out_uop_prs1, %slots_24.io_out_uop_prs1 : i7
    %4109 = comb.mux %4087, %slots_25.io_out_uop_pdst, %slots_24.io_out_uop_pdst : i7
    %4110 = comb.mux %4087, %slots_25.io_out_uop_stq_idx, %slots_24.io_out_uop_stq_idx : i5
    %4111 = comb.mux %4087, %slots_25.io_out_uop_ldq_idx, %slots_24.io_out_uop_ldq_idx : i5
    %4112 = comb.mux %4087, %slots_25.io_out_uop_rob_idx, %slots_24.io_out_uop_rob_idx : i7
    %4113 = comb.mux %4087, %slots_25.io_out_uop_imm_packed, %slots_24.io_out_uop_imm_packed : i20
    %4114 = comb.mux %4087, %slots_25.io_out_uop_taken, %slots_24.io_out_uop_taken : i1
    %4115 = comb.mux %4087, %slots_25.io_out_uop_pc_lob, %slots_24.io_out_uop_pc_lob : i6
    %4116 = comb.mux %4087, %slots_25.io_out_uop_edge_inst, %slots_24.io_out_uop_edge_inst : i1
    %4117 = comb.mux %4087, %slots_25.io_out_uop_ftq_idx, %slots_24.io_out_uop_ftq_idx : i6
    %4118 = comb.mux %4087, %slots_25.io_out_uop_br_tag, %slots_24.io_out_uop_br_tag : i5
    %4119 = comb.mux %4087, %slots_25.io_out_uop_br_mask, %slots_24.io_out_uop_br_mask : i20
    %4120 = comb.mux %4087, %slots_25.io_out_uop_is_sfb, %slots_24.io_out_uop_is_sfb : i1
    %4121 = comb.mux %4087, %slots_25.io_out_uop_is_jal, %slots_24.io_out_uop_is_jal : i1
    %4122 = comb.mux %4087, %slots_25.io_out_uop_is_jalr, %slots_24.io_out_uop_is_jalr : i1
    %4123 = comb.mux %4087, %slots_25.io_out_uop_is_br, %slots_24.io_out_uop_is_br : i1
    %4124 = comb.mux %4087, %slots_25.io_out_uop_iw_p2_poisoned, %slots_24.io_out_uop_iw_p2_poisoned : i1
    %4125 = comb.mux %4087, %slots_25.io_out_uop_iw_p1_poisoned, %slots_24.io_out_uop_iw_p1_poisoned : i1
    %4126 = comb.mux %4087, %slots_25.io_out_uop_iw_state, %slots_24.io_out_uop_iw_state : i2
    %4127 = comb.mux %4087, %slots_25.io_out_uop_fu_code, %slots_24.io_out_uop_fu_code : i10
    %4128 = comb.mux %4087, %slots_25.io_out_uop_is_rvc, %slots_24.io_out_uop_is_rvc : i1
    %4129 = comb.mux %4087, %slots_25.io_out_uop_uopc, %slots_24.io_out_uop_uopc : i7
    %4130 = comb.icmp eq %1839, %c4_i4 : i4
    %4131 = comb.mux %4130, %slots_26.io_will_be_valid, %4088 : i1
    %4132 = comb.mux %4130, %slots_26.io_out_uop_fp_val, %4089 : i1
    %4133 = comb.mux %4130, %slots_26.io_out_uop_lrs2_rtype, %4090 : i2
    %4134 = comb.mux %4130, %slots_26.io_out_uop_lrs1_rtype, %4091 : i2
    %4135 = comb.mux %4130, %slots_26.io_out_uop_dst_rtype, %4092 : i2
    %4136 = comb.mux %4130, %slots_26.io_out_uop_ldst_val, %4093 : i1
    %4137 = comb.mux %4130, %slots_26.io_out_uop_uses_stq, %4094 : i1
    %4138 = comb.mux %4130, %slots_26.io_out_uop_uses_ldq, %4095 : i1
    %4139 = comb.mux %4130, %slots_26.io_out_uop_is_amo, %4096 : i1
    %4140 = comb.mux %4130, %slots_26.io_out_uop_is_fence, %4097 : i1
    %4141 = comb.mux %4130, %slots_26.io_out_uop_mem_signed, %4098 : i1
    %4142 = comb.mux %4130, %slots_26.io_out_uop_mem_size, %4099 : i2
    %4143 = comb.mux %4130, %slots_26.io_out_uop_mem_cmd, %4100 : i5
    %4144 = comb.mux %4130, %slots_26.io_out_uop_bypassable, %4101 : i1
    %4145 = comb.mux %4130, %slots_26.io_out_uop_ppred_busy, %4102 : i1
    %4146 = comb.mux %4130, %slots_26.io_out_uop_prs3_busy, %4103 : i1
    %4147 = comb.mux %4130, %slots_26.io_out_uop_prs2_busy, %4104 : i1
    %4148 = comb.mux %4130, %slots_26.io_out_uop_prs1_busy, %4105 : i1
    %4149 = comb.mux %4130, %slots_26.io_out_uop_prs3, %4106 : i7
    %4150 = comb.mux %4130, %slots_26.io_out_uop_prs2, %4107 : i7
    %4151 = comb.mux %4130, %slots_26.io_out_uop_prs1, %4108 : i7
    %4152 = comb.mux %4130, %slots_26.io_out_uop_pdst, %4109 : i7
    %4153 = comb.mux %4130, %slots_26.io_out_uop_stq_idx, %4110 : i5
    %4154 = comb.mux %4130, %slots_26.io_out_uop_ldq_idx, %4111 : i5
    %4155 = comb.mux %4130, %slots_26.io_out_uop_rob_idx, %4112 : i7
    %4156 = comb.mux %4130, %slots_26.io_out_uop_imm_packed, %4113 : i20
    %4157 = comb.mux %4130, %slots_26.io_out_uop_taken, %4114 : i1
    %4158 = comb.mux %4130, %slots_26.io_out_uop_pc_lob, %4115 : i6
    %4159 = comb.mux %4130, %slots_26.io_out_uop_edge_inst, %4116 : i1
    %4160 = comb.mux %4130, %slots_26.io_out_uop_ftq_idx, %4117 : i6
    %4161 = comb.mux %4130, %slots_26.io_out_uop_br_tag, %4118 : i5
    %4162 = comb.mux %4130, %slots_26.io_out_uop_br_mask, %4119 : i20
    %4163 = comb.mux %4130, %slots_26.io_out_uop_is_sfb, %4120 : i1
    %4164 = comb.mux %4130, %slots_26.io_out_uop_is_jal, %4121 : i1
    %4165 = comb.mux %4130, %slots_26.io_out_uop_is_jalr, %4122 : i1
    %4166 = comb.mux %4130, %slots_26.io_out_uop_is_br, %4123 : i1
    %4167 = comb.mux %4130, %slots_26.io_out_uop_iw_p2_poisoned, %4124 : i1
    %4168 = comb.mux %4130, %slots_26.io_out_uop_iw_p1_poisoned, %4125 : i1
    %4169 = comb.mux %4130, %slots_26.io_out_uop_iw_state, %4126 : i2
    %4170 = comb.mux %4130, %slots_26.io_out_uop_fu_code, %4127 : i10
    %4171 = comb.mux %4130, %slots_26.io_out_uop_is_rvc, %4128 : i1
    %4172 = comb.mux %4130, %slots_26.io_out_uop_uopc, %4129 : i7
    %4173 = comb.icmp eq %1847, %c-8_i4 : i4
    %issue_slots_27_will_be_valid = sv.wire sym @issue_slots_27_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_27_will_be_valid, %slots_27.io_will_be_valid : i1
    %4174 = comb.mux %4173, %slots_27.io_will_be_valid, %4131 {sv.namehint = "_issue_slots_23_in_uop_valid"} : i1
    %issue_slots_23_in_uop_valid = sv.wire sym @issue_slots_23_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_23_in_uop_valid, %4174 : i1
    %issue_slots_27_out_uop_fp_val = sv.wire sym @issue_slots_27_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_fp_val, %slots_27.io_out_uop_fp_val : i1
    %issue_slots_27_out_uop_lrs2_rtype = sv.wire sym @issue_slots_27_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_27_out_uop_lrs2_rtype, %slots_27.io_out_uop_lrs2_rtype : i2
    %issue_slots_27_out_uop_lrs1_rtype = sv.wire sym @issue_slots_27_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_27_out_uop_lrs1_rtype, %slots_27.io_out_uop_lrs1_rtype : i2
    %issue_slots_27_out_uop_dst_rtype = sv.wire sym @issue_slots_27_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_27_out_uop_dst_rtype, %slots_27.io_out_uop_dst_rtype : i2
    %issue_slots_27_out_uop_ldst_val = sv.wire sym @issue_slots_27_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_ldst_val, %slots_27.io_out_uop_ldst_val : i1
    %issue_slots_27_out_uop_uses_stq = sv.wire sym @issue_slots_27_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_uses_stq, %slots_27.io_out_uop_uses_stq : i1
    %issue_slots_27_out_uop_uses_ldq = sv.wire sym @issue_slots_27_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_uses_ldq, %slots_27.io_out_uop_uses_ldq : i1
    %issue_slots_27_out_uop_is_amo = sv.wire sym @issue_slots_27_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_is_amo, %slots_27.io_out_uop_is_amo : i1
    %issue_slots_27_out_uop_is_fence = sv.wire sym @issue_slots_27_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_is_fence, %slots_27.io_out_uop_is_fence : i1
    %issue_slots_27_out_uop_mem_signed = sv.wire sym @issue_slots_27_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_mem_signed, %slots_27.io_out_uop_mem_signed : i1
    %issue_slots_27_out_uop_mem_size = sv.wire sym @issue_slots_27_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_27_out_uop_mem_size, %slots_27.io_out_uop_mem_size : i2
    %issue_slots_27_out_uop_mem_cmd = sv.wire sym @issue_slots_27_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_27_out_uop_mem_cmd, %slots_27.io_out_uop_mem_cmd : i5
    %issue_slots_27_out_uop_bypassable = sv.wire sym @issue_slots_27_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_bypassable, %slots_27.io_out_uop_bypassable : i1
    %issue_slots_27_out_uop_ppred_busy = sv.wire sym @issue_slots_27_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_ppred_busy, %slots_27.io_out_uop_ppred_busy : i1
    %issue_slots_27_out_uop_prs3_busy = sv.wire sym @issue_slots_27_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_prs3_busy, %slots_27.io_out_uop_prs3_busy : i1
    %issue_slots_27_out_uop_prs2_busy = sv.wire sym @issue_slots_27_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_prs2_busy, %slots_27.io_out_uop_prs2_busy : i1
    %issue_slots_27_out_uop_prs1_busy = sv.wire sym @issue_slots_27_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_prs1_busy, %slots_27.io_out_uop_prs1_busy : i1
    %issue_slots_27_out_uop_prs3 = sv.wire sym @issue_slots_27_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_27_out_uop_prs3, %slots_27.io_out_uop_prs3 : i7
    %issue_slots_27_out_uop_prs2 = sv.wire sym @issue_slots_27_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_27_out_uop_prs2, %slots_27.io_out_uop_prs2 : i7
    %issue_slots_27_out_uop_prs1 = sv.wire sym @issue_slots_27_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_27_out_uop_prs1, %slots_27.io_out_uop_prs1 : i7
    %issue_slots_27_out_uop_pdst = sv.wire sym @issue_slots_27_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_27_out_uop_pdst, %slots_27.io_out_uop_pdst : i7
    %issue_slots_27_out_uop_stq_idx = sv.wire sym @issue_slots_27_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_27_out_uop_stq_idx, %slots_27.io_out_uop_stq_idx : i5
    %issue_slots_27_out_uop_ldq_idx = sv.wire sym @issue_slots_27_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_27_out_uop_ldq_idx, %slots_27.io_out_uop_ldq_idx : i5
    %issue_slots_27_out_uop_rob_idx = sv.wire sym @issue_slots_27_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_27_out_uop_rob_idx, %slots_27.io_out_uop_rob_idx : i7
    %issue_slots_27_out_uop_imm_packed = sv.wire sym @issue_slots_27_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_27_out_uop_imm_packed, %slots_27.io_out_uop_imm_packed : i20
    %issue_slots_27_out_uop_taken = sv.wire sym @issue_slots_27_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_taken, %slots_27.io_out_uop_taken : i1
    %issue_slots_27_out_uop_pc_lob = sv.wire sym @issue_slots_27_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_27_out_uop_pc_lob, %slots_27.io_out_uop_pc_lob : i6
    %issue_slots_27_out_uop_edge_inst = sv.wire sym @issue_slots_27_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_edge_inst, %slots_27.io_out_uop_edge_inst : i1
    %issue_slots_27_out_uop_ftq_idx = sv.wire sym @issue_slots_27_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_27_out_uop_ftq_idx, %slots_27.io_out_uop_ftq_idx : i6
    %issue_slots_27_out_uop_br_tag = sv.wire sym @issue_slots_27_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_27_out_uop_br_tag, %slots_27.io_out_uop_br_tag : i5
    %issue_slots_27_out_uop_br_mask = sv.wire sym @issue_slots_27_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_27_out_uop_br_mask, %slots_27.io_out_uop_br_mask : i20
    %issue_slots_27_out_uop_is_sfb = sv.wire sym @issue_slots_27_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_is_sfb, %slots_27.io_out_uop_is_sfb : i1
    %issue_slots_27_out_uop_is_jal = sv.wire sym @issue_slots_27_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_is_jal, %slots_27.io_out_uop_is_jal : i1
    %issue_slots_27_out_uop_is_jalr = sv.wire sym @issue_slots_27_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_is_jalr, %slots_27.io_out_uop_is_jalr : i1
    %issue_slots_27_out_uop_is_br = sv.wire sym @issue_slots_27_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_is_br, %slots_27.io_out_uop_is_br : i1
    %issue_slots_27_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_27_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_iw_p2_poisoned, %slots_27.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_27_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_27_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_iw_p1_poisoned, %slots_27.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_27_out_uop_iw_state = sv.wire sym @issue_slots_27_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_27_out_uop_iw_state, %slots_27.io_out_uop_iw_state : i2
    %issue_slots_27_out_uop_fu_code = sv.wire sym @issue_slots_27_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_27_out_uop_fu_code, %slots_27.io_out_uop_fu_code : i10
    %issue_slots_27_out_uop_is_rvc = sv.wire sym @issue_slots_27_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_27_out_uop_is_rvc, %slots_27.io_out_uop_is_rvc : i1
    %issue_slots_27_out_uop_uopc = sv.wire sym @issue_slots_27_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_27_out_uop_uopc, %slots_27.io_out_uop_uopc : i7
    %4175 = comb.icmp ne %1815, %c0_i4 {sv.namehint = "_issue_slots_23_clear"} : i4
    %issue_slots_23_clear = sv.wire sym @issue_slots_23_clear  : !hw.inout<i1>
    sv.assign %issue_slots_23_clear, %4175 : i1
    %4176 = comb.icmp eq %1831, %c1_i4 : i4
    %4177 = comb.and %4176, %slots_25.io_will_be_valid : i1
    %4178 = comb.icmp eq %1839, %c2_i4 : i4
    %4179 = comb.mux %4178, %slots_26.io_will_be_valid, %4177 : i1
    %4180 = comb.mux %4178, %slots_26.io_out_uop_fp_val, %slots_25.io_out_uop_fp_val : i1
    %4181 = comb.mux %4178, %slots_26.io_out_uop_lrs2_rtype, %slots_25.io_out_uop_lrs2_rtype : i2
    %4182 = comb.mux %4178, %slots_26.io_out_uop_lrs1_rtype, %slots_25.io_out_uop_lrs1_rtype : i2
    %4183 = comb.mux %4178, %slots_26.io_out_uop_dst_rtype, %slots_25.io_out_uop_dst_rtype : i2
    %4184 = comb.mux %4178, %slots_26.io_out_uop_ldst_val, %slots_25.io_out_uop_ldst_val : i1
    %4185 = comb.mux %4178, %slots_26.io_out_uop_uses_stq, %slots_25.io_out_uop_uses_stq : i1
    %4186 = comb.mux %4178, %slots_26.io_out_uop_uses_ldq, %slots_25.io_out_uop_uses_ldq : i1
    %4187 = comb.mux %4178, %slots_26.io_out_uop_is_amo, %slots_25.io_out_uop_is_amo : i1
    %4188 = comb.mux %4178, %slots_26.io_out_uop_is_fence, %slots_25.io_out_uop_is_fence : i1
    %4189 = comb.mux %4178, %slots_26.io_out_uop_mem_signed, %slots_25.io_out_uop_mem_signed : i1
    %4190 = comb.mux %4178, %slots_26.io_out_uop_mem_size, %slots_25.io_out_uop_mem_size : i2
    %4191 = comb.mux %4178, %slots_26.io_out_uop_mem_cmd, %slots_25.io_out_uop_mem_cmd : i5
    %4192 = comb.mux %4178, %slots_26.io_out_uop_bypassable, %slots_25.io_out_uop_bypassable : i1
    %4193 = comb.mux %4178, %slots_26.io_out_uop_ppred_busy, %slots_25.io_out_uop_ppred_busy : i1
    %4194 = comb.mux %4178, %slots_26.io_out_uop_prs3_busy, %slots_25.io_out_uop_prs3_busy : i1
    %4195 = comb.mux %4178, %slots_26.io_out_uop_prs2_busy, %slots_25.io_out_uop_prs2_busy : i1
    %4196 = comb.mux %4178, %slots_26.io_out_uop_prs1_busy, %slots_25.io_out_uop_prs1_busy : i1
    %4197 = comb.mux %4178, %slots_26.io_out_uop_prs3, %slots_25.io_out_uop_prs3 : i7
    %4198 = comb.mux %4178, %slots_26.io_out_uop_prs2, %slots_25.io_out_uop_prs2 : i7
    %4199 = comb.mux %4178, %slots_26.io_out_uop_prs1, %slots_25.io_out_uop_prs1 : i7
    %4200 = comb.mux %4178, %slots_26.io_out_uop_pdst, %slots_25.io_out_uop_pdst : i7
    %4201 = comb.mux %4178, %slots_26.io_out_uop_stq_idx, %slots_25.io_out_uop_stq_idx : i5
    %4202 = comb.mux %4178, %slots_26.io_out_uop_ldq_idx, %slots_25.io_out_uop_ldq_idx : i5
    %4203 = comb.mux %4178, %slots_26.io_out_uop_rob_idx, %slots_25.io_out_uop_rob_idx : i7
    %4204 = comb.mux %4178, %slots_26.io_out_uop_imm_packed, %slots_25.io_out_uop_imm_packed : i20
    %4205 = comb.mux %4178, %slots_26.io_out_uop_taken, %slots_25.io_out_uop_taken : i1
    %4206 = comb.mux %4178, %slots_26.io_out_uop_pc_lob, %slots_25.io_out_uop_pc_lob : i6
    %4207 = comb.mux %4178, %slots_26.io_out_uop_edge_inst, %slots_25.io_out_uop_edge_inst : i1
    %4208 = comb.mux %4178, %slots_26.io_out_uop_ftq_idx, %slots_25.io_out_uop_ftq_idx : i6
    %4209 = comb.mux %4178, %slots_26.io_out_uop_br_tag, %slots_25.io_out_uop_br_tag : i5
    %4210 = comb.mux %4178, %slots_26.io_out_uop_br_mask, %slots_25.io_out_uop_br_mask : i20
    %4211 = comb.mux %4178, %slots_26.io_out_uop_is_sfb, %slots_25.io_out_uop_is_sfb : i1
    %4212 = comb.mux %4178, %slots_26.io_out_uop_is_jal, %slots_25.io_out_uop_is_jal : i1
    %4213 = comb.mux %4178, %slots_26.io_out_uop_is_jalr, %slots_25.io_out_uop_is_jalr : i1
    %4214 = comb.mux %4178, %slots_26.io_out_uop_is_br, %slots_25.io_out_uop_is_br : i1
    %4215 = comb.mux %4178, %slots_26.io_out_uop_iw_p2_poisoned, %slots_25.io_out_uop_iw_p2_poisoned : i1
    %4216 = comb.mux %4178, %slots_26.io_out_uop_iw_p1_poisoned, %slots_25.io_out_uop_iw_p1_poisoned : i1
    %4217 = comb.mux %4178, %slots_26.io_out_uop_iw_state, %slots_25.io_out_uop_iw_state : i2
    %4218 = comb.mux %4178, %slots_26.io_out_uop_fu_code, %slots_25.io_out_uop_fu_code : i10
    %4219 = comb.mux %4178, %slots_26.io_out_uop_is_rvc, %slots_25.io_out_uop_is_rvc : i1
    %4220 = comb.mux %4178, %slots_26.io_out_uop_uopc, %slots_25.io_out_uop_uopc : i7
    %4221 = comb.icmp eq %1847, %c4_i4 : i4
    %4222 = comb.mux %4221, %slots_27.io_will_be_valid, %4179 : i1
    %4223 = comb.mux %4221, %slots_27.io_out_uop_fp_val, %4180 : i1
    %4224 = comb.mux %4221, %slots_27.io_out_uop_lrs2_rtype, %4181 : i2
    %4225 = comb.mux %4221, %slots_27.io_out_uop_lrs1_rtype, %4182 : i2
    %4226 = comb.mux %4221, %slots_27.io_out_uop_dst_rtype, %4183 : i2
    %4227 = comb.mux %4221, %slots_27.io_out_uop_ldst_val, %4184 : i1
    %4228 = comb.mux %4221, %slots_27.io_out_uop_uses_stq, %4185 : i1
    %4229 = comb.mux %4221, %slots_27.io_out_uop_uses_ldq, %4186 : i1
    %4230 = comb.mux %4221, %slots_27.io_out_uop_is_amo, %4187 : i1
    %4231 = comb.mux %4221, %slots_27.io_out_uop_is_fence, %4188 : i1
    %4232 = comb.mux %4221, %slots_27.io_out_uop_mem_signed, %4189 : i1
    %4233 = comb.mux %4221, %slots_27.io_out_uop_mem_size, %4190 : i2
    %4234 = comb.mux %4221, %slots_27.io_out_uop_mem_cmd, %4191 : i5
    %4235 = comb.mux %4221, %slots_27.io_out_uop_bypassable, %4192 : i1
    %4236 = comb.mux %4221, %slots_27.io_out_uop_ppred_busy, %4193 : i1
    %4237 = comb.mux %4221, %slots_27.io_out_uop_prs3_busy, %4194 : i1
    %4238 = comb.mux %4221, %slots_27.io_out_uop_prs2_busy, %4195 : i1
    %4239 = comb.mux %4221, %slots_27.io_out_uop_prs1_busy, %4196 : i1
    %4240 = comb.mux %4221, %slots_27.io_out_uop_prs3, %4197 : i7
    %4241 = comb.mux %4221, %slots_27.io_out_uop_prs2, %4198 : i7
    %4242 = comb.mux %4221, %slots_27.io_out_uop_prs1, %4199 : i7
    %4243 = comb.mux %4221, %slots_27.io_out_uop_pdst, %4200 : i7
    %4244 = comb.mux %4221, %slots_27.io_out_uop_stq_idx, %4201 : i5
    %4245 = comb.mux %4221, %slots_27.io_out_uop_ldq_idx, %4202 : i5
    %4246 = comb.mux %4221, %slots_27.io_out_uop_rob_idx, %4203 : i7
    %4247 = comb.mux %4221, %slots_27.io_out_uop_imm_packed, %4204 : i20
    %4248 = comb.mux %4221, %slots_27.io_out_uop_taken, %4205 : i1
    %4249 = comb.mux %4221, %slots_27.io_out_uop_pc_lob, %4206 : i6
    %4250 = comb.mux %4221, %slots_27.io_out_uop_edge_inst, %4207 : i1
    %4251 = comb.mux %4221, %slots_27.io_out_uop_ftq_idx, %4208 : i6
    %4252 = comb.mux %4221, %slots_27.io_out_uop_br_tag, %4209 : i5
    %4253 = comb.mux %4221, %slots_27.io_out_uop_br_mask, %4210 : i20
    %4254 = comb.mux %4221, %slots_27.io_out_uop_is_sfb, %4211 : i1
    %4255 = comb.mux %4221, %slots_27.io_out_uop_is_jal, %4212 : i1
    %4256 = comb.mux %4221, %slots_27.io_out_uop_is_jalr, %4213 : i1
    %4257 = comb.mux %4221, %slots_27.io_out_uop_is_br, %4214 : i1
    %4258 = comb.mux %4221, %slots_27.io_out_uop_iw_p2_poisoned, %4215 : i1
    %4259 = comb.mux %4221, %slots_27.io_out_uop_iw_p1_poisoned, %4216 : i1
    %4260 = comb.mux %4221, %slots_27.io_out_uop_iw_state, %4217 : i2
    %4261 = comb.mux %4221, %slots_27.io_out_uop_fu_code, %4218 : i10
    %4262 = comb.mux %4221, %slots_27.io_out_uop_is_rvc, %4219 : i1
    %4263 = comb.mux %4221, %slots_27.io_out_uop_uopc, %4220 : i7
    %4264 = comb.icmp eq %1855, %c-8_i4 : i4
    %issue_slots_28_will_be_valid = sv.wire sym @issue_slots_28_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_28_will_be_valid, %slots_28.io_will_be_valid : i1
    %4265 = comb.mux %4264, %slots_28.io_will_be_valid, %4222 {sv.namehint = "_issue_slots_24_in_uop_valid"} : i1
    %issue_slots_24_in_uop_valid = sv.wire sym @issue_slots_24_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_24_in_uop_valid, %4265 : i1
    %issue_slots_28_out_uop_fp_val = sv.wire sym @issue_slots_28_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_fp_val, %slots_28.io_out_uop_fp_val : i1
    %issue_slots_28_out_uop_lrs2_rtype = sv.wire sym @issue_slots_28_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_28_out_uop_lrs2_rtype, %slots_28.io_out_uop_lrs2_rtype : i2
    %issue_slots_28_out_uop_lrs1_rtype = sv.wire sym @issue_slots_28_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_28_out_uop_lrs1_rtype, %slots_28.io_out_uop_lrs1_rtype : i2
    %issue_slots_28_out_uop_dst_rtype = sv.wire sym @issue_slots_28_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_28_out_uop_dst_rtype, %slots_28.io_out_uop_dst_rtype : i2
    %issue_slots_28_out_uop_ldst_val = sv.wire sym @issue_slots_28_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_ldst_val, %slots_28.io_out_uop_ldst_val : i1
    %issue_slots_28_out_uop_uses_stq = sv.wire sym @issue_slots_28_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_uses_stq, %slots_28.io_out_uop_uses_stq : i1
    %issue_slots_28_out_uop_uses_ldq = sv.wire sym @issue_slots_28_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_uses_ldq, %slots_28.io_out_uop_uses_ldq : i1
    %issue_slots_28_out_uop_is_amo = sv.wire sym @issue_slots_28_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_is_amo, %slots_28.io_out_uop_is_amo : i1
    %issue_slots_28_out_uop_is_fence = sv.wire sym @issue_slots_28_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_is_fence, %slots_28.io_out_uop_is_fence : i1
    %issue_slots_28_out_uop_mem_signed = sv.wire sym @issue_slots_28_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_mem_signed, %slots_28.io_out_uop_mem_signed : i1
    %issue_slots_28_out_uop_mem_size = sv.wire sym @issue_slots_28_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_28_out_uop_mem_size, %slots_28.io_out_uop_mem_size : i2
    %issue_slots_28_out_uop_mem_cmd = sv.wire sym @issue_slots_28_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_28_out_uop_mem_cmd, %slots_28.io_out_uop_mem_cmd : i5
    %issue_slots_28_out_uop_bypassable = sv.wire sym @issue_slots_28_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_bypassable, %slots_28.io_out_uop_bypassable : i1
    %issue_slots_28_out_uop_ppred_busy = sv.wire sym @issue_slots_28_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_ppred_busy, %slots_28.io_out_uop_ppred_busy : i1
    %issue_slots_28_out_uop_prs3_busy = sv.wire sym @issue_slots_28_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_prs3_busy, %slots_28.io_out_uop_prs3_busy : i1
    %issue_slots_28_out_uop_prs2_busy = sv.wire sym @issue_slots_28_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_prs2_busy, %slots_28.io_out_uop_prs2_busy : i1
    %issue_slots_28_out_uop_prs1_busy = sv.wire sym @issue_slots_28_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_prs1_busy, %slots_28.io_out_uop_prs1_busy : i1
    %issue_slots_28_out_uop_prs3 = sv.wire sym @issue_slots_28_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_28_out_uop_prs3, %slots_28.io_out_uop_prs3 : i7
    %issue_slots_28_out_uop_prs2 = sv.wire sym @issue_slots_28_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_28_out_uop_prs2, %slots_28.io_out_uop_prs2 : i7
    %issue_slots_28_out_uop_prs1 = sv.wire sym @issue_slots_28_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_28_out_uop_prs1, %slots_28.io_out_uop_prs1 : i7
    %issue_slots_28_out_uop_pdst = sv.wire sym @issue_slots_28_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_28_out_uop_pdst, %slots_28.io_out_uop_pdst : i7
    %issue_slots_28_out_uop_stq_idx = sv.wire sym @issue_slots_28_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_28_out_uop_stq_idx, %slots_28.io_out_uop_stq_idx : i5
    %issue_slots_28_out_uop_ldq_idx = sv.wire sym @issue_slots_28_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_28_out_uop_ldq_idx, %slots_28.io_out_uop_ldq_idx : i5
    %issue_slots_28_out_uop_rob_idx = sv.wire sym @issue_slots_28_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_28_out_uop_rob_idx, %slots_28.io_out_uop_rob_idx : i7
    %issue_slots_28_out_uop_imm_packed = sv.wire sym @issue_slots_28_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_28_out_uop_imm_packed, %slots_28.io_out_uop_imm_packed : i20
    %issue_slots_28_out_uop_taken = sv.wire sym @issue_slots_28_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_taken, %slots_28.io_out_uop_taken : i1
    %issue_slots_28_out_uop_pc_lob = sv.wire sym @issue_slots_28_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_28_out_uop_pc_lob, %slots_28.io_out_uop_pc_lob : i6
    %issue_slots_28_out_uop_edge_inst = sv.wire sym @issue_slots_28_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_edge_inst, %slots_28.io_out_uop_edge_inst : i1
    %issue_slots_28_out_uop_ftq_idx = sv.wire sym @issue_slots_28_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_28_out_uop_ftq_idx, %slots_28.io_out_uop_ftq_idx : i6
    %issue_slots_28_out_uop_br_tag = sv.wire sym @issue_slots_28_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_28_out_uop_br_tag, %slots_28.io_out_uop_br_tag : i5
    %issue_slots_28_out_uop_br_mask = sv.wire sym @issue_slots_28_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_28_out_uop_br_mask, %slots_28.io_out_uop_br_mask : i20
    %issue_slots_28_out_uop_is_sfb = sv.wire sym @issue_slots_28_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_is_sfb, %slots_28.io_out_uop_is_sfb : i1
    %issue_slots_28_out_uop_is_jal = sv.wire sym @issue_slots_28_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_is_jal, %slots_28.io_out_uop_is_jal : i1
    %issue_slots_28_out_uop_is_jalr = sv.wire sym @issue_slots_28_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_is_jalr, %slots_28.io_out_uop_is_jalr : i1
    %issue_slots_28_out_uop_is_br = sv.wire sym @issue_slots_28_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_is_br, %slots_28.io_out_uop_is_br : i1
    %issue_slots_28_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_28_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_iw_p2_poisoned, %slots_28.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_28_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_28_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_iw_p1_poisoned, %slots_28.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_28_out_uop_iw_state = sv.wire sym @issue_slots_28_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_28_out_uop_iw_state, %slots_28.io_out_uop_iw_state : i2
    %issue_slots_28_out_uop_fu_code = sv.wire sym @issue_slots_28_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_28_out_uop_fu_code, %slots_28.io_out_uop_fu_code : i10
    %issue_slots_28_out_uop_is_rvc = sv.wire sym @issue_slots_28_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_28_out_uop_is_rvc, %slots_28.io_out_uop_is_rvc : i1
    %issue_slots_28_out_uop_uopc = sv.wire sym @issue_slots_28_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_28_out_uop_uopc, %slots_28.io_out_uop_uopc : i7
    %4266 = comb.icmp ne %1823, %c0_i4 {sv.namehint = "_issue_slots_24_clear"} : i4
    %issue_slots_24_clear = sv.wire sym @issue_slots_24_clear  : !hw.inout<i1>
    sv.assign %issue_slots_24_clear, %4266 : i1
    %4267 = comb.icmp eq %1839, %c1_i4 : i4
    %4268 = comb.and %4267, %slots_26.io_will_be_valid : i1
    %4269 = comb.icmp eq %1847, %c2_i4 : i4
    %4270 = comb.mux %4269, %slots_27.io_will_be_valid, %4268 : i1
    %4271 = comb.mux %4269, %slots_27.io_out_uop_fp_val, %slots_26.io_out_uop_fp_val : i1
    %4272 = comb.mux %4269, %slots_27.io_out_uop_lrs2_rtype, %slots_26.io_out_uop_lrs2_rtype : i2
    %4273 = comb.mux %4269, %slots_27.io_out_uop_lrs1_rtype, %slots_26.io_out_uop_lrs1_rtype : i2
    %4274 = comb.mux %4269, %slots_27.io_out_uop_dst_rtype, %slots_26.io_out_uop_dst_rtype : i2
    %4275 = comb.mux %4269, %slots_27.io_out_uop_ldst_val, %slots_26.io_out_uop_ldst_val : i1
    %4276 = comb.mux %4269, %slots_27.io_out_uop_uses_stq, %slots_26.io_out_uop_uses_stq : i1
    %4277 = comb.mux %4269, %slots_27.io_out_uop_uses_ldq, %slots_26.io_out_uop_uses_ldq : i1
    %4278 = comb.mux %4269, %slots_27.io_out_uop_is_amo, %slots_26.io_out_uop_is_amo : i1
    %4279 = comb.mux %4269, %slots_27.io_out_uop_is_fence, %slots_26.io_out_uop_is_fence : i1
    %4280 = comb.mux %4269, %slots_27.io_out_uop_mem_signed, %slots_26.io_out_uop_mem_signed : i1
    %4281 = comb.mux %4269, %slots_27.io_out_uop_mem_size, %slots_26.io_out_uop_mem_size : i2
    %4282 = comb.mux %4269, %slots_27.io_out_uop_mem_cmd, %slots_26.io_out_uop_mem_cmd : i5
    %4283 = comb.mux %4269, %slots_27.io_out_uop_bypassable, %slots_26.io_out_uop_bypassable : i1
    %4284 = comb.mux %4269, %slots_27.io_out_uop_ppred_busy, %slots_26.io_out_uop_ppred_busy : i1
    %4285 = comb.mux %4269, %slots_27.io_out_uop_prs3_busy, %slots_26.io_out_uop_prs3_busy : i1
    %4286 = comb.mux %4269, %slots_27.io_out_uop_prs2_busy, %slots_26.io_out_uop_prs2_busy : i1
    %4287 = comb.mux %4269, %slots_27.io_out_uop_prs1_busy, %slots_26.io_out_uop_prs1_busy : i1
    %4288 = comb.mux %4269, %slots_27.io_out_uop_prs3, %slots_26.io_out_uop_prs3 : i7
    %4289 = comb.mux %4269, %slots_27.io_out_uop_prs2, %slots_26.io_out_uop_prs2 : i7
    %4290 = comb.mux %4269, %slots_27.io_out_uop_prs1, %slots_26.io_out_uop_prs1 : i7
    %4291 = comb.mux %4269, %slots_27.io_out_uop_pdst, %slots_26.io_out_uop_pdst : i7
    %4292 = comb.mux %4269, %slots_27.io_out_uop_stq_idx, %slots_26.io_out_uop_stq_idx : i5
    %4293 = comb.mux %4269, %slots_27.io_out_uop_ldq_idx, %slots_26.io_out_uop_ldq_idx : i5
    %4294 = comb.mux %4269, %slots_27.io_out_uop_rob_idx, %slots_26.io_out_uop_rob_idx : i7
    %4295 = comb.mux %4269, %slots_27.io_out_uop_imm_packed, %slots_26.io_out_uop_imm_packed : i20
    %4296 = comb.mux %4269, %slots_27.io_out_uop_taken, %slots_26.io_out_uop_taken : i1
    %4297 = comb.mux %4269, %slots_27.io_out_uop_pc_lob, %slots_26.io_out_uop_pc_lob : i6
    %4298 = comb.mux %4269, %slots_27.io_out_uop_edge_inst, %slots_26.io_out_uop_edge_inst : i1
    %4299 = comb.mux %4269, %slots_27.io_out_uop_ftq_idx, %slots_26.io_out_uop_ftq_idx : i6
    %4300 = comb.mux %4269, %slots_27.io_out_uop_br_tag, %slots_26.io_out_uop_br_tag : i5
    %4301 = comb.mux %4269, %slots_27.io_out_uop_br_mask, %slots_26.io_out_uop_br_mask : i20
    %4302 = comb.mux %4269, %slots_27.io_out_uop_is_sfb, %slots_26.io_out_uop_is_sfb : i1
    %4303 = comb.mux %4269, %slots_27.io_out_uop_is_jal, %slots_26.io_out_uop_is_jal : i1
    %4304 = comb.mux %4269, %slots_27.io_out_uop_is_jalr, %slots_26.io_out_uop_is_jalr : i1
    %4305 = comb.mux %4269, %slots_27.io_out_uop_is_br, %slots_26.io_out_uop_is_br : i1
    %4306 = comb.mux %4269, %slots_27.io_out_uop_iw_p2_poisoned, %slots_26.io_out_uop_iw_p2_poisoned : i1
    %4307 = comb.mux %4269, %slots_27.io_out_uop_iw_p1_poisoned, %slots_26.io_out_uop_iw_p1_poisoned : i1
    %4308 = comb.mux %4269, %slots_27.io_out_uop_iw_state, %slots_26.io_out_uop_iw_state : i2
    %4309 = comb.mux %4269, %slots_27.io_out_uop_fu_code, %slots_26.io_out_uop_fu_code : i10
    %4310 = comb.mux %4269, %slots_27.io_out_uop_is_rvc, %slots_26.io_out_uop_is_rvc : i1
    %4311 = comb.mux %4269, %slots_27.io_out_uop_uopc, %slots_26.io_out_uop_uopc : i7
    %4312 = comb.icmp eq %1855, %c4_i4 : i4
    %4313 = comb.mux %4312, %slots_28.io_will_be_valid, %4270 : i1
    %4314 = comb.mux %4312, %slots_28.io_out_uop_fp_val, %4271 : i1
    %4315 = comb.mux %4312, %slots_28.io_out_uop_lrs2_rtype, %4272 : i2
    %4316 = comb.mux %4312, %slots_28.io_out_uop_lrs1_rtype, %4273 : i2
    %4317 = comb.mux %4312, %slots_28.io_out_uop_dst_rtype, %4274 : i2
    %4318 = comb.mux %4312, %slots_28.io_out_uop_ldst_val, %4275 : i1
    %4319 = comb.mux %4312, %slots_28.io_out_uop_uses_stq, %4276 : i1
    %4320 = comb.mux %4312, %slots_28.io_out_uop_uses_ldq, %4277 : i1
    %4321 = comb.mux %4312, %slots_28.io_out_uop_is_amo, %4278 : i1
    %4322 = comb.mux %4312, %slots_28.io_out_uop_is_fence, %4279 : i1
    %4323 = comb.mux %4312, %slots_28.io_out_uop_mem_signed, %4280 : i1
    %4324 = comb.mux %4312, %slots_28.io_out_uop_mem_size, %4281 : i2
    %4325 = comb.mux %4312, %slots_28.io_out_uop_mem_cmd, %4282 : i5
    %4326 = comb.mux %4312, %slots_28.io_out_uop_bypassable, %4283 : i1
    %4327 = comb.mux %4312, %slots_28.io_out_uop_ppred_busy, %4284 : i1
    %4328 = comb.mux %4312, %slots_28.io_out_uop_prs3_busy, %4285 : i1
    %4329 = comb.mux %4312, %slots_28.io_out_uop_prs2_busy, %4286 : i1
    %4330 = comb.mux %4312, %slots_28.io_out_uop_prs1_busy, %4287 : i1
    %4331 = comb.mux %4312, %slots_28.io_out_uop_prs3, %4288 : i7
    %4332 = comb.mux %4312, %slots_28.io_out_uop_prs2, %4289 : i7
    %4333 = comb.mux %4312, %slots_28.io_out_uop_prs1, %4290 : i7
    %4334 = comb.mux %4312, %slots_28.io_out_uop_pdst, %4291 : i7
    %4335 = comb.mux %4312, %slots_28.io_out_uop_stq_idx, %4292 : i5
    %4336 = comb.mux %4312, %slots_28.io_out_uop_ldq_idx, %4293 : i5
    %4337 = comb.mux %4312, %slots_28.io_out_uop_rob_idx, %4294 : i7
    %4338 = comb.mux %4312, %slots_28.io_out_uop_imm_packed, %4295 : i20
    %4339 = comb.mux %4312, %slots_28.io_out_uop_taken, %4296 : i1
    %4340 = comb.mux %4312, %slots_28.io_out_uop_pc_lob, %4297 : i6
    %4341 = comb.mux %4312, %slots_28.io_out_uop_edge_inst, %4298 : i1
    %4342 = comb.mux %4312, %slots_28.io_out_uop_ftq_idx, %4299 : i6
    %4343 = comb.mux %4312, %slots_28.io_out_uop_br_tag, %4300 : i5
    %4344 = comb.mux %4312, %slots_28.io_out_uop_br_mask, %4301 : i20
    %4345 = comb.mux %4312, %slots_28.io_out_uop_is_sfb, %4302 : i1
    %4346 = comb.mux %4312, %slots_28.io_out_uop_is_jal, %4303 : i1
    %4347 = comb.mux %4312, %slots_28.io_out_uop_is_jalr, %4304 : i1
    %4348 = comb.mux %4312, %slots_28.io_out_uop_is_br, %4305 : i1
    %4349 = comb.mux %4312, %slots_28.io_out_uop_iw_p2_poisoned, %4306 : i1
    %4350 = comb.mux %4312, %slots_28.io_out_uop_iw_p1_poisoned, %4307 : i1
    %4351 = comb.mux %4312, %slots_28.io_out_uop_iw_state, %4308 : i2
    %4352 = comb.mux %4312, %slots_28.io_out_uop_fu_code, %4309 : i10
    %4353 = comb.mux %4312, %slots_28.io_out_uop_is_rvc, %4310 : i1
    %4354 = comb.mux %4312, %slots_28.io_out_uop_uopc, %4311 : i7
    %4355 = comb.icmp eq %1863, %c-8_i4 : i4
    %issue_slots_29_will_be_valid = sv.wire sym @issue_slots_29_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_29_will_be_valid, %slots_29.io_will_be_valid : i1
    %4356 = comb.mux %4355, %slots_29.io_will_be_valid, %4313 {sv.namehint = "_issue_slots_25_in_uop_valid"} : i1
    %issue_slots_25_in_uop_valid = sv.wire sym @issue_slots_25_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_25_in_uop_valid, %4356 : i1
    %issue_slots_29_out_uop_fp_val = sv.wire sym @issue_slots_29_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_fp_val, %slots_29.io_out_uop_fp_val : i1
    %issue_slots_29_out_uop_lrs2_rtype = sv.wire sym @issue_slots_29_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_29_out_uop_lrs2_rtype, %slots_29.io_out_uop_lrs2_rtype : i2
    %issue_slots_29_out_uop_lrs1_rtype = sv.wire sym @issue_slots_29_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_29_out_uop_lrs1_rtype, %slots_29.io_out_uop_lrs1_rtype : i2
    %issue_slots_29_out_uop_dst_rtype = sv.wire sym @issue_slots_29_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_29_out_uop_dst_rtype, %slots_29.io_out_uop_dst_rtype : i2
    %issue_slots_29_out_uop_ldst_val = sv.wire sym @issue_slots_29_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_ldst_val, %slots_29.io_out_uop_ldst_val : i1
    %issue_slots_29_out_uop_uses_stq = sv.wire sym @issue_slots_29_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_uses_stq, %slots_29.io_out_uop_uses_stq : i1
    %issue_slots_29_out_uop_uses_ldq = sv.wire sym @issue_slots_29_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_uses_ldq, %slots_29.io_out_uop_uses_ldq : i1
    %issue_slots_29_out_uop_is_amo = sv.wire sym @issue_slots_29_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_is_amo, %slots_29.io_out_uop_is_amo : i1
    %issue_slots_29_out_uop_is_fence = sv.wire sym @issue_slots_29_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_is_fence, %slots_29.io_out_uop_is_fence : i1
    %issue_slots_29_out_uop_mem_signed = sv.wire sym @issue_slots_29_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_mem_signed, %slots_29.io_out_uop_mem_signed : i1
    %issue_slots_29_out_uop_mem_size = sv.wire sym @issue_slots_29_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_29_out_uop_mem_size, %slots_29.io_out_uop_mem_size : i2
    %issue_slots_29_out_uop_mem_cmd = sv.wire sym @issue_slots_29_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_29_out_uop_mem_cmd, %slots_29.io_out_uop_mem_cmd : i5
    %issue_slots_29_out_uop_bypassable = sv.wire sym @issue_slots_29_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_bypassable, %slots_29.io_out_uop_bypassable : i1
    %issue_slots_29_out_uop_ppred_busy = sv.wire sym @issue_slots_29_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_ppred_busy, %slots_29.io_out_uop_ppred_busy : i1
    %issue_slots_29_out_uop_prs3_busy = sv.wire sym @issue_slots_29_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_prs3_busy, %slots_29.io_out_uop_prs3_busy : i1
    %issue_slots_29_out_uop_prs2_busy = sv.wire sym @issue_slots_29_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_prs2_busy, %slots_29.io_out_uop_prs2_busy : i1
    %issue_slots_29_out_uop_prs1_busy = sv.wire sym @issue_slots_29_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_prs1_busy, %slots_29.io_out_uop_prs1_busy : i1
    %issue_slots_29_out_uop_prs3 = sv.wire sym @issue_slots_29_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_29_out_uop_prs3, %slots_29.io_out_uop_prs3 : i7
    %issue_slots_29_out_uop_prs2 = sv.wire sym @issue_slots_29_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_29_out_uop_prs2, %slots_29.io_out_uop_prs2 : i7
    %issue_slots_29_out_uop_prs1 = sv.wire sym @issue_slots_29_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_29_out_uop_prs1, %slots_29.io_out_uop_prs1 : i7
    %issue_slots_29_out_uop_pdst = sv.wire sym @issue_slots_29_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_29_out_uop_pdst, %slots_29.io_out_uop_pdst : i7
    %issue_slots_29_out_uop_stq_idx = sv.wire sym @issue_slots_29_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_29_out_uop_stq_idx, %slots_29.io_out_uop_stq_idx : i5
    %issue_slots_29_out_uop_ldq_idx = sv.wire sym @issue_slots_29_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_29_out_uop_ldq_idx, %slots_29.io_out_uop_ldq_idx : i5
    %issue_slots_29_out_uop_rob_idx = sv.wire sym @issue_slots_29_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_29_out_uop_rob_idx, %slots_29.io_out_uop_rob_idx : i7
    %issue_slots_29_out_uop_imm_packed = sv.wire sym @issue_slots_29_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_29_out_uop_imm_packed, %slots_29.io_out_uop_imm_packed : i20
    %issue_slots_29_out_uop_taken = sv.wire sym @issue_slots_29_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_taken, %slots_29.io_out_uop_taken : i1
    %issue_slots_29_out_uop_pc_lob = sv.wire sym @issue_slots_29_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_29_out_uop_pc_lob, %slots_29.io_out_uop_pc_lob : i6
    %issue_slots_29_out_uop_edge_inst = sv.wire sym @issue_slots_29_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_edge_inst, %slots_29.io_out_uop_edge_inst : i1
    %issue_slots_29_out_uop_ftq_idx = sv.wire sym @issue_slots_29_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_29_out_uop_ftq_idx, %slots_29.io_out_uop_ftq_idx : i6
    %issue_slots_29_out_uop_br_tag = sv.wire sym @issue_slots_29_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_29_out_uop_br_tag, %slots_29.io_out_uop_br_tag : i5
    %issue_slots_29_out_uop_br_mask = sv.wire sym @issue_slots_29_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_29_out_uop_br_mask, %slots_29.io_out_uop_br_mask : i20
    %issue_slots_29_out_uop_is_sfb = sv.wire sym @issue_slots_29_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_is_sfb, %slots_29.io_out_uop_is_sfb : i1
    %issue_slots_29_out_uop_is_jal = sv.wire sym @issue_slots_29_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_is_jal, %slots_29.io_out_uop_is_jal : i1
    %issue_slots_29_out_uop_is_jalr = sv.wire sym @issue_slots_29_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_is_jalr, %slots_29.io_out_uop_is_jalr : i1
    %issue_slots_29_out_uop_is_br = sv.wire sym @issue_slots_29_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_is_br, %slots_29.io_out_uop_is_br : i1
    %issue_slots_29_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_29_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_iw_p2_poisoned, %slots_29.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_29_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_29_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_iw_p1_poisoned, %slots_29.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_29_out_uop_iw_state = sv.wire sym @issue_slots_29_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_29_out_uop_iw_state, %slots_29.io_out_uop_iw_state : i2
    %issue_slots_29_out_uop_fu_code = sv.wire sym @issue_slots_29_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_29_out_uop_fu_code, %slots_29.io_out_uop_fu_code : i10
    %issue_slots_29_out_uop_is_rvc = sv.wire sym @issue_slots_29_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_29_out_uop_is_rvc, %slots_29.io_out_uop_is_rvc : i1
    %issue_slots_29_out_uop_uopc = sv.wire sym @issue_slots_29_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_29_out_uop_uopc, %slots_29.io_out_uop_uopc : i7
    %4357 = comb.icmp ne %1831, %c0_i4 {sv.namehint = "_issue_slots_25_clear"} : i4
    %issue_slots_25_clear = sv.wire sym @issue_slots_25_clear  : !hw.inout<i1>
    sv.assign %issue_slots_25_clear, %4357 : i1
    %4358 = comb.icmp eq %1847, %c1_i4 : i4
    %4359 = comb.and %4358, %slots_27.io_will_be_valid : i1
    %4360 = comb.icmp eq %1855, %c2_i4 : i4
    %4361 = comb.mux %4360, %slots_28.io_will_be_valid, %4359 : i1
    %4362 = comb.mux %4360, %slots_28.io_out_uop_fp_val, %slots_27.io_out_uop_fp_val : i1
    %4363 = comb.mux %4360, %slots_28.io_out_uop_lrs2_rtype, %slots_27.io_out_uop_lrs2_rtype : i2
    %4364 = comb.mux %4360, %slots_28.io_out_uop_lrs1_rtype, %slots_27.io_out_uop_lrs1_rtype : i2
    %4365 = comb.mux %4360, %slots_28.io_out_uop_dst_rtype, %slots_27.io_out_uop_dst_rtype : i2
    %4366 = comb.mux %4360, %slots_28.io_out_uop_ldst_val, %slots_27.io_out_uop_ldst_val : i1
    %4367 = comb.mux %4360, %slots_28.io_out_uop_uses_stq, %slots_27.io_out_uop_uses_stq : i1
    %4368 = comb.mux %4360, %slots_28.io_out_uop_uses_ldq, %slots_27.io_out_uop_uses_ldq : i1
    %4369 = comb.mux %4360, %slots_28.io_out_uop_is_amo, %slots_27.io_out_uop_is_amo : i1
    %4370 = comb.mux %4360, %slots_28.io_out_uop_is_fence, %slots_27.io_out_uop_is_fence : i1
    %4371 = comb.mux %4360, %slots_28.io_out_uop_mem_signed, %slots_27.io_out_uop_mem_signed : i1
    %4372 = comb.mux %4360, %slots_28.io_out_uop_mem_size, %slots_27.io_out_uop_mem_size : i2
    %4373 = comb.mux %4360, %slots_28.io_out_uop_mem_cmd, %slots_27.io_out_uop_mem_cmd : i5
    %4374 = comb.mux %4360, %slots_28.io_out_uop_bypassable, %slots_27.io_out_uop_bypassable : i1
    %4375 = comb.mux %4360, %slots_28.io_out_uop_ppred_busy, %slots_27.io_out_uop_ppred_busy : i1
    %4376 = comb.mux %4360, %slots_28.io_out_uop_prs3_busy, %slots_27.io_out_uop_prs3_busy : i1
    %4377 = comb.mux %4360, %slots_28.io_out_uop_prs2_busy, %slots_27.io_out_uop_prs2_busy : i1
    %4378 = comb.mux %4360, %slots_28.io_out_uop_prs1_busy, %slots_27.io_out_uop_prs1_busy : i1
    %4379 = comb.mux %4360, %slots_28.io_out_uop_prs3, %slots_27.io_out_uop_prs3 : i7
    %4380 = comb.mux %4360, %slots_28.io_out_uop_prs2, %slots_27.io_out_uop_prs2 : i7
    %4381 = comb.mux %4360, %slots_28.io_out_uop_prs1, %slots_27.io_out_uop_prs1 : i7
    %4382 = comb.mux %4360, %slots_28.io_out_uop_pdst, %slots_27.io_out_uop_pdst : i7
    %4383 = comb.mux %4360, %slots_28.io_out_uop_stq_idx, %slots_27.io_out_uop_stq_idx : i5
    %4384 = comb.mux %4360, %slots_28.io_out_uop_ldq_idx, %slots_27.io_out_uop_ldq_idx : i5
    %4385 = comb.mux %4360, %slots_28.io_out_uop_rob_idx, %slots_27.io_out_uop_rob_idx : i7
    %4386 = comb.mux %4360, %slots_28.io_out_uop_imm_packed, %slots_27.io_out_uop_imm_packed : i20
    %4387 = comb.mux %4360, %slots_28.io_out_uop_taken, %slots_27.io_out_uop_taken : i1
    %4388 = comb.mux %4360, %slots_28.io_out_uop_pc_lob, %slots_27.io_out_uop_pc_lob : i6
    %4389 = comb.mux %4360, %slots_28.io_out_uop_edge_inst, %slots_27.io_out_uop_edge_inst : i1
    %4390 = comb.mux %4360, %slots_28.io_out_uop_ftq_idx, %slots_27.io_out_uop_ftq_idx : i6
    %4391 = comb.mux %4360, %slots_28.io_out_uop_br_tag, %slots_27.io_out_uop_br_tag : i5
    %4392 = comb.mux %4360, %slots_28.io_out_uop_br_mask, %slots_27.io_out_uop_br_mask : i20
    %4393 = comb.mux %4360, %slots_28.io_out_uop_is_sfb, %slots_27.io_out_uop_is_sfb : i1
    %4394 = comb.mux %4360, %slots_28.io_out_uop_is_jal, %slots_27.io_out_uop_is_jal : i1
    %4395 = comb.mux %4360, %slots_28.io_out_uop_is_jalr, %slots_27.io_out_uop_is_jalr : i1
    %4396 = comb.mux %4360, %slots_28.io_out_uop_is_br, %slots_27.io_out_uop_is_br : i1
    %4397 = comb.mux %4360, %slots_28.io_out_uop_iw_p2_poisoned, %slots_27.io_out_uop_iw_p2_poisoned : i1
    %4398 = comb.mux %4360, %slots_28.io_out_uop_iw_p1_poisoned, %slots_27.io_out_uop_iw_p1_poisoned : i1
    %4399 = comb.mux %4360, %slots_28.io_out_uop_iw_state, %slots_27.io_out_uop_iw_state : i2
    %4400 = comb.mux %4360, %slots_28.io_out_uop_fu_code, %slots_27.io_out_uop_fu_code : i10
    %4401 = comb.mux %4360, %slots_28.io_out_uop_is_rvc, %slots_27.io_out_uop_is_rvc : i1
    %4402 = comb.mux %4360, %slots_28.io_out_uop_uopc, %slots_27.io_out_uop_uopc : i7
    %4403 = comb.icmp eq %1863, %c4_i4 : i4
    %4404 = comb.mux %4403, %slots_29.io_will_be_valid, %4361 : i1
    %4405 = comb.mux %4403, %slots_29.io_out_uop_fp_val, %4362 : i1
    %4406 = comb.mux %4403, %slots_29.io_out_uop_lrs2_rtype, %4363 : i2
    %4407 = comb.mux %4403, %slots_29.io_out_uop_lrs1_rtype, %4364 : i2
    %4408 = comb.mux %4403, %slots_29.io_out_uop_dst_rtype, %4365 : i2
    %4409 = comb.mux %4403, %slots_29.io_out_uop_ldst_val, %4366 : i1
    %4410 = comb.mux %4403, %slots_29.io_out_uop_uses_stq, %4367 : i1
    %4411 = comb.mux %4403, %slots_29.io_out_uop_uses_ldq, %4368 : i1
    %4412 = comb.mux %4403, %slots_29.io_out_uop_is_amo, %4369 : i1
    %4413 = comb.mux %4403, %slots_29.io_out_uop_is_fence, %4370 : i1
    %4414 = comb.mux %4403, %slots_29.io_out_uop_mem_signed, %4371 : i1
    %4415 = comb.mux %4403, %slots_29.io_out_uop_mem_size, %4372 : i2
    %4416 = comb.mux %4403, %slots_29.io_out_uop_mem_cmd, %4373 : i5
    %4417 = comb.mux %4403, %slots_29.io_out_uop_bypassable, %4374 : i1
    %4418 = comb.mux %4403, %slots_29.io_out_uop_ppred_busy, %4375 : i1
    %4419 = comb.mux %4403, %slots_29.io_out_uop_prs3_busy, %4376 : i1
    %4420 = comb.mux %4403, %slots_29.io_out_uop_prs2_busy, %4377 : i1
    %4421 = comb.mux %4403, %slots_29.io_out_uop_prs1_busy, %4378 : i1
    %4422 = comb.mux %4403, %slots_29.io_out_uop_prs3, %4379 : i7
    %4423 = comb.mux %4403, %slots_29.io_out_uop_prs2, %4380 : i7
    %4424 = comb.mux %4403, %slots_29.io_out_uop_prs1, %4381 : i7
    %4425 = comb.mux %4403, %slots_29.io_out_uop_pdst, %4382 : i7
    %4426 = comb.mux %4403, %slots_29.io_out_uop_stq_idx, %4383 : i5
    %4427 = comb.mux %4403, %slots_29.io_out_uop_ldq_idx, %4384 : i5
    %4428 = comb.mux %4403, %slots_29.io_out_uop_rob_idx, %4385 : i7
    %4429 = comb.mux %4403, %slots_29.io_out_uop_imm_packed, %4386 : i20
    %4430 = comb.mux %4403, %slots_29.io_out_uop_taken, %4387 : i1
    %4431 = comb.mux %4403, %slots_29.io_out_uop_pc_lob, %4388 : i6
    %4432 = comb.mux %4403, %slots_29.io_out_uop_edge_inst, %4389 : i1
    %4433 = comb.mux %4403, %slots_29.io_out_uop_ftq_idx, %4390 : i6
    %4434 = comb.mux %4403, %slots_29.io_out_uop_br_tag, %4391 : i5
    %4435 = comb.mux %4403, %slots_29.io_out_uop_br_mask, %4392 : i20
    %4436 = comb.mux %4403, %slots_29.io_out_uop_is_sfb, %4393 : i1
    %4437 = comb.mux %4403, %slots_29.io_out_uop_is_jal, %4394 : i1
    %4438 = comb.mux %4403, %slots_29.io_out_uop_is_jalr, %4395 : i1
    %4439 = comb.mux %4403, %slots_29.io_out_uop_is_br, %4396 : i1
    %4440 = comb.mux %4403, %slots_29.io_out_uop_iw_p2_poisoned, %4397 : i1
    %4441 = comb.mux %4403, %slots_29.io_out_uop_iw_p1_poisoned, %4398 : i1
    %4442 = comb.mux %4403, %slots_29.io_out_uop_iw_state, %4399 : i2
    %4443 = comb.mux %4403, %slots_29.io_out_uop_fu_code, %4400 : i10
    %4444 = comb.mux %4403, %slots_29.io_out_uop_is_rvc, %4401 : i1
    %4445 = comb.mux %4403, %slots_29.io_out_uop_uopc, %4402 : i7
    %4446 = comb.icmp eq %1871, %c-8_i4 : i4
    %issue_slots_30_will_be_valid = sv.wire sym @issue_slots_30_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_30_will_be_valid, %slots_30.io_will_be_valid : i1
    %4447 = comb.mux %4446, %slots_30.io_will_be_valid, %4404 {sv.namehint = "_issue_slots_26_in_uop_valid"} : i1
    %issue_slots_26_in_uop_valid = sv.wire sym @issue_slots_26_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_26_in_uop_valid, %4447 : i1
    %issue_slots_30_out_uop_fp_val = sv.wire sym @issue_slots_30_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_fp_val, %slots_30.io_out_uop_fp_val : i1
    %issue_slots_30_out_uop_lrs2_rtype = sv.wire sym @issue_slots_30_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_30_out_uop_lrs2_rtype, %slots_30.io_out_uop_lrs2_rtype : i2
    %issue_slots_30_out_uop_lrs1_rtype = sv.wire sym @issue_slots_30_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_30_out_uop_lrs1_rtype, %slots_30.io_out_uop_lrs1_rtype : i2
    %issue_slots_30_out_uop_dst_rtype = sv.wire sym @issue_slots_30_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_30_out_uop_dst_rtype, %slots_30.io_out_uop_dst_rtype : i2
    %issue_slots_30_out_uop_ldst_val = sv.wire sym @issue_slots_30_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_ldst_val, %slots_30.io_out_uop_ldst_val : i1
    %issue_slots_30_out_uop_uses_stq = sv.wire sym @issue_slots_30_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_uses_stq, %slots_30.io_out_uop_uses_stq : i1
    %issue_slots_30_out_uop_uses_ldq = sv.wire sym @issue_slots_30_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_uses_ldq, %slots_30.io_out_uop_uses_ldq : i1
    %issue_slots_30_out_uop_is_amo = sv.wire sym @issue_slots_30_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_is_amo, %slots_30.io_out_uop_is_amo : i1
    %issue_slots_30_out_uop_is_fence = sv.wire sym @issue_slots_30_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_is_fence, %slots_30.io_out_uop_is_fence : i1
    %issue_slots_30_out_uop_mem_signed = sv.wire sym @issue_slots_30_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_mem_signed, %slots_30.io_out_uop_mem_signed : i1
    %issue_slots_30_out_uop_mem_size = sv.wire sym @issue_slots_30_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_30_out_uop_mem_size, %slots_30.io_out_uop_mem_size : i2
    %issue_slots_30_out_uop_mem_cmd = sv.wire sym @issue_slots_30_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_30_out_uop_mem_cmd, %slots_30.io_out_uop_mem_cmd : i5
    %issue_slots_30_out_uop_bypassable = sv.wire sym @issue_slots_30_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_bypassable, %slots_30.io_out_uop_bypassable : i1
    %issue_slots_30_out_uop_ppred_busy = sv.wire sym @issue_slots_30_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_ppred_busy, %slots_30.io_out_uop_ppred_busy : i1
    %issue_slots_30_out_uop_prs3_busy = sv.wire sym @issue_slots_30_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_prs3_busy, %slots_30.io_out_uop_prs3_busy : i1
    %issue_slots_30_out_uop_prs2_busy = sv.wire sym @issue_slots_30_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_prs2_busy, %slots_30.io_out_uop_prs2_busy : i1
    %issue_slots_30_out_uop_prs1_busy = sv.wire sym @issue_slots_30_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_prs1_busy, %slots_30.io_out_uop_prs1_busy : i1
    %issue_slots_30_out_uop_prs3 = sv.wire sym @issue_slots_30_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_30_out_uop_prs3, %slots_30.io_out_uop_prs3 : i7
    %issue_slots_30_out_uop_prs2 = sv.wire sym @issue_slots_30_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_30_out_uop_prs2, %slots_30.io_out_uop_prs2 : i7
    %issue_slots_30_out_uop_prs1 = sv.wire sym @issue_slots_30_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_30_out_uop_prs1, %slots_30.io_out_uop_prs1 : i7
    %issue_slots_30_out_uop_pdst = sv.wire sym @issue_slots_30_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_30_out_uop_pdst, %slots_30.io_out_uop_pdst : i7
    %issue_slots_30_out_uop_stq_idx = sv.wire sym @issue_slots_30_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_30_out_uop_stq_idx, %slots_30.io_out_uop_stq_idx : i5
    %issue_slots_30_out_uop_ldq_idx = sv.wire sym @issue_slots_30_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_30_out_uop_ldq_idx, %slots_30.io_out_uop_ldq_idx : i5
    %issue_slots_30_out_uop_rob_idx = sv.wire sym @issue_slots_30_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_30_out_uop_rob_idx, %slots_30.io_out_uop_rob_idx : i7
    %issue_slots_30_out_uop_imm_packed = sv.wire sym @issue_slots_30_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_30_out_uop_imm_packed, %slots_30.io_out_uop_imm_packed : i20
    %issue_slots_30_out_uop_taken = sv.wire sym @issue_slots_30_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_taken, %slots_30.io_out_uop_taken : i1
    %issue_slots_30_out_uop_pc_lob = sv.wire sym @issue_slots_30_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_30_out_uop_pc_lob, %slots_30.io_out_uop_pc_lob : i6
    %issue_slots_30_out_uop_edge_inst = sv.wire sym @issue_slots_30_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_edge_inst, %slots_30.io_out_uop_edge_inst : i1
    %issue_slots_30_out_uop_ftq_idx = sv.wire sym @issue_slots_30_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_30_out_uop_ftq_idx, %slots_30.io_out_uop_ftq_idx : i6
    %issue_slots_30_out_uop_br_tag = sv.wire sym @issue_slots_30_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_30_out_uop_br_tag, %slots_30.io_out_uop_br_tag : i5
    %issue_slots_30_out_uop_br_mask = sv.wire sym @issue_slots_30_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_30_out_uop_br_mask, %slots_30.io_out_uop_br_mask : i20
    %issue_slots_30_out_uop_is_sfb = sv.wire sym @issue_slots_30_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_is_sfb, %slots_30.io_out_uop_is_sfb : i1
    %issue_slots_30_out_uop_is_jal = sv.wire sym @issue_slots_30_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_is_jal, %slots_30.io_out_uop_is_jal : i1
    %issue_slots_30_out_uop_is_jalr = sv.wire sym @issue_slots_30_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_is_jalr, %slots_30.io_out_uop_is_jalr : i1
    %issue_slots_30_out_uop_is_br = sv.wire sym @issue_slots_30_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_is_br, %slots_30.io_out_uop_is_br : i1
    %issue_slots_30_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_30_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_iw_p2_poisoned, %slots_30.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_30_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_30_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_iw_p1_poisoned, %slots_30.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_30_out_uop_iw_state = sv.wire sym @issue_slots_30_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_30_out_uop_iw_state, %slots_30.io_out_uop_iw_state : i2
    %issue_slots_30_out_uop_fu_code = sv.wire sym @issue_slots_30_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_30_out_uop_fu_code, %slots_30.io_out_uop_fu_code : i10
    %issue_slots_30_out_uop_is_rvc = sv.wire sym @issue_slots_30_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_30_out_uop_is_rvc, %slots_30.io_out_uop_is_rvc : i1
    %issue_slots_30_out_uop_uopc = sv.wire sym @issue_slots_30_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_30_out_uop_uopc, %slots_30.io_out_uop_uopc : i7
    %4448 = comb.icmp ne %1839, %c0_i4 {sv.namehint = "_issue_slots_26_clear"} : i4
    %issue_slots_26_clear = sv.wire sym @issue_slots_26_clear  : !hw.inout<i1>
    sv.assign %issue_slots_26_clear, %4448 : i1
    %4449 = comb.icmp eq %1855, %c1_i4 : i4
    %4450 = comb.and %4449, %slots_28.io_will_be_valid : i1
    %4451 = comb.icmp eq %1863, %c2_i4 : i4
    %4452 = comb.mux %4451, %slots_29.io_will_be_valid, %4450 : i1
    %4453 = comb.mux %4451, %slots_29.io_out_uop_fp_val, %slots_28.io_out_uop_fp_val : i1
    %4454 = comb.mux %4451, %slots_29.io_out_uop_lrs2_rtype, %slots_28.io_out_uop_lrs2_rtype : i2
    %4455 = comb.mux %4451, %slots_29.io_out_uop_lrs1_rtype, %slots_28.io_out_uop_lrs1_rtype : i2
    %4456 = comb.mux %4451, %slots_29.io_out_uop_dst_rtype, %slots_28.io_out_uop_dst_rtype : i2
    %4457 = comb.mux %4451, %slots_29.io_out_uop_ldst_val, %slots_28.io_out_uop_ldst_val : i1
    %4458 = comb.mux %4451, %slots_29.io_out_uop_uses_stq, %slots_28.io_out_uop_uses_stq : i1
    %4459 = comb.mux %4451, %slots_29.io_out_uop_uses_ldq, %slots_28.io_out_uop_uses_ldq : i1
    %4460 = comb.mux %4451, %slots_29.io_out_uop_is_amo, %slots_28.io_out_uop_is_amo : i1
    %4461 = comb.mux %4451, %slots_29.io_out_uop_is_fence, %slots_28.io_out_uop_is_fence : i1
    %4462 = comb.mux %4451, %slots_29.io_out_uop_mem_signed, %slots_28.io_out_uop_mem_signed : i1
    %4463 = comb.mux %4451, %slots_29.io_out_uop_mem_size, %slots_28.io_out_uop_mem_size : i2
    %4464 = comb.mux %4451, %slots_29.io_out_uop_mem_cmd, %slots_28.io_out_uop_mem_cmd : i5
    %4465 = comb.mux %4451, %slots_29.io_out_uop_bypassable, %slots_28.io_out_uop_bypassable : i1
    %4466 = comb.mux %4451, %slots_29.io_out_uop_ppred_busy, %slots_28.io_out_uop_ppred_busy : i1
    %4467 = comb.mux %4451, %slots_29.io_out_uop_prs3_busy, %slots_28.io_out_uop_prs3_busy : i1
    %4468 = comb.mux %4451, %slots_29.io_out_uop_prs2_busy, %slots_28.io_out_uop_prs2_busy : i1
    %4469 = comb.mux %4451, %slots_29.io_out_uop_prs1_busy, %slots_28.io_out_uop_prs1_busy : i1
    %4470 = comb.mux %4451, %slots_29.io_out_uop_prs3, %slots_28.io_out_uop_prs3 : i7
    %4471 = comb.mux %4451, %slots_29.io_out_uop_prs2, %slots_28.io_out_uop_prs2 : i7
    %4472 = comb.mux %4451, %slots_29.io_out_uop_prs1, %slots_28.io_out_uop_prs1 : i7
    %4473 = comb.mux %4451, %slots_29.io_out_uop_pdst, %slots_28.io_out_uop_pdst : i7
    %4474 = comb.mux %4451, %slots_29.io_out_uop_stq_idx, %slots_28.io_out_uop_stq_idx : i5
    %4475 = comb.mux %4451, %slots_29.io_out_uop_ldq_idx, %slots_28.io_out_uop_ldq_idx : i5
    %4476 = comb.mux %4451, %slots_29.io_out_uop_rob_idx, %slots_28.io_out_uop_rob_idx : i7
    %4477 = comb.mux %4451, %slots_29.io_out_uop_imm_packed, %slots_28.io_out_uop_imm_packed : i20
    %4478 = comb.mux %4451, %slots_29.io_out_uop_taken, %slots_28.io_out_uop_taken : i1
    %4479 = comb.mux %4451, %slots_29.io_out_uop_pc_lob, %slots_28.io_out_uop_pc_lob : i6
    %4480 = comb.mux %4451, %slots_29.io_out_uop_edge_inst, %slots_28.io_out_uop_edge_inst : i1
    %4481 = comb.mux %4451, %slots_29.io_out_uop_ftq_idx, %slots_28.io_out_uop_ftq_idx : i6
    %4482 = comb.mux %4451, %slots_29.io_out_uop_br_tag, %slots_28.io_out_uop_br_tag : i5
    %4483 = comb.mux %4451, %slots_29.io_out_uop_br_mask, %slots_28.io_out_uop_br_mask : i20
    %4484 = comb.mux %4451, %slots_29.io_out_uop_is_sfb, %slots_28.io_out_uop_is_sfb : i1
    %4485 = comb.mux %4451, %slots_29.io_out_uop_is_jal, %slots_28.io_out_uop_is_jal : i1
    %4486 = comb.mux %4451, %slots_29.io_out_uop_is_jalr, %slots_28.io_out_uop_is_jalr : i1
    %4487 = comb.mux %4451, %slots_29.io_out_uop_is_br, %slots_28.io_out_uop_is_br : i1
    %4488 = comb.mux %4451, %slots_29.io_out_uop_iw_p2_poisoned, %slots_28.io_out_uop_iw_p2_poisoned : i1
    %4489 = comb.mux %4451, %slots_29.io_out_uop_iw_p1_poisoned, %slots_28.io_out_uop_iw_p1_poisoned : i1
    %4490 = comb.mux %4451, %slots_29.io_out_uop_iw_state, %slots_28.io_out_uop_iw_state : i2
    %4491 = comb.mux %4451, %slots_29.io_out_uop_fu_code, %slots_28.io_out_uop_fu_code : i10
    %4492 = comb.mux %4451, %slots_29.io_out_uop_is_rvc, %slots_28.io_out_uop_is_rvc : i1
    %4493 = comb.mux %4451, %slots_29.io_out_uop_uopc, %slots_28.io_out_uop_uopc : i7
    %4494 = comb.icmp eq %1871, %c4_i4 : i4
    %4495 = comb.mux %4494, %slots_30.io_will_be_valid, %4452 : i1
    %4496 = comb.mux %4494, %slots_30.io_out_uop_fp_val, %4453 : i1
    %4497 = comb.mux %4494, %slots_30.io_out_uop_lrs2_rtype, %4454 : i2
    %4498 = comb.mux %4494, %slots_30.io_out_uop_lrs1_rtype, %4455 : i2
    %4499 = comb.mux %4494, %slots_30.io_out_uop_dst_rtype, %4456 : i2
    %4500 = comb.mux %4494, %slots_30.io_out_uop_ldst_val, %4457 : i1
    %4501 = comb.mux %4494, %slots_30.io_out_uop_uses_stq, %4458 : i1
    %4502 = comb.mux %4494, %slots_30.io_out_uop_uses_ldq, %4459 : i1
    %4503 = comb.mux %4494, %slots_30.io_out_uop_is_amo, %4460 : i1
    %4504 = comb.mux %4494, %slots_30.io_out_uop_is_fence, %4461 : i1
    %4505 = comb.mux %4494, %slots_30.io_out_uop_mem_signed, %4462 : i1
    %4506 = comb.mux %4494, %slots_30.io_out_uop_mem_size, %4463 : i2
    %4507 = comb.mux %4494, %slots_30.io_out_uop_mem_cmd, %4464 : i5
    %4508 = comb.mux %4494, %slots_30.io_out_uop_bypassable, %4465 : i1
    %4509 = comb.mux %4494, %slots_30.io_out_uop_ppred_busy, %4466 : i1
    %4510 = comb.mux %4494, %slots_30.io_out_uop_prs3_busy, %4467 : i1
    %4511 = comb.mux %4494, %slots_30.io_out_uop_prs2_busy, %4468 : i1
    %4512 = comb.mux %4494, %slots_30.io_out_uop_prs1_busy, %4469 : i1
    %4513 = comb.mux %4494, %slots_30.io_out_uop_prs3, %4470 : i7
    %4514 = comb.mux %4494, %slots_30.io_out_uop_prs2, %4471 : i7
    %4515 = comb.mux %4494, %slots_30.io_out_uop_prs1, %4472 : i7
    %4516 = comb.mux %4494, %slots_30.io_out_uop_pdst, %4473 : i7
    %4517 = comb.mux %4494, %slots_30.io_out_uop_stq_idx, %4474 : i5
    %4518 = comb.mux %4494, %slots_30.io_out_uop_ldq_idx, %4475 : i5
    %4519 = comb.mux %4494, %slots_30.io_out_uop_rob_idx, %4476 : i7
    %4520 = comb.mux %4494, %slots_30.io_out_uop_imm_packed, %4477 : i20
    %4521 = comb.mux %4494, %slots_30.io_out_uop_taken, %4478 : i1
    %4522 = comb.mux %4494, %slots_30.io_out_uop_pc_lob, %4479 : i6
    %4523 = comb.mux %4494, %slots_30.io_out_uop_edge_inst, %4480 : i1
    %4524 = comb.mux %4494, %slots_30.io_out_uop_ftq_idx, %4481 : i6
    %4525 = comb.mux %4494, %slots_30.io_out_uop_br_tag, %4482 : i5
    %4526 = comb.mux %4494, %slots_30.io_out_uop_br_mask, %4483 : i20
    %4527 = comb.mux %4494, %slots_30.io_out_uop_is_sfb, %4484 : i1
    %4528 = comb.mux %4494, %slots_30.io_out_uop_is_jal, %4485 : i1
    %4529 = comb.mux %4494, %slots_30.io_out_uop_is_jalr, %4486 : i1
    %4530 = comb.mux %4494, %slots_30.io_out_uop_is_br, %4487 : i1
    %4531 = comb.mux %4494, %slots_30.io_out_uop_iw_p2_poisoned, %4488 : i1
    %4532 = comb.mux %4494, %slots_30.io_out_uop_iw_p1_poisoned, %4489 : i1
    %4533 = comb.mux %4494, %slots_30.io_out_uop_iw_state, %4490 : i2
    %4534 = comb.mux %4494, %slots_30.io_out_uop_fu_code, %4491 : i10
    %4535 = comb.mux %4494, %slots_30.io_out_uop_is_rvc, %4492 : i1
    %4536 = comb.mux %4494, %slots_30.io_out_uop_uopc, %4493 : i7
    %4537 = comb.icmp eq %1879, %c-8_i4 : i4
    %issue_slots_31_will_be_valid = sv.wire sym @issue_slots_31_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_31_will_be_valid, %slots_31.io_will_be_valid : i1
    %4538 = comb.mux %4537, %slots_31.io_will_be_valid, %4495 {sv.namehint = "_issue_slots_27_in_uop_valid"} : i1
    %issue_slots_27_in_uop_valid = sv.wire sym @issue_slots_27_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_27_in_uop_valid, %4538 : i1
    %issue_slots_31_out_uop_fp_val = sv.wire sym @issue_slots_31_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_fp_val, %slots_31.io_out_uop_fp_val : i1
    %issue_slots_31_out_uop_lrs2_rtype = sv.wire sym @issue_slots_31_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_31_out_uop_lrs2_rtype, %slots_31.io_out_uop_lrs2_rtype : i2
    %issue_slots_31_out_uop_lrs1_rtype = sv.wire sym @issue_slots_31_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_31_out_uop_lrs1_rtype, %slots_31.io_out_uop_lrs1_rtype : i2
    %issue_slots_31_out_uop_dst_rtype = sv.wire sym @issue_slots_31_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_31_out_uop_dst_rtype, %slots_31.io_out_uop_dst_rtype : i2
    %issue_slots_31_out_uop_ldst_val = sv.wire sym @issue_slots_31_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_ldst_val, %slots_31.io_out_uop_ldst_val : i1
    %issue_slots_31_out_uop_uses_stq = sv.wire sym @issue_slots_31_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_uses_stq, %slots_31.io_out_uop_uses_stq : i1
    %issue_slots_31_out_uop_uses_ldq = sv.wire sym @issue_slots_31_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_uses_ldq, %slots_31.io_out_uop_uses_ldq : i1
    %issue_slots_31_out_uop_is_amo = sv.wire sym @issue_slots_31_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_is_amo, %slots_31.io_out_uop_is_amo : i1
    %issue_slots_31_out_uop_is_fence = sv.wire sym @issue_slots_31_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_is_fence, %slots_31.io_out_uop_is_fence : i1
    %issue_slots_31_out_uop_mem_signed = sv.wire sym @issue_slots_31_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_mem_signed, %slots_31.io_out_uop_mem_signed : i1
    %issue_slots_31_out_uop_mem_size = sv.wire sym @issue_slots_31_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_31_out_uop_mem_size, %slots_31.io_out_uop_mem_size : i2
    %issue_slots_31_out_uop_mem_cmd = sv.wire sym @issue_slots_31_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_31_out_uop_mem_cmd, %slots_31.io_out_uop_mem_cmd : i5
    %issue_slots_31_out_uop_bypassable = sv.wire sym @issue_slots_31_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_bypassable, %slots_31.io_out_uop_bypassable : i1
    %issue_slots_31_out_uop_ppred_busy = sv.wire sym @issue_slots_31_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_ppred_busy, %slots_31.io_out_uop_ppred_busy : i1
    %issue_slots_31_out_uop_prs3_busy = sv.wire sym @issue_slots_31_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_prs3_busy, %slots_31.io_out_uop_prs3_busy : i1
    %issue_slots_31_out_uop_prs2_busy = sv.wire sym @issue_slots_31_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_prs2_busy, %slots_31.io_out_uop_prs2_busy : i1
    %issue_slots_31_out_uop_prs1_busy = sv.wire sym @issue_slots_31_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_prs1_busy, %slots_31.io_out_uop_prs1_busy : i1
    %issue_slots_31_out_uop_prs3 = sv.wire sym @issue_slots_31_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_31_out_uop_prs3, %slots_31.io_out_uop_prs3 : i7
    %issue_slots_31_out_uop_prs2 = sv.wire sym @issue_slots_31_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_31_out_uop_prs2, %slots_31.io_out_uop_prs2 : i7
    %issue_slots_31_out_uop_prs1 = sv.wire sym @issue_slots_31_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_31_out_uop_prs1, %slots_31.io_out_uop_prs1 : i7
    %issue_slots_31_out_uop_pdst = sv.wire sym @issue_slots_31_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_31_out_uop_pdst, %slots_31.io_out_uop_pdst : i7
    %issue_slots_31_out_uop_stq_idx = sv.wire sym @issue_slots_31_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_31_out_uop_stq_idx, %slots_31.io_out_uop_stq_idx : i5
    %issue_slots_31_out_uop_ldq_idx = sv.wire sym @issue_slots_31_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_31_out_uop_ldq_idx, %slots_31.io_out_uop_ldq_idx : i5
    %issue_slots_31_out_uop_rob_idx = sv.wire sym @issue_slots_31_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_31_out_uop_rob_idx, %slots_31.io_out_uop_rob_idx : i7
    %issue_slots_31_out_uop_imm_packed = sv.wire sym @issue_slots_31_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_31_out_uop_imm_packed, %slots_31.io_out_uop_imm_packed : i20
    %issue_slots_31_out_uop_taken = sv.wire sym @issue_slots_31_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_taken, %slots_31.io_out_uop_taken : i1
    %issue_slots_31_out_uop_pc_lob = sv.wire sym @issue_slots_31_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_31_out_uop_pc_lob, %slots_31.io_out_uop_pc_lob : i6
    %issue_slots_31_out_uop_edge_inst = sv.wire sym @issue_slots_31_out_uop_edge_inst  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_edge_inst, %slots_31.io_out_uop_edge_inst : i1
    %issue_slots_31_out_uop_ftq_idx = sv.wire sym @issue_slots_31_out_uop_ftq_idx  : !hw.inout<i6>
    sv.assign %issue_slots_31_out_uop_ftq_idx, %slots_31.io_out_uop_ftq_idx : i6
    %issue_slots_31_out_uop_br_tag = sv.wire sym @issue_slots_31_out_uop_br_tag  : !hw.inout<i5>
    sv.assign %issue_slots_31_out_uop_br_tag, %slots_31.io_out_uop_br_tag : i5
    %issue_slots_31_out_uop_br_mask = sv.wire sym @issue_slots_31_out_uop_br_mask  : !hw.inout<i20>
    sv.assign %issue_slots_31_out_uop_br_mask, %slots_31.io_out_uop_br_mask : i20
    %issue_slots_31_out_uop_is_sfb = sv.wire sym @issue_slots_31_out_uop_is_sfb  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_is_sfb, %slots_31.io_out_uop_is_sfb : i1
    %issue_slots_31_out_uop_is_jal = sv.wire sym @issue_slots_31_out_uop_is_jal  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_is_jal, %slots_31.io_out_uop_is_jal : i1
    %issue_slots_31_out_uop_is_jalr = sv.wire sym @issue_slots_31_out_uop_is_jalr  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_is_jalr, %slots_31.io_out_uop_is_jalr : i1
    %issue_slots_31_out_uop_is_br = sv.wire sym @issue_slots_31_out_uop_is_br  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_is_br, %slots_31.io_out_uop_is_br : i1
    %issue_slots_31_out_uop_iw_p2_poisoned = sv.wire sym @issue_slots_31_out_uop_iw_p2_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_iw_p2_poisoned, %slots_31.io_out_uop_iw_p2_poisoned : i1
    %issue_slots_31_out_uop_iw_p1_poisoned = sv.wire sym @issue_slots_31_out_uop_iw_p1_poisoned  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_iw_p1_poisoned, %slots_31.io_out_uop_iw_p1_poisoned : i1
    %issue_slots_31_out_uop_iw_state = sv.wire sym @issue_slots_31_out_uop_iw_state  : !hw.inout<i2>
    sv.assign %issue_slots_31_out_uop_iw_state, %slots_31.io_out_uop_iw_state : i2
    %issue_slots_31_out_uop_fu_code = sv.wire sym @issue_slots_31_out_uop_fu_code  : !hw.inout<i10>
    sv.assign %issue_slots_31_out_uop_fu_code, %slots_31.io_out_uop_fu_code : i10
    %issue_slots_31_out_uop_is_rvc = sv.wire sym @issue_slots_31_out_uop_is_rvc  : !hw.inout<i1>
    sv.assign %issue_slots_31_out_uop_is_rvc, %slots_31.io_out_uop_is_rvc : i1
    %issue_slots_31_out_uop_uopc = sv.wire sym @issue_slots_31_out_uop_uopc  : !hw.inout<i7>
    sv.assign %issue_slots_31_out_uop_uopc, %slots_31.io_out_uop_uopc : i7
    %4539 = comb.icmp ne %1847, %c0_i4 {sv.namehint = "_issue_slots_27_clear"} : i4
    %issue_slots_27_clear = sv.wire sym @issue_slots_27_clear  : !hw.inout<i1>
    sv.assign %issue_slots_27_clear, %4539 : i1
    %4540 = comb.icmp eq %1863, %c1_i4 : i4
    %4541 = comb.and %4540, %slots_29.io_will_be_valid : i1
    %4542 = comb.icmp eq %1871, %c2_i4 : i4
    %4543 = comb.mux %4542, %slots_30.io_will_be_valid, %4541 : i1
    %4544 = comb.mux %4542, %slots_30.io_out_uop_fp_val, %slots_29.io_out_uop_fp_val : i1
    %4545 = comb.mux %4542, %slots_30.io_out_uop_lrs2_rtype, %slots_29.io_out_uop_lrs2_rtype : i2
    %4546 = comb.mux %4542, %slots_30.io_out_uop_lrs1_rtype, %slots_29.io_out_uop_lrs1_rtype : i2
    %4547 = comb.mux %4542, %slots_30.io_out_uop_dst_rtype, %slots_29.io_out_uop_dst_rtype : i2
    %4548 = comb.mux %4542, %slots_30.io_out_uop_ldst_val, %slots_29.io_out_uop_ldst_val : i1
    %4549 = comb.mux %4542, %slots_30.io_out_uop_uses_stq, %slots_29.io_out_uop_uses_stq : i1
    %4550 = comb.mux %4542, %slots_30.io_out_uop_uses_ldq, %slots_29.io_out_uop_uses_ldq : i1
    %4551 = comb.mux %4542, %slots_30.io_out_uop_is_amo, %slots_29.io_out_uop_is_amo : i1
    %4552 = comb.mux %4542, %slots_30.io_out_uop_is_fence, %slots_29.io_out_uop_is_fence : i1
    %4553 = comb.mux %4542, %slots_30.io_out_uop_mem_signed, %slots_29.io_out_uop_mem_signed : i1
    %4554 = comb.mux %4542, %slots_30.io_out_uop_mem_size, %slots_29.io_out_uop_mem_size : i2
    %4555 = comb.mux %4542, %slots_30.io_out_uop_mem_cmd, %slots_29.io_out_uop_mem_cmd : i5
    %4556 = comb.mux %4542, %slots_30.io_out_uop_bypassable, %slots_29.io_out_uop_bypassable : i1
    %4557 = comb.mux %4542, %slots_30.io_out_uop_ppred_busy, %slots_29.io_out_uop_ppred_busy : i1
    %4558 = comb.mux %4542, %slots_30.io_out_uop_prs3_busy, %slots_29.io_out_uop_prs3_busy : i1
    %4559 = comb.mux %4542, %slots_30.io_out_uop_prs2_busy, %slots_29.io_out_uop_prs2_busy : i1
    %4560 = comb.mux %4542, %slots_30.io_out_uop_prs1_busy, %slots_29.io_out_uop_prs1_busy : i1
    %4561 = comb.mux %4542, %slots_30.io_out_uop_prs3, %slots_29.io_out_uop_prs3 : i7
    %4562 = comb.mux %4542, %slots_30.io_out_uop_prs2, %slots_29.io_out_uop_prs2 : i7
    %4563 = comb.mux %4542, %slots_30.io_out_uop_prs1, %slots_29.io_out_uop_prs1 : i7
    %4564 = comb.mux %4542, %slots_30.io_out_uop_pdst, %slots_29.io_out_uop_pdst : i7
    %4565 = comb.mux %4542, %slots_30.io_out_uop_stq_idx, %slots_29.io_out_uop_stq_idx : i5
    %4566 = comb.mux %4542, %slots_30.io_out_uop_ldq_idx, %slots_29.io_out_uop_ldq_idx : i5
    %4567 = comb.mux %4542, %slots_30.io_out_uop_rob_idx, %slots_29.io_out_uop_rob_idx : i7
    %4568 = comb.mux %4542, %slots_30.io_out_uop_imm_packed, %slots_29.io_out_uop_imm_packed : i20
    %4569 = comb.mux %4542, %slots_30.io_out_uop_taken, %slots_29.io_out_uop_taken : i1
    %4570 = comb.mux %4542, %slots_30.io_out_uop_pc_lob, %slots_29.io_out_uop_pc_lob : i6
    %4571 = comb.mux %4542, %slots_30.io_out_uop_edge_inst, %slots_29.io_out_uop_edge_inst : i1
    %4572 = comb.mux %4542, %slots_30.io_out_uop_ftq_idx, %slots_29.io_out_uop_ftq_idx : i6
    %4573 = comb.mux %4542, %slots_30.io_out_uop_br_tag, %slots_29.io_out_uop_br_tag : i5
    %4574 = comb.mux %4542, %slots_30.io_out_uop_br_mask, %slots_29.io_out_uop_br_mask : i20
    %4575 = comb.mux %4542, %slots_30.io_out_uop_is_sfb, %slots_29.io_out_uop_is_sfb : i1
    %4576 = comb.mux %4542, %slots_30.io_out_uop_is_jal, %slots_29.io_out_uop_is_jal : i1
    %4577 = comb.mux %4542, %slots_30.io_out_uop_is_jalr, %slots_29.io_out_uop_is_jalr : i1
    %4578 = comb.mux %4542, %slots_30.io_out_uop_is_br, %slots_29.io_out_uop_is_br : i1
    %4579 = comb.mux %4542, %slots_30.io_out_uop_iw_p2_poisoned, %slots_29.io_out_uop_iw_p2_poisoned : i1
    %4580 = comb.mux %4542, %slots_30.io_out_uop_iw_p1_poisoned, %slots_29.io_out_uop_iw_p1_poisoned : i1
    %4581 = comb.mux %4542, %slots_30.io_out_uop_iw_state, %slots_29.io_out_uop_iw_state : i2
    %4582 = comb.mux %4542, %slots_30.io_out_uop_fu_code, %slots_29.io_out_uop_fu_code : i10
    %4583 = comb.mux %4542, %slots_30.io_out_uop_is_rvc, %slots_29.io_out_uop_is_rvc : i1
    %4584 = comb.mux %4542, %slots_30.io_out_uop_uopc, %slots_29.io_out_uop_uopc : i7
    %4585 = comb.icmp eq %1879, %c4_i4 : i4
    %4586 = comb.mux %4585, %slots_31.io_will_be_valid, %4543 : i1
    %4587 = comb.mux %4585, %slots_31.io_out_uop_fp_val, %4544 : i1
    %4588 = comb.mux %4585, %slots_31.io_out_uop_lrs2_rtype, %4545 : i2
    %4589 = comb.mux %4585, %slots_31.io_out_uop_lrs1_rtype, %4546 : i2
    %4590 = comb.mux %4585, %slots_31.io_out_uop_dst_rtype, %4547 : i2
    %4591 = comb.mux %4585, %slots_31.io_out_uop_ldst_val, %4548 : i1
    %4592 = comb.mux %4585, %slots_31.io_out_uop_uses_stq, %4549 : i1
    %4593 = comb.mux %4585, %slots_31.io_out_uop_uses_ldq, %4550 : i1
    %4594 = comb.mux %4585, %slots_31.io_out_uop_is_amo, %4551 : i1
    %4595 = comb.mux %4585, %slots_31.io_out_uop_is_fence, %4552 : i1
    %4596 = comb.mux %4585, %slots_31.io_out_uop_mem_signed, %4553 : i1
    %4597 = comb.mux %4585, %slots_31.io_out_uop_mem_size, %4554 : i2
    %4598 = comb.mux %4585, %slots_31.io_out_uop_mem_cmd, %4555 : i5
    %4599 = comb.mux %4585, %slots_31.io_out_uop_bypassable, %4556 : i1
    %4600 = comb.mux %4585, %slots_31.io_out_uop_ppred_busy, %4557 : i1
    %4601 = comb.mux %4585, %slots_31.io_out_uop_prs3_busy, %4558 : i1
    %4602 = comb.mux %4585, %slots_31.io_out_uop_prs2_busy, %4559 : i1
    %4603 = comb.mux %4585, %slots_31.io_out_uop_prs1_busy, %4560 : i1
    %4604 = comb.mux %4585, %slots_31.io_out_uop_prs3, %4561 : i7
    %4605 = comb.mux %4585, %slots_31.io_out_uop_prs2, %4562 : i7
    %4606 = comb.mux %4585, %slots_31.io_out_uop_prs1, %4563 : i7
    %4607 = comb.mux %4585, %slots_31.io_out_uop_pdst, %4564 : i7
    %4608 = comb.mux %4585, %slots_31.io_out_uop_stq_idx, %4565 : i5
    %4609 = comb.mux %4585, %slots_31.io_out_uop_ldq_idx, %4566 : i5
    %4610 = comb.mux %4585, %slots_31.io_out_uop_rob_idx, %4567 : i7
    %4611 = comb.mux %4585, %slots_31.io_out_uop_imm_packed, %4568 : i20
    %4612 = comb.mux %4585, %slots_31.io_out_uop_taken, %4569 : i1
    %4613 = comb.mux %4585, %slots_31.io_out_uop_pc_lob, %4570 : i6
    %4614 = comb.mux %4585, %slots_31.io_out_uop_edge_inst, %4571 : i1
    %4615 = comb.mux %4585, %slots_31.io_out_uop_ftq_idx, %4572 : i6
    %4616 = comb.mux %4585, %slots_31.io_out_uop_br_tag, %4573 : i5
    %4617 = comb.mux %4585, %slots_31.io_out_uop_br_mask, %4574 : i20
    %4618 = comb.mux %4585, %slots_31.io_out_uop_is_sfb, %4575 : i1
    %4619 = comb.mux %4585, %slots_31.io_out_uop_is_jal, %4576 : i1
    %4620 = comb.mux %4585, %slots_31.io_out_uop_is_jalr, %4577 : i1
    %4621 = comb.mux %4585, %slots_31.io_out_uop_is_br, %4578 : i1
    %4622 = comb.mux %4585, %slots_31.io_out_uop_iw_p2_poisoned, %4579 : i1
    %4623 = comb.mux %4585, %slots_31.io_out_uop_iw_p1_poisoned, %4580 : i1
    %4624 = comb.mux %4585, %slots_31.io_out_uop_iw_state, %4581 : i2
    %4625 = comb.mux %4585, %slots_31.io_out_uop_fu_code, %4582 : i10
    %4626 = comb.mux %4585, %slots_31.io_out_uop_is_rvc, %4583 : i1
    %4627 = comb.mux %4585, %slots_31.io_out_uop_uopc, %4584 : i7
    %4628 = comb.icmp eq %1887, %c-8_i4 : i4
    %issue_slots_32_will_be_valid = sv.wire sym @issue_slots_32_will_be_valid  : !hw.inout<i1>
    sv.assign %issue_slots_32_will_be_valid, %slots_32.io_will_be_valid : i1
    %4629 = comb.mux %4628, %slots_32.io_will_be_valid, %4586 {sv.namehint = "_issue_slots_28_in_uop_valid"} : i1
    %issue_slots_28_in_uop_valid = sv.wire sym @issue_slots_28_in_uop_valid  : !hw.inout<i1>
    sv.assign %issue_slots_28_in_uop_valid, %4629 : i1
    %issue_slots_32_out_uop_fp_val = sv.wire sym @issue_slots_32_out_uop_fp_val  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_fp_val, %slots_32.io_out_uop_fp_val : i1
    %issue_slots_32_out_uop_lrs2_rtype = sv.wire sym @issue_slots_32_out_uop_lrs2_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_32_out_uop_lrs2_rtype, %slots_32.io_out_uop_lrs2_rtype : i2
    %issue_slots_32_out_uop_lrs1_rtype = sv.wire sym @issue_slots_32_out_uop_lrs1_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_32_out_uop_lrs1_rtype, %slots_32.io_out_uop_lrs1_rtype : i2
    %issue_slots_32_out_uop_dst_rtype = sv.wire sym @issue_slots_32_out_uop_dst_rtype  : !hw.inout<i2>
    sv.assign %issue_slots_32_out_uop_dst_rtype, %slots_32.io_out_uop_dst_rtype : i2
    %issue_slots_32_out_uop_ldst_val = sv.wire sym @issue_slots_32_out_uop_ldst_val  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_ldst_val, %slots_32.io_out_uop_ldst_val : i1
    %issue_slots_32_out_uop_uses_stq = sv.wire sym @issue_slots_32_out_uop_uses_stq  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_uses_stq, %slots_32.io_out_uop_uses_stq : i1
    %issue_slots_32_out_uop_uses_ldq = sv.wire sym @issue_slots_32_out_uop_uses_ldq  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_uses_ldq, %slots_32.io_out_uop_uses_ldq : i1
    %issue_slots_32_out_uop_is_amo = sv.wire sym @issue_slots_32_out_uop_is_amo  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_is_amo, %slots_32.io_out_uop_is_amo : i1
    %issue_slots_32_out_uop_is_fence = sv.wire sym @issue_slots_32_out_uop_is_fence  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_is_fence, %slots_32.io_out_uop_is_fence : i1
    %issue_slots_32_out_uop_mem_signed = sv.wire sym @issue_slots_32_out_uop_mem_signed  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_mem_signed, %slots_32.io_out_uop_mem_signed : i1
    %issue_slots_32_out_uop_mem_size = sv.wire sym @issue_slots_32_out_uop_mem_size  : !hw.inout<i2>
    sv.assign %issue_slots_32_out_uop_mem_size, %slots_32.io_out_uop_mem_size : i2
    %issue_slots_32_out_uop_mem_cmd = sv.wire sym @issue_slots_32_out_uop_mem_cmd  : !hw.inout<i5>
    sv.assign %issue_slots_32_out_uop_mem_cmd, %slots_32.io_out_uop_mem_cmd : i5
    %issue_slots_32_out_uop_bypassable = sv.wire sym @issue_slots_32_out_uop_bypassable  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_bypassable, %slots_32.io_out_uop_bypassable : i1
    %issue_slots_32_out_uop_ppred_busy = sv.wire sym @issue_slots_32_out_uop_ppred_busy  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_ppred_busy, %slots_32.io_out_uop_ppred_busy : i1
    %issue_slots_32_out_uop_prs3_busy = sv.wire sym @issue_slots_32_out_uop_prs3_busy  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_prs3_busy, %slots_32.io_out_uop_prs3_busy : i1
    %issue_slots_32_out_uop_prs2_busy = sv.wire sym @issue_slots_32_out_uop_prs2_busy  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_prs2_busy, %slots_32.io_out_uop_prs2_busy : i1
    %issue_slots_32_out_uop_prs1_busy = sv.wire sym @issue_slots_32_out_uop_prs1_busy  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_prs1_busy, %slots_32.io_out_uop_prs1_busy : i1
    %issue_slots_32_out_uop_prs3 = sv.wire sym @issue_slots_32_out_uop_prs3  : !hw.inout<i7>
    sv.assign %issue_slots_32_out_uop_prs3, %slots_32.io_out_uop_prs3 : i7
    %issue_slots_32_out_uop_prs2 = sv.wire sym @issue_slots_32_out_uop_prs2  : !hw.inout<i7>
    sv.assign %issue_slots_32_out_uop_prs2, %slots_32.io_out_uop_prs2 : i7
    %issue_slots_32_out_uop_prs1 = sv.wire sym @issue_slots_32_out_uop_prs1  : !hw.inout<i7>
    sv.assign %issue_slots_32_out_uop_prs1, %slots_32.io_out_uop_prs1 : i7
    %issue_slots_32_out_uop_pdst = sv.wire sym @issue_slots_32_out_uop_pdst  : !hw.inout<i7>
    sv.assign %issue_slots_32_out_uop_pdst, %slots_32.io_out_uop_pdst : i7
    %issue_slots_32_out_uop_stq_idx = sv.wire sym @issue_slots_32_out_uop_stq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_32_out_uop_stq_idx, %slots_32.io_out_uop_stq_idx : i5
    %issue_slots_32_out_uop_ldq_idx = sv.wire sym @issue_slots_32_out_uop_ldq_idx  : !hw.inout<i5>
    sv.assign %issue_slots_32_out_uop_ldq_idx, %slots_32.io_out_uop_ldq_idx : i5
    %issue_slots_32_out_uop_rob_idx = sv.wire sym @issue_slots_32_out_uop_rob_idx  : !hw.inout<i7>
    sv.assign %issue_slots_32_out_uop_rob_idx, %slots_32.io_out_uop_rob_idx : i7
    %issue_slots_32_out_uop_imm_packed = sv.wire sym @issue_slots_32_out_uop_imm_packed  : !hw.inout<i20>
    sv.assign %issue_slots_32_out_uop_imm_packed, %slots_32.io_out_uop_imm_packed : i20
    %issue_slots_32_out_uop_taken = sv.wire sym @issue_slots_32_out_uop_taken  : !hw.inout<i1>
    sv.assign %issue_slots_32_out_uop_taken, %slots_32.io_out_uop_taken : i1
    %issue_slots_32_out_uop_pc_lob = sv.wire sym @issue_slots_32_out_uop_pc_lob  : !hw.inout<i6>
    sv.assign %issue_slots_32_out