LED_blink_by_ArtyS7.v

module top1(
   input wire CLK100MHZ,
   output  wire [3:0] led
   );
   
   reg [28:0] counter;
   reg LED_status;
   
   initial begin 
      counter <= 28'b0;
      LED_status <= 1'b0;
   end
   
   always @ (posedge CLK100MHZ) begin
      counter <= counter + 1'b1;
      if (counter > 100000000) begin
         LED_status <= !LED_status;
         counter <= 28'b0;
      end
   end
   
   assign led[0] = LED_status;
   assign led[1] = LED_status;
   assign led[2] = LED_status;
   assign led[3] = LED_status;
   
endmodule