Torsten Reuschel unbtorsten
unbtorsten
/ clock_forwarding_example.v
Created
December 11, 2021 00:30
— forked from controlpaths/clock_forwarding_example.v
Clock forwarding example for Xilinx 7 series
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| /* Clock forwarding for DAC. Single anded clock */ | |
| ODDR #( | |
| .DDR_CLK_EDGE("SAME_EDGE"), | |
| .INIT(1'b0), | |
| .SRTYPE("SYNC") | |
| )ODDR_CLKDAC( | |
| .Q(o_dac_clkout), | |
| .C(clk100mhz), | |
| .CE(1'b1), | |
| .D1(1'b0), |