UCF file for Digilent Xilinx CoolRunner-II CPLD Starter Board

README.md

User Constraints File for Digilent CoolRunner-II CPLD Starter Board

This is intended to be a complete and ready-to-use user constraints file for the [Digilent CoolRunner-II CPLD Starter Board][1] to ease the creation of projects within the Xilinx ISE software.

Hardware Interface Overview

Below is a list of the high-level I/O components featured on the board:

• LEDs - 4
• Slide Switches - 2
• Push Buttons - 2
• 4-digit, Common-Cathode "Seven Segment" LED Display
• 8MHz onboard oscillator
• 8-DIP footprint for additional oscillator (unpopulated)
• 40-pin (2x20) 0.1" Pin Header for I/O expansion (unpopulated) - Contains 37 I/O signals
• Pmod Connector (2-row) (2x6 female 0.1" pin header) - 4
• Interface to Atmel AT90USB162 - Provides multiple functions
  • Digilent (Adept) JTAG interface
  • 8 signals from Port D
  • 4 signals from Port C
• Voltage Regulator Reset Signal - output
• DS28E01Q-100 1-Wire EEPROM - provides secure memory

netio.ucf

#
# netio.ucf
#

##########
# CLOCKS #
##########
## PCLK (On-board 8MHz oscillator) -- P38 ##
NET "CLK"					LOC = "P38";
NET "CLK"					IOSTANDARD = LVCMOS33;
NET "CLK"					BUFG = CLK;
#NET "CLK"					COOL_CLK;

## ACLK (Auxilliary clock input via onboard socket) -- P32 ##
NET "ACLK"					LOC = "P32";
NET "ACLK"					IOSTANDARD = LVCMOS33;
NET "ACLK"					BUFG = CLK;
#NET "ACLK"					COOL_CLK;


#################
# ON-BOARD LEDS #
#################
NET "ONBOARD_LED<0>"		LOC = "P69";
NET "ONBOARD_LED<0>"		IOSTANDARD = LVCMOS33;
NET "ONBOARD_LED<1>"		LOC = "P68";
NET "ONBOARD_LED<1>"		IOSTANDARD = LVCMOS33;
NET "ONBOARD_LED<2>"		LOC = "P66";
NET "ONBOARD_LED<2>"		IOSTANDARD = LVCMOS33;
NET "ONBOARD_LED<3>"		LOC = "P64";
NET "ONBOARD_LED<3>"		IOSTANDARD = LVCMOS33;


#########################
# ON-BOARD PUSH BUTTONS #
#########################
NET "PUSH_BTN<0>"			LOC = "P143";
NET "PUSH_BTN<0>"			IOSTANDARD = LVCMOS33;
NET "PUSH_BTN<1>"			LOC = "P94";
NET "PUSH_BTN<1>"			IOSTANDARD = LVCMOS33;


###########################
# ON-BOARD SLIDE SWITCHES #
###########################
NET "SLIDE_SW<0>"			LOC = "P39";
NET "SLIDE_SW<0>"			IOSTANDARD = LVCMOS33;
NET "SLIDE_SW<1>"			LOC = "P124";
NET "SLIDE_SW<1>"			IOSTANDARD = LVCMOS33;


###########################################
# ON-BOARD 4-DIGIT, 7-SEGMENT LED DISPLAY #
###########################################
#
# CATHODES
# Shared between digits, active low
#
NET "SEVSEG_CATHODE<0>"		LOC = "P56";
NET "SEVSEG_CATHODE<0>"		IOSTANDARD = LVCMOS33;
NET "SEVSEG_CATHODE<1>"		LOC = "P53";
NET "SEVSEG_CATHODE<1>"		IOSTANDARD = LVCMOS33;
NET "SEVSEG_CATHODE<2>"		LOC = "P60";
NET "SEVSEG_CATHODE<2>"		IOSTANDARD = LVCMOS33;
NET "SEVSEG_CATHODE<3>"		LOC = "P58";
NET "SEVSEG_CATHODE<3>"		IOSTANDARD = LVCMOS33;
NET "SEVSEG_CATHODE<4>"		LOC = "P57";
NET "SEVSEG_CATHODE<4>"		IOSTANDARD = LVCMOS33;
NET "SEVSEG_CATHODE<5>"		LOC = "P54";
NET "SEVSEG_CATHODE<5>"		IOSTANDARD = LVCMOS33;
NET "SEVSEG_CATHODE<6>"		LOC = "P61";
NET "SEVSEG_CATHODE<6>"		IOSTANDARD = LVCMOS33;
NET "SEVSEG_CATHODE<7>"		LOC = "P59";
NET "SEVSEG_CATHODE<7>"		IOSTANDARD = LVCMOS33;


#
# ANODES
# Selects active digit, driven by high-side PNP transistor, active low
#
NET "SEVSEG_ANODE<3>"		LOC = "P130";
NET "SEVSEG_ANODE<3>"		IOSTANDARD = LVCMOS33;
NET "SEVSEG_ANODE<2>"		LOC = "P129";
NET "SEVSEG_ANODE<2>"		IOSTANDARD = LVCMOS33;
NET "SEVSEG_ANODE<1>"		LOC = "P128";
NET "SEVSEG_ANODE<1>"		IOSTANDARD = LVCMOS33;
NET "SEVSEG_ANODE<0>"		LOC = "P126";
NET "SEVSEG_ANODE<0>"		IOSTANDARD = LVCMOS33;


#
# Pmod Connectors
#
# Format: PMOD<connector_number>[T|B] (top/bottom row)
#

##
## Pmod 1
##
NET "PMOD1B<0>"				LOC = "P9";
NET "PMOD1B<0>"				IOSTANDARD = LVCMOS33;
NET "PMOD1B<1>"				LOC = "P6";
NET "PMOD1B<1>"				IOSTANDARD = LVCMOS33;
NET "PMOD1B<2>"				LOC = "P4";
NET "PMOD1B<2>"				IOSTANDARD = LVCMOS33;
NET "PMOD1B<3>"				LOC = "P2";
NET "PMOD1B<3>"				IOSTANDARD = LVCMOS33;

NET "PMOD1T<0>"				LOC = "P10";
NET "PMOD1T<0>"				IOSTANDARD = LVCMOS33;
NET "PMOD1T<1>"				LOC = "P7";
NET "PMOD1T<1>"				IOSTANDARD = LVCMOS33;
NET "PMOD1T<2>"				LOC = "P5";
NET "PMOD1T<2>"				IOSTANDARD = LVCMOS33;
NET "PMOD1T<3>"				LOC = "P3";
NET "PMOD1T<3>"				IOSTANDARD = LVCMOS33;


##
## Pmod 2
##
NET "PMOD2B<0>"				LOC = "P140";
NET "PMOD2B<0>"				IOSTANDARD = LVCMOS33;
NET "PMOD2B<1>"				LOC = "P138";
NET "PMOD2B<1>"				IOSTANDARD = LVCMOS33;
NET "PMOD2B<2>"				LOC = "P135";
NET "PMOD2B<2>"				IOSTANDARD = LVCMOS33;
NET "PMOD2B<3>"				LOC = "P133";
NET "PMOD2B<3>"				IOSTANDARD = LVCMOS33;

NET "PMOD2T<0>"				LOC = "P142";
NET "PMOD2T<0>"				IOSTANDARD = LVCMOS33;
NET "PMOD2T<1>"				LOC = "P139";
NET "PMOD2T<1>"				IOSTANDARD = LVCMOS33;
NET "PMOD2T<2>"				LOC = "P136";
NET "PMOD2T<2>"				IOSTANDARD = LVCMOS33;
NET "PMOD2T<3>"				LOC = "P134";
NET "PMOD2T<3>"				IOSTANDARD = LVCMOS33;


##
## Pmod 3
##
NET "PMOD3B<0>"				LOC = "P118";
NET "PMOD3B<0>"				IOSTANDARD = LVCMOS33;
NET "PMOD3B<1>"				LOC = "P116";
NET "PMOD3B<1>"				IOSTANDARD = LVCMOS33;
NET "PMOD3B<2>"				LOC = "P114";
NET "PMOD3B<2>"				IOSTANDARD = LVCMOS33;
NET "PMOD3B<3>"				LOC = "P112";
NET "PMOD3B<3>"				IOSTANDARD = LVCMOS33;

NET "PMOD3T<0>"				LOC = "P119";
NET "PMOD3T<0>"				IOSTANDARD = LVCMOS33;
NET "PMOD3T<1>"				LOC = "P117";
NET "PMOD3T<1>"				IOSTANDARD = LVCMOS33;
NET "PMOD3T<2>"				LOC = "P115";
NET "PMOD3T<2>"				IOSTANDARD = LVCMOS33;
NET "PMOD3T<3>"				LOC = "P113";
NET "PMOD3T<3>"				IOSTANDARD = LVCMOS33;


##
## Pmod 4
##
NET "PMOD4B<0>"				LOC = "P103";
NET "PMOD4B<0>"				IOSTANDARD = LVCMOS33;
NET "PMOD4B<1>"				LOC = "P101";
NET "PMOD4B<1>"				IOSTANDARD = LVCMOS33;
NET "PMOD4B<2>"				LOC = "P98";
NET "PMOD4B<2>"				IOSTANDARD = LVCMOS33;
NET "PMOD4B<3>"				LOC = "P96";
NET "PMOD4B<3>"				IOSTANDARD = LVCMOS33;

NET "PMOD4T<0>"				LOC = "P104";
NET "PMOD4T<0>"				IOSTANDARD = LVCMOS33;
NET "PMOD4T<1>"				LOC = "P102";
NET "PMOD4T<1>"				IOSTANDARD = LVCMOS33;
NET "PMOD4T<2>"				LOC = "P100";
NET "PMOD4T<2>"				IOSTANDARD = LVCMOS33;
NET "PMOD4T<3>"				LOC = "P97";
NET "PMOD4T<3>"				IOSTANDARD = LVCMOS33;


#
# GIO header
#
# 40-pin (2x20) 0.1" pin header, with 37 IO lines, labeled GIO1 - GIO37
#
NET "GIO<1>"				LOC = "P92";
NET "GIO<1>"				IOSTANDARD = LVCMOS33;
NET "GIO<2>"				LOC = "P91";
NET "GIO<2>"				IOSTANDARD = LVCMOS33;
NET "GIO<3>"				LOC = "P88";
NET "GIO<3>"				IOSTANDARD = LVCMOS33;
NET "GIO<4>"				LOC = "P87";
NET "GIO<4>"				IOSTANDARD = LVCMOS33;
NET "GIO<5>"				LOC = "P86";
NET "GIO<5>"				IOSTANDARD = LVCMOS33;
NET "GIO<6>"				LOC = "P85";
NET "GIO<6>"				IOSTANDARD = LVCMOS33;
NET "GIO<7>"				LOC = "P83";
NET "GIO<7>"				IOSTANDARD = LVCMOS33;
NET "GIO<8>"				LOC = "P82";
NET "GIO<8>"				IOSTANDARD = LVCMOS33;
NET "GIO<9>"				LOC = "P81";
NET "GIO<9>"				IOSTANDARD = LVCMOS33;
NET "GIO<10>"				LOC = "P80";
NET "GIO<10>"				IOSTANDARD = LVCMOS33;
NET "GIO<11>"				LOC = "P79";
NET "GIO<11>"				IOSTANDARD = LVCMOS33;
NET "GIO<12>"				LOC = "P78";
NET "GIO<12>"				IOSTANDARD = LVCMOS33;
NET "GIO<13>"				LOC = "P77";
NET "GIO<13>"				IOSTANDARD = LVCMOS33;
NET "GIO<14>"				LOC = "P76";
NET "GIO<14>"				IOSTANDARD = LVCMOS33;
NET "GIO<15>"				LOC = "P75";
NET "GIO<15>"				IOSTANDARD = LVCMOS33;
NET "GIO<16>"				LOC = "P74";
NET "GIO<16>"				IOSTANDARD = LVCMOS33;
NET "GIO<17>"				LOC = "P71";
NET "GIO<17>"				IOSTANDARD = LVCMOS33;
NET "GIO<18>"				LOC = "P70";
NET "GIO<18>"				IOSTANDARD = LVCMOS33;
NET "GIO<19>"				LOC = "P52";
NET "GIO<19>"				IOSTANDARD = LVCMOS33;
NET "GIO<20>"				LOC = "P51";
NET "GIO<20>"				IOSTANDARD = LVCMOS33;
NET "GIO<21>"				LOC = "P50";
NET "GIO<21>"				IOSTANDARD = LVCMOS33;
NET "GIO<22>"				LOC = "P49";
NET "GIO<22>"				IOSTANDARD = LVCMOS33;
NET "GIO<23>"				LOC = "P48";
NET "GIO<23>"				IOSTANDARD = LVCMOS33;
NET "GIO<24>"				LOC = "P46";
NET "GIO<24>"				IOSTANDARD = LVCMOS33;
NET "GIO<25>"				LOC = "P45";
NET "GIO<25>"				IOSTANDARD = LVCMOS33;
NET "GIO<26>"				LOC = "P44";
NET "GIO<26>"				IOSTANDARD = LVCMOS33;
NET "GIO<27>"				LOC = "P13";
NET "GIO<27>"				IOSTANDARD = LVCMOS33;
NET "GIO<28>"				LOC = "P14";
NET "GIO<28>"				IOSTANDARD = LVCMOS33;
NET "GIO<29>"				LOC = "P15";
NET "GIO<29>"				IOSTANDARD = LVCMOS33;
NET "GIO<30>"				LOC = "P16";
NET "GIO<30>"				IOSTANDARD = LVCMOS33;
NET "GIO<31>"				LOC = "P17";
NET "GIO<31>"				IOSTANDARD = LVCMOS33;
NET "GIO<32>"				LOC = "P18";
NET "GIO<32>"				IOSTANDARD = LVCMOS33;
NET "GIO<33>"				LOC = "P105";
NET "GIO<33>"				IOSTANDARD = LVCMOS33;
NET "GIO<34>"				LOC = "P106";
NET "GIO<34>"				IOSTANDARD = LVCMOS33;
NET "GIO<35>"				LOC = "P107";
NET "GIO<35>"				IOSTANDARD = LVCMOS33;
NET "GIO<36>"				LOC = "P110";
NET "GIO<36>"				IOSTANDARD = LVCMOS33;
NET "GIO<37>"				LOC = "P111";
NET "GIO<37>"				IOSTANDARD = LVCMOS33;


#
# misc
#

##
## Regulator Reset signal
##
NET "REG_RST"				LOC = "P95";
NET "REG_RST"				IOSTANDARD = LVCMOS33;

##
## Parallel Data Bus from microcontroller - Port "D"
##
NET "USB_DB<0>"				LOC = "P26";
NET "USB_DB<0>"				IOSTANDARD = LVCMOS33;
NET "USB_DB<1>"				LOC = "P25";
NET "USB_DB<1>"				IOSTANDARD = LVCMOS33;
NET "USB_DB<2>"				LOC = "P24";
NET "USB_DB<2>"				IOSTANDARD = LVCMOS33;
NET "USB_DB<3>"				LOC = "P23";
NET "USB_DB<3>"				IOSTANDARD = LVCMOS33;
NET "USB_DB<4>"				LOC = "P22";
NET "USB_DB<4>"				IOSTANDARD = LVCMOS33;
NET "USB_DB<5>"				LOC = "P21";
NET "USB_DB<5>"				IOSTANDARD = LVCMOS33;
NET "USB_DB<6>"				LOC = "P20";
NET "USB_DB<6>"				IOSTANDARD = LVCMOS33;
NET "USB_DB<7>"				LOC = "P19";
NET "USB_DB<7>"				IOSTANDARD = LVCMOS33;

##
## Parallel Data Bus from microcontroller - Port "C"
##
NET "USB_WAIT"				LOC = "P42";
NET "USB_WAIT"				IOSTANDARD = LVCMOS33;
NET "USB_WRITE"				LOC = "P41";
NET "USB_WRITE"				IOSTANDARD = LVCMOS33;
NET "USB_DSTB"				LOC = "P40";
NET "USB_DSTB"				IOSTANDARD = LVCMOS33;
NET "USB_ASTB"				LOC = "P35";
NET "USB_ASTB"				IOSTANDARD = LVCMOS33;


##
## 1-Wire memory signal
## Connected to onboard DS28E01Q-100 EEPROM device
##
NET "ONEWIRE_MEM1"			LOC = "P125";
NET "ONEWIRE_MEM1"			IOSTANDARD = LVCMOS33;




##
## Created by Constraints Editor (xc2c256-tq144-7) - 2017/10/08
##

NET "CLK" TNM_NET = CLK;
TIMESPEC TS_CLK = PERIOD "CLK" 8 MHz HIGH 50%;

NET "ACLK" TNM_NET = ACLK;
TIMESPEC TS_ACLK = PERIOD "ACLK" 25 MHz HIGH 50%;

Please note that this is a WORK IN PROGRESS, and is subject to change as improvements are made.

In time, I will add a README.md to accompany this, listing the various signals, etc.

Additionally, note that I am using an additional, external oscillator (a 25MHz DSC1003AE from Microchip) mounted on a small PCB in an 8-DIP socket at position IC3; this provides the CPLD with the GCLK1 signal on P32, and is labeled as XCCLK on the schematic.