Created
February 29, 2012 22:46
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m68k asm parser w/ scala parser combinators
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import scala.util.parsing.combinator.RegexParsers | |
object InputParser extends RegexParsers { | |
override val skipWhitespace = false | |
val WS = """[ ]+"""r | |
val CONST = """#([0-9]+|[A-Z]+)"""r | |
val const = CONST | |
val DATA_REG = """D[0-9]+"""r | |
val ADDR_REG = """A[0-9]+"""r | |
val register = DATA_REG | ADDR_REG | |
val indir = """\(""".r ~ register ~ """\)""".r | |
val indir_incr = indir ~ """\+""".r | |
val indir_decr = """-""".r ~ indir | |
val DISPL = """[0-9]+"""r | |
val index_displ = DISPL ~ indir | |
val SIZE = """\.[WL]"""r | |
var sized_register = register ~ SIZE | |
val index_base_displ = DISPL ~ """\(""".r ~ register ~ """,""".r ~ WS ~ sized_register ~ """\)""".r | |
val ADDRESS = """[0-9]+"""r | |
val absolute = ADDRESS ~ SIZE | |
val operand = const | register | indir | indir_incr | indir_decr | index_displ | index_base_displ | absolute | |
val DATA_OPCODE = """[A-Z]+"""r | |
val data_op_1 = DATA_OPCODE ~ opt(SIZE) ~ WS ~ operand | |
val data_op_2 = DATA_OPCODE ~ opt(SIZE) ~ WS ~ operand ~ """,""".r ~ WS ~ operand | |
val line = data_op_2 | data_op_1 | |
def parse(in: String) = parseAll(line, in) match { | |
case Success(res, _) => res | |
case f:Failure => throw new Exception(f.toString) | |
} | |
} | |
/*val lines = io.Source.stdin.getLines*/ | |
val lines = List( | |
"ADD #3" | |
, "ADD.W D3" | |
, "MUL D3, D2" | |
, "MUL -(D3)" | |
, "MUL 2(A3, D2.W), 33.W" | |
) | |
for (l <- lines) println(InputParser.parse(l)); | |
def tp(parser: InputParser.Parser[_], s: String) = | |
println(InputParser.parseAll(parser, s)) | |
tp(InputParser.operand, "D3") | |
tp(InputParser.line, "MUL D3, D2") |
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