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one.asm
;******************** (C) COPYRIGHT 2013 STMicroelectronics ********************
;* File Name : startup_stm32f051.s
;* Author : MCD Application Team
;* Version : V1.3.0
;* Date : 23-October-2013
;* Description : STM32F051 devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; @attention
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD RTC_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD TS_IRQHandler ; TS
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3 check
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
DCD 0 ; Reserved
DCD TIM14_IRQHandler ; TIM14
DCD TIM15_IRQHandler ; TIM15
DCD TIM16_IRQHandler ; TIM16
DCD TIM17_IRQHandler ; TIM17
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_IRQHandler ; I2C2
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD CEC_IRQHandler ; CEC
DCD 0 ; Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
TIM3_IRQHandler PROC
LDR R1,= 0x40000400 ;OK
LDR R2,[R1, #0x10] ;OK
LDR R0,= ~0x00000001 ;OK
ANDS R2, R0
STR R2, [R1, #0x10] ;OK
;toggle diod
LDR R1,= 0x48000000
LDR R2,[R1,#0x14]
LDR R0,= 0x00000800 ; 11
EORS R2,R0
STR R2, [R1,#0x14]
;exit from interrupt handler
BX LR
ENDP
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
; add
ENTRY
start_conditions
LDR R0, =2
LDR R1, =2
add_procstart
ADD R0, R1
CMP R0, #4
BEQ add_true
add_false
LDR R5, =0
B add_procend
add_true
LDR R5, =1
add_procend
timer_setup
LDR R1,= 0x40021000 ; OK: enabling of RCC module
LDR R2, [R1,#0x1C] ; OK standard shift
LDR R0,= 0x00000002 ; OK 1 for TIM3
ORRS R2,R0
STR R2, [R1,#0x1C] ; OK
LDR R1,= 0x40000400 ; OK enabling of TIM3 module
LDR R2,= 0x00000500 ; OK reset value
STR R2, [R1,#0x24] ; OK shift from rm
LDR R2,= 0x800 ; NOT SURE
STR R2, [R1,#0x2C] ; OK shift from rm
LDR R2,= 0x80 ; NOT SURE
STR R2, [R1,#0x28] ; OK value from rm
; TIM3_CR1
LDR R2,[R1,#0x00]
LDR R0,= 0x00000001 ; check
ORRS R2,R0
STR R2, [R1,#0x00]
; TIM3_DIER
LDR R2, [R1,#0x0C] ;OK shift
LDR R0,= 0x00000001 ;OK 0
ORRS R2, R0
STR R2, [R1,#0x0C] ;OK shift
; NVIC_ISER
LDR R1,= 0xE000E100 ; default
LDR R2,[R1,#0x00]
LDR R0,= 0x00010000
ORRS R2,R0
STR R2, [R1,#0x00]
ledblink_setup
LDR R1, =0x40021000 ; OK: our address
LDR R2, [R1, #0x14] ; OK: our shift
LDR R0, =0x00020000 ; OK: 17 for IOPA
ORRS R2, R0
STR R2, [R1, #0x14]
LDR R1, =0x48000000 ; OK:
LDR R2, [R1, #0x00]
LDR R0, =0x00400400 ; OK: MODER 5 (10-11) write 01
;
ORRS R2, R0
STR R2, [R1, #0x00]
LDR R2, [R1, #0x14]
LDR R0, =0x00000020 ; OK
ORRS R2, R0
STR R2, [R1, #0x14]
blink_loopstart
LDR R2, [R1, #0x14]
LDR R0, =0x00000020
EORS R2,R0
STR R2, [R1, #0x14]
blink_waitsetup
LDR R3, =100000; ticks
blink_waiting
SUBS R3, #1
CMP R3, #0
BNE blink_waiting
blink_loopend
B blink_loopstart
B .
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT TS_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
EXPORT ADC1_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
TS_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
DMA1_Channel4_5_IRQHandler
ADC1_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
;TIM3_IRQHandler
TIM6_DAC_IRQHandler
TIM14_IRQHandler
TIM15_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
CEC_IRQHandler
B .
ENDP
ALIGN
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
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