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valerionew/VHDL snippets for vscode.md

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Visual Studio Code VHDL snippets used in particular for Digital Electronic Systems Design course of Politecnico di Milano
Raw
VHDL snippets for vscode.md

Install

refer to https://code.visualstudio.com/docs/editor/userdefinedsnippets for installation

on my machine the file goes in %appdata%\Code\User\snippets

Reference

axism: Signals for AXI-Stream Master
axismgen: Generics for AXI-Stream Master
axiss: Signals for AXI-Stream Sink
axissgen: Generics for AXI-Stream Sink
tb: Generic process testbench
pm: Portmap entry
tbaxiss: AXI-Stream Sink process testbench
tbaxism: AXI-Stream Master process testbench
signal: signal declaration
axissp: AXI-Stream Sink process
axismp: AXI-Stream Master process

Raw
vhdl.json
{
"AXI-Stream Master Signals": {
"prefix": "axism",
"body": [
"m_axis_tvalid : out std_logic;",
"m_axis_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);",
"m_axis_tready : instd_logic$0"
],
"description": "Signals for AXI-Stream Master"
},
"AXI-Stream Master Generics": {
"prefix": "axismgen",
"body": [
"C_M_AXIS_TDATA_WIDTH : integer := ${1:<axi-stream bus width>}$0"
],
"description": "Generics for AXI-Stream Master"
},
"AXI-Stream Sink Signals": {
"prefix": "axiss",
"body": [
"s_axis_tready : out std_logic;",
"s_axis_tdata : in std_logic_vector(c_s_axis_tdata_width-1 downto 0);",
"s_axis_tvalid : in std_logic$0",
],
"description": "Signals for AXI-Stream Sink"
},
"AXI-Stream Sink Generics": {
"prefix": "axissgen",
"body": [
"C_S_AXIS_TDATA_WIDTH : integer := ${1:<axi-stream bus width>}$0"
],
"description": "Generics for AXI-Stream Sink"
},
"Testbench": {
"prefix": "tb",
"body": [
"library IEEE;",
" use IEEE.STD_LOGIC_1164.ALL;",
" use IEEE.NUMERIC_STD.ALL;",
"",
"entity ${1:$TM_FILENAME_BASE} is",
" -- Generic ( );",
"end ${1:$TM_FILENAME_BASE};",
"",
"architecture Behavioral of ${1:$TM_FILENAME_BASE} is",
"",
" constant CLK_PERIOD : TIME := ${2:10 ns};",
" constant RESET_TIME : TIME := ${3:4*CLK_PERIOD}; ",
" constant TB_CLK_INIT : STD_LOGIC := ${4|'0','1'|};",
" constant TB_RESET_INIT : STD_LOGIC := ${5|'1','0'|};",
"",
" signal reset : STD_LOGIC := TB_RESET_INIT;",
" signal clk : STD_LOGIC := TB_CLK_INIT;",
"",
"begin",
" -- clock",
" clk <= not clk after CLK_PERIOD/2;",
"",
" -- reset",
" reset_proc: process",
" begin",
" RESET <= TB_RESET_INIT;",
" wait for RESET_TIME;",
" ",
" RESET <= not RESET;",
" wait;",
" end process; ",
" ",
" signal_drive: process",
" begin",
" -- reset",
" ",
" wait for RESET_TIME;",
" ",
" -- data behavour",
" $0",
" wait for CLK_PERIOD;",
"",
" wait;",
" end process; ",
"end Behavioral;",
""
],
"description": "Generic process testbench"
},
"Portmap entry": {
"prefix": "pm",
"body": "$1 => $1,\n$0",
"description": "Portmap entry"
},
"AXI-Stream Sink Testbench": {
"prefix": "tbaxiss",
"body": [
"library IEEE;",
" use IEEE.STD_LOGIC_1164.ALL;",
" use IEEE.NUMERIC_STD.ALL;",
"",
"entity ${1:$TM_FILENAME_BASE} is",
"Generic (",
" C_S_AXIS_TDATA_WIDTH : integer := ${3:8}",
");",
"end ${1:$TM_FILENAME_BASE};",
"",
"architecture Behavioral of ${1:$TM_FILENAME_BASE} is",
"",
" constant CLK_PERIOD : TIME := ${4:10 ns};",
" constant RESET_TIME : TIME := ${5:4*CLK_PERIOD}; ",
" constant TB_CLK_INIT : STD_LOGIC := ${6|'0','1'|};",
" constant TB_RESET_INIT : STD_LOGIC := ${7|'1','0'|};",
"",
" signal reset : STD_LOGIC := TB_RESET_INIT;",
" signal clk : STD_LOGIC := TB_CLK_INIT;",
" -----------AXI-Stream-------------",
" signal s_axis_tready : STD_LOGIC;",
" signal S_AXIS_TDATA : STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);",
" signal S_AXIS_TVALID : STD_LOGIC := '1';",
"",
"Component ${2:dut_filename}",
"Generic (",
" C_S_AXIS_TDATA_WIDTH : integer := ${3:8}",
");",
"Port(",
" clk : IN STD_LOGIC; ",
" reset : IN STD_LOGIC; ",
"",
" s_axis_tready : OUT STD_LOGIC;",
" S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);",
" S_AXIS_TVALID : IN STD_LOGIC",
"",
");",
"end component;",
"begin",
"dut: ${2:dut_filename}",
"Generic Map(",
" C_S_AXIS_TDATA_WIDTH => ${3:8}",
")",
"Port Map(",
" CLK => CLK,",
" RESET => RESET, ",
" s_axis_tready => s_axis_tready,",
" S_AXIS_TDATA => S_AXIS_TDATA,",
" S_AXIS_TVALID => S_AXIS_TVALID",
");",
" -- clock",
" clk <= not clk after CLK_PERIOD/2;",
"",
" -- reset",
" reset_proc: process",
" begin",
" RESET <= TB_RESET_INIT;",
" wait for RESET_TIME;",
" ",
" RESET <= not RESET;",
" wait;",
" end process; ",
" ",
" signal_drive: process",
" begin",
" -- reset",
" S_AXIS_TDATA <= (Others => '0');",
" S_AXIS_TVALID <= '0';",
" wait for RESET_TIME;",
" ",
" -- valid data behavour",
" S_AXIS_TVALID <= '1';",
" S_AXIS_TDATA <= X\"00\";",
" wait for CLK_PERIOD;",
" S_AXIS_TDATA <= X\"07\";",
" wait for CLK_PERIOD;",
" S_AXIS_TDATA <= X\"F0\";",
" wait for CLK_PERIOD;",
" S_AXIS_TDATA <= X\"FF\";",
" wait for CLK_PERIOD;",
" ",
" -- unvalid data behavour",
" S_AXIS_TVALID <= '0';",
" S_AXIS_TDATA <= X\"00\";",
" wait for CLK_PERIOD;",
" S_AXIS_TDATA <= X\"07\";",
" wait for CLK_PERIOD;",
" S_AXIS_TDATA <= X\"F0\";",
" wait for CLK_PERIOD;",
" S_AXIS_TDATA <= X\"FF\";",
" wait for CLK_PERIOD;",
" $0",
" wait;",
" end process; ",
"end Behavioral;",
""
],
"description": "AXI-Stream Sink process testbench"
},
"AXI-Stream Master Testbench": {
"prefix": "tbaxism",
"body": [
"library IEEE;",
" use IEEE.STD_LOGIC_1164.ALL;",
" use IEEE.NUMERIC_STD.ALL;",
"",
"entity ${1:$TM_FILENAME_BASE} is",
"Generic (",
" C_M_AXIS_TDATA_WIDTH : integer := ${3:8}",
");",
"end ${1:$TM_FILENAME_BASE};",
"",
"architecture Behavioral of ${1:$TM_FILENAME_BASE} is",
"",
" constant CLK_PERIOD : TIME := 10 ns;",
" constant RESET_TIME : TIME := 4*CLK_PERIOD; ",
" constant TB_CLK_INIT : STD_LOGIC := '0';",
" constant TB_RESET_INIT : STD_LOGIC := '1';",
"",
" signal reset : STD_LOGIC := TB_RESET_INIT;",
" signal clk : STD_LOGIC := TB_CLK_INIT;",
" -- axi stream master",
" signal M_AXIS_TREADY : STD_LOGIC;",
" signal M_AXIS_TDATA : STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0);",
" signal M_AXIS_TVALID : STD_LOGIC;",
"",
"Component ${2:dut_filename}",
"Generic (",
" C_M_AXIS_TDATA_WIDTH : integer := ${3:8}",
");",
"Port(",
" clk : IN STD_LOGIC; ",
" reset : IN STD_LOGIC; ",
"",
" M_AXIS_TREADY : OUT STD_LOGIC;",
" M_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0);",
" M_AXIS_TVALID : IN STD_LOGIC",
"",
");",
"end component;",
"begin",
"dut: ${2:dut_filename}",
"Generic Map(",
" C_M_AXIS_TDATA_WIDTH => ${3:8}",
")",
"Port Map(",
" CLK => CLK,",
" RESET => RESET, ",
" ",
" M_AXIS_TREADY => M_AXIS_TREADY,",
" M_AXIS_TDATA => M_AXIS_TDATA,",
" M_AXIS_TVALID => M_AXIS_TVALID",
");",
" -- clock",
" clk <= not clk after CLK_PERIOD/2;",
"",
" -- reset",
" reset_proc: process",
" begin",
" RESET <= TB_RESET_INIT;",
" wait for RESET_TIME;",
" ",
" RESET <= not RESET;",
" wait;",
" end process; ",
" ",
" signal_drive: process",
" begin",
" -- reset",
" wait for RESET_TIME;",
"",
" ",
" wait;",
" end process; ",
"end Behavioral;",
],
"description": "AXI-Stream Master process testbench"
},
"Signal": {
"prefix": "signal",
"body": [ "signal $1 : $2 ${3|;,:= ;|}" ],
"description": "signal declaration"
},
"AXI-Stream Slave Process": {
"prefix": "axissp",
"body": [
"library IEEE;",
" use IEEE.STD_LOGIC_1164.ALL;",
" use IEEE.NUMERIC_STD.ALL;",
"",
"entity ${1:$TM_FILENAME_BASE} is",
" generic (",
" C_S_AXIS_TDATA_WIDTH : integer := ${2:8};",
" );",
" port (",
" clk : in std_logic;",
" reset : in std_logic;",
"",
" -- AXI4-Stream Tready",
" s_axis_tready : OUT STD_LOGIC := '0';",
" -- Data in",
" S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);",
" -- Data is in valid",
" S_AXIS_TVALID : in std_logic;",
" );",
"end ${1:$TM_FILENAME_BASE};",
"",
"architecture Behavioral of ${1:$TM_FILENAME_BASE} is",
"",
"begin ",
"",
"process (clk, reset)",
"begin",
"if reset = '1' then",
" s_axis_tready <= '0';",
"",
"elsif rising_edge(clk) then",
" s_axis_tready <= '1';",
"",
" if S_AXIS_TVALID = '1' then",
" -- data is valid",
"",
"",
" end if;",
"",
"end if;",
"end process;",
"end Behavioral;"
],
"description": "AXI-Stream Sink process"
},
"AXI-Stream Master Process": {
"prefix": "axismp",
"body": [
"library IEEE;",
" use IEEE.STD_LOGIC_1164.ALL;",
" use IEEE.NUMERIC_STD.ALL;",
"",
"entity ${1:$TM_FILENAME_BASE} is",
" generic (",
" C_M_AXIS_TDATA_WIDTH : integer := ${2:8}",
" );",
" Port ( ",
" clk : in std_logic;",
" reset : in std_logic;",
"",
" M_AXIS_TVALID : out std_logic;",
" M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0);",
" M_AXIS_TREADY : in std_logic;",
"",
" );",
"end ${1:$TM_FILENAME_BASE};",
"",
"architecture Behavioral of ${1:$TM_FILENAME_BASE} is",
"",
"-- needed to keep track of data already",
"signal M_AXIS_TVALID_int : std_logic := '0';",
"",
"",
"begin",
" ",
"-- needed to keep track of data already in the bus",
"M_AXIS_TVALID <= M_AXIS_TVALID_int;",
"",
"process (clk, reset)",
"begin",
" if reset = '1' then",
" M_AXIS_TVALID_int <= '0';",
" elsif rising_edge(clk) then ",
"",
" if M_AXIS_TREADY = '1' then",
" M_AXIS_TVALID_int <= '0';",
" end if;",
"",
" if (M_AXIS_TVALID_int = '0' OR M_AXIS_TREADY = '1') then",
" -- bus is free",
" -- M_AXIS_TDATA <= $0",
" M_AXIS_TVALID_int <= '1';",
" ",
" end if;",
" end if;",
"end process;",
"",
"",
"end Behavioral;",
],
"description": "AXI-Stream Master process"
}
}
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