microwatt-sim

microwatt-sim

#microwatt simulation using ghdl

prereq - install ghdl
       - Download powerpc cross compiler and add its bin directory to the path env variable

mkdir /opt/microwatt-sim
cd /opt/microwatt-sim
git clone https://github.com/antonblanchard/microwatt.git
cd microwatt
make
cd hello_world
make
cd ..
cp hello_world/hello_world.bin main_ram.bin 
./core_tb > /tmp/tb.log
stty sane



#microwatt implementation uisng fusesoc

prereq - install vivado
       - Download powerpc cross compiler and add its bin directory to the path env variable
pip3 install --user -U fusesoc
fusesoc init

mkdir /opt/microwatt-sim/microwatt-fusesoc
cd /opt/microwatt-sim/microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
source /opt/Xilinx/Vivado/2021.1/settings64.sh

fusesoc run --target=nexys_a7 microwatt --memory_size=16384 --ram_init_file=../microwatt/hello_world/hello_world.hex
fusesoc run --target=arty_a7-35 microwatt --memory_size=16384 --ram_init_file=../microwatt/hello_world/hello_world.hex




#libresoc toolchain setup

cd /opt
git clone https://github.com/varunmadhavam/libresoc-dev-env-setup.git
cd libresoc-dev-env-setup
sudo ./mk-deb-chroot libresocecp5
schroot -c libresocecp5
sudo chmod 777 /opt
mkdir /opt/libresoc
cd /opt/libresoc
git clone https://github.com/varunmadhavam/libresoc-dev-env-setup.git
sudo bash libresoc-dev-env-setup/install-hdl-apt-reqs
sudo bash libresoc-dev-env-setup/hdl-dev-repos
sudo bash libresoc-dev-env-setup/hdl-tools-yosys
sudo bash libresoc-dev-env-setup/nextpnr-ecp5-install
sudo bash libresoc-dev-env-setup/hdl-litex-repos

edit litex/build/io.py to change line return InferedSDRIO(dr.i, dr.o, dr.clk, dr.clk_domain) to  return InferedSDRIO(dr.i, dr.o, dr.clk)#, dr.clk_domain) in method "def lower(dr):" around line 67

wget https://toolchains.bootlin.com/downloads/releases/toolchains/powerpc64le-power8/tarballs/powerpc64le-power8--glibc--stable-2020.08-1.tar.bz2
tar -xvf powerpc64le-power8--glibc--stable-2020.08-1.tar.bz2
export PATH=$PATH:/opt/libresoc/powerpc64le-power8--glibc--stable-2020.08-1/bin

git clone https://git.libre-soc.org/git/libresoc-litex.git
cd libresoc-litex
cd libresoc
python3 /opt/libresoc/soc/src/soc/simple/issuer_verilog.py --debug=jtag --enable-core --disable-pll --enable-xics --disable-svp64 libresoc.v
cd ..
export PATH=$PATH:/usr/local/libtrellis/bin
python3 versa_ecp5.py --sys-clk-freq=55e6 --build