error.txt

(xc7) (libreSOC)varun@varuns5600x:/opt/src/litex/libresoc-litex$ ./fpga.py --sys-clk-freq=100e6 --fpga=artya735t --build
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2021-10-06 13:47:04)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc7a35ticsg324-1L.
INFO:SoC:System clock: 100.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0xc0000000, Size: 0x10000000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:cpu_bus0 Bus converted from Wishbone 64-bit to Wishbone 32-bit.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 Bus converted from Wishbone 64-bit to Wishbone 32-bit.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCBusHandler:cpu_bus2 added as Bus Master.
INFO:SoCCSRHandler:cpu CSR allocated at Location 1.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00010000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00010000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 2.
INFO:SoCCSRHandler:uart_phy CSR allocated at Location 3.
INFO:SoCCSRHandler:uart CSR allocated at Location 4.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 5.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:S7PLL:Creating S7PLL, speedgrade -1.
INFO:S7PLL:Registering Single Ended ClkIn of 100.00MHz.
INFO:S7PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut1 sys4x of 400.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut2 sys4x_dqs of 400.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut3 idelay of 200.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut4 eth of 25.00MHz (+-10000.00ppm).
INFO:SoCCSRHandler:ddrphy CSR allocated at Location 6.
INFO:SoCCSRHandler:sdram CSR allocated at Location 7.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoCCSRHandler:leds CSR allocated at Location 8.
INFO:S7PLL:Config:
divclk_divide : 1
clkout0_freq  : 100.00MHz
clkout0_divide: 16
clkout0_phase : 0.00°
clkout1_freq  : 400.00MHz
clkout1_divide: 4
clkout1_phase : 0.00°
clkout2_freq  : 400.00MHz
clkout2_divide: 4
clkout2_phase : 90.00°
clkout3_freq  : 200.00MHz
clkout3_divide: 8
clkout3_phase : 0.00°
clkout4_freq  : 25.00MHz
clkout4_divide: 64
clkout4_phase : 0.00°
vco           : 1600.00MHz
clkfbout_mult : 16
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0xc0000000, Size: 0x10000000, Mode: RW, Cached: False Linker: False
Bus Regions: (3)
rom                 : Origin: 0x00000000, Size: 0x00010000, Mode: R, Cached: True Linker: False
sram                : Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
main_ram            : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
Bus Masters: (3)
- cpu_bus0
- cpu_bus1
- cpu_bus2
Bus Slaves: (3)
- rom
- sram
- main_ram
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (9)
- ctrl           : 0
- cpu            : 1
- identifier_mem : 2
- uart_phy       : 3
- uart           : 4
- timer0         : 5
- ddrphy         : 6
- sdram          : 7
- leds           : 8
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart   : 0
- timer0 : 1
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:csr Region added at Origin: 0xc0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (3 <-> 4).
make: Entering directory '/opt/src/litex/libresoc-litex/build/arty/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/opt/src/litex/libresoc-litex/build/arty/software/libcompiler_rt'
make: Entering directory '/opt/src/litex/libresoc-litex/build/arty/software/libbase'
 CC       exception.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       spiflash.o
 CC       i2c.o
 CC       memtest.o
 AR       libbase.a
 AR       libbase-nofloat.a
make: Leaving directory '/opt/src/litex/libresoc-litex/build/arty/software/libbase'
make: Entering directory '/opt/src/litex/libresoc-litex/build/arty/software/liblitedram'
 CC       sdram.o
 AR       liblitedram.a
make: Leaving directory '/opt/src/litex/libresoc-litex/build/arty/software/liblitedram'
make: Entering directory '/opt/src/litex/libresoc-litex/build/arty/software/libliteeth'
 CC       udp.o
 CC       mdio.o
 AR       libliteeth.a
make: Leaving directory '/opt/src/litex/libresoc-litex/build/arty/software/libliteeth'
make: Entering directory '/opt/src/litex/libresoc-litex/build/arty/software/liblitespi'
 CC       spiflash.o
 AR       liblitespi.a
make: Leaving directory '/opt/src/litex/libresoc-litex/build/arty/software/liblitespi'
make: Entering directory '/opt/src/litex/libresoc-litex/build/arty/software/liblitesdcard'
 CC       sdcard.o
 CC       spisdcard.o
 AR       liblitesdcard.a
make: Leaving directory '/opt/src/litex/libresoc-litex/build/arty/software/liblitesdcard'
make: Entering directory '/opt/src/litex/libresoc-litex/build/arty/software/bios'
 CC       isr.o
 CC       boot.o
/opt/src/litex/litex/litex/litex/soc/software/bios/boot.c: In function ‘serialboot’:
/opt/src/litex/litex/litex/litex/soc/software/bios/boot.c:218:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  218 |     writepointer = (char *) get_uint32(&frame.payload[0]);
      |                    ^
 CC       cmd_bios.o
/opt/src/litex/litex/litex/litex/soc/software/bios/cmds/cmd_bios.c: In function ‘crc’:
/opt/src/litex/litex/litex/litex/soc/software/bios/cmds/cmd_bios.c:124:30: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  124 |  printf("CRC32: %08x", crc32((unsigned char *)addr, length));
      |                              ^
 CC       cmd_mem.o
 CC       cmd_boot.o
 CC       cmd_i2c.o
 CC       cmd_spiflash.o
 CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       main.o
 LD       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /opt/src/litex/libresoc-litex/build/arty/software/bios/../include/generated/regions.ld powerpc64le-linux

ROM usage: 34.13KiB     (53.33%)
RAM usage: 1.67KiB      (20.90%)

make: Leaving directory '/opt/src/litex/libresoc-litex/build/arty/software/bios'
symbiflow_synth -t arty -v /opt/src/litex/libresoc-litex/libresoc/libresoc.v /opt/src/litex/libresoc-litex/libresoc/pll.v /opt/src/litex/libresoc-litex/libresoc/SPBlock_512W64B8W.v /opt/src/litex/libresoc-litex/build/arty/gateware/arty.v -d artix7 -p xc7a35tcsg324-1 -x arty.xdc > /dev/null
ERROR: Conflicting init values for signal 1'0 (\test_issuer.ti.jtag.dmi0_datasr_update_core = 1'0 != 1'x).
make: *** [Makefile:36: arty.eblif] Error 1
Traceback (most recent call last):
  File "./fpga.py", line 171, in <module>
    main()
  File "./fpga.py", line 163, in main
    builder.build(run=args.build)
  File "/opt/src/litex/litex/litex/litex/soc/integration/builder.py", line 211, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/opt/src/litex/litex/litex/litex/soc/integration/soc.py", line 1045, in build
    return self.platform.build(self, *args, **kwargs)
  File "/opt/src/litex/litex/litex/litex/build/xilinx/platform.py", line 50, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/opt/src/litex/litex/litex/litex/build/xilinx/symbiflow.py", line 252, in build
    _run_make()
  File "/opt/src/litex/litex/litex/litex/build/xilinx/symbiflow.py", line 95, in _run_make
    raise OSError("Subprocess failed")
OSError: Subprocess failed
(xc7) (libreSOC)varun@varuns5600x:/opt/src/litex/libresoc-litex$