fpgatest.v

module fpgatest(
    input                           OSC_50_B7A,  // 50 MHz clock

    output             [3:0]        LED,
    output             [3:0]        LED_BRACKET,
    output                          LED_RJ45_L,
    output                          LED_RJ45_R
);

assign clk_main = OSC_50_B7A;

// Offsets for desired frequencies
parameter c_CNT_2HZ = 25000000;    // period = 1/2 seconds
parameter c_CNT_3HZ = 16666667;    // period = 1/3 seconds

// Counter
reg [31:0] r_CNT_2HZ = 0;
reg [31:0] r_CNT_3HZ = 0;

reg led_2HZ_on;
reg led_3HZ_on;

always @ (posedge clk_main)
    begin
        if (r_CNT_2HZ == c_CNT_2HZ - 1)    // -1, since counter starts at 0
            begin
                led_2HZ_on         <= !led_2HZ_on;
                r_CNT_2HZ        <= 0;
            end
        else
            r_CNT_2HZ <= r_CNT_2HZ + 1;
    end
    
    
always @ (posedge clk_main)
    begin
        if (r_CNT_3HZ == c_CNT_3HZ - 1)
            begin
                led_3HZ_on         <= !led_3HZ_on;
                r_CNT_3HZ        <= 0;
            end
        else
            r_CNT_3HZ <= r_CNT_3HZ + 1;
    end

    
assign LED_RJ45_L = led_2HZ_on;
assign LED_RJ45_R = led_3HZ_on;

assign LED[0] = led_2HZ_on;
assign LED[1] = led_2HZ_on;
assign LED[2] = led_3HZ_on;
assign LED[3] = led_3HZ_on;

assign LED_BRACKET[0] = led_2HZ_on;
assign LED_BRACKET[1] = led_2HZ_on;
assign LED_BRACKET[2] = led_3HZ_on;
assign LED_BRACKET[3] = led_3HZ_on;

endmodule