Created
April 21, 2016 16:53
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ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation can not advance in time because signals can not resolve to a stable value Line 229.
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begin | |
-- Instantiations -- | |
AL : ALU port map (out_di_ex_b, out_di_ex_c ,out_di_ex_op(2 downto 0), out_alu, out_N, out_O, out_Z, out_C); | |
-- DATA <= out_mem_re_b; W <= 1; -- AFC on écrit (W <= 1) - ADD_W <= out_mem_re_a; | |
BR : Banc_registres port map (out_li_di_b(addr_size_BR-1 downto 0), out_li_di_c(addr_size_BR-1 downto 0) , | |
out_mem_re_a(addr_size_BR-1 downto 0), w,out_mem_re_b, RST, CK, out_QA,out_QB); | |
-- TODO : check | |
w <= '0' when out_mem_re_op = OP_STORE else '1'; | |
-- R : 1(LOAD) - W : 0 (STORE) | |
rw <= '0' when out_mem_re_op = OP_STORE else '1'; | |
MD : Mem_donnee port map ( in_addr_md, out_ex_mem_b , rw, RST, CK, out_DoutD); | |
MI : Mem_inst port map (out_CP, CK, out_MI); | |
CP : compteur port map (CK , RST , '1' , in_cpt_load ,alea , in_cpt_in, out_CP); | |
-- Multiplexors-- | |
-- MUX JM -- | |
-- MUX JMP si x"09" JMZ si x"0A" | |
with out_li_di_op & out_Z select in_cpt_load <= | |
'1' when OP_JMP &'1' | OP_JMP&'0' , | |
'1' when OP_JMF &'1', | |
'0' when others; | |
in_cpt_in <= out_li_di_a when out_li_di_op = OP_JMP else (others=>'0'); -- TODO : JMP 0x1 (JMP @R1) - JMZ 0x1 (JMZ @R1) | |
-- MUX_BR -- defini si on veut B ou val @B | |
in_di_ex_b <= out_QA when out_li_di_op = OP_COP or (out_li_di_op >= OP_ADD and out_li_di_op <= OP_DIV) else out_li_di_b; | |
-- MUX_UAL -- ADD x01 SUB x02 .. DIV x04 | |
in_ex_mem_b <= out_alu when out_di_ex_op >= OP_ADD and out_di_ex_op <= OP_DIV else out_di_ex_b; | |
-- MUX_MD -- A si OP = STORE B si OP = LOAD | |
in_addr_md <= out_ex_mem_a when out_ex_mem_op = OP_STORE else out_ex_mem_b; | |
in_mem_re_b <= out_DoutD when out_ex_mem_op = OP_LOAD or out_ex_mem_op = OP_STORE else out_ex_mem_b; | |
-- Unité de détection des aléas | |
alea <= '1' when ((in_di_ex_op = OP_AFC or in_di_ex_op = OP_COP) and in_li_di_op = OP_COP and in_di_ex_a = in_li_di_b) | |
-- or (in_di_ex_op >= OP_ADD and in_di_ex_op <= OP_DIV and in_li_di_op >= OP_ADD and in_li_di_op <= OP_DIV and (in_di_ex_a = in_li_di_b or in_di_ex_b = in_li_di_c)) | |
else '0'; | |
-- Pipelines -- | |
in_li_di_c <= out_MI(size_op-1 downto 0); | |
in_li_di_b <= out_MI(2*size_op-1 downto size_op); | |
in_li_di_a <= out_MI(3*size_op-1 downto 2*size_op); | |
in_li_di_op <= out_MI(4*size_op-1 downto 3*size_op) when alea = '0' else OP_NOP; | |
in_di_ex_op <= out_li_di_op; | |
in_di_ex_a <= out_li_di_a; | |
PLI2DI : pipeline port map(in_li_di_op,in_li_di_a,in_li_di_b,in_li_di_c, out_li_di_op,out_li_di_a, out_li_di_b, out_li_di_c, CK ); | |
PDI2EX : pipeline port map(in_di_ex_op, in_di_ex_a, in_di_ex_b, out_QB ,out_di_ex_op,out_di_ex_a,out_di_ex_b,out_di_ex_c, CK ); | |
PEX2MEM : pipeline port map(out_di_ex_op,out_di_ex_a,in_ex_mem_b,(others=>'0'),out_ex_mem_op,out_ex_mem_a,out_ex_mem_b,open, CK ); | |
PMEM2RE : pipeline port map(out_ex_mem_op,out_ex_mem_a,in_mem_re_b,(others=>'0'),out_mem_re_op,out_mem_re_a,out_mem_re_b,open, CK ); | |
end Behavioral; |
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