Skip to content

Instantly share code, notes, and snippets.

@vijfhoek
Last active April 16, 2021 05:55
Show Gist options
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save vijfhoek/6d8f059c6115335c95cafc36f5d0dadd to your computer and use it in GitHub Desktop.
Save vijfhoek/6d8f059c6115335c95cafc36f5d0dadd to your computer and use it in GitHub Desktop.
TIMx->PSC = 47;
TIMx->ARR = 8;
TIMx->CCR1 = 4;
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE;
TIMx->CCER |= TIM_CCER_CC1E;
TIMx->BDTR |= TIM_BDTR_MOE;
TIMx->CR1 |= TIM_CR1_CEN;
TIMx->EGR |= TIM_EGR_UG;
// RCC initialisation
let mut rcc = device
.RCC
.configure()
.usbsrc(USBClockSource::HSI48)
.hsi48()
.enable_crs(device.CRS)
.sysclk(48.mhz())
.pclk(24.mhz())
.freeze(&mut device.FLASH);
// GPIO initialisation
let gpioa = device.GPIOA.split(&mut rcc);
let pwm3 = interrupt::free(|cs| {
gpioa.pa8.into_push_pull_output(cs).into_alternate_af2(cs)
});
// Setup PWM timers
let tim1 = device.TIM1;
// Configure pre-scaler for 48 MHz / (47 + 1) = 1 MHz
tim1.psc.write(|w| w.psc().bits(47));
// Configure auto-reload register for (39 + 1) / 1 MHz = 25 kHz
tim1.arr.write(|w| w.arr().bits(39));
// Set half duty cycle (half of ARR)
tim1.ccr1.write(|w| w.ccr().bits(20));
tim1.ccmr1_output()
.write(|w| w.oc1pe().set_bit().oc1m().pwm_mode1());
tim1.ccer.write(|w| w.cc1e().set_bit());
tim1.bdtr.write(|w| w.moe().set_bit());
tim1.cr1.write(|w| w.cen().set_bit());
tim1.egr.write(|w| w.ug().set_bit());
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment