16x4 RAM VHDL XILINX

ram_tb.vhd

-- test bench solution to ex09

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;

entity Ram_TB is
end entity Ram_TB;

architecture Bench of Ram_TB is

  signal Address :Std_logic_vector(3 downto 0);
  signal DataIn, DataOut :Std_logic_vector(3 downto 0);
  signal WE : Std_logic;
  signal clock : Std_logic;
  signal StopClock : boolean := FALSE;

begin

  UUT: entity work.sync_ram(RTL)
  port map (
    clock   => clock,
    we      => WE,
    address => Address,
    datain  => DataIn,
    DataOut => DataOut
  );

  ClockGen: process is
  begin
    while not StopClock loop
      clock <= '0';
      wait for 5 ns;
      clock <= '1';
      wait for 5 ns;
    end loop;
    wait;
  end process ClockGen;

  Stim: process is

  begin

    wait until rising_edge(clock); -- cycle 1
    datain <=    "0000";
    address <= "0001";
    we <= '0';

    wait until rising_edge(clock); -- cycle 2
    we <= '1';
    datain <= "0100";

    wait until rising_edge(clock); -- cycle 3
    datain <=    "0111";
    address <= "0010";

    wait until rising_edge(clock); -- cycle 4
    we <= '0';

    wait until rising_edge(clock); -- cycle 5
    address <= "0001";

    wait until rising_edge(clock); -- cycle 6
    address <= "0010";

    wait until rising_edge(clock); -- cycle 7
    wait until rising_edge(clock); -- cycle 8

    StopClock <= true;
    wait;
  end process;

end architecture Bench;

architecture Bench2 of Ram_TB is

  signal Address :Std_logic_vector(3 downto 0);
  signal DataIn, DataOut :Std_logic_vector(3 downto 0);
  signal WE : Std_logic;
  signal clock : Std_logic;
  signal StopClock : boolean := FALSE;

  signal ok: boolean := true;

begin

  UUT: entity work.sync_ram(RTL)
  port map (
    clock   => clock,
    we      => WE,
    address => Address,
    datain  => DataIn,
    DataOut => DataOut
  );

  ClockGen: process is
  begin
    while not StopClock loop
      clock <= '0';
      wait for 5 ns;
      clock <= '1';
      wait for 5 ns;
    end loop;
    wait;
  end process ClockGen;

  Stim: process is

  begin

    -- Initialise input signals
    address <= "0000";
    datain  <=   "0000";
    we <= '0';
    wait until rising_edge(clock);

    -- write to all addresses
    while address /= "1111" loop
      we <= '1';
      wait until rising_edge(clock);
      address <= std_logic_vector(unsigned(address) + 1);
      datain  <= std_logic_vector(unsigned(datain) + 1);
    end loop;

    -- stop writing
    address <= "0000";
    datain  <=   "0000";
    we <= '0';
    wait until rising_edge(clock);

    -- read from all addresses
    while address /= "1111" loop
      address <= std_logic_vector(unsigned(address) + 1);
      wait until rising_edge(clock);
      -- ok should permanently go false on the first error
      ok <= ok and dataout = std_logic_vector(unsigned(address(3 downto 0)) - 1);
    end loop;

    StopClock <= true;
    wait;
  end process;

end architecture Bench2;

ramchip.vhd

-- Simple generic RAM Model
--
-- +-----------------------------+
-- |    Copyright 2008 DOULOS    |
-- |   designer :  JK            |
-- +-----------------------------+

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;

entity sync_ram is
  port (
    clock   : in  std_logic;
    we      : in  std_logic;
    address : in  std_logic_vector (3 downto 0);
    datain  : in  std_logic_vector (3 downto 0);
    dataout : out std_logic_vector (3 downto 0)
  );
end entity sync_ram;

architecture RTL of sync_ram is

   type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
   signal ram : ram_type;
   signal read_address : std_logic_vector(address'range);

begin

  RamProc: process(clock) is

  begin
    if rising_edge(clock) then
      if we = '1' then
        ram(to_integer(unsigned(address))) <= datain;
      end if;
      read_address <= address;
    end if;
  end process RamProc;

  dataout <= ram(to_integer(unsigned(read_address)));

end architecture RTL;