Verilog: EDA Playground to VS Code

.bashrc

# Shorthand for compiling and running Verilog code
function verilog() {
    # Default, like in EDA playground
    local FILENAMES="'design.sv' 'testbench.sv'"

    # If any arguments were provided at all, use those as filenames instead
    if [ $# -ne 0 ]; then
        FILENAMES=""
        # This automatically loops over all items in $@
        for i; do
            FILENAMES="${FILENAMES}${i@Q} "
        done
        # Remove trailing whitespace, I don't know why this works
        # https://stackoverflow.com/a/3352015/14226122
        FILENAMES="${FILENAMES%"${FILENAMES##*[![:space:]]}"}"
    fi

    # Using same compiler options as in EDA playground
    local COMMAND="iverilog -Wall -g2012 ${FILENAMES} && vvp a.out"

    # Dimmed echo to display to caller what was really run under the hood
    echo -e "\x1b[2mverilog: ${COMMAND}\x1b[22m"

    # Evaluate the command and echo success/failure just for convenience
    if eval " ${COMMAND}"; then
        echo "$(tput setaf 2)Exited without error$(tput sgr0)"
        return 0
    else
        echo "$(tput setaf 1)Exited with error$(tput sgr0)"
        return 1
    fi
}

instructions.md

This is a little thing I did for my UCLA W23 COM SCI M152A: Introductory Digital Design Laboratory course when we first started learning Verilog:

Hey y'all, for those who want to be able to play around with Verilog code in a more familiar editor, here's what I did:

1. Install the Icarus Verilog compiler (the one we used on EDA playground) on your local machine.

   1. For Windows, I found one at https://bleyer.org/icarus/. Remember to choose "Add to user PATH" in the installation wizard, or you'll have to do it manually later.

   2. For Mac users, you can install it with Homebrew (https://formulae.brew.sh/formula/icarus-verilog):

   brew install icarus-verilog
   

   (Disclaimer: I don't actually have a Mac and only tested it on my WSL copy of Homebrew)

2. Open up VS Code in whatever folder you want to play around in. Create testbench.sv and design.sv, just like in the playground.

3. Write your code.

4. Compile the code at the command line with the syntax very similar to GCC: iverilog [FLAGS] FILENAMES... [-o BINARY_NAME]:

iverilog -Wall -g2012 design.sv testbench.sv -o a.out

5. Run the compiled executable with:

vvp a.out

6. If you're familiar with them, you can use scripts or Makefiles to automate the compilation. I also wrote a helper function you can paste straight into your ~/.bashrc so all you have to do is enter verilog at the command line and it'll be like you hit the blue play button in the playground. You can also override the default filenames with your own. Here's how you use it:

$ code ~/.bashrc  # or whatever editor you use
$ # ...paste my function...
$ source ~/.bashrc  # refresh your shell
$ verilog
verilog: iverilog -Wall -g2012 'design.sv' 'testbench.sv' && vvp a.out
1
Exited without error

Example with one of your custom files instead:

$ verilog testbench.sv "my custom adder.sv"
verilog: iverilog -Wall -g2012 'testbench.sv' 'my custom adder.sv' && vvp a.out
1
Exited without error