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PIC16F18313 SSD1306 OLED test program xc8 source
// CONFIG1
#pragma config FEXTOSC = OFF // FEXTOSC External Oscillator mode Selection bits (Oscillator not enabled)
#pragma config RSTOSC = HFINT32 // Power-up default value for COSC bits (HFINTOSC with 2x PLL (32MHz))
#pragma config CLKOUTEN = OFF // Clock Out Enable bit (CLKOUT function is disabled; I/O or oscillator function on OSC2)
#pragma config CSWEN = ON // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
#pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor is enabled)
// CONFIG2
#pragma config MCLRE = ON // Master Clear Enable bit (MCLR/VPP pin function is MCLR; Weak pull-up enabled )
#pragma config PWRTE = OFF // Power-up Timer Enable bit (PWRT disabled)
#pragma config WDTE = OFF // Watchdog Timer Enable bits (WDT disabled; SWDTEN is ignored)
#pragma config LPBOREN = OFF // Low-power BOR enable bit (ULPBOR disabled)
#pragma config BOREN = ON // Brown-out Reset Enable bits (Brown-out Reset enabled, SBOREN bit ignored)
#pragma config BORV = LOW // Brown-out Reset Voltage selection bit (Brown-out voltage (Vbor) set to 2.45V)
#pragma config PPS1WAY = ON // PPSLOCK bit One-Way Set Enable bit (The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle)
#pragma config STVREN = ON // Stack Overflow/Underflow Reset Enable bit (Stack Overflow or Underflow will cause a Reset)
#pragma config DEBUG = OFF // Debugger enable bit (Background debugger disabled)
// CONFIG3
#pragma config WRT = OFF // User NVM self-write protection bits (Write protection off)
#pragma config LVP = ON // Low Voltage Programming Enable bit (Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.)
// CONFIG4
#pragma config CP = OFF // User NVM Program Memory Code Protection bit (User NVM code protection disabled)
#pragma config CPD = OFF // Data NVM Memory Code Protection bit (Data NVM code protection disabled)
#include <xc.h>
#define _XTAL_FREQ 32000000UL
#define _I2C_FREQ 100000UL
#define OLED_ADRS 0x78
void i2c_init(void){
ANSA0 = 0; // Desable analog
TRISA0 = 1; // RA0 input
WPUA0 = 1; // Week pullup
RA0PPS = 0x19; // RA0->DAT1 out
SSP1DATPPS = 0; // DAT1 in->RA0
ANSA1 = 0; // Desable analog
TRISA1 = 1; // RA1 input
WPUA1 = 1; // Week pullup
RA1PPS = 0x18; // RA1->CLK1 out
SSP1CLKPPS = 1; // CLK1 in->RA1
SSP1STAT = 0x00; // Clear status
SSP1CON1 = 0x08; // I2C Master mode
SSP1CON2 = 0x00; // Default I2C mode
SSP1ADD = _XTAL_FREQ / (4 * _I2C_FREQ) - 1; // Clock setting
SSPEN = 1; // I2C enable
}
void i2c_start(void){
SEN = 1; // Start condition
while(SEN); // Wait for start
}
void i2c_stop(void){
PEN = 1; // Stop condition
while(PEN); // Wait for Stop
}
void i2c_write(unsigned char d){
SSP1IF = 0; // Clear flag
SSP1BUF = d; // Write
while(!SSP1IF); // Wait for write done
}
void oled_init(){
i2c_start();
i2c_write(OLED_ADRS); // OLED slave address
i2c_write(0x00); // Control byte Co=0, D/C=0
i2c_write(0x8d); // Set charge pump
i2c_write(0x14); // Enable charge pump
i2c_write(0xaf); // Display ON
i2c_stop();
}
void oled_pattern(void){
unsigned int i;
i2c_start();
i2c_write(OLED_ADRS); // OLED slave address
i2c_write(0x00); // Control byte Co=0, D/C=0
i2c_write(0x20); // Set memory addressing mode
i2c_write(0x00); // Horizontal addressing mode
i2c_write(0x21); // Set column address
i2c_write(0x00); // Column start address
i2c_write(0x7f); // Column end address
i2c_write(0x22); // Set page address
i2c_write(0x00); // Page start address 0
i2c_write(0x07); // Page end address 7
i2c_stop();
i2c_start();
i2c_write(OLED_ADRS); // OLED slave address
i2c_write(0x40); // Control byte Co=0, D/C=1
for(i=0; i<512; i++){ // 128 x 8
i2c_write(0x55); // fill pattern
i2c_write(0xAA); // fill pattern
}
i2c_stop();
}
void main(void) {
WPUA = 1; // Week pullups enable
i2c_init(); // I2C initialize
oled_init(); // OLED initialize
oled_pattern(); // Fill pattern
while(1);
}
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