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@virtualirfan
virtualirfan / LcHoc.scala
Created March 17, 2018 01:11 — forked from bfleischhacker/LcHoc.scala
Using a JS Higher-Order-Component (https://github.com/viktorbergehall/lcHOC) with scala-react-interface (sri)
import sri.core.{ComponentConstructor, ReactClass}
import scala.scalajs.js
import scala.scalajs.js.ConstructorTag
object LcHoc {
def apply[T <: ReactClass {type PropsType; type StateType}](params: js.UndefOr[LcHocParams] = js.undefined)
(implicit tag: ConstructorTag[T]): ComponentConstructor {
type ComponentType = T
type PropsType = T#PropsType
@virtualirfan
virtualirfan / latency.txt
Created January 17, 2018 06:43 — forked from eshelman/latency.txt
HPC-oriented Latency Numbers Every Programmer Should Know
Latency Comparison Numbers
--------------------------
L1 cache reference/hit 1.5 ns 4 cycles
Floating-point add/mult/FMA operation 1.5 ns 4 cycles
L2 cache reference/hit 5 ns 12 ~ 17 cycles
Branch mispredict 6 ns 15 ~ 20 cycles
L3 cache hit (unshared cache line) 16 ns 42 cycles
L3 cache hit (shared line in another core) 25 ns 65 cycles
Mutex lock/unlock 25 ns
L3 cache hit (modified in another core) 29 ns 75 cycles
@virtualirfan
virtualirfan / brew-instructions.sh
Created December 4, 2016 06:41 — forked from petemcw/brew-instructions.sh
Setup dnsmasq on Mac OS X
# Install `dnsmasq` and configure for *.dev domains
$ brew install dnsmasq
$ vim /usr/local/etc/dnsmasq.conf
# Reload configuration and clear cache
$ sudo launchctl unload /Library/LaunchDaemons/homebrew.mxcl.dnsmasq.plist
$ sudo launchctl load /Library/LaunchDaemons/homebrew.mxcl.dnsmasq.plist
$ dscacheutil -flushcache
@virtualirfan
virtualirfan / tmux-cheatsheet.markdown
Created November 13, 2016 09:25 — forked from MohamedAlaa/tmux-cheatsheet.markdown
tmux shortcuts & cheatsheet

tmux shortcuts & cheatsheet

start new:

tmux

start new with session name:

tmux new -s myname
@virtualirfan
virtualirfan / latency.txt
Created August 4, 2012 22:07 — forked from h2oai/latency.txt
Latency numbers every programmer should know
L1 cache reference 0.5 ns
Branch mispredict 5 ns
L2 cache reference 7 ns 14x L1 cache
Mutex lock/unlock 25 ns
Main memory reference 100 ns 20x L2 cache, 200x L1 cache
Compress 1K bytes with Zippy 3,000 ns
Send 1K bytes over 1 Gbps network 10,000 ns 0.01 ms
Read 4K randomly from SSD 150,000 ns 0.15 ms
Read 1 MB sequentially from memory 250,000 ns 0.25 ms
Round trip within same datacenter 500,000 ns 0.5 ms