vishbin

# Set CLICOLOR if you want Ansi Colors in iTerm2 
export CLICOLOR=1
export LSCOLORS=GxFxCxDxBxegedabagaced


#------------------------------------------////
# Prompt:
#------------------------------------------////
#PS1='\[\033[01;32m\]\u\[\033[01;34m\]@\[\033[01;31m\]\h\[\033[00;34m\](\[\033[01;34m\]\w\[\033[00;34m\])\[\033[01;32m\]:\[\033[00m\]'

vishbin

function query() {
  var 
    // HN is done with very unsemantic classes.
    job_list = Array.prototype.slice.call(document.querySelectorAll('.c5a,.cae,.c00,.c9c,.cdd,.c73,.c88')),
    query_list = Array.prototype.slice.call(arguments),
    shown = 0, total = job_list.length;
    
  // Traverses up the dom stack trying to find a match of a specific class
  function up_to(node, klass) {
    if (node.classList.contains(klass)) {

vishbin

Effective Engineer - Notes

• By Edmond Lau
• Highly Recommended 👍
• http://www.theeffectiveengineer.com/

What's an Effective Engineer?

• They are the people who get things done. Effective Engineers produce results.

Adopt the Right Mindsets

vishbin

{
        "bridge": {
                "name": "Homebridge",
                "username": "00:0C:43:43:60:99”,
                "port": 51826
        },

        "description": "This is an example configuration file with one fake accessory and
 one fake platform. You can use this as a template for creating your own configuration fi
le containing devices you actually own.",

vishbin

Programming Achievements: How to Level Up as a Developer

This gist is part of a blog post. Check it out at:

http://jasonrudolph.com/blog/2011/08/09/programming-achievements-how-to-level-up-as-a-developer

vishbin

Latency Comparison Numbers
--------------------------
L1 cache reference/hit                       1.5 ns                      4 cycles
Floating-point add/mult/FMA operation        1.5 ns                      4 cycles
L2 cache reference/hit                       5   ns                      12 ~ 17 cycles
Branch mispredict                            6   ns                      15 ~ 20 cycles
L3 cache hit (unshared cache line)          16   ns                      42 cycles
L3 cache hit (shared line in another core)  25   ns                      65 cycles
Mutex lock/unlock                           25   ns
L3 cache hit (modified in another core)     29   ns                      75 cycles