gistfile1.txt

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:39:45 04/14/2016 
// Design Name: 
// Module Name:    FPCVT 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module FPCVT(
    input [11:0] D,
    output S,
    output [2:0] E,
    output [3:0] F
    );

assign S = D[11];

//2's Complement Converter
wire [11:0] twosc;
assign twosc = D[11] ? ~D+1 : D;
/*if(D[11] == 1'b1)
begin
	assign twosc = ~D + 1;
end
else
begin
	assign twosc = D;
end */

//Count leading zeroes
wire [3:0] countz;
assign countz =
	(twosc[11]) ? 0:
	(twosc[10]) ? 1:	
	(twosc[9]) ? 2 :
	(twosc[8]) ? 3 :
	(twosc[7]) ? 4 :
	(twosc[6]) ? 5 :
	(twosc[5]) ? 6 :
	(twosc[5]) ? 7 : 8;

wire [2:0] exponent;
assign exponent = 
	(countz == 0) ? 8:
	(countz == 1) ? 7:
	(countz == 2) ? 6:
	(countz == 3) ? 5:
	(countz == 4) ? 4:
	(countz == 5) ? 3:
	(countz == 6) ? 2:
	(countz == 7) ? 1: 0;
 
	
//Extract leading bits
wire [3:0] leadbits;
assign leadbits[3] = twosc[11 - countz];
assign leadbits[2] = twosc[11 - (countz + 1)];
assign leadbits[1] = twosc[11 - (countz + 2)];
assign leadbits[0] = twosc[11 - (countz + 3)];

wire fifthbit = (countz == 8) ? 0: twosc[11 - (countz + 4)];
wire [3:0] significand = leadbits;

//Rounding
wire overflow = (significand == 4'b1111) ? 1 : 0;
wire [4:0] incremented_significand = significand + fifthbit;
wire [2:0] updated_exponent = exponent + overflow;
wire [3:0] updated_significand = incremented_significand >> overflow;
assign E = updated_exponent;
assign F = updated_significand;
endmodule