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@vishvanand
Created April 21, 2016 16:40
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:55:46 04/19/2016
// Design Name:
// Module Name: floating_point
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module floating_point(
D,
S,
E,
F
);
input [11:0] D;
output S;
output [2:0] E;
output [3:0] F;
wire [11:0] D;
wire S;
wire [2:0] E;
wire [3:0] F;
assign S = D[11];
//To implement: convert negative to signed 1's complement
wire [11:0] P;
assign P = S? ~D + 1 : D;
wire [4:0] Fround;
assign Fround = P[10] ? P[10:5] :
P[9] ? P[9:4] :
P[8] ? P[8:3] :
P[7] ? P[7:2] :
P[6] ? P[6:1] :
P[5] ? P[5:0] :
P[4:0];
wire [4:0] Froundp;
assign Froundp = (Fround[0] + Fround) >> 1;
assign F = Froundp[4:1];
assign E = P[10] ? 8 :
P[9] ? 7 :
P[8] ? 6 :
P[7] ? 5 :
P[6] ? 4 :
P[5] ? 3 :
P[4] ? 2 :
1;
endmodule
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