Created
May 31, 2016 16:57
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`timescale 1ns / 1ps | |
//////////////////////////////////////////////////////////////////////////////// | |
// Company: | |
// Engineer: | |
// | |
// Create Date: 03:14:12 05/31/2016 | |
// Design Name: finalproject | |
// Module Name: D:/XilinxVerilog/CSFiles/finalproject/testfinal.v | |
// Project Name: finalproject | |
// Target Device: | |
// Tool versions: | |
// Description: | |
// | |
// Verilog Test Fixture created by ISE for module: finalproject | |
// | |
// Dependencies: | |
// | |
// Revision: | |
// Revision 0.01 - File Created | |
// Additional Comments: | |
// | |
//////////////////////////////////////////////////////////////////////////////// | |
module testfinal; | |
// Inputs | |
reg clk; | |
reg reset; | |
reg swtch1; | |
reg swtch2; | |
// Outputs | |
wire [3:0] Anode; | |
wire [6:0] Cathode; | |
wire [7:0] Led; | |
// Instantiate the Unit Under Test (UUT) | |
finalproject uut ( | |
.clk(clk), | |
.reset(reset), | |
.Anode(Anode), | |
.Cathode(Cathode), | |
.Led(Led), | |
.swtch1(swtch1), | |
.swtch2(swtch2) | |
); | |
initial begin | |
// Initialize Inputs | |
clk = 0; | |
reset = 0; | |
swtch1 = 0; | |
swtch2 = 0; | |
// Wait 100 ns for global reset to finish | |
#100; | |
// Add stimulus here | |
end | |
always | |
begin | |
#0.005 clk = ~clk; | |
end | |
endmodule | |
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