gistfile1.txt

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:10:23 04/19/2016
// Design Name:   FPCVT
// Module Name:   C:/Users/User/Documents/Classes/CS M152a/Lab2/FPCVT/FPCVT_TB.v
// Project Name:  FPCVT
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: FPCVT
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module FPCVT_TB;

	// Inputs
	reg [11:0] D;

	// Outputs
	wire S;
	wire [2:0] E;
	wire [3:0] F;

	// Instantiate the Unit Under Test (UUT)
	FPCVT uut (
		.D(D), 
		.S(S), 
		.E(E), 
		.F(F)
	);

	initial begin
		// Initialize Inputs
		D = 0;

		// Wait 10 ns for global reset to finish
		#10;
        
		// Add stimulus here
		D = -40;
		#10
		D = 56;
		#10     // Rounding Tests
		D = 44; //0 010 1011
		#10
		D = 45; //0 010 1011
		# 10
		D = 46; //0 010 1100
		#10 
		D = 47; //0 010 1100
		# 10
		D = 125; //0 100 1000
		# 10
		D = 128;
		# 10
		D = 129; 
	end
      
endmodule