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1:26 AM, lab 289, Apr 30, 2013.
draft of Match filter for BPSK Costas loop for EE 287.
Debugging night in lab
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| //`define ntaps 43 | |
| `timescale 1ns/10ps | |
| //`include "DW02_mult_2_stage.v" | |
| module fir(clk,reset,flagin,din,dout,flagout); | |
| input clk, flagin,reset; | |
| input [31:0] din; | |
| output signed [31:0] dout; | |
| //input [5:0] waddr; | |
| //input wstrobe; | |
| //input [31:0] wdata; | |
| //output [31:0] rdata; | |
| reg flagin1,flagin2,flagin3,flagin4; | |
| output flagout; | |
| reg signed [63:0] sum[0:42]; | |
| reg signed[63:0] sumout; | |
| reg signed[31:0] coef[0:42]; | |
| // wire [31:0] sr1; | |
| // wire [63:0] pr1; | |
| reg signed [31:0] sr[0:42]; | |
| reg signed[63:0] pr[0:42]; | |
| reg signed [63:0] pr_dw0, pr_dw1, pr_dw2, pr_dw3, pr_dw4, pr_dw5, pr_dw6, pr_dw7, pr_dw8, pr_dw9, pr_dw10, pr_dw11, pr_dw12, pr_dw13, pr_dw14, pr_dw15, pr_dw16, pr_dw17, pr_dw18, pr_dw19, pr_dw20, pr_dw21, pr_dw22, pr_dw23, pr_dw24, pr_dw25, pr_dw26, pr_dw27, pr_dw28, pr_dw29, pr_dw30, pr_dw31, pr_dw32, pr_dw33, pr_dw34, pr_dw35, pr_dw36, pr_dw37, pr_dw38, pr_dw39, pr_dw40, pr_dw41, pr_dw42; | |
| //reg [42:0] flag_out_reg; | |
| //wire [63:0] pr_sample; | |
| //reg [63:0] sum; | |
| always @(negedge clk) | |
| begin | |
| coef[0]= 32'd2; | |
| coef[1]=32'd4; | |
| coef[2]=32'd4; | |
| coef[3]=32'd2; | |
| coef[4]=-32'd3; | |
| coef[5]=-32'd10; | |
| coef[6]=-32'd14; | |
| coef[7]=-32'd14; | |
| coef[8]=-32'd6; | |
| coef[9]=32'd7; | |
| coef[10]=32'd19; | |
| coef[11]= 32'd22; | |
| coef[12]=32'd12; | |
| coef[13]=-32'd11; | |
| coef[14]=-32'd36; | |
| coef[15]=-32'd48; | |
| coef[16]=-32'd35; | |
| coef[17]=32'd11; | |
| coef[18]=32'd83; | |
| coef[19]=32'd161; | |
| coef[20]=32'd221; | |
| coef[21]=32'd244; | |
| coef[22]=32'd221; | |
| coef[23]=32'd161; | |
| coef[24]=32'd83; | |
| coef[25]=32'd11; | |
| coef[26]=-32'd35; | |
| coef[27]=-32'd48; | |
| coef[28]=-32'd36; | |
| coef[29]=-32'd11; | |
| coef[30]=32'd12; | |
| coef[31]=32'd22; | |
| coef[32]=32'd19; | |
| coef[33]=32'd7; | |
| coef[34]=32'd6; | |
| coef[35]=-32'd14; | |
| coef[36]=-32'd14; | |
| coef[37]=-32'd10; | |
| coef[38]=-32'd3; | |
| coef[39]=32'd2; | |
| coef[40]=32'd4; | |
| coef[41]=32'd4; | |
| coef[42]=32'd2; | |
| //$display ("coef[0]=%d",coef[0]); | |
| end | |
| always @(negedge clk or posedge reset) | |
| begin | |
| if (reset) begin | |
| /*sr[0] <= #1 32'd0; | |
| sr[1] <= #1 32'd0; | |
| sr[2] <= #1 32'd0; | |
| sr[3] <= #1 32'd0; | |
| sr[4] <= #1 32'd0; | |
| sr[5] <= #1 32'd0; | |
| sr[6] <= #1 32'd0; | |
| sr[7] <= #1 32'd0; | |
| sr[8] <= #1 32'd0; | |
| sr[9] <= #1 32'd0; | |
| sr[10] <= #1 32'd0; | |
| sr[11] <= #1 32'd0; | |
| sr[12] <= #1 32'd0; | |
| sr[13] <= #1 32'd0; | |
| sr[14] <= #1 32'd0; | |
| sr[15] <= #1 32'd0; | |
| sr[16] <= #1 32'd0; | |
| sr[17] <= #1 32'd0; | |
| sr[18] <= #1 32'd0; | |
| sr[19] <= #1 32'd0; | |
| sr[20] <= #1 32'd0; | |
| sr[21] <= #1 32'd0; | |
| sr[22] <= #1 32'd0; | |
| sr[23] <= #1 32'd0; | |
| sr[24] <= #1 32'd0; | |
| sr[25] <= #1 32'd0; | |
| sr[26] <= #1 32'd0; | |
| sr[27] <= #1 32'd0; | |
| sr[28] <= #1 32'd0; | |
| sr[29] <= #1 32'd0; | |
| sr[30] <= #1 32'd0; | |
| sr[31] <= #1 32'd0; | |
| sr[32] <= #1 32'd0; | |
| sr[33] <= #1 32'd0; | |
| sr[34] <= #1 32'd0; | |
| sr[35] <= #1 32'd0; | |
| sr[36] <= #1 32'd0; | |
| sr[37] <= #1 32'd0; | |
| sr[38] <= #1 32'd0; | |
| sr[39] <= #1 32'd0; | |
| sr[40] <= #1 32'd0; | |
| sr[41] <= #1 32'd0; | |
| sr[42] <= #1 32'd0;*/ | |
| pr_dw0 <= 64'd0; | |
| pr_dw1 <= 64'd0; | |
| pr_dw2 <= 64'd0; | |
| pr_dw3 <= 64'd0; | |
| pr_dw4 <= 64'd0; | |
| pr_dw5 <= 64'd0; | |
| pr_dw6 <= 64'd0; | |
| pr_dw7 <= 64'd0; | |
| pr_dw8 <= 64'd0; | |
| pr_dw9 <= 64'd0; | |
| pr_dw10 <= 64'd0; | |
| pr_dw11 <= 64'd0; | |
| pr_dw12 <= 64'd0; | |
| pr_dw13 <= 64'd0; | |
| pr_dw14 <= 64'd0; | |
| pr_dw15 <= 64'd0; | |
| pr_dw16 <= 64'd0; | |
| pr_dw17 <= 64'd0; | |
| pr_dw18 <= 64'd0; | |
| pr_dw19 <= 64'd0; | |
| pr_dw20 <= 64'd0; | |
| pr_dw21 <= 64'd0; | |
| pr_dw22 <= 64'd0; | |
| pr_dw23 <= 64'd0; | |
| pr_dw24 <= 64'd0; | |
| pr_dw25 <= 64'd0; | |
| pr_dw26 <= 64'd0; | |
| pr_dw27 <= 64'd0; | |
| pr_dw28 <= 64'd0; | |
| pr_dw29 <= 64'd0; | |
| pr_dw30 <= 64'd0; | |
| pr_dw31 <= 64'd0; | |
| pr_dw32 <= 64'd0; | |
| pr_dw33 <= 64'd0; | |
| pr_dw34 <= 64'd0; | |
| pr_dw35 <= 64'd0; | |
| pr_dw36 <= 64'd0; | |
| pr_dw37 <= 64'd0; | |
| pr_dw38 <= 64'd0; | |
| pr_dw39 <= 64'd0; | |
| pr_dw40 <= 64'd0; | |
| pr_dw41 <= 64'd0; | |
| pr_dw42 <= 64'd0; | |
| flagin2 <= #1 0; end | |
| else if (flagin1 == 1)begin | |
| flagin2 <= #1 flagin1; | |
| pr_dw0 <= sr[0] * coef[0]; | |
| pr_dw1 <= sr[1] * coef[1]; | |
| pr_dw2 <= sr[2] * coef[2]; | |
| pr_dw3 <= sr[3] * coef[3]; | |
| pr_dw4 <= sr[4] * coef[4]; | |
| pr_dw5 <= sr[5] * coef[5]; | |
| pr_dw6 <= sr[6] * coef[6]; | |
| pr_dw7 <= sr[7] * coef[7]; | |
| pr_dw8 <= sr[8] * coef[8]; | |
| pr_dw9 <= sr[9] * coef[9]; | |
| pr_dw10 <= sr[10] * coef[10]; | |
| pr_dw11 <= sr[11] * coef[11]; | |
| pr_dw12 <= sr[12] * coef[12]; | |
| pr_dw13 <= sr[13] * coef[13]; | |
| pr_dw14 <= sr[14] * coef[14]; | |
| pr_dw15 <= sr[15] * coef[15]; | |
| pr_dw16 <= sr[16] * coef[16]; | |
| pr_dw17 <= sr[17] * coef[17]; | |
| pr_dw18 <= sr[18] * coef[18]; | |
| pr_dw19 <= sr[19] * coef[19]; | |
| pr_dw20 <= sr[20] * coef[20]; | |
| pr_dw21 <= sr[21] * coef[21]; | |
| pr_dw22 <= sr[22] * coef[22]; | |
| pr_dw23 <= sr[23] * coef[23]; | |
| pr_dw24 <= sr[24] * coef[24]; | |
| pr_dw25 <= sr[25] * coef[25]; | |
| pr_dw26 <= sr[26] * coef[26]; | |
| pr_dw27 <= sr[27] * coef[27]; | |
| pr_dw28 <= sr[28] * coef[28]; | |
| pr_dw29 <= sr[29] * coef[29]; | |
| pr_dw30 <= sr[30] * coef[30]; | |
| pr_dw31 <= sr[31] * coef[31]; | |
| pr_dw32 <= sr[32] * coef[32]; | |
| pr_dw33 <= sr[33] * coef[33]; | |
| pr_dw34 <= sr[34] * coef[34]; | |
| pr_dw35 <= sr[35] * coef[35]; | |
| pr_dw36 <= sr[36] * coef[36]; | |
| pr_dw37 <= sr[37] * coef[37]; | |
| pr_dw38 <= sr[38] * coef[38]; | |
| pr_dw39 <= sr[39] * coef[39]; | |
| pr_dw40 <= sr[40] * coef[40]; | |
| pr_dw41 <= sr[41] * coef[41]; | |
| pr_dw42 <= sr[42] * coef[42]; | |
| end | |
| else flagin2 <= #1 0; | |
| end | |
| always @(negedge clk or posedge reset) | |
| begin:block2 | |
| integer i,k,j; | |
| if (reset) begin | |
| //dout <= #1 0; | |
| //sum <= #1 64'd0; | |
| flagin1 <= #1 0; | |
| sr[0] <= #1 32'd0; | |
| sr[1] <= #1 32'd0; | |
| sr[2] <= #1 32'd0; | |
| sr[3] <= #1 32'd0; | |
| sr[4] <= #1 32'd0; | |
| sr[5] <= #1 32'd0; | |
| sr[6] <= #1 32'd0; | |
| sr[7] <= #1 32'd0; | |
| sr[8] <= #1 32'd0; | |
| sr[9] <= #1 32'd0; | |
| sr[10] <= #1 32'd0; | |
| sr[11] <= #1 32'd0; | |
| sr[12] <= #1 32'd0; | |
| sr[13] <= #1 32'd0; | |
| sr[14] <= #1 32'd0; | |
| sr[15] <= #1 32'd0; | |
| sr[16] <= #1 32'd0; | |
| sr[17] <= #1 32'd0; | |
| sr[18] <= #1 32'd0; | |
| sr[19] <= #1 32'd0; | |
| sr[20] <= #1 32'd0; | |
| sr[21] <= #1 32'd0; | |
| sr[22] <= #1 32'd0; | |
| sr[23] <= #1 32'd0; | |
| sr[24] <= #1 32'd0; | |
| sr[25] <= #1 32'd0; | |
| sr[26] <= #1 32'd0; | |
| sr[27] <= #1 32'd0; | |
| sr[28] <= #1 32'd0; | |
| sr[29] <= #1 32'd0; | |
| sr[30] <= #1 32'd0; | |
| sr[31] <= #1 32'd0; | |
| sr[32] <= #1 32'd0; | |
| sr[33] <= #1 32'd0; | |
| sr[34] <= #1 32'd0; | |
| sr[35] <= #1 32'd0; | |
| sr[36] <= #1 32'd0; | |
| sr[37] <= #1 32'd0; | |
| sr[38] <= #1 32'd0; | |
| sr[39] <= #1 32'd0; | |
| sr[40] <= #1 32'd0; | |
| sr[41] <= #1 32'd0; | |
| sr[42] <= #1 32'd0; | |
| /* | |
| pr[0] <= #1 64'd0; | |
| pr[1] <= #1 64'd0; | |
| pr[2] <= #1 64'd0; | |
| pr[3] <= #1 64'd0; | |
| pr[4] <= #1 64'd0; | |
| pr[5] <= #1 64'd0; | |
| pr[6] <= #1 64'd0; | |
| pr[7] <= #1 64'd0; | |
| pr[8] <= #1 64'd0; | |
| pr[9] <= #1 64'd0; | |
| pr[10] <= #1 64'd0; | |
| pr[11] <= #1 64'd0; | |
| pr[12] <= #1 64'd0; | |
| pr[13] <= #1 64'd0; | |
| pr[14] <= #1 64'd0; | |
| pr[15] <= #1 64'd0; | |
| pr[16] <= #1 64'd0; | |
| pr[17] <= #1 64'd0; | |
| pr[18] <= #1 64'd0; | |
| pr[19] <= #1 64'd0; | |
| pr[20] <= #1 64'd0; block 1; | |
| pr[21] <= #1 64'd0; | |
| pr[22] <= #1 64'd0; | |
| pr[23] <= #1 64'd0; | |
| pr[24] <= #1 64'd0; | |
| pr[25] <= #1 64'd0; | |
| pr[26] <= #1 64'd0; | |
| pr[27] <= #1 64'd0; | |
| pr[28] <= #1 64'd0; | |
| pr[29] <= #1 64'd0; | |
| pr[30] <= #1 64'd0; | |
| pr[31] <= #1 64'd0; | |
| pr[32] <= #1 64'd0; | |
| pr[33] <= #1 64'd0; | |
| pr[34] <= #1 64'd0; | |
| pr[35] <= #1 64'd0; | |
| pr[36] <= #1 64'd0; | |
| pr[37] <= #1 64'd0; | |
| pr[38] <= #1 64'd0; | |
| pr[39] <= #1 64'd0; | |
| pr[40] <= #1 64'd0; | |
| pr[41] <= #1 64'd0; | |
| pr[42] <= #1 64'd0; | |
| //$display ("pr=%d,sr=%d",pr[0],sr[0]); | |
| //for (k =0; k< 42; k = k+1) | |
| //begin | |
| //sr[k] <= #1 0; end | |
| //for (j = 0; j< 42; j=j+1) | |
| //begin | |
| //pr[j] <= #1 0; | |
| //flag_out_reg <= #1 43'd0 ; */ | |
| end | |
| else | |
| if(flagin==1) | |
| begin | |
| sr[0] <= #1 din; | |
| flagin1 <= #1 flagin; | |
| for (i=1; i < 43; i=i+1) begin | |
| sr[i] <= #1 sr[i-1]; | |
| end | |
| end | |
| else flagin1 <= #1 0; | |
| end | |
| /* | |
| always @(negedge clk or posedge reset) | |
| begin | |
| if (reset) begin | |
| flagin1 <= #1 0; | |
| sr[0] <= #1 0; end | |
| else begin | |
| if(flagin==1)begin | |
| sr[0] <= #1 din; | |
| flagin1 <= #1 flagin; end | |
| //$display ("sr[0]=%d",sr[0]); | |
| end | |
| end | |
| */ | |
| always @ (negedge clk or posedge reset) | |
| begin:block3 | |
| if (reset) | |
| begin | |
| /*sr[0] <= #1 32'd0; | |
| sr[1] <= #1 32'd0; | |
| sr[2] <= #1 32'd0; | |
| sr[3] <= #1 32'd0; | |
| sr[4] <= #1 32'd0; | |
| sr[5] <= #1 32'd0; | |
| sr[6] <= #1 32'd0; | |
| sr[7] <= #1 32'd0; | |
| sr[8] <= #1 32'd0; | |
| sr[9] <= #1 32'd0; | |
| sr[10] <= #1 32'd0; | |
| sr[11] <= #1 32'd0; | |
| sr[12] <= #1 32'd0; | |
| sr[13] <= #1 32'd0; | |
| sr[14] <= #1 32'd0; | |
| sr[15] <= #1 32'd0; | |
| sr[16] <= #1 32'd0; | |
| sr[17] <= #1 32'd0; | |
| sr[18] <= #1 32'd0; | |
| sr[19] <= #1 32'd0; | |
| sr[20] <= #1 32'd0; | |
| sr[21] <= #1 32'd0; | |
| sr[22] <= #1 32'd0; | |
| sr[23] <= #1 32'd0; | |
| sr[24] <= #1 32'd0; | |
| sr[25] <= #1 32'd0; | |
| sr[26] <= #1 32'd0; | |
| sr[27] <= #1 32'd0; | |
| sr[28] <= #1 32'd0; | |
| sr[29] <= #1 32'd0; | |
| sr[30] <= #1 32'd0; | |
| sr[31] <= #1 32'd0; | |
| sr[32] <= #1 32'd0; | |
| sr[33] <= #1 32'd0; | |
| sr[34] <= #1 32'd0; | |
| sr[35] <= #1 32'd0; | |
| sr[36] <= #1 32'd0; | |
| sr[37] <= #1 32'd0; | |
| sr[38] <= #1 32'd0; | |
| sr[39] <= #1 32'd0; | |
| sr[40] <= #1 32'd0; | |
| sr[41] <= #1 32'd0; | |
| sr[42] <= #1 32'd0; | |
| */ | |
| pr[0] <= #1 pr_dw0; | |
| pr[1] <= #1 pr_dw1; | |
| pr[2] <= #1 pr_dw2; | |
| pr[3] <= #1 pr_dw3; | |
| pr[4] <= #1 pr_dw4; | |
| pr[5] <= #1 pr_dw5; | |
| pr[6] <= #1 pr_dw6; | |
| pr[7] <= #1 pr_dw7; | |
| pr[8] <= #1 pr_dw8; | |
| pr[9] <= #1 pr_dw9; | |
| pr[10] <= #1 pr_dw10; | |
| pr[11] <= #1 pr_dw11; | |
| pr[12] <= #1 pr_dw12; | |
| pr[13] <= #1 pr_dw13; | |
| pr[14] <= #1 pr_dw14; | |
| pr[15] <= #1 pr_dw15; | |
| pr[16] <= #1 pr_dw16; | |
| pr[17] <= #1 pr_dw17; | |
| pr[18] <= #1 pr_dw18; | |
| pr[19] <= #1 pr_dw19; | |
| pr[20] <= #1 pr_dw20; | |
| pr[21] <= #1 pr_dw21; | |
| pr[22] <= #1 pr_dw22; | |
| pr[23] <= #1 pr_dw23; | |
| pr[24] <= #1 pr_dw24; | |
| pr[25] <= #1 pr_dw25; | |
| pr[26] <= #1 pr_dw26; | |
| pr[27] <= #1 pr_dw27; | |
| pr[28] <= #1 pr_dw28; | |
| pr[29] <= #1 pr_dw29; | |
| pr[30] <= #1 pr_dw30; | |
| pr[31] <= #1 pr_dw31; | |
| pr[32] <= #1 pr_dw32; | |
| pr[33] <= #1 pr_dw33; | |
| pr[34] <= #1 pr_dw34; | |
| pr[35] <= #1 pr_dw35; | |
| pr[36] <= #1 pr_dw36; | |
| pr[37] <= #1 pr_dw37; | |
| pr[38] <= #1 pr_dw38; | |
| pr[39] <= #1 pr_dw39; | |
| pr[40] <= #1 pr_dw40; | |
| pr[41] <= #1 pr_dw41; | |
| pr[42] <= #1 pr_dw42; | |
| flagin3 <= #1 0; end | |
| //flag_out_reg <= #1 42'd0 ; end | |
| else if (flagin2 == 1)begin | |
| flagin3 <= #1 flagin2; | |
| pr[0] <= #1 pr_dw0; //$display ("pr[0]=%d", pr[0]);$display ("pr_dw0=%d", pr_dw0); | |
| pr[1] <= #1 pr_dw1; | |
| pr[2] <= #1 pr_dw2; | |
| pr[3] <= #1 pr_dw3; | |
| pr[4] <= #1 pr_dw4; | |
| pr[5] <= #1 pr_dw5; | |
| pr[6] <= #1 pr_dw6; | |
| pr[7] <= #1 pr_dw7; | |
| pr[8] <= #1 pr_dw8; | |
| pr[9] <= #1 pr_dw9; | |
| pr[10] <= #1 pr_dw10; | |
| pr[11] <= #1 pr_dw11; | |
| pr[12] <= #1 pr_dw12; | |
| pr[13] <= #1 pr_dw13; | |
| pr[14] <= #1 pr_dw14; | |
| pr[15] <= #1 pr_dw15; | |
| pr[16] <= #1 pr_dw16; | |
| pr[17] <= #1 pr_dw17; | |
| pr[18] <= #1 pr_dw18; | |
| pr[19] <= #1 pr_dw19; | |
| pr[20] <= #1 pr_dw20; | |
| pr[21] <= #1 pr_dw21; | |
| pr[22] <= #1 pr_dw22; | |
| pr[23] <= #1 pr_dw23; | |
| pr[24] <= #1 pr_dw24; | |
| pr[25] <= #1 pr_dw25; | |
| pr[26] <= #1 pr_dw26; | |
| pr[27] <= #1 pr_dw27; | |
| pr[28] <= #1 pr_dw28; | |
| pr[29] <= #1 pr_dw29; | |
| pr[30] <= #1 pr_dw30; | |
| pr[31] <= #1 pr_dw31; | |
| pr[32] <= #1 pr_dw32; | |
| pr[33] <= #1 pr_dw33; | |
| pr[34] <= #1 pr_dw34; | |
| pr[35] <= #1 pr_dw35; | |
| pr[36] <= #1 pr_dw36; | |
| pr[37] <= #1 pr_dw37; | |
| pr[38] <= #1 pr_dw38; | |
| pr[39] <= #1 pr_dw39; | |
| pr[40] <= #1 pr_dw40; | |
| pr[41] <= #1 pr_dw41; | |
| pr[42] <= #1 pr_dw42; | |
| end | |
| else flagin3 <= #1 0; | |
| end | |
| always @ (*) begin | |
| //if (reset) begin | |
| //sum =0; end | |
| //else begin | |
| //if (reset) begin | |
| sum[0]= pr[0]; //$display ("sum[0]= %d",sum[0]); | |
| sum[1]= pr[1] + sum[0];//$display ("sum[1]= %d",sum[1]); | |
| sum[2]= pr[2] + sum[1];//$display ("sum[2]= %d",sum[2]); | |
| sum[3]= pr[3] + sum[2];//$display ("sum[3]= %d",sum[3]); | |
| sum[4]= pr[4] + sum[3];//$display ("sum[4]= %d",sum[4]); | |
| sum[5]= pr[5] + sum[4];//$display ("sum[5]= %d",sum[5]); | |
| sum[6]= pr[6] + sum[5];//$display ("sum[6]= %d",sum[6]); | |
| sum[7]= pr[7] + sum[6];//$display ("sum[7]= %d",sum[7]); | |
| sum[8]= pr[8] + sum[7];//$display ("sum[8]= %d",sum[8]); | |
| sum[9]= pr[9] + sum[8]; | |
| sum[10]= pr[10] + sum[9]; | |
| sum[11]= pr[11] + sum[10]; | |
| sum[12]= pr[12] + sum[11]; | |
| sum[13]= pr[13] + sum[12]; | |
| sum[14]= pr[14] + sum[13]; | |
| sum[15]= pr[15] + sum[14]; | |
| sum[16]= pr[16] + sum[15]; | |
| sum[17]= pr[17] + sum[16]; | |
| sum[18]= pr[18] + sum[17]; | |
| sum[19]= pr[19] + sum[18];//$display ("sum[19]= %d",sum[19]); | |
| sum[20]= pr[20] + sum[19]; | |
| sum[21]= pr[21] + sum[20]; | |
| sum[22]= pr[22] + sum[21]; | |
| sum[23]= pr[23] + sum[22]; | |
| sum[24]= pr[24] + sum[23]; | |
| sum[25]= pr[25] + sum[24]; | |
| sum[26]= pr[26] + sum[25]; | |
| sum[27]= pr[27] + sum[26]; | |
| sum[28]= pr[28] + sum[27]; | |
| sum[29]= pr[29] + sum[28]; | |
| sum[30]= pr[30] + sum[29];//$display ("sum[30]= %d",sum[30]); | |
| sum[31]= pr[31] + sum[30]; | |
| sum[32]= pr[32] + sum[31]; | |
| sum[33]= pr[33] + sum[32]; | |
| sum[34]= pr[34] + sum[33]; | |
| sum[35]= pr[35] + sum[34]; | |
| sum[36]= pr[36] + sum[35]; | |
| sum[37]= pr[37] + sum[36];//$display ("sum[36]= %d",sum[36]); | |
| sum[38]= pr[38] + sum[37]; | |
| sum[39]= pr[39] + sum[38]; | |
| sum[40]= pr[40] + sum[39]; | |
| sum[41]= pr[41] + sum[40]; | |
| sum[42]= pr[42] + sum[41]; //$display("sum[42]= %d",sum[42]); | |
| end | |
| always @(negedge clk or posedge reset) | |
| begin | |
| if (reset) begin | |
| flagin4 <= #1 0; | |
| sumout <= #1 64'd0; end | |
| else if (flagin3 == 1)begin | |
| flagin4 <= #1 flagin3; | |
| sumout <= #1 sum[42]; end | |
| else flagin4 <= #1 0; | |
| end | |
| assign dout=sumout[39:8]; | |
| //assign dout=sumout[31:0]; | |
| //assign dout={{12{sumout[28]}},sumout[27:8]}; | |
| //assign dout=sumout; | |
| assign flagout=flagin4; | |
| endmodule |
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| `timescale 1ns/10ps | |
| module mf(clk,reset,flagin,din,dout,flagout); | |
| input clk, flagin,reset; | |
| input [31:0] din; | |
| output reg [31:0] dout; | |
| reg [4:0] flag_in_reg; | |
| reg [31:0] dout1; | |
| output flagout; | |
| //reg signed [63:0] sum[0:42]; | |
| //reg signed[63:0] sumout; | |
| reg signed[31:0] sr[0:499]; | |
| // 4 stages of addition | |
| reg signed[31:0] pre0 [0:99]; | |
| reg signed[31:0] p1 [0:19]; | |
| reg signed[31:0] p2 [0:3]; | |
| reg signed[31:0] p3; | |
| reg sync; | |
| reg syncflag; | |
| reg [9:0] final; | |
| integer cnt, cnt10; | |
| wire [31:0] sr13; | |
| ////////////////////////////////////////////////////////// | |
| // input FF | |
| ////////////////////////////////////////////////////////// | |
| always @(negedge clk or negedge reset) | |
| begin: block1 | |
| integer i,j,k; | |
| if (reset || sync) begin | |
| for (i=0; i<500; i=i+1) begin | |
| sr[i] <= #1 0; | |
| end | |
| end | |
| else if (flagin == 1) begin | |
| //sr[0] <= #1 din; | |
| flag_in_reg[0] <= #1 flagin; | |
| //for (k=0; k < 25; k=k+1) begin //credit for Jayesh!!! NICE | |
| sr[0] <= #1 din; | |
| //end | |
| for (j=1; j<500; j=j+1) begin | |
| sr[j] <= #1 sr[j-1]; | |
| end | |
| end else | |
| flag_in_reg[0] <= #1 0; | |
| end | |
| always @ (negedge clk or posedge reset) | |
| begin: block2 | |
| integer l; | |
| if (reset) begin | |
| for (l=0; l<100; l=l+1) begin | |
| pre0[l] <= #1 0; | |
| end | |
| end else if (flag_in_reg[0] == 1) begin | |
| flag_in_reg[1] <= #1 flag_in_reg[0]; | |
| // the first stage | |
| pre0[5] <= #1 sr[25]+sr[26]+sr[27]+sr[28]+sr[29]; | |
| pre0[6] <= #1 sr[30]+sr[31]+sr[32]+sr[33]+sr[34]; | |
| pre0[7] <= #1 sr[35]+sr[36]+sr[37]+sr[38]+sr[39]; | |
| pre0[8] <= #1 sr[40]+sr[41]+sr[42]+sr[43]+sr[44]; | |
| pre0[9] <= #1 sr[45]+sr[46]+sr[47]+sr[48]+sr[49]; | |
| pre0[10] <= #1 sr[50]+sr[51]+sr[52]+sr[53]+sr[54]; | |
| pre0[11] <= #1 sr[55]+sr[56]+sr[57]+sr[58]+sr[59]; | |
| pre0[12] <= #1 sr[60]+sr[61]+sr[62]+sr[63]+sr[64]; | |
| pre0[13] <= #1 sr[65]+sr[66]+sr[67]+sr[68]+sr[69]; | |
| pre0[14] <= #1 sr[70]+sr[71]+sr[72]+sr[73]+sr[74]; | |
| pre0[40] <= #1 sr[200]+sr[201]+sr[202]+sr[203]+sr[204]; | |
| pre0[41] <= #1 sr[205]+sr[206]+sr[207]+sr[208]+sr[209]; | |
| pre0[42] <= #1 sr[210]+sr[211]+sr[212]+sr[213]+sr[214]; | |
| pre0[43] <= #1 sr[215]+sr[216]+sr[217]+sr[218]+sr[219]; | |
| pre0[44] <= #1 sr[220]+sr[221]+sr[222]+sr[223]+sr[224]; | |
| pre0[45] <= #1 sr[225]+sr[226]+sr[227]+sr[228]+sr[229]; | |
| pre0[46] <= #1 sr[230]+sr[231]+sr[232]+sr[233]+sr[234]; | |
| pre0[47] <= #1 sr[235]+sr[236]+sr[237]+sr[238]+sr[239]; | |
| pre0[48] <= #1 sr[240]+sr[241]+sr[242]+sr[243]+sr[244]; | |
| pre0[49] <= #1 sr[245]+sr[246]+sr[247]+sr[248]+sr[249]; | |
| pre0[50] <= #1 sr[250]+sr[251]+sr[252]+sr[253]+sr[254]; | |
| pre0[51] <= #1 sr[255]+sr[256]+sr[257]+sr[258]+sr[259]; | |
| pre0[52] <= #1 sr[260]+sr[261]+sr[262]+sr[263]+sr[264]; | |
| pre0[53] <= #1 sr[265]+sr[266]+sr[267]+sr[268]+sr[269]; | |
| pre0[54] <= #1 sr[270]+sr[271]+sr[272]+sr[273]+sr[274]; | |
| pre0[65] <= #1 sr[325]+sr[326]+sr[327]+sr[328]+sr[329]; | |
| pre0[66] <= #1 sr[330]+sr[331]+sr[332]+sr[333]+sr[334]; | |
| pre0[67] <= #1 sr[335]+sr[336]+sr[337]+sr[338]+sr[339]; | |
| pre0[68] <= #1 sr[340]+sr[341]+sr[342]+sr[343]+sr[344]; | |
| pre0[69] <= #1 sr[345]+sr[346]+sr[347]+sr[348]+sr[349]; | |
| pre0[75] <= #1 sr[375]+sr[376]+sr[377]+sr[378]+sr[379]; | |
| pre0[76] <= #1 sr[380]+sr[381]+sr[382]+sr[383]+sr[384]; | |
| pre0[77] <= #1 sr[385]+sr[386]+sr[387]+sr[388]+sr[389]; | |
| pre0[78] <= #1 sr[390]+sr[391]+sr[392]+sr[393]+sr[394]; | |
| pre0[79] <= #1 sr[395]+sr[396]+sr[397]+sr[398]+sr[399]; | |
| pre0[80] <= #1 sr[400]+sr[401]+sr[402]+sr[403]+sr[404]; | |
| pre0[81] <= #1 sr[405]+sr[406]+sr[407]+sr[408]+sr[409]; | |
| pre0[82] <= #1 sr[410]+sr[411]+sr[412]+sr[413]+sr[414]; | |
| pre0[83] <= #1 sr[415]+sr[416]+sr[417]+sr[418]+sr[419]; | |
| pre0[84] <= #1 sr[420]+sr[421]+sr[422]+sr[423]+sr[424]; | |
| pre0[0] <= #1 sr[0]+sr[1]+sr[2]+sr[3]+sr[4]; | |
| pre0[1] <= #1 sr[5]+sr[6]+sr[7]+sr[8]+sr[9]; | |
| pre0[2] <= #1 sr[10]+sr[11]+sr[12]+sr[13]+sr[14]; | |
| pre0[3] <= #1 sr[15]+sr[16]+sr[17]+sr[18]+sr[19]; | |
| pre0[4] <= #1 sr[20]+sr[21]+sr[22]+sr[23]+sr[24]; | |
| pre0[15] <= #1 sr[75]+sr[76]+sr[77]+sr[78]+sr[79]; | |
| pre0[16] <= #1 sr[80]+sr[81]+sr[82]+sr[83]+sr[84]; | |
| pre0[17] <= #1 sr[85]+sr[86]+sr[87]+sr[88]+sr[89]; | |
| pre0[18] <= #1 sr[90]+sr[91]+sr[92]+sr[93]+sr[94]; | |
| pre0[19] <= #1 sr[95]+sr[96]+sr[97]+sr[98]+sr[99]; | |
| pre0[25] <= #1 sr[125]+sr[126]+sr[127]+sr[128]+sr[129]; | |
| pre0[26] <= #1 sr[130]+sr[131]+sr[132]+sr[133]+sr[134]; | |
| pre0[27] <= #1 sr[135]+sr[136]+sr[137]+sr[138]+sr[139]; | |
| pre0[28] <= #1 sr[140]+sr[141]+sr[142]+sr[143]+sr[144]; | |
| pre0[29] <= #1 sr[145]+sr[146]+sr[147]+sr[148]+sr[149]; | |
| pre0[30] <= #1 sr[150]+sr[151]+sr[152]+sr[153]+sr[154]; | |
| pre0[31] <= #1 sr[155]+sr[156]+sr[157]+sr[158]+sr[159]; | |
| pre0[32] <= #1 sr[160]+sr[161]+sr[162]+sr[163]+sr[164]; | |
| pre0[33] <= #1 sr[165]+sr[166]+sr[167]+sr[168]+sr[169]; | |
| pre0[34] <= #1 sr[170]+sr[171]+sr[172]+sr[173]+sr[174]; | |
| pre0[35] <= #1 sr[175]+sr[176]+sr[177]+sr[178]+sr[179]; | |
| pre0[36] <= #1 sr[180]+sr[181]+sr[182]+sr[183]+sr[184]; | |
| pre0[37] <= #1 sr[185]+sr[186]+sr[187]+sr[188]+sr[189]; | |
| pre0[38] <= #1 sr[190]+sr[191]+sr[192]+sr[193]+sr[194]; | |
| pre0[39] <= #1 sr[195]+sr[196]+sr[197]+sr[198]+sr[199]; | |
| pre0[55] <= #1 sr[275]+sr[276]+sr[277]+sr[278]+sr[279]; | |
| pre0[56] <= #1 sr[280]+sr[281]+sr[282]+sr[283]+sr[284]; | |
| pre0[57] <= #1 sr[285]+sr[286]+sr[287]+sr[288]+sr[289]; | |
| pre0[58] <= #1 sr[290]+sr[291]+sr[292]+sr[293]+sr[294]; | |
| pre0[59] <= #1 sr[295]+sr[296]+sr[297]+sr[298]+sr[299]; | |
| pre0[60] <= #1 sr[300]+sr[301]+sr[302]+sr[303]+sr[304]; | |
| pre0[61] <= #1 sr[305]+sr[306]+sr[307]+sr[308]+sr[309]; | |
| pre0[62] <= #1 sr[310]+sr[311]+sr[312]+sr[313]+sr[314]; | |
| pre0[63] <= #1 sr[315]+sr[316]+sr[317]+sr[318]+sr[319]; | |
| pre0[64] <= #1 sr[320]+sr[321]+sr[322]+sr[323]+sr[324]; | |
| pre0[90] <= #1 sr[450]+sr[451]+sr[452]+sr[453]+sr[454]; | |
| pre0[91] <= #1 sr[455]+sr[456]+sr[457]+sr[458]+sr[459]; | |
| pre0[92] <= #1 sr[460]+sr[461]+sr[462]+sr[463]+sr[464]; | |
| pre0[93] <= #1 sr[465]+sr[466]+sr[467]+sr[468]+sr[469]; | |
| pre0[94] <= #1 sr[470]+sr[471]+sr[472]+sr[473]+sr[474]; | |
| pre0[95] <= #1 sr[475]+sr[476]+sr[477]+sr[478]+sr[479]; | |
| pre0[96] <= #1 sr[480]+sr[481]+sr[482]+sr[483]+sr[484]; | |
| pre0[97] <= #1 sr[485]+sr[486]+sr[487]+sr[488]+sr[489]; | |
| pre0[98] <= #1 sr[490]+sr[491]+sr[492]+sr[493]+sr[494]; | |
| pre0[99] <= #1 sr[495]+sr[496]+sr[497]+sr[498]+sr[499]; | |
| // | |
| end else | |
| flag_in_reg[1] <= #1 0; | |
| end | |
| ////////////////////////////////////////////////////////// | |
| // 2nd calculation, add all the 100 pre0 values | |
| ////////////////////////////////////////////////////////// | |
| always @ (negedge clk or posedge reset) begin:begin3 | |
| integer l; | |
| if (reset) begin | |
| for (l=0; l<20; l=l+1) begin | |
| p1[l] <= #1 0; | |
| end | |
| end else if (flag_in_reg[1] == 1) begin | |
| flag_in_reg[2] <= #1 flag_in_reg[1]; | |
| p1[0] <= #1 pre0[0]+pre0[1]+pre0[2]+pre0[3]+pre0[4]; | |
| p1[1] <= #1 pre0[5]+pre0[6]+pre0[7]+pre0[8]+pre0[9]; | |
| p1[2] <= #1 (~(pre0[10]+pre0[11]+pre0[12]+pre0[13]+pre0[14])+32'd1);// 2's complement taken accordinf to 1001111100 0110000011 | |
| p1[3] <= #1 (~(pre0[15]+pre0[16]+pre0[17]+pre0[18]+pre0[19])+32'd1);// | |
| p1[4] <= #1 (~(pre0[20]+pre0[21]+pre0[22]+pre0[23]+pre0[24])+32'd1);// | |
| p1[5] <= #1 (~(pre0[25]+pre0[26]+pre0[27]+pre0[28]+pre0[29])+32'd1);// | |
| p1[6] <= #1 (~(pre0[30]+pre0[31]+pre0[32]+pre0[33]+pre0[34])+32'd1);// | |
| p1[7] <= #1 pre0[35]+pre0[36]+pre0[37]+pre0[38]+pre0[39]; | |
| p1[8] <= #1 pre0[40]+pre0[41]+pre0[42]+pre0[43]+pre0[44]; | |
| p1[9] <= #1 (~(pre0[45]+pre0[46]+pre0[47]+pre0[48]+pre0[49])+32'd1);// | |
| p1[10] <= #1 (~(pre0[50]+pre0[51]+pre0[52]+pre0[53]+pre0[54])+32'd1);// | |
| p1[11] <= #1 (~(pre0[55]+pre0[56]+pre0[57]+pre0[58]+pre0[59])+32'd1);// | |
| p1[12] <= #1 pre0[60]+pre0[61]+pre0[62]+pre0[63]+pre0[64]; | |
| p1[13] <= #1 pre0[65]+pre0[66]+pre0[67]+pre0[68]+pre0[69]; | |
| p1[14] <= #1 pre0[70]+pre0[71]+pre0[72]+pre0[73]+pre0[74]; | |
| p1[15] <= #1 pre0[75]+pre0[76]+pre0[77]+pre0[78]+pre0[79]; | |
| p1[16] <= #1 pre0[80]+pre0[81]+pre0[82]+pre0[83]+pre0[84]; | |
| p1[17] <= #1 (~(pre0[85]+pre0[86]+pre0[87]+pre0[88]+pre0[89])+32'd1);// | |
| p1[18] <= #1 (~(pre0[90]+pre0[91]+pre0[92]+pre0[93]+pre0[94])+32'd1);// | |
| p1[19] <= #1 pre0[95]+pre0[96]+pre0[97]+pre0[98]+pre0[99]; | |
| end else | |
| flag_in_reg[2] <= #1 0; | |
| end | |
| ////////////////////////////////////////////////////////// | |
| // 3rd calculation, add all the 100 pre0 values | |
| ////////////////////////////////////////////////////////// | |
| always @ (negedge clk or posedge reset) begin:block4 | |
| integer m; | |
| if (reset) begin | |
| for (m=0; m<4; m=m+1) begin | |
| p2[m] <= #1 0; | |
| end | |
| end else if (flag_in_reg[2] == 1) begin | |
| flag_in_reg[3] <= #1 flag_in_reg[2]; | |
| p2[0] <= #1 p1[0]+p1[1]+p1[2]+p1[3]+p1[4]; | |
| p2[1] <= #1 p1[5]+p1[6]+p1[7]+p1[8]+p1[9]; | |
| p2[2] <= #1 p1[10]+p1[11]+p1[12]+p1[13]+p1[14]; | |
| p2[3] <= #1 p1[15]+p1[16]+p1[17]+p1[18]+p1[19]; | |
| end else | |
| flag_in_reg[3] <= #1 0; | |
| end | |
| ////////////////////////////////////////////////////////// | |
| // 3rd calculation, add all the 100 pre0 values | |
| ////////////////////////////////////////////////////////// | |
| always @ (negedge clk or posedge reset) begin | |
| if (reset) begin | |
| p3 <= #1 0; | |
| end | |
| else if (flag_in_reg[3] == 1) begin | |
| flag_in_reg[4] <= #1 flag_in_reg[3]; | |
| p3 <= #1 p2[0]+p2[1]+p2[2]+p2[3]; | |
| end else | |
| flag_in_reg[4] <= #1 0; | |
| end | |
| always @(*) begin | |
| dout1=p3; | |
| //less = ($signed(dout) > $signed(32'd800000000) \); | |
| end | |
| assign flagout = flag_in_reg[4]; | |
| ///////////////////////////////////////////////////////// | |
| // Creating a sync flag and flushing the shift register | |
| ///////////////////////////////////////////////////////// | |
| always @(negedge clk or posedge reset) begin | |
| if (reset) sync <= #1 0; | |
| else | |
| //sync <= #1 (dout > 32'd800000000 || dout < -32'd800000000)?1:0; | |
| if (((flagout == 1) && ($signed(dout1) > $signed(32'd800000000))) || ($signed(dout1) < $signed(-32'd800000000) && (flagout == 1))) | |
| sync <= #1 1; | |
| else | |
| sync <= #1 0; | |
| end | |
| ////////////////////////////////////////////////// | |
| ////// | |
| //Taking in data (13th sample of each) | |
| //////////////////////////////////////////////////////// | |
| reg [31:0] reg250[0:249]; // shift reg for 10 bits signal data | |
| reg [31:0] d0,d1,d2,d3,d4,d5,d6,d7,d8,d9 | |
| reg eof; | |
| reg [9:0] final_out; | |
| // Setting and clearing sync flag | |
| always @(*) begin | |
| if(sync == 1) begin | |
| syncflag = 1; | |
| eof = 0; | |
| end else begin | |
| syncflag = (eof ==1)?0:syncflag; //syncflag shows the data are signal data | |
| cnt = (cnt == 251)?1:cnt; | |
| /*if(eof == 1) syncflag = 0; | |
| if (cnt == 251) begin // good point, credit for Jayesh, Apr29, 2013 | |
| cnt = 1; | |
| end | |
| else cnt = cnt;*/ | |
| end | |
| // putting 250 samples in a register | |
| always @(negedge clk or posedge reset) begin: bl | |
| integer i,j,k; | |
| if (reset) begin | |
| eof <= #1 0; //initialize eof | |
| //syncflag <= #1 0; | |
| for(i=0;i<250;i=i+1) begin: g1 | |
| reg250[i] <= #1 0; | |
| end | |
| end else begin | |
| if (flagin && syncflag) begin | |
| reg250[0] <= #1 din; //reg250 is a shift reg | |
| cnt <= #1 1; | |
| for (j=1; j<250; j=j+1) begin | |
| reg250[j] <= #1 reg250[j-1]; | |
| cnt <= #1 cnt + 1; | |
| end | |
| end else | |
| for(k=0;k<250;k=k+1) | |
| reg250[k] <= #1 reg250[k]; | |
| end | |
| end | |
| // Taking out 13th sample from 250 reg into 10 bit reg | |
| always @(negedge clk) begin: gh | |
| integer j; | |
| if ((cnt == 250) && (syncflag == 1) ) begin | |
| //if (syncflag) begin | |
| d0 <= #1 reg250[12][31]; //d0 <= #1 reg250[12][31]; it will recognize the | |
| //first element as the array order and the 2nd as | |
| //the MSB | |
| d8 <= #1 reg250[37]; | |
| d7 <= #1 reg250[62]; | |
| d6 <= #1 reg250[87]; | |
| d5 <= #1 reg250[112]; | |
| d4 <= #1 reg250[137]; | |
| d3 <= #1 reg250[162]; | |
| d2 <= #1 reg250[187]; | |
| d1 <= #1 reg250[212]; | |
| d0 <= #1 reg250[237]; | |
| //end | |
| //d0 = reg250[j]; | |
| end | |
| end | |
| always @(negedge clk or posedge reset) begin:bh | |
| integer l,m; | |
| if (reset || eof) begin | |
| cnt <= #1 0; | |
| for(l=0;l<10;l=l+1) | |
| final[l] <= #1 0; | |
| end | |
| else begin | |
| if (cnt == 250 && flagin) begin | |
| final[0] <= #1 (d0[31]) ? 0 : 1; | |
| final[1] <= #1 (d1[31]) ? 0 : 1; | |
| final[2] <= #1 (d2[31]) ? 0 : 1; | |
| final[3] <= #1 (d3[31]) ? 0 : 1; | |
| final[4] <= #1 (d4[31]) ? 0 : 1; | |
| final[5] <= #1 (d5[31]) ? 0 : 1; | |
| final[6] <= #1 (d6[31]) ? 0 : 1; | |
| final[7] <= #1 (d7[31]) ? 0 : 1; | |
| final[8] <= #1 (d8[31]) ? 0 : 1; | |
| final[9] <= #1 (d9[31]) ? 0 : 1; | |
| /*final[0] <= #1 (d0[31]) ? 0 : 1; | |
| for(m=0;m<10;m=m+1) final[m] <= #1 (flagin) ? final[m-1] : final[m]; | |
| end | |
| //else final <= #1 final;*/ | |
| end | |
| end | |
| end | |
| `include "decode.v" | |
| always @(*) begin | |
| //eof = ((final == 10'h143 || final == 10'h2BC )) ? 1 : 0; // earlier 10'b1001111100 10'b0110000011 | |
| if (final == 10'h143 || final == 10'h2BC) begin | |
| eof = 1; | |
| if (syncflag && (cnt == 250) && (eof == 0)) | |
| dout = decode(final); | |
| end | |
| else begin | |
| eof = 0; | |
| dout = dout; | |
| end | |
| end | |
| //`include "decode.v" | |
| ///assign dout = () ? decode(final) : dout; | |
| endmodule |
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